7fe9a5d9b4
MachineScheduler when clustering loads or stores checks if base pointers point to the same memory. This check is done through comparison of base registers of two memory instructions. This works fine when instructions have separate offset operand. If they require a full calculated pointer such instructions can never be clustered according to such logic. Changed shouldClusterMemOps to accept base registers as well and let it decide what to do about it. Differential Revision: https://reviews.llvm.org/D37698 llvm-svn: 313208
169 lines
7.1 KiB
LLVM
169 lines
7.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}fadd_f16
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; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
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; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @fadd_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%b.val = load half, half addrspace(1)* %b
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%r.val = fadd half %a.val, %b.val
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fadd_f16_imm_a
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; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], 1.0, v[[B_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 1.0, v[[B_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @fadd_f16_imm_a(
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half addrspace(1)* %r,
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half addrspace(1)* %b) {
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entry:
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%b.val = load half, half addrspace(1)* %b
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%r.val = fadd half 1.0, %b.val
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fadd_f16_imm_b
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; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], 2.0, v[[A_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 2.0, v[[A_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @fadd_f16_imm_b(
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half addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = fadd half %a.val, 2.0
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fadd_v2f16:
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; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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; SI: buffer_load_dword v[[B_V2_F16:[0-9]+]]
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; VI: flat_load_dword v[[B_V2_F16:[0-9]+]]
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; VI: flat_load_dword v[[A_V2_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]
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; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]
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; SI-DAG: v_add_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]], v[[B_F32_0]]
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; SI-DAG: v_add_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]], v[[B_F32_1]]
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; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
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; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
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; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
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; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
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; VI-DAG: v_add_f16_e32 v[[R_F16_LO:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]]
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; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_LO]], v[[R_F16_HI]]
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; GCN: buffer_store_dword v[[R_V2_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @fadd_v2f16(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a,
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<2 x half> addrspace(1)* %b) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.a = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %a, i32 %tid
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%gep.b = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %b, i32 %tid
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %gep.a
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%b.val = load <2 x half>, <2 x half> addrspace(1)* %gep.b
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%r.val = fadd <2 x half> %a.val, %b.val
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fadd_v2f16_imm_a:
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; GCN-DAG: {{buffer|flat}}_load_dword v[[B_V2_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]
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; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]
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; SI: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 1.0, v[[B_F32_0]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
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; SI: v_add_f32_e32 v[[R_F32_1:[0-9]+]], 2.0, v[[B_F32_1]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
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; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
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; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
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; VI-DAG: v_mov_b32_e32 v[[CONST2:[0-9]+]], 0x4000
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; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[B_V2_F16]], v[[CONST2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], 1.0, v[[B_V2_F16]]
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; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
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; GCN: buffer_store_dword v[[R_V2_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @fadd_v2f16_imm_a(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %b) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.b = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %b, i32 %tid
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%b.val = load <2 x half>, <2 x half> addrspace(1)* %gep.b
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%r.val = fadd <2 x half> <half 1.0, half 2.0>, %b.val
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fadd_v2f16_imm_b:
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; GCN-DAG: {{buffer|flat}}_load_dword v[[A_V2_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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; SI: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 2.0, v[[A_F32_0]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
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; SI: v_add_f32_e32 v[[R_F32_1:[0-9]+]], 1.0, v[[A_F32_1]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
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; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
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; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
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; VI-DAG: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00
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; VI-DAG: v_add_f16_sdwa v[[R_F16_0:[0-9]+]], v[[A_V2_F16]], v[[CONST1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; VI-DAG: v_add_f16_e32 v[[R_F16_1:[0-9]+]], 2.0, v[[A_V2_F16]]
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; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
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; GCN: buffer_store_dword v[[R_V2_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @fadd_v2f16_imm_b(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.a = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %a, i32 %tid
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %gep.a
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%r.val = fadd <2 x half> %a.val, <half 2.0, half 1.0>
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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