d3b9f61c52
Change the ISel matching of 'ins', 'dins[mu]' from tablegen code to C++ code. This resolves an issue where ISel would select 'dins' instead of 'dinsm' when the instructions size and position were individually in range but their sum was out of range according to the ISA specification. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39117 llvm-svn: 317331
102 lines
4.3 KiB
LLVM
102 lines
4.3 KiB
LLVM
; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \
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; RUN: -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R2
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; RUN: llc -O2 -verify-machineinstrs -march=mips -mcpu=mips32r2 < %s -o - \
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; RUN: | FileCheck %s -check-prefix=MIPS32R2
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; RUN: llc -O2 -verify-machineinstrs -march=mips -mattr=mips16 < %s -o - \
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; RUN: | FileCheck %s -check-prefix=MIPS16
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; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \
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; RUN: -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N32
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; #include <stdint.h>
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; #include <stdio.h>
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; struct cvmx_buf_ptr {
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; struct {
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; unsigned long long addr :37;
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; unsigned long long addr1 :15;
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; unsigned int lenght:14;
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; uint64_t total_bytes:16;
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; uint64_t segs : 6;
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; } s;
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; }
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;
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; unsigned long long foo(volatile struct cvmx_buf_ptr bufptr) {
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; bufptr.s.addr = 123;
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; bufptr.s.segs = 4;
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; bufptr.s.lenght = 5;
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; bufptr.s.total_bytes = bufptr.s.lenght;
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; return bufptr.s.addr;
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; }
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; Testing of selection INS/DINS instruction
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define i64 @f123(i64 inreg %bufptr.coerce0, i64 inreg %bufptr.coerce1) local_unnamed_addr #0 {
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entry:
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%bufptr.sroa.0 = alloca i64, align 8
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%bufptr.sroa.4 = alloca i64, align 8
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store i64 %bufptr.coerce0, i64* %bufptr.sroa.0, align 8
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store i64 %bufptr.coerce1, i64* %bufptr.sroa.4, align 8
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%bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load = load volatile i64, i64* %bufptr.sroa.0, align 8
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%bf.clear = and i64 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load, 134217727
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%bf.set = or i64 %bf.clear, 16508780544
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store volatile i64 %bf.set, i64* %bufptr.sroa.0, align 8
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%bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load2 = load volatile i64, i64* %bufptr.sroa.4, align 8
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%bf.clear3 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load2, -16911433729
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%bf.set4 = or i64 %bf.clear3, 1073741824
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store volatile i64 %bf.set4, i64* %bufptr.sroa.4, align 8
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%bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load6 = load volatile i64, i64* %bufptr.sroa.4, align 8
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%bf.clear7 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load6, 1125899906842623
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%bf.set8 = or i64 %bf.clear7, 5629499534213120
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store volatile i64 %bf.set8, i64* %bufptr.sroa.4, align 8
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%bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load11 = load volatile i64, i64* %bufptr.sroa.4, align 8
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%bf.lshr = lshr i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load11, 50
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%bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load13 = load volatile i64, i64* %bufptr.sroa.4, align 8
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%bf.shl = shl nuw nsw i64 %bf.lshr, 34
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%bf.clear14 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load13, -1125882726973441
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%bf.set15 = or i64 %bf.clear14, %bf.shl
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store volatile i64 %bf.set15, i64* %bufptr.sroa.4, align 8
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%bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load17 = load volatile i64, i64* %bufptr.sroa.0, align 8
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%bf.lshr18 = lshr i64 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load17, 27
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ret i64 %bf.lshr18
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}
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; CHECK-LABEL: f123:
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; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 123
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; MIPS64R2: dinsm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 27, 37
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; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 4
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; MIPS64R2: dinsm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 28, 6
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; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 5
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; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50, 14
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; MIPS64R2: dsrl $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50
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; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 34, 16
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; MIPS32R2: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 16
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; MIPS32R2-NOT: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 18, 46
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; MIPS16-NOT: ins{{[[:space:]].*}}
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; int foo(volatile int x) {
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; int y = x;
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; y = y & -4;
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; x = y | 8;
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; return y;
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; }
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define i32 @foo(i32 signext %x) {
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entry:
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%x.addr = alloca i32, align 4
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store volatile i32 %x, i32* %x.addr, align 4
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%x.addr.0.x.addr.0. = load volatile i32, i32* %x.addr, align 4
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%and = and i32 %x.addr.0.x.addr.0., -4
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%or = or i32 %and, 8
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store volatile i32 %or, i32* %x.addr, align 4
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ret i32 %and
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}
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; CHECK-LABEL: foo:
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; MIPS64R2: ori $[[R0:[0-9]+]], $[[R0:[0-9]+]], 8
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; MIPS64R2-NOT: ins {{[[:space:]].*}}
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; MIPS32R2: ori $[[R0:[0-9]+]], $[[R0:[0-9]+]], 8
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; MIPS32R2-NOT: ins {{[[:space:]].*}}
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; MIPS64R2N32: ori $[[R0:[0-9]+]], $[[R0:[0-9]+]], 8
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; MIPS64R2N32-NOT: ins {{[[:space:]].*}}
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