Craig Topper 6d9e090a64 [Mips][AMDGPU] Update test cases to not use vector lt/gt compares that can be simplified to an equality/inequality or to always true/false. ...

For example 'ugt X, 0' can be simplified to 'ne X, 0'. Or 'uge X, 0' is always true.

We already simplify this for scalars in SimplifySetCC, but we don't currently for vectors in SimplifySetCC. D42948 proposes to change that.

llvm-svn: 324436

2018-02-07 00:51:37 +00:00

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2r_vector_scalar.ll

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2r.ll

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2rf_exup.ll

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2rf_float_int.ll

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2rf_fq.ll

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2rf_int_float.ll

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2rf_tq.ll

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2rf.ll

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3r_4r_widen.ll

[mips][msa] Prevent output operand from commuting for dpadd_[su].df ins

2017-03-31 14:31:55 +00:00

3r_4r.ll

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3r_splat.ll

[mips][msa] Splat.d endianness check

2017-06-23 09:09:31 +00:00

3r-a.ll

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3r-b.ll

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3r-c.ll

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3r-d.ll

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3r-i.ll

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3r-m.ll

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3r-p.ll

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3r-s.ll

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3r-v.ll

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3rf_4rf_q.ll

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3rf_4rf.ll

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3rf_exdo.ll

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3rf_float_int.ll

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3rf_int_float.ll

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3rf_q.ll

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3rf.ll

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arithmetic_float.ll

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arithmetic.ll

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basic_operations_float.ll

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basic_operations.ll

[mips][msa] Accept more values for constant splats

2017-03-10 13:27:14 +00:00

bit.ll

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bitcast.ll

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bitwise.ll

[mips][msa] Fix generation of bm(n)zi and bins[lr]i instructions

2017-04-07 13:31:36 +00:00

bmzi_bmnzi.ll

Elide stores which are overwritten without being observed.

2017-05-16 19:43:56 +00:00

compare_float.ll

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compare.ll

[Mips][AMDGPU] Update test cases to not use vector lt/gt compares that can be simplified to an equality/inequality or to always true/false.

2018-02-07 00:51:37 +00:00

elm_copy.ll

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elm_cxcmsa.ll

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elm_insv.ll

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elm_move.ll

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elm_shift_slide.ll

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emergency-spill.mir

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

endian.ll

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f16-llvm-ir.ll

[mips] Alter register classes for MSA pseudo f16 instructions

2017-07-18 12:05:35 +00:00

fexuprl.ll

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frameindex.ll

[mips] Use register scavenging with MSA.

2017-11-02 12:47:22 +00:00

i5_ld_st.ll

In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.

2017-03-14 00:34:14 +00:00

i5-a.ll

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i5-b.ll

[mips][msa] Fix generation of bm(n)zi and bins[lr]i instructions

2017-04-07 13:31:36 +00:00

i5-c.ll

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i5-m.ll

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i5-s.ll

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i8.ll

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i10.ll

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immediates-bad.ll

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immediates.ll

[mips][msa] Fix generation of bm(n)zi and bins[lr]i instructions

2017-04-07 13:31:36 +00:00

inline-asm.ll

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llvm-stress-s449609655-simplified.ll

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llvm-stress-s525530439.ll

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llvm-stress-s997348632.ll

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llvm-stress-s1704963983.ll

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llvm-stress-s1935737938.ll

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llvm-stress-s2090927243-simplified.ll

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llvm-stress-s2501752154-simplified.ll

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llvm-stress-s2704903805.ll

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llvm-stress-s3861334421.ll

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llvm-stress-s3926023935.ll

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llvm-stress-s3997499501.ll

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llvm-stress-sz1-s742806235.ll

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msa-nooddspreg.ll

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shift_constant_pool.ll

[mips][msa] Mask vectors holding shift amounts

2017-04-20 13:26:46 +00:00

shift_no_and.ll

[mips][msa] Mask vectors holding shift amounts

2017-04-20 13:26:46 +00:00

shift-dagcombine.ll

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shuffle.ll

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special.ll

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spill.ll

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vec.ll

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vecs10.ll

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