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clang-p2996/llvm/test/CodeGen/PowerPC
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Clement Courbet c6638c813b [MergeICmps] Revert 324317 "Enable the MergeICmps Pass by default." 
While working on PR36557.

llvm-svn: 326575
2018-03-02 14:34:49 +00:00
..
2004-11-29-ShrCrash.ll
…
2004-11-30-shift-crash.ll
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2004-11-30-shr-var-crash.ll
…
2004-12-12-ZeroSizeCommon.ll
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2005-01-14-SetSelectCrash.ll
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2005-01-14-UndefLong.ll
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2005-08-12-rlwimi-crash.ll
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2005-09-02-LegalizeDuplicatesCalls.ll
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2005-10-08-ArithmeticRotate.ll
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2005-11-30-vastart-crash.ll
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2006-01-11-darwin-fp-argument.ll
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2006-01-20-ShiftPartsCrash.ll
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2006-04-01-FloatDoubleExtend.ll
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2006-04-05-splat-ish.ll
…
2006-04-19-vmaddfp-crash.ll
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2006-05-12-rlwimi-crash.ll
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2006-07-07-ComputeMaskedBits.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
2006-07-19-stwbrx-crash.ll
…
2006-08-11-RetVector.ll
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2006-08-15-SelectionCrash.ll
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2006-09-28-shift_64.ll
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2006-10-13-Miscompile.ll
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2006-10-17-brcc-miscompile.ll
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2006-10-17-ppc64-alloca.ll
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2006-11-10-DAGCombineMiscompile.ll
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2006-11-29-AltivecFPSplat.ll
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2006-12-07-LargeAlloca.ll
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2006-12-07-SelectCrash.ll
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2007-01-04-ArgExtension.ll
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2007-01-15-AsmDialect.ll
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2007-01-29-lbrx-asm.ll
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2007-01-31-InlineAsmAddrMode.ll
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2007-02-16-AlignPacked.ll
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2007-02-16-InlineAsmNConstraint.ll
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2007-02-23-lr-saved-twice.ll
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2007-03-24-cntlzd.ll
…
2007-03-30-SpillerCrash.ll
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2007-04-24-InlineAsm-I-Modifier.ll
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2007-04-30-InlineAsmEarlyClobber.ll
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2007-05-03-InlineAsm-S-Constraint.ll
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2007-05-14-InlineAsmSelectCrash.ll
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2007-05-22-tailmerge-3.ll
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2007-05-30-dagcombine-miscomp.ll
…
2007-06-28-BCCISelBug.ll
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2007-08-04-CoalescerAssert.ll
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2007-09-04-AltivecDST.ll
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2007-09-07-LoadStoreIdxForms.ll
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2007-09-08-unaligned.ll
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2007-09-11-RegCoalescerAssert.ll
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2007-09-12-LiveIntervalsAssert.ll
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2007-10-16-InlineAsmFrameOffset.ll
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2007-10-18-PtrArithmetic.ll
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2007-10-21-LocalRegAllocAssert2.ll
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2007-10-21-LocalRegAllocAssert.ll
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2007-11-04-CoalescerCrash.ll
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2007-11-16-landingpad-split.ll
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2007-11-19-VectorSplitting.ll
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2008-02-05-LiveIntervalsAssert.ll
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2008-02-09-LocalRegAllocAssert.ll
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2008-03-05-RegScavengerAssert.ll
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2008-03-17-RegScavengerCrash.ll
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2008-03-18-RegScavengerAssert.ll
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2008-03-24-AddressRegImm.ll
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2008-03-24-CoalescerBug.ll
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2008-03-26-CoalescerBug.ll
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2008-04-10-LiveIntervalCrash.ll
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2008-04-16-CoalescerBug.ll
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2008-04-23-CoalescerCrash.ll
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2008-05-01-ppc_fp128.ll
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2008-06-19-LegalizerCrash.ll
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2008-06-21-F128LoadStore.ll
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2008-06-23-LiveVariablesCrash.ll
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2008-07-10-SplatMiscompile.ll
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2008-07-15-Bswap.ll
…
2008-07-15-Fabs.ll
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2008-07-15-SignExtendInreg.ll
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2008-07-17-Fneg.ll
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2008-07-24-PPC64-CCBug.ll
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2008-09-12-CoalescerBug.ll
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2008-10-17-AsmMatchingOperands.ll
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2008-10-28-f128-i32.ll
…
2008-10-28-UnprocessedNode.ll
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2008-10-31-PPCF128Libcalls.ll
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2008-12-02-LegalizeTypeAssert.ll
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2009-01-16-DeclareISelBug.ll
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2009-03-17-LSRBug.ll
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2009-05-28-LegalizeBRCC.ll
…
2009-07-16-InlineAsm-M-Operand.ll
[CodeGen] Print external symbols as $symbol in both MIR and debug output
2017-12-14 10:02:58 +00:00
2009-08-17-inline-asm-addr-mode-breakage.ll
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2009-09-18-carrybit.ll
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2009-11-15-ProcImpDefsBug.ll
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2009-11-25-ImpDefBug.ll
…
2010-02-04-EmptyGlobal.ll
…
2010-02-12-saveCR.ll
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2010-03-09-indirect-call.ll
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2010-04-01-MachineCSEBug.ll
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2010-05-03-retaddr1.ll
…
2010-10-11-Fast-Varargs.ll
…
2010-12-18-PPCStackRefs.ll
…
2011-12-05-NoSpillDupCR.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2011-12-06-SpillAndRestoreCR.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
2011-12-08-DemandedBitsMiscompile.ll
…
2012-09-16-TOC-entry-check.ll
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2012-10-11-dynalloc.ll
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2012-10-12-bitcast.ll
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2012-11-16-mischedcall.ll
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2013-05-15-preinc-fold.ll
…
2013-07-01-PHIElimBug.ll
…
2016-01-07-BranchWeightCrash.ll
…
2016-04-16-ADD8TLS.ll
…
2016-04-17-combine.ll
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2016-04-28-setjmp.ll
…
a2-fp-basic.ll
…
a2q-stackalign.ll
…
a2q.ll
…
aa-tbaa.ll
…
aantidep-def-ec.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
aantidep-inline-asm-use.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
add-fi.ll
…
addc.ll
…
addegluecrash.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
addi-licm.ll
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addi-offset-fold.ll
…
addi-reassoc.ll
…
addisdtprelha-nonr3.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
addrfuncstr.ll
…
aggressive-anti-dep-breaker-subreg.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
alias.ll
…
align.ll
…
allocate-r0.ll
…
altivec-ord.ll
…
and_add.ll
…
and_sext.ll
…
and_sra.ll
…
and-branch.ll
…
and-elim.ll
…
and-imm.ll
…
andc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
anon_aggr.ll
…
anyext_srl.ll
…
arr-fp-arg-no-copy.ll
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ashr-neg1.ll
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asm-constraints.ll
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asm-dialect.ll
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asm-printer-topological-order.ll
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asm-Zy.ll
…
asym-regclass-copy.ll
…
atomic-1.ll
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atomic-2.ll
…
atomic-minmax.ll
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Atomics-64.ll
…
atomics-constant.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
atomics-fences.ll
…
atomics-indexed.ll
…
atomics-regression.ll
[PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP
2018-01-12 14:58:41 +00:00
atomics.ll
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available-externally.ll
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bdzlr.ll
…
big-endian-actual-args.ll
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big-endian-call-result.ll
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big-endian-formal-args.ll
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bitcasts-direct-move.ll
…
blockaddress.ll
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BoolRetToIntTest-2.ll
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BoolRetToIntTest.ll
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bperm.ll
…
branch_coalesce.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
branch-hint.ll
…
branch-opt.ll
…
BreakableToken-reduced.ll
…
bswap64.ll
[PPC] Use xxbrd to speed up bswap64
2017-11-06 19:09:38 +00:00
bswap-load-store.ll
…
build-vector-tests.ll
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
2017-12-15 07:27:53 +00:00
buildvec_canonicalize.ll
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builtins-ppc-elf2-abi.ll
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builtins-ppc-p8vector.ll
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bv-pres-v8i1.ll
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bv-widen-undef.ll
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byval-agg-info.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
byval-aliased.ll
…
calls.ll
…
can-lower-ret.ll
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cannonicalize-vector-shifts.ll
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cc.ll
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change-no-infs.ll
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cmp_elimination.ll
[PowerPC] fix a bug in redundant compare elimination
2017-12-20 05:18:19 +00:00
cmp-cmp.ll
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cmpb-ppc32.ll
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cmpb.ll
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coal-sections.ll
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coalesce-ext.ll
…
code-align.ll
…
coldcc2.ll
Re-commit : [PowerPC] Add handling for ColdCC calling convention and a pass to mark
2018-01-30 16:17:22 +00:00
coldcc.ll
Re-commit : [PowerPC] Add handling for ColdCC calling convention and a pass to mark
2018-01-30 16:17:22 +00:00
combine_loads_from_build_pair.ll
Unbreak test relying on debug output after r321540.
2017-12-28 21:36:10 +00:00
combine-to-pre-index-store-crash.ll
…
compare-duplicate.ll
…
compare-simm.ll
…
CompareEliminationSpillIssue.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
complex-return.ll
…
constants-i64.ll
…
constants.ll
…
convert-rr-to-ri-instrs-out-of-range.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
convert-rr-to-ri-instrs-R0-special-handling.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
convert-rr-to-ri-instrs.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
copysignl.ll
…
cr1eq-no-extra-moves.ll
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cr1eq.ll
…
cr_spilling.ll
…
cr-spills.ll
…
crash.ll
…
crbit-asm-disabled.ll
…
crbit-asm.ll
…
crbits.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
crsave.ll
…
crypto_bifs.ll
…
ctr-cleanup.ll
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ctr-loop-tls-const.ll
…
ctr-minmaxnum.ll
[PowerPC] Add profitablilty check for conversion to mtctr loops
2017-10-12 16:43:33 +00:00
ctrloop-asm.ll
…
ctrloop-cpsgn.ll
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ctrloop-fp64.ll
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ctrloop-i64.ll
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ctrloop-i128.ll
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ctrloop-intrin.ll
…
ctrloop-large-ec.ll
…
ctrloop-le.ll
…
ctrloop-lt.ll
…
ctrloop-ne.ll
…
ctrloop-reg.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
ctrloop-s000.ll
…
ctrloop-sh.ll
…
ctrloop-shortLoops.ll
[PowerPC] Add profitablilty check for conversion to mtctr loops
2017-10-12 16:43:33 +00:00
ctrloop-sums.ll
…
ctrloop-udivti3.ll
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ctrloops-hot-exit.ll
[PowerPC] Check hot loop exit edge in PPCCTRLoops
2018-02-05 12:25:29 +00:00
ctrloops-softfloat.ll
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ctrloops.ll
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cttz.ll
…
cxx_tlscc64.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
darwin-labels.ll
…
dbg.ll
…
DbgValueOtherTargets.test
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dcbt-sched.ll
…
debuginfo-split-int.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
debuginfo-stackarg.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
delete-node.ll
…
direct-move-profit.ll
[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.
2017-11-20 14:38:30 +00:00
div-2.ll
…
div-e-32.ll
…
div-e-all.ll
…
duplicate-returns-for-tailcall.ll
[PowerPC] fix a bug in TCO eligibility check
2017-12-30 08:09:04 +00:00
dyn-alloca-aligned.ll
…
dyn-alloca-offset.ll
…
e500-1.ll
…
early-ret2.ll
…
early-ret.ll
…
ec-input.ll
…
eh-dwarf-cfa.ll
…
empty-functions.ll
…
emptystruct.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
emutls_generic.ll
[TLS] use emulated TLS if the target supports only this mode
2018-02-28 17:48:55 +00:00
eqv-andc-orc-nor.ll
…
expand-contiguous-isel.ll
[PowerPC] Partially enable the ISEL expansion pass.
2017-12-11 20:42:37 +00:00
expand-foldable-isel.ll
[PowerPC] Partially enable the ISEL expansion pass.
2017-12-11 20:42:37 +00:00
expand-isel-1.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel-2.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel-3.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel-4.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel-5.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel-6.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel-7.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel-8.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel-9.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel-10.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
expand-isel.ll
[PowerPC] Partially enable the ISEL expansion pass.
2017-12-11 20:42:37 +00:00
ext-bool-trunc-repl.ll
…
extra-toc-reg-deps.ll
…
extsh.ll
…
f32-to-i64.ll
…
fabs.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fast-isel-binary.ll
…
fast-isel-br-const.ll
…
fast-isel-call.ll
[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.
2017-12-18 19:21:56 +00:00
fast-isel-cmp-imm.ll
…
fast-isel-const.ll
…
fast-isel-conversion-p5.ll
…
fast-isel-conversion.ll
…
fast-isel-crash.ll
…
fast-isel-ext.ll
…
fast-isel-fcmp-nan.ll
…
fast-isel-fold.ll
…
fast-isel-fpconv.ll
…
fast-isel-GEP-coalesce.ll
…
fast-isel-i64offset.ll
…
fast-isel-icmp-split.ll
…
fast-isel-indirectbr.ll
…
fast-isel-load-store-vsx.ll
…
fast-isel-load-store.ll
…
fast-isel-redefinition.ll
…
fast-isel-ret.ll
…
fast-isel-shifter.ll
…
fastcc_stacksize.ll
[PowerPC] Reduce stack frame for fastcc functions by only allocating parameter save area when needed
2018-02-20 15:09:45 +00:00
fastisel-gep-promote-before-add.ll
…
fcpsgn.ll
…
fdiv-combine.ll
…
float-asmprint.ll
…
float-to-int.ll
…
floatPSA.ll
…
flt-preinc.ll
…
fma-aggr-FMF.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fma-assoc.ll
…
fma-ext.ll
…
fma-mutate-duplicate-vreg.ll
…
fma-mutate-register-constraint.ll
…
fma-mutate.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
fma.ll
…
fmaxnum.ll
…
fminnum.ll
…
fnabs.ll
…
fneg.ll
…
fold-li.ll
…
fold-zero.ll
…
fp2int2fp-ppcfp128.ll
…
fp64-to-int16.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
fp128-bitcast-after-operation.ll
…
fp_to_uint.ll
…
fp-branch.ll
…
fp-int128-fp-combine.ll
[PPC] Avoid incorrect fp-i128-fp lowering.
2018-01-23 22:06:57 +00:00
fp-int-conversions-direct-moves.ll
…
fp-int-fp.ll
…
fp-splat.ll
…
fp-to-int-ext.ll
…
fp-to-int-to-fp.ll
…
fpcopy.ll
…
frame-size.ll
…
frameaddr.ll
…
Frames-alloca.ll
…
Frames-large.ll
…
Frames-leaf.ll
…
Frames-small.ll
…
frounds.ll
…
fsel.ll
…
fsl-e500mc.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
fsl-e5500.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
fsqrt.ll
…
func-addr-consts.ll
…
func-addr.ll
…
glob-comp-aa-crash.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
gpr-vsr-spill.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
hello-reloc.s
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
hello.ll
…
hidden-vis-2.ll
…
hidden-vis.ll
…
htm.ll
…
i1-ext-fold.ll
…
i1-to-double.ll
…
i32-to-float.ll
…
i64_fp_round.ll
…
i64_fp.ll
…
i64-to-float.ll
…
i128-and-beyond.ll
…
ia-mem-r0.ll
…
ia-neg-const.ll
…
iabs.ll
…
ifcvt-forked-bug-2016-08-08.ll
…
ifcvt.ll
…
illegal-element-type.ll
…
in-asm-f64-reg.ll
…
indexed-load.ll
…
indirect-hidden.ll
…
indirectbr.ll
…
inline-asm-s-modifier.ll
…
inline-asm-scalar-to-vector-error.ll
…
inlineasm-copy.ll
…
inlineasm-i64-reg.ll
…
int-fp-conv-0.ll
…
int-fp-conv-1.ll
…
inverted-bool-compares.ll
…
isel-rc-nox0.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
isel.ll
…
ispositive.ll
…
itofp128.ll
…
jaggedstructs.ll
…
LargeAbsoluteAddr.ll
…
lbz-from-ld-shift.ll
…
lbzux.ll
…
ld-st-upd.ll
…
ldtoc-inv.ll
…
lha.ll
…
licm-remat.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
licm-tocReg.ll
[PowerPC] Return true in enableMultipleCopyHints().
2018-01-31 09:26:51 +00:00
lit.local.cfg
…
livephysregs.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
load-constant-addr.ll
…
load-shift-combine.ll
…
load-two-flts.ll
[PowerPC] Return true in enableMultipleCopyHints().
2018-01-31 09:26:51 +00:00
load-v4i8-improved.ll
…
logic-ops-on-compares.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
long-compare.ll
…
longcall.ll
…
longdbl-truncate.ll
…
loop-data-prefetch-inner.ll
…
loop-data-prefetch.ll
…
loop-prep-all.ll
…
lsa.ll
…
lsr-postinc-pos.ll
…
lxv-aligned-stack-slots.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
lxvw4x-bug.ll
…
machine-combiner.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
mask64.ll
…
mature-mc-support.ll
Run these tests, the errors were old and not valid anymore.
2018-02-16 23:02:28 +00:00
mc-instrlat.ll
…
mcm-1.ll
…
mcm-2.ll
…
mcm-3.ll
…
mcm-4.ll
…
mcm-5.ll
…
mcm-6.ll
…
mcm-7.ll
…
mcm-8.ll
…
mcm-9.ll
…
mcm-10.ll
…
mcm-11.ll
…
mcm-12.ll
…
mcm-13.ll
…
mcm-default.ll
…
mcm-obj-2.ll
…
mcm-obj.ll
…
mcount-insertion.ll
Rename CountingFunctionInserter and use for both mcount and cygprofile calls, before and after inlining
2017-11-14 21:09:45 +00:00
MCSE-caller-preserved-reg.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
mem_update.ll
…
mem-rr-addr-mode.ll
…
memcmp-mergeexpand.ll
[MergeICmps] Revert 324317 "Enable the MergeICmps Pass by default."
2018-03-02 14:34:49 +00:00
memcmp.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
memcmpIR.ll
…
memCmpUsedInZeroEqualityComparison.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
memcpy_dereferenceable.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memcpy-vec.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset-nc-le.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
memset-nc.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
merge_stores_dereferenceable.ll
…
merge-st-chain-op.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
MergeConsecutiveStores.ll
…
mftb.ll
…
misched-inorder-latency.ll
…
misched.ll
…
MMO-flags-assertion.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
mtvsrdd.ll
…
mul-neg-power-2.ll
…
mul-with-overflow.ll
…
mulhs.ll
…
mulli64.ll
…
mult-alt-generic-powerpc64.ll
…
mult-alt-generic-powerpc.ll
…
multi-return.ll
…
named-reg-alloc-r0.ll
…
named-reg-alloc-r1-64.ll
…
named-reg-alloc-r1.ll
…
named-reg-alloc-r2-64.ll
…
named-reg-alloc-r2.ll
…
named-reg-alloc-r13-64.ll
…
named-reg-alloc-r13.ll
…
neg.ll
…
negate-i1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
negctr.ll
…
no-dead-strip.ll
…
no-dup-spill-fp.ll
…
no-ext-with-count-zeros.ll
…
no-extra-fp-conv-ldst.ll
…
no-pref-jumps.ll
…
no-rlwimi-trivial-commute.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
non-simple-args-intrin.ll
[PowerPC] Can not assume an intrinsic argument is a simple type.
2018-01-09 03:03:41 +00:00
novrsave.ll
…
opt-cmp-inst-cr0-live.ll
[CodeGen] Don't omit any redundant information in -debug output
2018-02-26 15:23:42 +00:00
opt-li-add-to-addi.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
opt-sub-inst-cr0-live.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
optcmp.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
optnone-crbits-i1-ret.ll
…
or-addressing-mode.ll
…
ori_imm32.ll
…
p8-isel-sched.ll
…
p8-scalar_vector_conversions.ll
Revert "[PowerPC] Try to simplify a Swap if it feeds a Splat"
2017-10-30 19:55:38 +00:00
p8altivec-shuffles-pred.ll
…
p9-vector-compares-and-counts.ll
…
p9-vinsert-vextract.ll
Use new vector insert half-word and byte instructions when we see insertelement on '8 x i16' and '16 x i8' types. Also extended existing lit testcase to cover these cases.
2017-11-07 20:55:43 +00:00
p9-xxinsertw-xxextractuw.ll
[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.
2017-11-20 14:38:30 +00:00
peephole-align.ll
…
pie.ll
…
pip-inner.ll
…
popcnt.ll
…
post-ra-ec.ll
…
power9-moves-and-splats.ll
…
ppc32-align-long-double-sf.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
ppc32-constant-BE-ppcf128.ll
…
ppc32-cyclecounter.ll
…
ppc32-i1-vaarg.ll
…
ppc32-lshrti3.ll
…
ppc32-nest.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
ppc32-pic-large.ll
…
ppc32-pic.ll
…
ppc32-skip-regs.ll
…
ppc32-vacopy.ll
…
ppc64-32bit-addic.ll
…
ppc64-abi-extend.ll
…
ppc64-align-long-double.ll
[NFC] fix trivial typos in comments and documents
2018-01-26 08:15:29 +00:00
ppc64-altivec-abi.ll
…
ppc64-anyregcc-crash.ll
…
ppc64-anyregcc.ll
…
ppc64-blnop.ll
…
ppc64-byval-align.ll
[PowerPC] Return true in enableMultipleCopyHints().
2018-01-31 09:26:51 +00:00
ppc64-calls.ll
…
ppc64-crash.ll
…
ppc64-cyclecounter.ll
…
ppc64-elf-abi.ll
…
ppc64-fastcc-fast-isel.ll
…
ppc64-fastcc.ll
…
ppc64-func-desc-hoist.ll
…
ppc64-gep-opt.ll
…
ppc64-get-cache-line-size.ll
…
ppc64-i128-abi.ll
…
ppc64-icbt-pwr7.ll
…
ppc64-icbt-pwr8.ll
…
ppc64-linux-func-size.ll
…
ppc64-nest.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
ppc64-nonfunc-calls.ll
…
ppc64-P9-mod.ll
…
ppc64-P9-vabsd.ll
…
ppc64-patchpoint.ll
…
ppc64-pre-inc-no-extra-phi.ll
…
ppc64-prefetch.ll
…
ppc64-r2-alloc.ll
…
ppc64-sibcall-shrinkwrap.ll
…
ppc64-sibcall.ll
[PowerPC] fix a bug in TCO eligibility check
2017-12-30 08:09:04 +00:00
ppc64-smallarg.ll
…
ppc64-stackmap-nops.ll
…
ppc64-stackmap.ll
…
ppc64-toc.ll
…
ppc64-vaarg-int.ll
…
ppc64-zext.ll
…
ppc64le-aggregates.ll
…
ppc64le-calls.ll
…
ppc64le-crsave.ll
…
ppc64le-localentry-large.ll
…
ppc64le-localentry.ll
…
ppc64le-smallarg.ll
[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.
2017-11-20 14:38:30 +00:00
ppc440-fp-basic.ll
…
ppc440-msync.ll
…
ppc-crbits-onoff.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
ppc-ctr-dead-code.ll
Disabling the transformation introduced in r315888
2017-10-20 00:36:46 +00:00
ppc-empty-fs.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
ppc-prologue.ll
…
ppc-redzone-alignment-bug.ll
Revert "[PowerPC] Manually schedule the prologue and epilogue"
2018-01-12 13:12:49 +00:00
ppc-shrink-wrapping.ll
Revert "[PowerPC] Manually schedule the prologue and epilogue"
2018-01-12 13:12:49 +00:00
ppc-vaarg-agg.ll
…
ppcf128-1-opt.ll
…
ppcf128-1.ll
…
ppcf128-2.ll
…
ppcf128-3.ll
…
ppcf128-4.ll
…
ppcf128-endian.ll
…
ppcf128sf.ll
…
ppcsoftops.ll
…
pr3711_widen_bit.ll
…
pr12757.ll
…
pr13641.ll
…
pr13891.ll
…
pr15031.ll
…
pr15359.ll
…
pr15630.ll
…
pr15632.ll
…
pr16556-2.ll
…
pr16556.ll
…
pr16573.ll
…
pr17168.ll
…
pr17354.ll
…
pr18663-2.ll
…
pr18663.ll
…
pr20442.ll
…
pr22711.ll
…
pr24216.ll
…
pr24546.ll
…
pr24636.ll
…
pr25157-peephole.ll
[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.
2017-11-20 14:38:30 +00:00
pr25157.ll
[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.
2017-11-20 14:38:30 +00:00
pr26180.ll
…
pr26193.ll
…
pr26356.ll
…
pr26378.ll
…
pr26381.ll
…
pr26617.ll
…
pr26690.ll
…
pr27078.ll
…
pr27350.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
pr28130.ll
…
pr28630.ll
…
pr30451.ll
…
pr30640.ll
…
pr30663.ll
…
pr30715.ll
…
pr31144.ll
…
pr32063.ll
…
pr32140.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr33093.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
pr33547.ll
[PowerPC] Disable shrink-wrapping when getting PC address through the LR
2018-02-23 23:08:34 +00:00
pr35688.ll
[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversion
2017-12-29 12:22:27 +00:00
pr36068.ll
[PowerPC] Tell VSX swap removal that scalar conversions are lane-sensitive
2018-02-01 21:09:04 +00:00
pr36292.ll
[PowerPC] Do not produce invalid CTR loop with an FRem
2018-02-22 03:02:41 +00:00
PR3488.ll
…
PR33636.ll
…
PR33671.ll
…
PR35812-neg-cmpxchg.ll
[LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization.
2018-01-17 22:04:36 +00:00
preemption.ll
Represent runtime preemption in the IR.
2017-10-26 15:00:26 +00:00
preinc-ld-sel-crash.ll
…
preincprep-invoke.ll
…
preincprep-nontrans-crash.ll
…
private.ll
…
pwr3-6x.ll
…
pwr7-gt-nop.ll
…
pzero-fp-xored.ll
…
qpx-bv-sint.ll
…
qpx-bv.ll
…
qpx-func-clobber.ll
…
qpx-load-splat.ll
…
qpx-load.ll
…
qpx-recipest.ll
…
qpx-rounding-ops.ll
…
qpx-s-load.ll
…
qpx-s-sel.ll
…
qpx-s-store.ll
…
qpx-sel.ll
…
qpx-split-vsetcc.ll
…
qpx-store.ll
…
qpx-unal-cons-lds.ll
…
qpx-unalperm.ll
…
quadint-return.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
r31.ll
…
recipest.ll
…
reg-coalesce-simple.ll
…
reg-names.ll
First step towards more human-friendly PPC assembler output:
2017-11-29 23:05:56 +00:00
reloc-align.ll
…
remap-crash.ll
…
remat-imm.ll
…
remove-redundant-moves.ll
…
remove-redundant-toc-saves.ll
[PowerPC] Remove redundant TOC saves
2017-11-27 20:26:36 +00:00
resolvefi-basereg.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
resolvefi-disp.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
restore-r30.ll
…
retaddr2.ll
…
retaddr.ll
…
return-val-i128.ll
…
rlwimi2.ll
…
rlwimi3.ll
…
rlwimi-and-or-bits.ll
…
rlwimi-and.ll
…
rlwimi-commute.ll
…
rlwimi-dyn-and.ll
…
rlwimi-keep-rsh.ll
…
rlwimi.ll
…
rlwinm2.ll
…
rlwinm-zero-ext.ll
…
rlwinm.ll
…
rm-zext.ll
…
rotl-2.ll
…
rotl-64.ll
…
rotl-rotr-crash.ll
…
rotl.ll
…
rounding-ops.ll
…
rs-undef-use.ll
…
s000-alias-misched.ll
…
save-bp.ll
…
save-cr-ppc32svr4.ll
…
save-crbp-ppc32svr4.ll
…
scavenging.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
sdag-ppcf128.ll
…
sdiv-pow2.ll
…
sections.ll
…
select_const.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
select_lt0.ll
…
select-addrRegRegOnly.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
select-cc.ll
…
select-i1-vs-i1.ll
[PowerPC] Return true in enableMultipleCopyHints().
2018-01-31 09:26:51 +00:00
selectiondag-extload-computeknownbits.ll
…
selectiondag-sextload.ll
[DAGCombine] Don't combine sext with extload if sextload is not supported and extload has multi users
2017-10-27 21:54:24 +00:00
set0-v8i16.ll
…
setcc_no_zext.ll
…
setcc-logic.ll
[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.
2017-12-18 19:21:56 +00:00
setcc-to-sub.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
setcclike-or-comb.ll
…
seteq-0.ll
…
shift128.ll
…
shift_mask.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
shift-cmp.ll
…
shl_elim.ll
…
shl_sext.ll
…
sign_ext_inreg1.ll
…
simplifyConstCmpToISEL.ll
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
2017-12-15 07:27:53 +00:00
sj-ctr-loop.ll
…
sjlj_no0x.ll
…
sjlj.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
small-arguments.ll
…
spill-nor0.ll
…
splat-bug.ll
…
splat-larger-types-as-v16i8.ll
…
split-index-tc.ll
…
srl-mask.ll
…
stack-no-redzone.ll
…
stack-protector.ll
…
stack-realign.ll
…
stackmap-frame-setup.ll
…
stacksize.ll
…
std-unal-fi.ll
…
stdux-constuse.ll
…
stfiwx-2.ll
…
stfiwx.ll
…
store-constant.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
store-load-fwd.ll
…
store-update.ll
…
structsinmem.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
structsinregs.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
stubs.ll
…
stwu8.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
stwu-gta.ll
…
stwux.ll
…
sub-bv-types.ll
…
subc.ll
…
subreg-postra-2.ll
[LICM] sink through non-trivially replicable PHI
2017-11-03 16:24:53 +00:00
subreg-postra.ll
…
subtract_from_imm.ll
…
svr4-redzone.ll
…
swaps-le-1.ll
…
swaps-le-2.ll
…
swaps-le-3.ll
…
swaps-le-4.ll
…
swaps-le-5.ll
…
swaps-le-6.ll
…
swaps-le-7.ll
…
tail-dup-analyzable-fallthrough.ll
…
tail-dup-branch-to-fallthrough.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
tail-dup-break-cfg.ll
…
tail-dup-layout.ll
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
2018-02-27 16:59:10 +00:00
tailcall1-64.ll
…
tailcall1.ll
…
tailcall-string-rvo.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
tailcallpic1.ll
…
testBitReverse.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesi32gtu.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesi32leu.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesi32ltu.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesieqsc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesieqsi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesieqsll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesieqss.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiequc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiequi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiequll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiequs.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesigesc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesigesi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesigesll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesigess.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesigeuc.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
testComparesigeui.ll
[PowerPC] Sign-extend negative constant stores
2017-12-11 14:35:48 +00:00
testComparesigeull.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesigeus.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
testComparesigtsc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesigtsi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesigtsll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesigtss.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesigtuc.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesigtui.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesigtus.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesilesc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesilesi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesilesll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiless.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesileuc.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesileui.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesileull.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesileus.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesiltsc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiltsi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiltsll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiltss.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiltuc.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesiltui.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesiltus.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesinesc.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesinesi.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesinesll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesiness.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesineuc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesineui.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesineull.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesineus.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testCompareslleqsc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testCompareslleqsi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testCompareslleqsll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testCompareslleqss.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllequc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllequi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllequll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllequs.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllgesc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllgesi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllgesll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllgess.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllgeuc.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
testComparesllgeui.ll
[PowerPC] Sign-extend negative constant stores
2017-12-11 14:35:48 +00:00
testComparesllgeull.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesllgeus.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
testComparesllgtsll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllgtuc.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesllgtui.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesllgtus.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testCompareslllesc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testCompareslllesi.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testCompareslllesll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllless.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllleuc.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesllleui.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesllleull.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesllleus.ll
[PowerPC] Recommit r314244 with refactoring and off by default
2017-11-30 13:39:10 +00:00
testComparesllltsll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllltuc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllltui.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllltus.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllnesll.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
testComparesllneull.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
thread-pointer.ll
…
tls_get_addr_clobbers.ll
Revert "[PowerPC] Manually schedule the prologue and epilogue"
2018-01-12 13:12:49 +00:00
tls_get_addr_fence1.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
tls_get_addr_fence2.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
tls_get_addr_stackframe.ll
…
tls-cse.ll
…
tls-pic.ll
…
tls-store2.ll
…
tls.ll
…
toc-load-sched-bug.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
trampoline.ll
…
uint-to-ppcfp128-crash.ll
[PowerPC] Fix parest build failure in SPEC2017.
2017-12-21 15:42:50 +00:00
unal4-std.ll
…
unal-altivec2.ll
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unal-altivec-wint.ll
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unal-altivec.ll
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unal-vec-ldst.ll
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unal-vec-negarith.ll
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unaligned.ll
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
2017-12-15 07:27:53 +00:00
unsafe-math.ll
…
unwind-dw2-g.ll
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unwind-dw2.ll
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vaddsplat.ll
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varargs-struct-float.ll
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varargs.ll
…
variable_elem_vec_extracts.ll
[SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left.
2017-12-22 17:18:13 +00:00
vcmp-fold.ll
…
vec_abs.ll
…
vec_absd.ll
…
vec_add_sub_doubleword.ll
…
vec_add_sub_quadword.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_auto_constant.ll
…
vec_br_cmp.ll
…
vec_buildvector_loadstore.ll
…
vec_call.ll
…
vec_clz.ll
…
vec_cmp.ll
…
vec_cmpd.ll
…
vec_constants.ll
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vec_conv.ll
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vec_extload.ll
…
vec_extract_p9_2.ll
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
2018-03-01 22:32:25 +00:00
vec_extract_p9.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_fmuladd.ll
…
vec_fneg.ll
…
vec_insert.ll
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vec_int_ext.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_mergeow.ll
…
vec_minmax.ll
…
vec_misaligned.ll
…
vec_mul_even_odd.ll
…
vec_mul.ll
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vec_perf_shuffle.ll
…
vec_popcnt.ll
…
vec_revb.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_rotate_shift.ll
…
vec_rounding.ll
…
vec_select.ll
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vec_shift.ll
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vec_shuffle_le.ll
…
vec_shuffle_p8vector_le.ll
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vec_shuffle_p8vector.ll
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vec_shuffle.ll
…
vec_sldwi.ll
…
vec_splat_constant.ll
…
vec_splat.ll
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vec_sqrt.ll
…
vec_urem_const.ll
…
vec_veqv_vnand_vorc.ll
…
vec_vrsave.ll
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vec_xxpermdi.ll
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vec_zero.ll
…
vec-abi-align.ll
…
vec-asm-disabled.ll
…
vector-identity-shuffle.ll
…
vector-merge-store-fp-constants.ll
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vector.ll
…
vperm-instcombine.ll
…
vperm-lowering.ll
…
vrsave-spill.ll
…
vrspill.ll
…
vsel-prom.ll
…
vselect-constants.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vsx_insert_extract_le.ll
[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.
2017-11-20 14:38:30 +00:00
vsx_scalar_ld_st.ll
[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.
2017-11-20 14:38:30 +00:00
vsx_shuffle_le.ll
…
vsx-args.ll
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VSX-DForm-Scalars.ll
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vsx-div.ll
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vsx-elementary-arith.ll
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vsx-fma-m.ll
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vsx-fma-mutate-trivial-copy.ll
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vsx-fma-mutate-undef.ll
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vsx-fma-sp.ll
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vsx-infl-copy1.ll
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vsx-infl-copy2.ll
…
vsx-ldst-builtin-le.ll
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vsx-ldst.ll
…
vsx-minmax.ll
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vsx-p8.ll
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vsx-p9.ll
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vsx-partword-int-loads-and-stores.ll
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vsx-recip-est.ll
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vsx-self-copy.ll
…
vsx-spill-norwstore.ll
…
vsx-spill.ll
…
vsx-vec-spill.ll
…
vsx-word-splats.ll
…
VSX-XForm-Scalars.ll
[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.
2017-11-20 14:38:30 +00:00
vsx.ll
…
vsxD-Form-spills.ll
Revert "[PowerPC] Manually schedule the prologue and epilogue"
2018-01-12 13:12:49 +00:00
vtable-reloc.ll
…
weak_def_can_be_hidden.ll
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xray-attribute-instrumentation.ll
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xray-conditional-return.ll
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xray-ret-is-terminator.ll
…
xray-tail-call-hidden.ll
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xray-tail-call-sled.ll
…
xvcmpeqdp-v2f64.ll
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xxleqv_xxlnand_xxlorc.ll
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zero-not-run.ll
…
zext-and-cmp.ll
[PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.
2017-11-29 04:09:29 +00:00
zext-bitperm.ll
…
zext-free.ll
…