43e94b15ea
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
33 lines
1.8 KiB
LLVM
33 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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define void @foo() {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # implicit-def: $rax
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; CHECK-NEXT: jmpq *%rax
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; CHECK-NEXT: .LBB0_1:
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; CHECK-NEXT: # implicit-def: $rax
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
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; CHECK-NEXT: movdqu %xmm1, (%rax)
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; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) # 16-byte Spill
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: retq
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indirectbr i8* undef, [label %9, label %1]
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; <label>:1: ; preds = %0
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%2 = shufflevector <16 x i8> zeroinitializer, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
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%3 = shufflevector <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
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%4 = or <16 x i8> %3, %2
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%5 = shufflevector <16 x i8> %4, <16 x i8> undef, <16 x i32> <i32 8, i32 5, i32 1, i32 13, i32 15, i32 10, i32 14, i32 0, i32 3, i32 2, i32 7, i32 4, i32 6, i32 9, i32 11, i32 12>
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%6 = bitcast <16 x i8> %5 to <2 x i64>
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%7 = xor <2 x i64> %6, zeroinitializer
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%8 = xor <2 x i64> %7, <i64 -1, i64 -1>
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store <2 x i64> %8, <2 x i64>* undef, align 1
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unreachable
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; <label>:9: ; preds = %0
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ret void
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}
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