eb8c408e50
This reverses instcombine's demanded bits' transform which always tries to clear bits in constants. As noted in PR35792 and shown in the test diffs: https://bugs.llvm.org/show_bug.cgi?id=35792 ...we can do better in codegen by trying to form -1. The x86 sub test shows a missed opportunity. I did investigate changing instcombine's behavior, but it would be more work to change canonicalization in IR. Clearing bits / shrinking constants can allow killing instructions, so we'd have to figure out how to not regress those cases. Differential Revision: https://reviews.llvm.org/D42986 llvm-svn: 324839
141 lines
3.3 KiB
LLVM
141 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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; Various tests for ands that should be implemented with movzx, but aren't due
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; demanded bits shortcomings.
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; The backend will insert a zext to promote the shift to i32.
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define i16 @test1(i16 %x) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: shrl %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%y = lshr i16 %x, 1
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ret i16 %y
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: shrl %eax
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; CHECK-NEXT: retq
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%y = and i32 %x, 65535
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%z = lshr i32 %y, 1
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ret i32 %z
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}
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define i32 @test3(i32 %x) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: shrl %eax
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; CHECK-NEXT: retq
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%y = and i32 %x, 255
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%z = lshr i32 %y, 1
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ret i32 %z
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}
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define i16 @test4(i16 %x) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: shrl %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%y = and i16 %x, 255
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%z = lshr i16 %y, 1
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ret i16 %z
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}
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define i16 @test5(i16 %x) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: shrl $9, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%y = lshr i16 %x, 9
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ret i16 %y
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}
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define i32 @test6(i32 %x) {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: shrl $9, %eax
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; CHECK-NEXT: retq
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%y = and i32 %x, 65535
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%z = lshr i32 %y, 9
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ret i32 %z
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}
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; TODO: We could turn this and into a zero extend.
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define i32 @test7(i32 %x) {
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; CHECK-LABEL: test7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $65534, %edi # imm = 0xFFFE
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; CHECK-NEXT: leal 1(%rdi), %eax
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; CHECK-NEXT: retq
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%y = and i32 %x, 65534
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%z = or i32 %y, 1
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ret i32 %z
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}
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; We actually get a movzx on this one, but only because we canonicalize the and
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; after the or before SimplifyDemandedBits messes it up.
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define i32 @test8(i32 %x) {
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; CHECK-LABEL: test8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: orl $1, %edi
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: retq
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%y = and i32 %x, 65535
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%z = or i32 %y, 1
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ret i32 %z
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}
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define i64 @add_neg_one(i64 %x) {
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; CHECK-LABEL: add_neg_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: leal -1(%rdi), %eax
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; CHECK-NEXT: andl %edi, %eax
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: retq
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%a1 = and i64 %x, 65535
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%a2 = add i64 %x, 65535
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%r = and i64 %a1, %a2
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ret i64 %r
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}
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define i64 @sub_neg_one(i64 %x) {
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; CHECK-LABEL: sub_neg_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: leal -65535(%rdi), %eax
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; CHECK-NEXT: andl %edi, %eax
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: retq
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%a1 = and i64 %x, 65535
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%a2 = sub i64 %x, 65535
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%r = and i64 %a1, %a2
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ret i64 %r
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}
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define i64 @mul_neg_one(i64 %x) {
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; CHECK-LABEL: mul_neg_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: negl %eax
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; CHECK-NEXT: andl %edi, %eax
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: retq
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%a1 = and i64 %x, 65535
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%a2 = mul i64 %x, 65535
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%r = and i64 %a1, %a2
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ret i64 %r
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}
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