4a36e96c3f
This simple heuristic uses the estimated live range length combined with the number of registers in the class to switch which heuristic to use. This was taking the raw number of registers in the class, even though not all of them may be available. AMDGPU heavily relies on dynamically reserved numbers of registers based on user attributes to satisfy occupancy constraints, so the raw number is highly misleading. There are still a few problems here. In the original testcase that made me notice this, the live range size is incorrect after the scheduler rearranges instructions, since the instructions don't have the original InstrDist offsets. Additionally, I think it would be more appropriate to use the number of disjointly allocatable registers in the class. For the AMDGPU register tuples, there are a large number of registers in each tuple class, but only a small fraction can actually be allocated at the same time since they all overlap with each other. It seems we do not have a query that corresponds to the number of independently allocatable registers. Relatedly, I'm still debugging some allocation failures where overlapping tuples seem to not be handled correctly. The test changes are mostly noise. There are a handful of x86 tests that look like regressions with an additional spill, and a handful that now avoid a spill. The worst looking regression is likely test/Thumb2/mve-vld4.ll which introduces a few additional spills. test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll shows a massive improvement by completely eliminating a large number of spills inside a loop.
614 lines
18 KiB
LLVM
614 lines
18 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=X64,SSE
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx | FileCheck %s --check-prefixes=X64,AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx2 | FileCheck %s --check-prefixes=X64,AVX,AVX2
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; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=X86
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; The i1 parameter is not codegen-relevant right now.
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declare i8 @llvm.abs.i8(i8, i1)
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declare i16 @llvm.abs.i16(i16, i1)
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declare i24 @llvm.abs.i24(i24, i1)
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declare i32 @llvm.abs.i32(i32, i1)
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declare i64 @llvm.abs.i64(i64, i1)
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declare i128 @llvm.abs.i128(i128, i1)
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declare <1 x i32> @llvm.abs.v1i32(<1 x i32>, i1)
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declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)
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declare <3 x i32> @llvm.abs.v3i32(<3 x i32>, i1)
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declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
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declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)
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declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)
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declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)
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define i8 @test_i8(i8 %a) nounwind {
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; X64-LABEL: test_i8:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: sarb $7, %cl
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; X64-NEXT: leal (%rdi,%rcx), %eax
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; X64-NEXT: xorb %cl, %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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;
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; X86-LABEL: test_i8:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: sarb $7, %cl
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; X86-NEXT: addb %cl, %al
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; X86-NEXT: xorb %cl, %al
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; X86-NEXT: retl
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%r = call i8 @llvm.abs.i8(i8 %a, i1 false)
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ret i8 %r
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}
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define i16 @test_i16(i16 %a) nounwind {
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; X64-LABEL: test_i16:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negw %ax
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; X64-NEXT: cmovlw %di, %ax
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; X64-NEXT: retq
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;
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; X86-LABEL: test_i16:
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; X86: # %bb.0:
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: negw %ax
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; X86-NEXT: cmovlw %cx, %ax
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; X86-NEXT: retl
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%r = call i16 @llvm.abs.i16(i16 %a, i1 false)
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ret i16 %r
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}
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define i24 @test_i24(i24 %a) nounwind {
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; X64-LABEL: test_i24:
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; X64: # %bb.0:
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; X64-NEXT: shll $8, %edi
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; X64-NEXT: sarl $8, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: cmovll %edi, %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: test_i24:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: shll $8, %ecx
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; X86-NEXT: sarl $8, %ecx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: negl %eax
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; X86-NEXT: cmovll %ecx, %eax
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; X86-NEXT: retl
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%r = call i24 @llvm.abs.i24(i24 %a, i1 false)
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ret i24 %r
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}
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define i32 @test_i32(i32 %a) nounwind {
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; X64-LABEL: test_i32:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: cmovll %edi, %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: test_i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: negl %eax
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; X86-NEXT: cmovll %ecx, %eax
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; X86-NEXT: retl
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%r = call i32 @llvm.abs.i32(i32 %a, i1 false)
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ret i32 %r
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}
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define i64 @test_i64(i64 %a) nounwind {
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; X64-LABEL: test_i64:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: negq %rax
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; X64-NEXT: cmovlq %rdi, %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: test_i64:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %edx, %ecx
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; X86-NEXT: sarl $31, %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: addl %ecx, %eax
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; X86-NEXT: adcl %ecx, %edx
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; X86-NEXT: xorl %ecx, %edx
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; X86-NEXT: xorl %ecx, %eax
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; X86-NEXT: retl
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%r = call i64 @llvm.abs.i64(i64 %a, i1 false)
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ret i64 %r
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}
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define i128 @test_i128(i128 %a) nounwind {
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; X64-LABEL: test_i128:
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; X64: # %bb.0:
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; X64-NEXT: movq %rsi, %rdx
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movq %rsi, %rcx
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; X64-NEXT: sarq $63, %rcx
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; X64-NEXT: addq %rcx, %rax
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; X64-NEXT: adcq %rcx, %rdx
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; X64-NEXT: xorq %rcx, %rax
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; X64-NEXT: xorq %rcx, %rdx
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; X64-NEXT: retq
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;
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; X86-LABEL: test_i128:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %edx
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; X86-NEXT: sarl $31, %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: addl %edx, %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: adcl %edx, %edi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; X86-NEXT: adcl %edx, %ebx
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; X86-NEXT: adcl %edx, %ecx
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; X86-NEXT: xorl %edx, %ecx
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; X86-NEXT: xorl %edx, %ebx
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; X86-NEXT: xorl %edx, %edi
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; X86-NEXT: xorl %edx, %esi
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; X86-NEXT: movl %esi, (%eax)
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; X86-NEXT: movl %edi, 4(%eax)
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; X86-NEXT: movl %ebx, 8(%eax)
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; X86-NEXT: movl %ecx, 12(%eax)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: retl $4
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%r = call i128 @llvm.abs.i128(i128 %a, i1 false)
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ret i128 %r
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}
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define <1 x i32> @test_v1i32(<1 x i32> %a) nounwind {
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; X64-LABEL: test_v1i32:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: cmovll %edi, %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: test_v1i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: negl %eax
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; X86-NEXT: cmovll %ecx, %eax
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; X86-NEXT: retl
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%r = call <1 x i32> @llvm.abs.v1i32(<1 x i32> %a, i1 false)
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ret <1 x i32> %r
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}
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define <2 x i32> @test_v2i32(<2 x i32> %a) nounwind {
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; SSE-LABEL: test_v2i32:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: pxor %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_v2i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vpabsd %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; X86-LABEL: test_v2i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %edx, %eax
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; X86-NEXT: negl %eax
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; X86-NEXT: cmovll %edx, %eax
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; X86-NEXT: movl %ecx, %edx
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; X86-NEXT: negl %edx
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; X86-NEXT: cmovll %ecx, %edx
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; X86-NEXT: retl
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%r = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %a, i1 false)
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ret <2 x i32> %r
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}
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define <3 x i32> @test_v3i32(<3 x i32> %a) nounwind {
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; SSE-LABEL: test_v3i32:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: pxor %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_v3i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vpabsd %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; X86-LABEL: test_v3i32:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %edx, %eax
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; X86-NEXT: negl %eax
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; X86-NEXT: cmovll %edx, %eax
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; X86-NEXT: movl %ecx, %edx
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; X86-NEXT: negl %edx
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; X86-NEXT: cmovll %ecx, %edx
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; X86-NEXT: movl %esi, %ecx
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; X86-NEXT: negl %ecx
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; X86-NEXT: cmovll %esi, %ecx
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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%r = call <3 x i32> @llvm.abs.v3i32(<3 x i32> %a, i1 false)
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ret <3 x i32> %r
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}
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define <4 x i32> @test_v4i32(<4 x i32> %a) nounwind {
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; SSE-LABEL: test_v4i32:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: pxor %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_v4i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vpabsd %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; X86-LABEL: test_v4i32:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; X86-NEXT: movl %ebx, %edx
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; X86-NEXT: negl %edx
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; X86-NEXT: cmovll %ebx, %edx
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; X86-NEXT: movl %edi, %ebx
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; X86-NEXT: negl %ebx
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; X86-NEXT: cmovll %edi, %ebx
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; X86-NEXT: movl %esi, %edi
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; X86-NEXT: negl %edi
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; X86-NEXT: cmovll %esi, %edi
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; X86-NEXT: movl %ecx, %esi
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; X86-NEXT: negl %esi
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; X86-NEXT: cmovll %ecx, %esi
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; X86-NEXT: movl %esi, 12(%eax)
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; X86-NEXT: movl %edi, 8(%eax)
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; X86-NEXT: movl %ebx, 4(%eax)
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; X86-NEXT: movl %edx, (%eax)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: retl $4
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%r = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false)
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ret <4 x i32> %r
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}
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define <8 x i32> @test_v8i32(<8 x i32> %a) nounwind {
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; SSE-LABEL: test_v8i32:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: psrad $31, %xmm2
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; SSE-NEXT: paddd %xmm2, %xmm0
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; SSE-NEXT: pxor %xmm2, %xmm0
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrad $31, %xmm2
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; SSE-NEXT: paddd %xmm2, %xmm1
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; SSE-NEXT: pxor %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test_v8i32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpabsd %xmm0, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpabsd %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test_v8i32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpabsd %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; X86-LABEL: test_v8i32:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %edx, %ecx
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; X86-NEXT: negl %ecx
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; X86-NEXT: cmovll %edx, %ecx
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; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; X86-NEXT: movl %esi, %ecx
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; X86-NEXT: negl %ecx
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; X86-NEXT: cmovll %esi, %ecx
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; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
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; X86-NEXT: movl %ebx, %esi
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; X86-NEXT: negl %esi
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; X86-NEXT: cmovll %ebx, %esi
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; X86-NEXT: movl %ebp, %ebx
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; X86-NEXT: negl %ebx
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; X86-NEXT: cmovll %ebp, %ebx
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; X86-NEXT: movl %edi, %ebp
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; X86-NEXT: negl %ebp
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; X86-NEXT: cmovll %edi, %ebp
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; X86-NEXT: movl %eax, %edi
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; X86-NEXT: negl %edi
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; X86-NEXT: cmovll %eax, %edi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: negl %eax
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; X86-NEXT: cmovll %ecx, %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
; X86-NEXT: movl %edx, %ecx
|
|
; X86-NEXT: negl %ecx
|
|
; X86-NEXT: cmovll %edx, %ecx
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
; X86-NEXT: movl %ecx, 28(%edx)
|
|
; X86-NEXT: movl %eax, 24(%edx)
|
|
; X86-NEXT: movl %edi, 20(%edx)
|
|
; X86-NEXT: movl %ebp, 16(%edx)
|
|
; X86-NEXT: movl %ebx, 12(%edx)
|
|
; X86-NEXT: movl %esi, 8(%edx)
|
|
; X86-NEXT: movl (%esp), %eax # 4-byte Reload
|
|
; X86-NEXT: movl %eax, 4(%edx)
|
|
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
|
|
; X86-NEXT: movl %eax, (%edx)
|
|
; X86-NEXT: movl %edx, %eax
|
|
; X86-NEXT: addl $8, %esp
|
|
; X86-NEXT: popl %esi
|
|
; X86-NEXT: popl %edi
|
|
; X86-NEXT: popl %ebx
|
|
; X86-NEXT: popl %ebp
|
|
; X86-NEXT: retl $4
|
|
%r = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 false)
|
|
ret <8 x i32> %r
|
|
}
|
|
|
|
define <8 x i16> @test_v8i16(<8 x i16> %a) nounwind {
|
|
; SSE-LABEL: test_v8i16:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: pxor %xmm1, %xmm1
|
|
; SSE-NEXT: psubw %xmm0, %xmm1
|
|
; SSE-NEXT: pmaxsw %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: test_v8i16:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vpabsw %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
;
|
|
; X86-LABEL: test_v8i16:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: pushl %ebp
|
|
; X86-NEXT: pushl %ebx
|
|
; X86-NEXT: pushl %edi
|
|
; X86-NEXT: pushl %esi
|
|
; X86-NEXT: pushl %eax
|
|
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
|
|
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edi
|
|
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ebp
|
|
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ebx
|
|
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %esi
|
|
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
|
|
; X86-NEXT: movl %edx, %ecx
|
|
; X86-NEXT: negw %cx
|
|
; X86-NEXT: cmovlw %dx, %cx
|
|
; X86-NEXT: movw %cx, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
|
|
; X86-NEXT: movl %esi, %ecx
|
|
; X86-NEXT: negw %cx
|
|
; X86-NEXT: cmovlw %si, %cx
|
|
; X86-NEXT: movw %cx, (%esp) # 2-byte Spill
|
|
; X86-NEXT: movl %ebx, %esi
|
|
; X86-NEXT: negw %si
|
|
; X86-NEXT: cmovlw %bx, %si
|
|
; X86-NEXT: movl %ebp, %ebx
|
|
; X86-NEXT: negw %bx
|
|
; X86-NEXT: cmovlw %bp, %bx
|
|
; X86-NEXT: movl %edi, %ebp
|
|
; X86-NEXT: negw %bp
|
|
; X86-NEXT: cmovlw %di, %bp
|
|
; X86-NEXT: movl %eax, %edi
|
|
; X86-NEXT: negw %di
|
|
; X86-NEXT: cmovlw %ax, %di
|
|
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
|
|
; X86-NEXT: movl %ecx, %eax
|
|
; X86-NEXT: negw %ax
|
|
; X86-NEXT: cmovlw %cx, %ax
|
|
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
|
|
; X86-NEXT: movl %edx, %ecx
|
|
; X86-NEXT: negw %cx
|
|
; X86-NEXT: cmovlw %dx, %cx
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
; X86-NEXT: movw %cx, 14(%edx)
|
|
; X86-NEXT: movw %ax, 12(%edx)
|
|
; X86-NEXT: movw %di, 10(%edx)
|
|
; X86-NEXT: movw %bp, 8(%edx)
|
|
; X86-NEXT: movw %bx, 6(%edx)
|
|
; X86-NEXT: movw %si, 4(%edx)
|
|
; X86-NEXT: movzwl (%esp), %eax # 2-byte Folded Reload
|
|
; X86-NEXT: movw %ax, 2(%edx)
|
|
; X86-NEXT: movzwl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 2-byte Folded Reload
|
|
; X86-NEXT: movw %ax, (%edx)
|
|
; X86-NEXT: movl %edx, %eax
|
|
; X86-NEXT: addl $4, %esp
|
|
; X86-NEXT: popl %esi
|
|
; X86-NEXT: popl %edi
|
|
; X86-NEXT: popl %ebx
|
|
; X86-NEXT: popl %ebp
|
|
; X86-NEXT: retl $4
|
|
%r = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 false)
|
|
ret <8 x i16> %r
|
|
}
|
|
|
|
define <16 x i8> @test_v16i8(<16 x i8> %a) nounwind {
|
|
; SSE-LABEL: test_v16i8:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: pxor %xmm1, %xmm1
|
|
; SSE-NEXT: psubb %xmm0, %xmm1
|
|
; SSE-NEXT: pminub %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: test_v16i8:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vpabsb %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
;
|
|
; X86-LABEL: test_v16i8:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: pushl %ebx
|
|
; X86-NEXT: pushl %esi
|
|
; X86-NEXT: subl $12, %esp
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %bh
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %bl
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %dh
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %ch
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %ah
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
|
|
; X86-NEXT: movb %cl, %al
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %cl
|
|
; X86-NEXT: xorb %al, %cl
|
|
; X86-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
|
|
; X86-NEXT: movb %dl, %al
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %dl
|
|
; X86-NEXT: xorb %al, %dl
|
|
; X86-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
|
|
; X86-NEXT: movb %ah, %al
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %ah
|
|
; X86-NEXT: xorb %al, %ah
|
|
; X86-NEXT: movb %ah, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
|
|
; X86-NEXT: movb %ch, %al
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %ch
|
|
; X86-NEXT: xorb %al, %ch
|
|
; X86-NEXT: movb %ch, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
|
|
; X86-NEXT: movb %dh, %al
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %dh
|
|
; X86-NEXT: xorb %al, %dh
|
|
; X86-NEXT: movb %dh, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
|
|
; X86-NEXT: movl %ebx, %eax
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %bl
|
|
; X86-NEXT: xorb %al, %bl
|
|
; X86-NEXT: movb %bl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
|
|
; X86-NEXT: movb %bh, %al
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %bh
|
|
; X86-NEXT: xorb %al, %bh
|
|
; X86-NEXT: movb %bh, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
|
|
; X86-NEXT: movl %ecx, %eax
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %cl
|
|
; X86-NEXT: xorb %al, %cl
|
|
; X86-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
|
|
; X86-NEXT: movl %ecx, %eax
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %cl
|
|
; X86-NEXT: xorb %al, %cl
|
|
; X86-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %bh
|
|
; X86-NEXT: movb %bh, %al
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %bh
|
|
; X86-NEXT: xorb %al, %bh
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %bl
|
|
; X86-NEXT: movl %ebx, %eax
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %bl
|
|
; X86-NEXT: xorb %al, %bl
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %dh
|
|
; X86-NEXT: movb %dh, %al
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %dh
|
|
; X86-NEXT: xorb %al, %dh
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %ch
|
|
; X86-NEXT: movb %ch, %al
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %ch
|
|
; X86-NEXT: xorb %al, %ch
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
|
|
; X86-NEXT: movl %edx, %eax
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %dl
|
|
; X86-NEXT: xorb %al, %dl
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
|
|
; X86-NEXT: movl %ecx, %eax
|
|
; X86-NEXT: sarb $7, %al
|
|
; X86-NEXT: addb %al, %cl
|
|
; X86-NEXT: xorb %al, %cl
|
|
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
|
|
; X86-NEXT: movb %al, %ah
|
|
; X86-NEXT: sarb $7, %ah
|
|
; X86-NEXT: addb %ah, %al
|
|
; X86-NEXT: xorb %ah, %al
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
|
|
; X86-NEXT: movb %al, 15(%esi)
|
|
; X86-NEXT: movb %cl, 14(%esi)
|
|
; X86-NEXT: movb %dl, 13(%esi)
|
|
; X86-NEXT: movb %ch, 12(%esi)
|
|
; X86-NEXT: movb %dh, 11(%esi)
|
|
; X86-NEXT: movb %bl, 10(%esi)
|
|
; X86-NEXT: movb %bh, 9(%esi)
|
|
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
|
|
; X86-NEXT: movb %al, 8(%esi)
|
|
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
|
|
; X86-NEXT: movb %al, 7(%esi)
|
|
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
|
|
; X86-NEXT: movb %al, 6(%esi)
|
|
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
|
|
; X86-NEXT: movb %al, 5(%esi)
|
|
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
|
|
; X86-NEXT: movb %al, 4(%esi)
|
|
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
|
|
; X86-NEXT: movb %al, 3(%esi)
|
|
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
|
|
; X86-NEXT: movb %al, 2(%esi)
|
|
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
|
|
; X86-NEXT: movb %al, 1(%esi)
|
|
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
|
|
; X86-NEXT: movb %al, (%esi)
|
|
; X86-NEXT: movl %esi, %eax
|
|
; X86-NEXT: addl $12, %esp
|
|
; X86-NEXT: popl %esi
|
|
; X86-NEXT: popl %ebx
|
|
; X86-NEXT: retl $4
|
|
%r = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 false)
|
|
ret <16 x i8> %r
|
|
}
|