3ac6711aec
The idea is that the instruction to be emulated is actually executed on the hardware to be emulated, with the before and after state of the hardware being captured and 'freeze-dried' into .dat files. The emulation testing code then loads the before & after state from the .dat file, emulates the instruction using the before state, and compares the resulting state to the 'after' state. If they match, the emulation is accurate, otherwise there is a problem. The final format of the .dat files needs a bit more work; the plan is to generalize them a bit and to convert the plain values to key-value pairs. But I wanted to get this first pass committed. This commit adds arm instruction emulation testing to the testsuite, along with many initial .dat files. It also fixes a bug in the llvm disassembler, where 32-bit thumb opcodes were getting their upper & lower 16-bits reversed. There is a new Instruction sub-class, that is intended to be loaded from a .dat file rather than read from an executable. There is also a new EmulationStateARM class, for handling the before & after states. EmulationStates for other architetures can be added later when we emulate their instructions. llvm-svn: 129832
569 lines
17 KiB
C++
569 lines
17 KiB
C++
//===-- DisassemblerLLVM.cpp ------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "DisassemblerLLVM.h"
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#include "llvm-c/EnhancedDisassembly.h"
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#include "lldb/Core/Address.h"
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#include "lldb/Core/DataExtractor.h"
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#include "lldb/Core/Disassembler.h"
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#include "lldb/Core/Module.h"
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Core/Stream.h"
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#include "lldb/Core/StreamString.h"
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#include "lldb/Symbol/SymbolContext.h"
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#include "lldb/Target/ExecutionContext.h"
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#include "lldb/Target/Process.h"
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#include "lldb/Target/RegisterContext.h"
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#include "lldb/Target/Target.h"
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#include <assert.h>
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using namespace lldb;
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using namespace lldb_private;
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static int
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DataExtractorByteReader (uint8_t *byte, uint64_t address, void *arg)
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{
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DataExtractor &extractor = *((DataExtractor *)arg);
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if (extractor.ValidOffset(address))
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{
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*byte = *(extractor.GetDataStart() + address);
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return 0;
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}
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else
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{
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return -1;
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}
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}
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namespace {
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struct RegisterReaderArg {
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const lldb::addr_t instructionPointer;
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const EDDisassemblerRef disassembler;
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RegisterReaderArg(lldb::addr_t ip,
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EDDisassemblerRef dis) :
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instructionPointer(ip),
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disassembler(dis)
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{
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}
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};
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}
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static int IPRegisterReader(uint64_t *value, unsigned regID, void* arg)
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{
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uint64_t instructionPointer = ((RegisterReaderArg*)arg)->instructionPointer;
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EDDisassemblerRef disassembler = ((RegisterReaderArg*)arg)->disassembler;
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if (EDRegisterIsProgramCounter(disassembler, regID)) {
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*value = instructionPointer;
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return 0;
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}
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return -1;
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}
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InstructionLLVM::InstructionLLVM (const Address &addr,
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AddressClass addr_class,
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EDDisassemblerRef disassembler,
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bool force_raw) :
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Instruction (addr, addr_class),
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m_disassembler (disassembler),
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m_force_raw (force_raw)
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{
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}
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InstructionLLVM::~InstructionLLVM()
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{
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}
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static void
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PadString(Stream *s, const std::string &str, size_t width)
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{
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int diff = width - str.length();
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if (diff > 0)
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s->Printf("%s%*.*s", str.c_str(), diff, diff, "");
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else
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s->Printf("%s ", str.c_str());
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}
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void
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InstructionLLVM::Dump
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(
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Stream *s,
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uint32_t max_opcode_byte_size,
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bool show_address,
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bool show_bytes,
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const lldb_private::ExecutionContext* exe_ctx,
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bool raw
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)
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{
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const size_t opcodeColumnWidth = 7;
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const size_t operandColumnWidth = 25;
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ExecutionContextScope *exe_scope = NULL;
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if (exe_ctx)
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exe_scope = exe_ctx->GetBestExecutionContextScope();
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// If we have an address, print it out
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if (GetAddress().IsValid() && show_address)
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{
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if (GetAddress().Dump (s,
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exe_scope,
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Address::DumpStyleLoadAddress,
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Address::DumpStyleModuleWithFileAddress,
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0))
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s->PutCString(": ");
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}
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// If we are supposed to show bytes, "bytes" will be non-NULL.
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if (show_bytes)
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{
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if (m_opcode.GetType() == Opcode::eTypeBytes)
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{
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// x86_64 and i386 are the only ones that use bytes right now so
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// pad out the byte dump to be able to always show 15 bytes (3 chars each)
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// plus a space
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if (max_opcode_byte_size > 0)
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m_opcode.Dump (s, max_opcode_byte_size * 3 + 1);
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else
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m_opcode.Dump (s, 15 * 3 + 1);
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}
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else
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{
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// Else, we have ARM which can show up to a uint32_t 0x00000000 (10 spaces)
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// plus two for padding...
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if (max_opcode_byte_size > 0)
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m_opcode.Dump (s, max_opcode_byte_size * 3 + 1);
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else
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m_opcode.Dump (s, 12);
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}
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}
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int numTokens = -1;
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if (!raw)
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raw = m_force_raw;
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if (!raw)
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numTokens = EDNumTokens(m_inst);
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int currentOpIndex = -1;
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bool printTokenized = false;
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if (numTokens != -1 && !raw)
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{
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addr_t base_addr = LLDB_INVALID_ADDRESS;
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RegisterReaderArg rra(base_addr + EDInstByteSize(m_inst), m_disassembler);
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if (exe_ctx && exe_ctx->target && !exe_ctx->target->GetSectionLoadList().IsEmpty())
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base_addr = GetAddress().GetLoadAddress (exe_ctx->target);
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if (base_addr == LLDB_INVALID_ADDRESS)
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base_addr = GetAddress().GetFileAddress ();
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printTokenized = true;
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// Handle the opcode column.
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StreamString opcode;
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int tokenIndex = 0;
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EDTokenRef token;
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const char *tokenStr;
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if (EDGetToken(&token, m_inst, tokenIndex))
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printTokenized = false;
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if (!printTokenized || !EDTokenIsOpcode(token))
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printTokenized = false;
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if (!printTokenized || EDGetTokenString(&tokenStr, token))
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printTokenized = false;
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// Put the token string into our opcode string
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opcode.PutCString(tokenStr);
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// If anything follows, it probably starts with some whitespace. Skip it.
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tokenIndex++;
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if (printTokenized && tokenIndex < numTokens)
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{
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if(!printTokenized || EDGetToken(&token, m_inst, tokenIndex))
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printTokenized = false;
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if(!printTokenized || !EDTokenIsWhitespace(token))
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printTokenized = false;
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}
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tokenIndex++;
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// Handle the operands and the comment.
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StreamString operands;
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StreamString comment;
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if (printTokenized)
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{
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bool show_token;
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for (; tokenIndex < numTokens; ++tokenIndex)
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{
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if (EDGetToken(&token, m_inst, tokenIndex))
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return;
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if (raw)
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{
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show_token = true;
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}
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else
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{
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int operandIndex = EDOperandIndexForToken(token);
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if (operandIndex >= 0)
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{
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if (operandIndex != currentOpIndex)
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{
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show_token = true;
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currentOpIndex = operandIndex;
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EDOperandRef operand;
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if (!EDGetOperand(&operand, m_inst, currentOpIndex))
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{
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if (EDOperandIsMemory(operand))
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{
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uint64_t operand_value;
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if (!EDEvaluateOperand(&operand_value, operand, IPRegisterReader, &rra))
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{
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if (EDInstIsBranch(m_inst))
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{
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operands.Printf("0x%llx ", operand_value);
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show_token = false;
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}
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else
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{
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// Put the address value into the comment
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comment.Printf("0x%llx ", operand_value);
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}
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lldb_private::Address so_addr;
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if (exe_ctx && exe_ctx->target && !exe_ctx->target->GetSectionLoadList().IsEmpty())
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{
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if (exe_ctx->target->GetSectionLoadList().ResolveLoadAddress (operand_value, so_addr))
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so_addr.Dump(&comment, exe_scope, Address::DumpStyleResolvedDescriptionNoModule, Address::DumpStyleSectionNameOffset);
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}
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else
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{
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Module *module = GetAddress().GetModule();
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if (module)
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{
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if (module->ResolveFileAddress (operand_value, so_addr))
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so_addr.Dump(&comment, exe_scope, Address::DumpStyleResolvedDescriptionNoModule, Address::DumpStyleSectionNameOffset);
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}
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}
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} // EDEvaluateOperand
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} // EDOperandIsMemory
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} // EDGetOperand
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} // operandIndex != currentOpIndex
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} // operandIndex >= 0
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} // else(raw)
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if (show_token)
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{
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if(EDGetTokenString(&tokenStr, token))
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{
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printTokenized = false;
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break;
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}
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operands.PutCString(tokenStr);
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}
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} // for (tokenIndex)
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if (printTokenized)
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{
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if (operands.GetString().empty())
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{
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s->PutCString(opcode.GetString().c_str());
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}
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else
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{
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PadString(s, opcode.GetString(), opcodeColumnWidth);
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if (comment.GetString().empty())
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{
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s->PutCString(operands.GetString().c_str());
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}
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else
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{
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PadString(s, operands.GetString(), operandColumnWidth);
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s->PutCString("; ");
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s->PutCString(comment.GetString().c_str());
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} // else (comment.GetString().empty())
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} // else (operands.GetString().empty())
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} // printTokenized
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} // for (tokenIndex)
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} // numTokens != -1
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if (!printTokenized)
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{
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const char *str;
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if (EDGetInstString(&str, m_inst))
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return;
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else
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s->Write(str, strlen(str) - 1);
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}
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}
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bool
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InstructionLLVM::DoesBranch() const
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{
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return EDInstIsBranch(m_inst);
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}
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size_t
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InstructionLLVM::Decode (const Disassembler &disassembler,
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const lldb_private::DataExtractor &data,
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uint32_t data_offset)
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{
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if (EDCreateInsts(&m_inst, 1, m_disassembler, DataExtractorByteReader, data_offset, (void*)(&data)))
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{
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const int byte_size = EDInstByteSize(m_inst);
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uint32_t offset = data_offset;
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// Make a copy of the opcode in m_opcode
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switch (disassembler.GetArchitecture().GetMachine())
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{
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case llvm::Triple::x86:
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case llvm::Triple::x86_64:
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m_opcode.SetOpcodeBytes (data.PeekData (data_offset, byte_size), byte_size);
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break;
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case llvm::Triple::arm:
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case llvm::Triple::thumb:
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switch (byte_size)
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{
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case 2:
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m_opcode.SetOpcode16 (data.GetU16 (&offset));
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break;
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case 4:
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{
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if (GetAddressClass() == eAddressClassCodeAlternateISA)
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{
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// If it is a 32-bit THUMB instruction, we need to swap the upper & lower halves.
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uint32_t orig_bytes = data.GetU32 (&offset);
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uint16_t upper_bits = (orig_bytes >> 16) & ((1u << 16) - 1);
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uint16_t lower_bits = orig_bytes & ((1u << 16) - 1);
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uint32_t swapped = (lower_bits << 16) | upper_bits;
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m_opcode.SetOpcode32 (swapped);
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}
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else
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m_opcode.SetOpcode32 (data.GetU32 (&offset));
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}
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break;
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default:
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assert (!"Invalid ARM opcode size");
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break;
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}
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break;
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default:
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assert (!"This shouldn't happen since we control the architecture we allow DisassemblerLLVM to be created for");
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break;
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}
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return byte_size;
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}
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else
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return 0;
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}
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static inline EDAssemblySyntax_t
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SyntaxForArchSpec (const ArchSpec &arch)
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{
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switch (arch.GetMachine ())
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{
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case llvm::Triple::x86:
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case llvm::Triple::x86_64:
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return kEDAssemblySyntaxX86ATT;
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case llvm::Triple::arm:
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case llvm::Triple::thumb:
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return kEDAssemblySyntaxARMUAL;
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default:
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break;
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}
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return (EDAssemblySyntax_t)0; // default
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}
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Disassembler *
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DisassemblerLLVM::CreateInstance(const ArchSpec &arch)
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{
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std::auto_ptr<DisassemblerLLVM> disasm_ap (new DisassemblerLLVM(arch));
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if (disasm_ap.get() && disasm_ap->IsValid())
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return disasm_ap.release();
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return NULL;
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}
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DisassemblerLLVM::DisassemblerLLVM(const ArchSpec &arch) :
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Disassembler (arch),
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m_disassembler (NULL),
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m_disassembler_thumb (NULL) // For ARM only
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{
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const std::string &arch_triple = arch.GetTriple().str();
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if (!arch_triple.empty())
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{
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if (EDGetDisassembler(&m_disassembler, arch_triple.c_str(), SyntaxForArchSpec (arch)))
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m_disassembler = NULL;
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llvm::Triple::ArchType llvm_arch = arch.GetTriple().getArch();
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// Don't have the lldb::Triple::thumb architecture here. If someone specifies
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// "thumb" as the architecture, we want a thumb only disassembler. But if any
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// architecture starting with "arm" if specified, we want to auto detect the
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// arm/thumb code automatically using the AddressClass from section offset
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// addresses.
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if (llvm_arch == llvm::Triple::arm)
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{
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if (EDGetDisassembler(&m_disassembler_thumb, "thumb-apple-darwin", kEDAssemblySyntaxARMUAL))
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m_disassembler_thumb = NULL;
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}
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}
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}
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DisassemblerLLVM::~DisassemblerLLVM()
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{
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}
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size_t
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DisassemblerLLVM::DecodeInstructions
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(
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const Address &base_addr,
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const DataExtractor& data,
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uint32_t data_offset,
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uint32_t num_instructions,
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bool append
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)
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{
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if (m_disassembler == NULL)
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return 0;
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size_t total_inst_byte_size = 0;
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if (!append)
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m_instruction_list.Clear();
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while (data.ValidOffset(data_offset) && num_instructions)
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{
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Address inst_addr (base_addr);
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inst_addr.Slide(data_offset);
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bool use_thumb = false;
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// If we have a thumb disassembler, then we have an ARM architecture
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// so we need to check what the instruction address class is to make
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// sure we shouldn't be disassembling as thumb...
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AddressClass inst_address_class = eAddressClassInvalid;
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if (m_disassembler_thumb)
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{
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inst_address_class = inst_addr.GetAddressClass ();
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if (inst_address_class == eAddressClassCodeAlternateISA)
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use_thumb = true;
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}
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bool force_raw = false;
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switch (m_arch.GetMachine())
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{
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case llvm::Triple::arm:
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case llvm::Triple::thumb:
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force_raw = true;
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break;
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default:
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break;
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}
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InstructionSP inst_sp (new InstructionLLVM (inst_addr,
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inst_address_class,
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use_thumb ? m_disassembler_thumb : m_disassembler,
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force_raw));
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size_t inst_byte_size = inst_sp->Decode (*this, data, data_offset);
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if (inst_byte_size == 0)
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break;
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m_instruction_list.Append (inst_sp);
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total_inst_byte_size += inst_byte_size;
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data_offset += inst_byte_size;
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num_instructions--;
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}
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return total_inst_byte_size;
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}
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|
|
void
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DisassemblerLLVM::Initialize()
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|
{
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PluginManager::RegisterPlugin (GetPluginNameStatic(),
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GetPluginDescriptionStatic(),
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CreateInstance);
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}
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void
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DisassemblerLLVM::Terminate()
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{
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PluginManager::UnregisterPlugin (CreateInstance);
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}
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const char *
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DisassemblerLLVM::GetPluginNameStatic()
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{
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return "llvm";
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}
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const char *
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DisassemblerLLVM::GetPluginDescriptionStatic()
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{
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return "Disassembler that uses LLVM opcode tables to disassemble i386, x86_64 and ARM.";
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}
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//------------------------------------------------------------------
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// PluginInterface protocol
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//------------------------------------------------------------------
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const char *
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DisassemblerLLVM::GetPluginName()
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{
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return "DisassemblerLLVM";
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}
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const char *
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DisassemblerLLVM::GetShortPluginName()
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{
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return GetPluginNameStatic();
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}
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uint32_t
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DisassemblerLLVM::GetPluginVersion()
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{
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return 1;
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}
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