Chris Lattner 6d277517d1 Recommit the fix for rdar://9289512 with a couple tweaks to ...

fix bugs exposed by the gcc dejagnu testsuite:
1. The load may actually be used by a dead instruction, which
   would cause an assert.
2. The load may not be used by the current chain of instructions,
   and we could move it past a side-effecting instruction. Change
   how we process uses to define the problem away.

llvm-svn: 130018

2011-04-22 21:59:37 +00:00

..

Alpha

If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.

2010-12-06 22:39:26 +00:00

ARM

Fix DWARF description of Q registers.

2011-04-21 23:22:35 +00:00

Blackfin

Don't completely eliminate identity copies that also modify super register liveness.

2011-03-31 17:55:25 +00:00

CBackend

…

CellSPU

don't test for codegen of 'store undef'

2011-04-09 02:31:26 +00:00

CPP

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Generic

Un-XFAIL this test for ARM. <rdar://problem/7662569>

2011-04-20 21:47:45 +00:00

MBlaze

Add scheduling information for the MBlaze backend.

2011-04-11 22:31:52 +00:00

Mips

Make tests register allocation independent again.

2011-04-19 00:14:43 +00:00

MSP430

Enhance ComputeMaskedBits to know that aligned frameindexes

2011-02-13 22:25:43 +00:00

PowerPC

These tests no longer require linear scan because reserved register coalescing is now universal.

2011-04-05 21:40:41 +00:00

PTX

ptx: fix parameter ordering

2011-04-21 10:56:58 +00:00

SPARC

These tests no longer require linear scan because reserved register coalescing is now universal.

2011-04-05 21:40:41 +00:00

SystemZ

Fix SystemZ tests

2011-03-31 23:02:12 +00:00

Thumb

Make tests register allocation independent again.

2011-04-19 00:14:43 +00:00

Thumb2

In Thumb2 mode, lower frame indix references to:

2011-04-22 01:42:52 +00:00

X86

Recommit the fix for rdar://9289512 with a couple tweaks to

2011-04-22 21:59:37 +00:00

XCore

Fix Mips, Sparc, and XCore tests that were dependent on register allocation.

2011-03-31 18:42:43 +00:00