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Austin Kerbow 527e9f9a3f AMDGPU: Fix infinite searches in SIFixSGPRCopies 
Summary:
Two conditions could lead to infinite loops when processing PHI nodes in
SIFixSGPRCopies.

The first condition involves a REG_SEQUENCE that uses registers defined by both
a PHI and a COPY.

The second condition arises when a physical register is copied to a virtual
register which is then used in a PHI node. If the same virtual register is
copied to the same physical register, the result is an endless loop.

%0:sgpr_64 = COPY $sgpr0_sgpr1
%2 = PHI %0, %bb.0, %1, %bb.1
$sgpr0_sgpr1 = COPY %0

Reviewers: alex-t, rampitec, arsenm

Reviewed By: rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68970

llvm-svn: 374944
2019-10-15 19:59:45 +00:00
..
AsmParser
[AMDGPU][MC][GFX10] Enabled null for 64-bit dst operands
2019-10-11 14:35:11 +00:00
Disassembler
[AMDGPU][MC][GFX10][WS32] Corrected decoding of dst operand for v_cmp_*_sdwa opcodes
2019-10-04 13:04:17 +00:00
MCTargetDesc
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
TargetInfo
Revert CMake: Make most target symbols hidden by default
2019-06-11 03:21:13 +00:00
Utils
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
AMDGPU.h
[AMDGPU] Printf runtime binding pass
2019-08-12 17:12:29 +00:00
AMDGPU.td
[AMDGPU] w/a for gfx908 mfma SrcC literal HW bug
2019-08-23 22:09:58 +00:00
AMDGPUAliasAnalysis.cpp
AMDGPU: Improve alias analysis for GDS
2019-07-17 11:22:19 +00:00
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
…
AMDGPUAnnotateKernelFeatures.cpp
Use llvm::StringLiteral instead of StringRef in few places
2019-09-20 14:31:42 +00:00
AMDGPUAnnotateUniformValues.cpp
…
AMDGPUArgumentUsageInfo.cpp
[AMDGPU] Packed thread ids in function call ABI
2019-06-28 01:52:13 +00:00
AMDGPUArgumentUsageInfo.h
AMDGPU: Fix Register copypaste error
2019-09-05 23:07:10 +00:00
AMDGPUAsmPrinter.cpp
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
AMDGPUAsmPrinter.h
[AMDGPU] separate accounting for agprs
2019-10-02 00:26:58 +00:00
AMDGPUAtomicOptimizer.cpp
[AMDGPU] gfx10 atomic optimizer changes.
2019-08-23 10:07:43 +00:00
AMDGPUCallingConv.td
[AMDGPU] Adjust number of SGPRs available in Calling Convention
2019-08-28 15:00:45 +00:00
AMDGPUCallLowering.cpp
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC
2019-09-09 23:06:13 +00:00
AMDGPUCallLowering.h
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC
2019-09-09 23:06:13 +00:00
AMDGPUCodeGenPrepare.cpp
AMDGPU: Preserve value name when inserting mul24 intrinsic
2019-08-24 22:17:10 +00:00
AMDGPUFeatures.td
…
AMDGPUFixFunctionBitcasts.cpp
…
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
AMDGPU/GlobalISel: Fix RegBankSelect for 1024-bit values
2019-10-02 01:02:14 +00:00
AMDGPUGISel.td
GlobalISel: Add target pre-isel instructions
2019-10-07 18:43:29 +00:00
AMDGPUHSAMetadataStreamer.cpp
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
AMDGPUHSAMetadataStreamer.h
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
AMDGPUInline.cpp
[AMDGPU] Tune inlining parameters for AMDGPU target
2019-07-17 16:51:29 +00:00
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
…
AMDGPUInstrInfo.td
AMDGPU/GlobalISel: Select cvt pk intrinsics
2019-09-10 17:17:05 +00:00
AMDGPUInstructions.td
AMDGPU/GlobalISel: Select local atomic cmpxchg
2019-08-01 03:41:41 +00:00
AMDGPUInstructionSelector.cpp
AMDGPU/GlobalISel: Handle more G_INSERT cases
2019-10-07 19:16:26 +00:00
AMDGPUInstructionSelector.h
AMDGPU/GlobalISel: Select s1 src G_SITOFP/G_UITOFP
2019-10-01 02:23:20 +00:00
AMDGPUISelDAGToDAG.cpp
AMDGPU: Fix redundant setting of m0 for atomic load/store
2019-10-14 18:30:31 +00:00
AMDGPUISelLowering.cpp
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
AMDGPUISelLowering.h
AMDGPU: Move SelectFlatOffset back into AMDGPUISelDAGToDAG
2019-10-11 01:28:27 +00:00
AMDGPULegalizerInfo.cpp
GlobalISel: Implement fewerElementsVector for G_BUILD_VECTOR
2019-10-09 22:44:43 +00:00
AMDGPULegalizerInfo.h
AMDGPU/GlobalISel: Legalize G_GLOBAL_VALUE
2019-10-01 01:06:43 +00:00
AMDGPULibCalls.cpp
[AMDGPU] Use math constants defined in MathExtras (NFC)
2019-10-09 20:00:43 +00:00
AMDGPULibFunc.cpp
[AMDGPU] Downgrade from StringLiteral to const char* in an attempt to make GCC 5 happy
2019-08-25 12:47:31 +00:00
AMDGPULibFunc.h
…
AMDGPULowerIntrinsics.cpp
…
AMDGPULowerKernelArguments.cpp
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
AMDGPULowerKernelAttributes.cpp
…
AMDGPUMachineCFGStructurizer.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
AMDGPUMachineFunction.cpp
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
AMDGPUMachineFunction.h
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
AMDGPUMachineModuleInfo.cpp
…
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
[AMDGPU] link dpp pseudos and real instructions on gfx10
2019-10-11 22:03:36 +00:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
Fix parameter name comments using clang-tidy. NFC.
2019-07-16 04:46:31 +00:00
AMDGPUPerfHintAnalysis.cpp
AMDGPU: Fix assert in clang test
2019-07-05 21:09:53 +00:00
AMDGPUPerfHintAnalysis.h
AMDGPU: Make AMDGPUPerfHintAnalysis an SCC pass
2019-07-05 20:26:13 +00:00
AMDGPUPrintfRuntimeBinding.cpp
[AMDGPU] Make printf lowering faster when there are no printfs
2019-10-02 08:44:15 +00:00
AMDGPUPromoteAlloca.cpp
[Alignment][NFC] Remove dependency on GlobalObject::setAlignment(unsigned)
2019-10-15 11:24:36 +00:00
AMDGPUPropagateAttributes.cpp
AMDGPU: Move DEBUG_TYPE definition below includes
2019-07-08 18:48:39 +00:00
AMDGPUPTNote.h
…
AMDGPURegisterBankInfo.cpp
AMDGPU/GlobalISel: Fix crash on wide constant load with VGPR pointer
2019-10-09 22:44:49 +00:00
AMDGPURegisterBankInfo.h
AMDGPU/GlobalISel: Split 64-bit vector extracts during RegBankSelect
2019-10-03 17:55:27 +00:00
AMDGPURegisterBanks.td
AMDGPU/GlobalISel: Increase max legal size to 1024
2019-10-01 16:35:06 +00:00
AMDGPURegisterInfo.cpp
AMDGPU/GlobalISel: Handle more G_INSERT cases
2019-10-07 19:16:26 +00:00
AMDGPURegisterInfo.h
AMDGPU/GlobalISel: Handle more G_INSERT cases
2019-10-07 19:16:26 +00:00
AMDGPURegisterInfo.td
[AMDGPU] gfx908 register file changes
2019-07-09 19:41:51 +00:00
AMDGPURewriteOutArguments.cpp
…
AMDGPUSearchableTables.td
AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}
2019-08-05 09:36:06 +00:00
AMDGPUSubtarget.cpp
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
AMDGPUSubtarget.h
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
AMDGPUTargetMachine.cpp
Revert "[AMDGPU] Run unreachable-mbb-elimination after isel to clean up PHIs."
2019-10-10 13:34:31 +00:00
AMDGPUTargetMachine.h
…
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
AMDGPU: Add intrinsics for address space identification
2019-09-05 02:20:39 +00:00
AMDGPUTargetTransformInfo.h
[System Model] [TTI] Define AMDGPUTTIImpl::getST and AMDGPUTTIImpl::getTLI
2019-10-09 20:48:54 +00:00
AMDGPUUnifyDivergentExitNodes.cpp
Update phis in AMDGPUUnifyDivergentExitNodes
2019-06-25 18:55:16 +00:00
AMDGPUUnifyMetadata.cpp
…
AMDILCFGStructurizer.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
AMDKernelCodeT.h
[AMDGPU] gfx1010 wave32 metadata
2019-06-17 16:48:56 +00:00
BUFInstructions.td
[AMDGPU][MC][GFX6][GFX7][GFX10] Added instructions buffer_atomic_[fcmpswap/fmin/fmax]*
2019-10-11 14:44:51 +00:00
CaymanInstructions.td
…
CMakeLists.txt
[AMDGPU] Printf runtime binding pass
2019-08-12 17:12:29 +00:00
DSInstructions.td
[AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_[read/write]_addtid_b32
2019-10-11 14:53:26 +00:00
EvergreenInstructions.td
AMDGPU: Start redefining atomic PatFrags
2019-08-01 03:25:52 +00:00
FLATInstructions.td
[AMDGPU][MC][GFX10] Corrected definition of FLAT GLOBAL/SCRATCH instructions
2019-10-04 12:10:22 +00:00
GCNDPPCombine.cpp
[AMDGPU] Support mov dpp with 64 bit operands
2019-10-15 16:41:15 +00:00
GCNHazardRecognizer.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
GCNHazardRecognizer.h
[AMDGPU] gfx908 hazard recognizer
2019-07-11 21:30:34 +00:00
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
GCNIterativeScheduler.h
…
GCNMinRegStrategy.cpp
…
GCNNSAReassign.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
GCNProcessors.td
[AMDGPU] gfx908 target
2019-07-09 18:10:06 +00:00
GCNRegBankReassign.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
GCNRegPressure.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
GCNRegPressure.h
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
2019-08-01 23:27:28 +00:00
GCNSchedStrategy.cpp
[AMDGPU] Add VerifyScheduling support.
2019-10-01 15:45:47 +00:00
GCNSchedStrategy.h
AMDGPU: Avoid constructing new std::vector in initCandidate
2019-09-05 22:44:06 +00:00
LLVMBuild.txt
[AMDGPU] Move InstPrinter files to MCTargetDesc. NFC
2019-05-11 00:03:35 +00:00
MIMGInstructions.td
[AMDGPU] Use PredicateControl in MIMGBaseOpcode. NFC.
2019-08-12 22:32:21 +00:00
R600.td
…
R600AsmPrinter.cpp
[Alignment][NFC] Remove unneeded llvm:: scoping on Align types
2019-09-27 12:54:21 +00:00
R600AsmPrinter.h
…
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600FrameLowering.cpp
…
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600InstrInfo.h
…
R600Instructions.td
AMDGPU: Redefine load PatFrags
2019-07-16 17:38:50 +00:00
R600ISelLowering.cpp
[AMDGPU] Use math constants defined in MathExtras (NFC)
2019-10-09 20:00:43 +00:00
R600ISelLowering.h
[TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR42123)
2019-06-12 17:14:03 +00:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600MachineScheduler.h
…
R600OpenCLImageTypeLoweringPass.cpp
…
R600OptimizeVectorRegisters.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600Packetizer.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600Processors.td
…
R600RegisterInfo.cpp
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
2019-08-01 23:27:28 +00:00
R600RegisterInfo.h
CodeGen: Introduce a class for registers
2019-06-24 15:50:29 +00:00
R600RegisterInfo.td
…
R600Schedule.td
…
R700Instructions.td
…
SIAddIMGInit.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
SIAnnotateControlFlow.cpp
[AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32
2019-06-13 23:47:36 +00:00
SIDefines.h
[AMDGPU] Added MI bit IsDOT
2019-09-17 17:56:13 +00:00
SIFixSGPRCopies.cpp
AMDGPU: Fix infinite searches in SIFixSGPRCopies
2019-10-15 19:59:45 +00:00
SIFixupVectorISel.cpp
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
2019-08-01 23:27:28 +00:00
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
AMDGPU: Don't fold copies to physregs
2019-10-09 22:51:42 +00:00
SIFormMemoryClauses.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
SIFrameLowering.cpp
[AArch64] Static (de)allocation of SVE stack objects.
2019-10-03 11:33:50 +00:00
SIFrameLowering.h
[AMDGPU] Add the adjusted FP as a livein register.
2019-07-16 15:57:12 +00:00
SIInsertSkips.cpp
[AMDGPU] gfx10 conditional registers handling
2019-06-16 17:13:09 +00:00
SIInsertWaitcnts.cpp
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
SIInstrFormats.td
[AMDGPU] Added MI bit IsDOT
2019-09-17 17:56:13 +00:00
SIInstrInfo.cpp
AMDGPU: Fix infinite searches in SIFixSGPRCopies
2019-10-15 19:59:45 +00:00
SIInstrInfo.h
[AMDGPU] Support mov dpp with 64 bit operands
2019-10-15 16:41:15 +00:00
SIInstrInfo.td
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
SIInstructions.td
[AMDGPU] Support mov dpp with 64 bit operands
2019-10-15 16:41:15 +00:00
SIISelLowering.cpp
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
SIISelLowering.h
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
SILoadStoreOptimizer.cpp
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
SILowerControlFlow.cpp
[AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed
2019-09-17 09:08:58 +00:00
SILowerI1Copies.cpp
[Dominators][AMDGPU] Don't use virtual exit node in findNearestCommonDominator. Cleanup MachinePostDominators.
2019-09-25 14:04:36 +00:00
SILowerSGPRSpills.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
SIMachineFunctionInfo.cpp
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
SIMachineFunctionInfo.h
AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization
2019-08-27 18:18:38 +00:00
SIMachineScheduler.cpp
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
SIMachineScheduler.h
…
SIMemoryLegalizer.cpp
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
SIModeRegister.cpp
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
SIOptimizeExecMasking.cpp
Revert "AMDGPU: Fix iterator error when lowering SI_END_CF"
2019-08-20 17:45:25 +00:00
SIOptimizeExecMaskingPreRA.cpp
AMDGPU: Propagate undef flag during pre-RA exec mask optimizations
2019-10-08 12:46:32 +00:00
SIPeepholeSDWA.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
SIPreAllocateWWMRegs.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
SIProgramInfo.h
[AMDGPU] separate accounting for agprs
2019-10-02 00:26:58 +00:00
SIRegisterInfo.cpp
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
SIRegisterInfo.h
[AMDGPU] w/a for gfx908 mfma SrcC literal HW bug
2019-08-23 22:09:58 +00:00
SIRegisterInfo.td
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
SISchedule.td
[AMDGPU] gfx908 scheduling
2019-07-11 21:25:00 +00:00
SIShrinkInstructions.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
SIWholeQuadMode.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
SMInstructions.td
AMDGPU/GlobalISel: Select SMRD loads for more types
2019-09-16 00:54:07 +00:00
SOPInstructions.td
AMDGPU/GlobalISel: Allow selection of scalar min/max
2019-09-21 02:37:33 +00:00
VIInstrFormats.td
…
VIInstructions.td
…
VOP1Instructions.td
[AMDGPU] link dpp pseudos and real instructions on gfx10
2019-10-11 22:03:36 +00:00
VOP2Instructions.td
[AMDGPU] link dpp pseudos and real instructions on gfx10
2019-10-11 22:03:36 +00:00
VOP3Instructions.td
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
VOP3PInstructions.td
[AMDGPU] Added MI bit IsDOT
2019-09-17 17:56:13 +00:00
VOPCInstructions.td
AMDGPU/GlobalISel: Select llvm.amdgcn.class
2019-09-09 18:29:45 +00:00
VOPInstructions.td
[AMDGPU] copy OtherPredicates from pseudo to VOP3_Real
2019-09-26 21:06:17 +00:00