9802268ad3
In loop-vectorize, interleave count and vector factor depend on target register number. Currently, it does not estimate different register pressure for different register class separately(especially for scalar type, float type should not be on the same position with int type), so it's not accurate. Specifically, it causes too many times interleaving/unrolling, result in too many register spills in loop body and hurting performance. So we need classify the register classes in IR level, and importantly these are abstract register classes, and are not the target register class of backend provided in td file. It's used to establish the mapping between the types of IR values and the number of simultaneous live ranges to which we'd like to limit for some set of those types. For example, POWER target, register num is special when VSX is enabled. When VSX is enabled, the number of int scalar register is 32(GPR), float is 64(VSR), but for int and float vector register both are 64(VSR). So there should be 2 kinds of register class when vsx is enabled, and 3 kinds of register class when VSX is NOT enabled. It runs on POWER target, it makes big(+~30%) performance improvement in one specific bmk(503.bwaves_r) of spec2017 and no other obvious degressions. Differential revision: https://reviews.llvm.org/D67148 llvm-svn: 374634
84 lines
2.8 KiB
C++
84 lines
2.8 KiB
C++
//===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the WebAssembly-specific TargetTransformInfo
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/// implementation.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyTargetTransformInfo.h"
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#include "llvm/CodeGen/CostTable.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasmtti"
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TargetTransformInfo::PopcntSupportKind
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WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return TargetTransformInfo::PSK_FastHardware;
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}
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unsigned WebAssemblyTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
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unsigned Result = BaseT::getNumberOfRegisters(ClassID);
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// For SIMD, use at least 16 registers, as a rough guess.
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bool Vector = (ClassID == 1);
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if (Vector)
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Result = std::max(Result, 16u);
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return Result;
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}
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unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const {
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if (Vector && getST()->hasSIMD128())
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return 128;
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return 64;
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}
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unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
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TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
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unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
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Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
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if (auto *VTy = dyn_cast<VectorType>(Ty)) {
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switch (Opcode) {
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case Instruction::LShr:
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case Instruction::AShr:
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case Instruction::Shl:
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// SIMD128's shifts currently only accept a scalar shift count. For each
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// element, we'll need to extract, op, insert. The following is a rough
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// approxmation.
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if (Opd2Info != TTI::OK_UniformValue &&
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Opd2Info != TTI::OK_UniformConstantValue)
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Cost = VTy->getNumElements() *
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(TargetTransformInfo::TCC_Basic +
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getArithmeticInstrCost(Opcode, VTy->getElementType()) +
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TargetTransformInfo::TCC_Basic);
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break;
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}
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}
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return Cost;
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}
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unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) {
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unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
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// SIMD128's insert/extract currently only take constant indices.
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if (Index == -1u)
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return Cost + 25 * TargetTransformInfo::TCC_Expensive;
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return Cost;
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}
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