c4d256a590
Detailed description:
After https://reviews.llvm.org/D59990 submit several issues were discovered.
Changes in common code were preserved but AMDGPU specific part was reverted to keep the backend working correctly.
Discovered issues were addressed in the following commits:
https://reviews.llvm.org/D67662
https://reviews.llvm.org/D67101
https://reviews.llvm.org/D63953
https://reviews.llvm.org/D63731
This change brings back AMDGPU specific changes.
Reviewed by: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D68635
llvm-svn: 374767
337 lines
12 KiB
LLVM
337 lines
12 KiB
LLVM
; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -verify-machineinstrs -disable-block-placement < %s | FileCheck -check-prefix=GCN %s
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; Uses llvm.amdgcn.break
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; OPT-LABEL: @break_loop(
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; OPT: bb1:
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; OPT: icmp slt i32
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT: load volatile
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; OPT: icmp slt i32
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; OPT: xor i1 %cmp1
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; OPT: br label %Flow
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; OPT: Flow:
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; OPT: call i64 @llvm.amdgcn.if.break.i64.i64(
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; OPT: call i1 @llvm.amdgcn.loop.i64(i64
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; OPT: br i1 %{{[0-9]+}}, label %bb9, label %bb1
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; OPT: bb9:
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; OPT: call void @llvm.amdgcn.end.cf.i64(i64
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; GCN-LABEL: {{^}}break_loop:
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; GCN: s_mov_b64 [[ACCUM_MASK:s\[[0-9]+:[0-9]+\]]], 0{{$}}
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; GCN: [[LOOP_ENTRY:BB[0-9]+_[0-9]+]]: ; %bb1
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; GCN: s_add_i32 s4, s4, 1
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; GCN: s_or_b64 [[INNER_MASK:s\[[0-9]+:[0-9]+\]]], [[INNER_MASK]], exec
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; GCN: s_cmp_gt_i32 s4, -1
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; GCN: s_cbranch_scc1 [[FLOW:BB[0-9]+_[0-9]+]]
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; GCN: ; %bb4
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; GCN: buffer_load_dword
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; GCN: v_cmp_ge_i32_e32 vcc
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; GCN: s_andn2_b64 [[INNER_MASK]], [[INNER_MASK]], exec
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; GCN: s_and_b64 [[BROKEN_MASK:s\[[0-9]+:[0-9]+\]]], vcc, exec
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; GCN: s_or_b64 [[INNER_MASK]], [[INNER_MASK]], [[BROKEN_MASK]]
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; GCN: [[FLOW]]: ; %Flow
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; GCN: ; in Loop: Header=BB0_1 Depth=1
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; GCN: s_and_b64 [[BROKEN_MASK]], exec, [[INNER_MASK]]
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; GCN: s_or_b64 [[BROKEN_MASK]], [[BROKEN_MASK]], [[ACCUM_MASK]]
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; GCN: s_mov_b64 [[ACCUM_MASK]], [[BROKEN_MASK]]
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; GCN: s_andn2_b64 exec, exec, [[BROKEN_MASK]]
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; GCN-NEXT: s_cbranch_execnz [[LOOP_ENTRY]]
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; GCN: ; %bb.4: ; %bb9
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1:
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%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %bb9
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bb4:
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp slt i32 %tmp, %load
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br i1 %cmp1, label %bb1, label %bb9
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bb9:
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ret void
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}
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; OPT-LABEL: @undef_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %0, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NEXT: %lsr.iv.next = add i32 %lsr.iv, 1
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; OPT-NEXT: %cmp0 = icmp slt i32 %lsr.iv.next, 0
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %0 = call i64 @llvm.amdgcn.if.break.i64.i64(i1 %tmp3, i64 %phi.broken)
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; OPT-NEXT: %1 = call i1 @llvm.amdgcn.loop.i64(i64 %0)
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; OPT-NEXT: br i1 %1, label %bb9, label %bb1
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; OPT: bb9: ; preds = %Flow
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %0)
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; OPT-NEXT: store volatile i32 7
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; OPT-NEXT: ret void
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define amdgpu_kernel void @undef_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ undef, %bb1 ]
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br i1 %tmp3, label %bb9, label %bb1
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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; FIXME: ConstantExpr compare of address to null folds away
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@lds = addrspace(3) global i32 undef
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; OPT-LABEL: @constexpr_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %0, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NEXT: %lsr.iv.next = add i32 %lsr.iv, 1
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; OPT-NEXT: %cmp0 = icmp slt i32 %lsr.iv.next, 0
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ icmp ne (i32 addrspace(3)* inttoptr (i32 4 to i32 addrspace(3)*), i32 addrspace(3)* @lds), %bb1 ]
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; OPT-NEXT: %0 = call i64 @llvm.amdgcn.if.break.i64.i64(i1 %tmp3, i64 %phi.broken)
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; OPT-NEXT: %1 = call i1 @llvm.amdgcn.loop.i64(i64 %0)
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; OPT-NEXT: br i1 %1, label %bb9, label %bb1
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; OPT: bb9: ; preds = %Flow
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %0)
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; OPT-NEXT: store volatile i32 7
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; OPT-NEXT: ret void
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define amdgpu_kernel void @constexpr_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ icmp ne (i32 addrspace(3)* inttoptr (i32 4 to i32 addrspace(3)*), i32 addrspace(3)* @lds), %bb1 ]
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br i1 %tmp3, label %bb9, label %bb1
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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; OPT-LABEL: @true_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %0, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NEXT: %lsr.iv.next = add i32 %lsr.iv, 1
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; OPT-NEXT: %cmp0 = icmp slt i32 %lsr.iv.next, 0
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ]
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; OPT-NEXT: %0 = call i64 @llvm.amdgcn.if.break.i64.i64(i1 %tmp3, i64 %phi.broken)
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; OPT-NEXT: %1 = call i1 @llvm.amdgcn.loop.i64(i64 %0)
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; OPT-NEXT: br i1 %1, label %bb9, label %bb1
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; OPT: bb9: ; preds = %Flow
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %0)
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; OPT-NEXT: store volatile i32 7
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; OPT-NEXT: ret void
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define amdgpu_kernel void @true_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ]
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br i1 %tmp3, label %bb9, label %bb1
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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; OPT-LABEL: @false_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %0, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NOT: call
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; OPT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ false, %bb1 ]
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; OPT-NEXT: %0 = call i64 @llvm.amdgcn.if.break.i64.i64(i1 %tmp3, i64 %phi.broken)
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; OPT-NEXT: %1 = call i1 @llvm.amdgcn.loop.i64(i64 %0)
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; OPT-NEXT: br i1 %1, label %bb9, label %bb1
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; OPT: bb9: ; preds = %Flow
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %0)
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; OPT-NEXT: store volatile i32 7
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; OPT-NEXT: ret void
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define amdgpu_kernel void @false_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ false, %bb1 ]
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br i1 %tmp3, label %bb9, label %bb1
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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; Swap order of branches in flow block so that the true phi is
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; continue.
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; OPT-LABEL: @invert_true_phi_cond_break_loop(
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; OPT: bb1:
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; OPT-NEXT: %phi.broken = phi i64 [ %1, %Flow ], [ 0, %bb ]
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; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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; OPT-NEXT: %lsr.iv.next = add i32 %lsr.iv, 1
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; OPT-NEXT: %cmp0 = icmp slt i32 %lsr.iv.next, 0
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; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow
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; OPT: bb4:
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; OPT-NEXT: %load = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: %cmp1 = icmp sge i32 %tmp, %load
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; OPT-NEXT: br label %Flow
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; OPT: Flow:
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; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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; OPT-NEXT: %tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ]
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; OPT-NEXT: %0 = xor i1 %tmp3, true
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; OPT-NEXT: %1 = call i64 @llvm.amdgcn.if.break.i64.i64(i1 %0, i64 %phi.broken)
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; OPT-NEXT: %2 = call i1 @llvm.amdgcn.loop.i64(i64 %1)
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; OPT-NEXT: br i1 %2, label %bb9, label %bb1
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; OPT: bb9:
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %1)
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; OPT-NEXT: store volatile i32 7, i32 addrspace(3)* undef
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; OPT-NEXT: ret void
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define amdgpu_kernel void @invert_true_phi_cond_break_loop(i32 %arg) #0 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1: ; preds = %Flow, %bb
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%lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %Flow
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bb4: ; preds = %bb1
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp sge i32 %tmp, %load
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br label %Flow
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Flow: ; preds = %bb4, %bb1
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%tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
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%tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ]
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br i1 %tmp3, label %bb1, label %bb9
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bb9: ; preds = %Flow
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store volatile i32 7, i32 addrspace(3)* undef
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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