24194090e1
This is an alternative of D157485 and a pre-feature to support AVX10. AVX10 Architecture Specification: https://cdrdv2.intel.com/v1/dl/getContent/784267 AVX10 Technical Paper: https://cdrdv2.intel.com/v1/dl/getContent/784343 RFC: https://discourse.llvm.org/t/rfc-design-for-avx10-feature-support/72661 Based on the feedbacks from LLVM and GCC community, we have agreed to start from supporting `-m[no-]evex512` on existing AVX512 features. The option `-mno-evex512` can be used with `-mavx512xxx` to build binaries that can run on both legacy AVX512 targets and AVX10-256. There're still arguments about what's the expected behavior when this option as well as `-mavx512xxx` used together with `-mavx10.1-256`. We decided to defer the support of `-mavx10.1` after we made consensus. Or furthermore, we start from supporting AVX10.2 and not providing any AVX10.1 options. Reviewed By: RKSimon, skan Differential Revision: https://reviews.llvm.org/D159250
29 lines
1.6 KiB
C
29 lines
1.6 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -emit-llvm %s -o - -ffreestanding -target-feature +avx512vl -triple=x86_64-pc-win32 | FileCheck %s --check-prefix=Win
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// RUN: %clang_cc1 -emit-llvm %s -o - -ffreestanding -target-feature +avx512vl -triple=x86_64-pc-linux-gnu | FileCheck %s --check-prefix=Lin
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#include <immintrin.h>
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typedef struct {
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__m512d r1[4];
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__m512 r2[4];
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} __sVector;
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__sVector A;
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__sVector __regcall foo(int a) {
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return A;
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}
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double __regcall bar(__sVector a) {
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return a.r1[0][4];
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}
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// FIXME: Do we need to change for Windows?
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// Win: define dso_local x86_regcallcc void @__regcall3__foo(ptr noalias sret(%struct.__sVector) align 64 %agg.result, i32 noundef %a) #0
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// Win: define dso_local x86_regcallcc double @__regcall3__bar(ptr noundef %a) #0
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// Win: attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+avx,+avx2,+avx512f,+avx512vl,+crc32,+cx8,+evex512,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" }
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// Lin: define dso_local x86_regcallcc %struct.__sVector @__regcall3__foo(i32 noundef %a) #0
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// Lin: define dso_local x86_regcallcc double @__regcall3__bar([4 x <8 x double>] %a.coerce0, [4 x <16 x float>] %a.coerce1) #0
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// Lin: attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="512" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+avx,+avx2,+avx512f,+avx512vl,+crc32,+cx8,+evex512,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" }
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