0c6f2f629c
The default version of OpenMP is updated from 5.0 to 5.1 which means if -fopenmp is specified but -fopenmp-version is not specified with clang, the default version of OpenMP is taken to be 5.1. After modifying the Frontend for that, various LIT tests were updated. This patch contains all such changes. At a high level, these are the patterns of changes observed in LIT tests - # RUN lines which mentioned `-fopenmp-version=50` need to kept only if the IR for version 5.0 and 5.1 are different. Otherwise only one RUN line with no version info(i.e. default version) needs to be there. # Test cases of this sort already had the RUN lines with respect to the older default version 5.0 and the version 5.1. Only swapping the version specification flag `-fopenmp-version` from newer version RUN line to older version RUN line is required. # Diagnostics: Remove the 5.0 version specific RUN lines if there was no difference in the Diagnostics messages with respect to the default 5.1. # Diagnostics: In case there was any difference in diagnostics messages between 5.0 and 5.1, mention version specific messages in tests. # If the test contained version specific ifdef's e.g. "#ifdef OMP5" but there were no RUN lines for any other version than 5.X, then bring the code guarded by ifdef's outside and remove the ifdef's. # Some tests had RUN lines for both 5.0 and 5.1 versions, but it is found that the IR for 5.0 is not different from the 5.1, therefore such RUN lines are redundant. So, such duplicated lines are removed. # To generate CHECK lines automatically, use the script llvm/utils/update_cc_test_checks.py Reviewed By: saiislam, ABataev Differential Revision: https://reviews.llvm.org/D129635 (cherry picked from commit 9dd2999907dc791136a75238a6000f69bf67cf4e)
61969 lines
3.3 MiB
61969 lines
3.3 MiB
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs
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// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
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// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
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// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
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// RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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void foo(void) {
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char cx, ce, cd;
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unsigned char ucx, uce, ucd;
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short sx, se, sd;
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unsigned short usx, use, usd;
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int ix, ie, id;
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unsigned int uix, uie, uid;
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long lx, le, ld;
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unsigned long ulx, ule, uld;
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long long llx, lle, lld;
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unsigned long long ullx, ulle, ulld;
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float fx, fe, fd;
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double dx, de, dd;
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#pragma omp atomic compare
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cx = cx > ce ? ce : cx;
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#pragma omp atomic compare
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cx = cx < ce ? ce : cx;
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#pragma omp atomic compare
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cx = ce > cx ? ce : cx;
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#pragma omp atomic compare
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cx = ce < cx ? ce : cx;
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#pragma omp atomic compare
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if (cx > ce)
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cx = ce;
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#pragma omp atomic compare
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if (cx < ce)
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cx = ce;
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#pragma omp atomic compare
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if (ce > cx)
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cx = ce;
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#pragma omp atomic compare
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if (ce < cx)
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cx = ce;
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#pragma omp atomic compare
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cx = cx == ce ? cd : cx;
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#pragma omp atomic compare
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cx = ce == cx ? cd : cx;
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#pragma omp atomic compare
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if (cx == ce)
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cx = cd;
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#pragma omp atomic compare
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if (ce == cx)
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cx = cd;
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#pragma omp atomic compare
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ucx = ucx > uce ? uce : ucx;
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#pragma omp atomic compare
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ucx = ucx < uce ? uce : ucx;
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#pragma omp atomic compare
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ucx = uce > ucx ? uce : ucx;
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#pragma omp atomic compare
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ucx = uce < ucx ? uce : ucx;
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#pragma omp atomic compare
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if (ucx > uce)
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ucx = uce;
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#pragma omp atomic compare
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if (ucx < uce)
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ucx = uce;
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#pragma omp atomic compare
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if (uce > ucx)
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ucx = uce;
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#pragma omp atomic compare
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if (uce < ucx)
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ucx = uce;
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#pragma omp atomic compare
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ucx = ucx == uce ? ucd : ucx;
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#pragma omp atomic compare
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ucx = uce == ucx ? ucd : ucx;
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#pragma omp atomic compare
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if (ucx == uce)
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ucx = ucd;
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#pragma omp atomic compare
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if (uce == ucx)
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ucx = ucd;
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#pragma omp atomic compare acq_rel
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cx = cx > ce ? ce : cx;
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#pragma omp atomic compare acq_rel
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cx = cx < ce ? ce : cx;
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#pragma omp atomic compare acq_rel
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cx = ce > cx ? ce : cx;
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#pragma omp atomic compare acq_rel
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cx = ce < cx ? ce : cx;
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#pragma omp atomic compare acq_rel
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if (cx > ce)
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cx = ce;
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#pragma omp atomic compare acq_rel
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if (cx < ce)
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cx = ce;
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#pragma omp atomic compare acq_rel
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if (ce > cx)
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cx = ce;
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#pragma omp atomic compare acq_rel
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if (ce < cx)
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cx = ce;
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#pragma omp atomic compare acq_rel
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cx = cx == ce ? cd : cx;
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#pragma omp atomic compare acq_rel
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cx = ce == cx ? cd : cx;
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#pragma omp atomic compare acq_rel
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if (cx == ce)
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cx = cd;
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#pragma omp atomic compare acq_rel
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if (ce == cx)
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cx = cd;
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#pragma omp atomic compare acq_rel
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ucx = ucx > uce ? uce : ucx;
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#pragma omp atomic compare acq_rel
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ucx = ucx < uce ? uce : ucx;
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#pragma omp atomic compare acq_rel
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ucx = uce > ucx ? uce : ucx;
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#pragma omp atomic compare acq_rel
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ucx = uce < ucx ? uce : ucx;
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#pragma omp atomic compare acq_rel
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if (ucx > uce)
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ucx = uce;
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#pragma omp atomic compare acq_rel
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if (ucx < uce)
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ucx = uce;
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#pragma omp atomic compare acq_rel
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if (uce > ucx)
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ucx = uce;
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#pragma omp atomic compare acq_rel
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if (uce < ucx)
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ucx = uce;
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#pragma omp atomic compare acq_rel
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ucx = ucx == uce ? ucd : ucx;
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#pragma omp atomic compare acq_rel
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ucx = uce == ucx ? ucd : ucx;
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#pragma omp atomic compare acq_rel
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if (ucx == uce)
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ucx = ucd;
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#pragma omp atomic compare acq_rel
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if (uce == ucx)
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ucx = ucd;
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#pragma omp atomic compare acquire
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cx = cx > ce ? ce : cx;
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#pragma omp atomic compare acquire
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cx = cx < ce ? ce : cx;
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#pragma omp atomic compare acquire
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cx = ce > cx ? ce : cx;
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#pragma omp atomic compare acquire
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cx = ce < cx ? ce : cx;
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#pragma omp atomic compare acquire
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if (cx > ce)
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cx = ce;
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#pragma omp atomic compare acquire
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if (cx < ce)
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cx = ce;
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#pragma omp atomic compare acquire
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if (ce > cx)
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cx = ce;
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#pragma omp atomic compare acquire
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if (ce < cx)
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cx = ce;
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#pragma omp atomic compare acquire
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cx = cx == ce ? cd : cx;
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#pragma omp atomic compare acquire
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cx = ce == cx ? cd : cx;
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#pragma omp atomic compare acquire
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if (cx == ce)
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cx = cd;
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#pragma omp atomic compare acquire
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if (ce == cx)
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cx = cd;
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#pragma omp atomic compare acquire
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ucx = ucx > uce ? uce : ucx;
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#pragma omp atomic compare acquire
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ucx = ucx < uce ? uce : ucx;
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#pragma omp atomic compare acquire
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ucx = uce > ucx ? uce : ucx;
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#pragma omp atomic compare acquire
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ucx = uce < ucx ? uce : ucx;
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#pragma omp atomic compare acquire
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if (ucx > uce)
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ucx = uce;
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#pragma omp atomic compare acquire
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if (ucx < uce)
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ucx = uce;
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#pragma omp atomic compare acquire
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if (uce > ucx)
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ucx = uce;
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#pragma omp atomic compare acquire
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if (uce < ucx)
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ucx = uce;
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#pragma omp atomic compare acquire
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ucx = ucx == uce ? ucd : ucx;
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#pragma omp atomic compare acquire
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ucx = uce == ucx ? ucd : ucx;
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#pragma omp atomic compare acquire
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if (ucx == uce)
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ucx = ucd;
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#pragma omp atomic compare acquire
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if (uce == ucx)
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ucx = ucd;
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#pragma omp atomic compare relaxed
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cx = cx > ce ? ce : cx;
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#pragma omp atomic compare relaxed
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cx = cx < ce ? ce : cx;
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#pragma omp atomic compare relaxed
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cx = ce > cx ? ce : cx;
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#pragma omp atomic compare relaxed
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cx = ce < cx ? ce : cx;
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#pragma omp atomic compare relaxed
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if (cx > ce)
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cx = ce;
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#pragma omp atomic compare relaxed
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if (cx < ce)
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cx = ce;
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#pragma omp atomic compare relaxed
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if (ce > cx)
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cx = ce;
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#pragma omp atomic compare relaxed
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if (ce < cx)
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cx = ce;
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#pragma omp atomic compare relaxed
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cx = cx == ce ? cd : cx;
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#pragma omp atomic compare relaxed
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cx = ce == cx ? cd : cx;
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#pragma omp atomic compare relaxed
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if (cx == ce)
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cx = cd;
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#pragma omp atomic compare relaxed
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if (ce == cx)
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cx = cd;
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#pragma omp atomic compare relaxed
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ucx = ucx > uce ? uce : ucx;
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#pragma omp atomic compare relaxed
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ucx = ucx < uce ? uce : ucx;
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#pragma omp atomic compare relaxed
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ucx = uce > ucx ? uce : ucx;
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#pragma omp atomic compare relaxed
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ucx = uce < ucx ? uce : ucx;
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#pragma omp atomic compare relaxed
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if (ucx > uce)
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ucx = uce;
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#pragma omp atomic compare relaxed
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if (ucx < uce)
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ucx = uce;
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#pragma omp atomic compare relaxed
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if (uce > ucx)
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ucx = uce;
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#pragma omp atomic compare relaxed
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if (uce < ucx)
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ucx = uce;
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#pragma omp atomic compare relaxed
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ucx = ucx == uce ? ucd : ucx;
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#pragma omp atomic compare relaxed
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ucx = uce == ucx ? ucd : ucx;
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#pragma omp atomic compare relaxed
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if (ucx == uce)
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ucx = ucd;
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#pragma omp atomic compare relaxed
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if (uce == ucx)
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ucx = ucd;
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#pragma omp atomic compare release
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cx = cx > ce ? ce : cx;
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#pragma omp atomic compare release
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cx = cx < ce ? ce : cx;
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#pragma omp atomic compare release
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cx = ce > cx ? ce : cx;
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#pragma omp atomic compare release
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cx = ce < cx ? ce : cx;
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#pragma omp atomic compare release
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if (cx > ce)
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cx = ce;
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#pragma omp atomic compare release
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if (cx < ce)
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cx = ce;
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#pragma omp atomic compare release
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if (ce > cx)
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cx = ce;
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#pragma omp atomic compare release
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if (ce < cx)
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cx = ce;
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#pragma omp atomic compare release
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cx = cx == ce ? cd : cx;
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#pragma omp atomic compare release
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cx = ce == cx ? cd : cx;
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#pragma omp atomic compare release
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if (cx == ce)
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cx = cd;
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#pragma omp atomic compare release
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if (ce == cx)
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cx = cd;
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#pragma omp atomic compare release
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ucx = ucx > uce ? uce : ucx;
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#pragma omp atomic compare release
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ucx = ucx < uce ? uce : ucx;
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#pragma omp atomic compare release
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ucx = uce > ucx ? uce : ucx;
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#pragma omp atomic compare release
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ucx = uce < ucx ? uce : ucx;
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#pragma omp atomic compare release
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if (ucx > uce)
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ucx = uce;
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#pragma omp atomic compare release
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if (ucx < uce)
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ucx = uce;
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#pragma omp atomic compare release
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if (uce > ucx)
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ucx = uce;
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#pragma omp atomic compare release
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if (uce < ucx)
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ucx = uce;
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#pragma omp atomic compare release
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ucx = ucx == uce ? ucd : ucx;
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#pragma omp atomic compare release
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ucx = uce == ucx ? ucd : ucx;
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#pragma omp atomic compare release
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if (ucx == uce)
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ucx = ucd;
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#pragma omp atomic compare release
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if (uce == ucx)
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ucx = ucd;
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#pragma omp atomic compare seq_cst
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cx = cx > ce ? ce : cx;
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#pragma omp atomic compare seq_cst
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cx = cx < ce ? ce : cx;
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#pragma omp atomic compare seq_cst
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cx = ce > cx ? ce : cx;
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#pragma omp atomic compare seq_cst
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cx = ce < cx ? ce : cx;
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#pragma omp atomic compare seq_cst
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if (cx > ce)
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cx = ce;
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#pragma omp atomic compare seq_cst
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if (cx < ce)
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cx = ce;
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#pragma omp atomic compare seq_cst
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if (ce > cx)
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cx = ce;
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#pragma omp atomic compare seq_cst
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if (ce < cx)
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cx = ce;
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#pragma omp atomic compare seq_cst
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cx = cx == ce ? cd : cx;
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#pragma omp atomic compare seq_cst
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cx = ce == cx ? cd : cx;
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#pragma omp atomic compare seq_cst
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if (cx == ce)
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cx = cd;
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#pragma omp atomic compare seq_cst
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if (ce == cx)
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cx = cd;
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#pragma omp atomic compare seq_cst
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ucx = ucx > uce ? uce : ucx;
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#pragma omp atomic compare seq_cst
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ucx = ucx < uce ? uce : ucx;
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#pragma omp atomic compare seq_cst
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ucx = uce > ucx ? uce : ucx;
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#pragma omp atomic compare seq_cst
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ucx = uce < ucx ? uce : ucx;
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#pragma omp atomic compare seq_cst
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if (ucx > uce)
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ucx = uce;
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#pragma omp atomic compare seq_cst
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if (ucx < uce)
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ucx = uce;
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#pragma omp atomic compare seq_cst
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if (uce > ucx)
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ucx = uce;
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#pragma omp atomic compare seq_cst
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if (uce < ucx)
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ucx = uce;
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#pragma omp atomic compare seq_cst
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ucx = ucx == uce ? ucd : ucx;
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#pragma omp atomic compare seq_cst
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ucx = uce == ucx ? ucd : ucx;
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#pragma omp atomic compare seq_cst
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if (ucx == uce)
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ucx = ucd;
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#pragma omp atomic compare seq_cst
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if (uce == ucx)
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ucx = ucd;
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#pragma omp atomic compare
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sx = sx > se ? se : sx;
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#pragma omp atomic compare
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sx = sx < se ? se : sx;
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#pragma omp atomic compare
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sx = se > sx ? se : sx;
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#pragma omp atomic compare
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sx = se < sx ? se : sx;
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#pragma omp atomic compare
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if (sx > se)
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sx = se;
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#pragma omp atomic compare
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if (sx < se)
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sx = se;
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#pragma omp atomic compare
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if (se > sx)
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sx = se;
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#pragma omp atomic compare
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if (se < sx)
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sx = se;
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#pragma omp atomic compare
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sx = sx == se ? sd : sx;
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#pragma omp atomic compare
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sx = se == sx ? sd : sx;
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#pragma omp atomic compare
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if (sx == se)
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sx = sd;
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#pragma omp atomic compare
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if (se == sx)
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sx = sd;
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#pragma omp atomic compare
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usx = usx > use ? use : usx;
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#pragma omp atomic compare
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usx = usx < use ? use : usx;
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#pragma omp atomic compare
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usx = use > usx ? use : usx;
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#pragma omp atomic compare
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usx = use < usx ? use : usx;
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#pragma omp atomic compare
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if (usx > use)
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usx = use;
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#pragma omp atomic compare
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if (usx < use)
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usx = use;
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#pragma omp atomic compare
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if (use > usx)
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usx = use;
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#pragma omp atomic compare
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if (use < usx)
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usx = use;
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|
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#pragma omp atomic compare
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usx = usx == use ? usd : usx;
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#pragma omp atomic compare
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usx = use == usx ? usd : usx;
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#pragma omp atomic compare
|
|
if (usx == use)
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usx = usd;
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#pragma omp atomic compare
|
|
if (use == usx)
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usx = usd;
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|
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#pragma omp atomic compare acq_rel
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sx = sx > se ? se : sx;
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#pragma omp atomic compare acq_rel
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sx = sx < se ? se : sx;
|
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#pragma omp atomic compare acq_rel
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|
sx = se > sx ? se : sx;
|
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#pragma omp atomic compare acq_rel
|
|
sx = se < sx ? se : sx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (sx > se)
|
|
sx = se;
|
|
#pragma omp atomic compare acq_rel
|
|
if (sx < se)
|
|
sx = se;
|
|
#pragma omp atomic compare acq_rel
|
|
if (se > sx)
|
|
sx = se;
|
|
#pragma omp atomic compare acq_rel
|
|
if (se < sx)
|
|
sx = se;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
sx = sx == se ? sd : sx;
|
|
#pragma omp atomic compare acq_rel
|
|
sx = se == sx ? sd : sx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (sx == se)
|
|
sx = sd;
|
|
#pragma omp atomic compare acq_rel
|
|
if (se == sx)
|
|
sx = sd;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
usx = usx > use ? use : usx;
|
|
#pragma omp atomic compare acq_rel
|
|
usx = usx < use ? use : usx;
|
|
#pragma omp atomic compare acq_rel
|
|
usx = use > usx ? use : usx;
|
|
#pragma omp atomic compare acq_rel
|
|
usx = use < usx ? use : usx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (usx > use)
|
|
usx = use;
|
|
#pragma omp atomic compare acq_rel
|
|
if (usx < use)
|
|
usx = use;
|
|
#pragma omp atomic compare acq_rel
|
|
if (use > usx)
|
|
usx = use;
|
|
#pragma omp atomic compare acq_rel
|
|
if (use < usx)
|
|
usx = use;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
usx = usx == use ? usd : usx;
|
|
#pragma omp atomic compare acq_rel
|
|
usx = use == usx ? usd : usx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (usx == use)
|
|
usx = usd;
|
|
#pragma omp atomic compare acq_rel
|
|
if (use == usx)
|
|
usx = usd;
|
|
|
|
#pragma omp atomic compare acquire
|
|
sx = sx > se ? se : sx;
|
|
#pragma omp atomic compare acquire
|
|
sx = sx < se ? se : sx;
|
|
#pragma omp atomic compare acquire
|
|
sx = se > sx ? se : sx;
|
|
#pragma omp atomic compare acquire
|
|
sx = se < sx ? se : sx;
|
|
#pragma omp atomic compare acquire
|
|
if (sx > se)
|
|
sx = se;
|
|
#pragma omp atomic compare acquire
|
|
if (sx < se)
|
|
sx = se;
|
|
#pragma omp atomic compare acquire
|
|
if (se > sx)
|
|
sx = se;
|
|
#pragma omp atomic compare acquire
|
|
if (se < sx)
|
|
sx = se;
|
|
|
|
#pragma omp atomic compare acquire
|
|
sx = sx == se ? sd : sx;
|
|
#pragma omp atomic compare acquire
|
|
sx = se == sx ? sd : sx;
|
|
#pragma omp atomic compare acquire
|
|
if (sx == se)
|
|
sx = sd;
|
|
#pragma omp atomic compare acquire
|
|
if (se == sx)
|
|
sx = sd;
|
|
|
|
#pragma omp atomic compare acquire
|
|
usx = usx > use ? use : usx;
|
|
#pragma omp atomic compare acquire
|
|
usx = usx < use ? use : usx;
|
|
#pragma omp atomic compare acquire
|
|
usx = use > usx ? use : usx;
|
|
#pragma omp atomic compare acquire
|
|
usx = use < usx ? use : usx;
|
|
#pragma omp atomic compare acquire
|
|
if (usx > use)
|
|
usx = use;
|
|
#pragma omp atomic compare acquire
|
|
if (usx < use)
|
|
usx = use;
|
|
#pragma omp atomic compare acquire
|
|
if (use > usx)
|
|
usx = use;
|
|
#pragma omp atomic compare acquire
|
|
if (use < usx)
|
|
usx = use;
|
|
|
|
#pragma omp atomic compare acquire
|
|
usx = usx == use ? usd : usx;
|
|
#pragma omp atomic compare acquire
|
|
usx = use == usx ? usd : usx;
|
|
#pragma omp atomic compare acquire
|
|
if (usx == use)
|
|
usx = usd;
|
|
#pragma omp atomic compare acquire
|
|
if (use == usx)
|
|
usx = usd;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
sx = sx > se ? se : sx;
|
|
#pragma omp atomic compare relaxed
|
|
sx = sx < se ? se : sx;
|
|
#pragma omp atomic compare relaxed
|
|
sx = se > sx ? se : sx;
|
|
#pragma omp atomic compare relaxed
|
|
sx = se < sx ? se : sx;
|
|
#pragma omp atomic compare relaxed
|
|
if (sx > se)
|
|
sx = se;
|
|
#pragma omp atomic compare relaxed
|
|
if (sx < se)
|
|
sx = se;
|
|
#pragma omp atomic compare relaxed
|
|
if (se > sx)
|
|
sx = se;
|
|
#pragma omp atomic compare relaxed
|
|
if (se < sx)
|
|
sx = se;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
sx = sx == se ? sd : sx;
|
|
#pragma omp atomic compare relaxed
|
|
sx = se == sx ? sd : sx;
|
|
#pragma omp atomic compare relaxed
|
|
if (sx == se)
|
|
sx = sd;
|
|
#pragma omp atomic compare relaxed
|
|
if (se == sx)
|
|
sx = sd;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
usx = usx > use ? use : usx;
|
|
#pragma omp atomic compare relaxed
|
|
usx = usx < use ? use : usx;
|
|
#pragma omp atomic compare relaxed
|
|
usx = use > usx ? use : usx;
|
|
#pragma omp atomic compare relaxed
|
|
usx = use < usx ? use : usx;
|
|
#pragma omp atomic compare relaxed
|
|
if (usx > use)
|
|
usx = use;
|
|
#pragma omp atomic compare relaxed
|
|
if (usx < use)
|
|
usx = use;
|
|
#pragma omp atomic compare relaxed
|
|
if (use > usx)
|
|
usx = use;
|
|
#pragma omp atomic compare relaxed
|
|
if (use < usx)
|
|
usx = use;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
usx = usx == use ? usd : usx;
|
|
#pragma omp atomic compare relaxed
|
|
usx = use == usx ? usd : usx;
|
|
#pragma omp atomic compare relaxed
|
|
if (usx == use)
|
|
usx = usd;
|
|
#pragma omp atomic compare relaxed
|
|
if (use == usx)
|
|
usx = usd;
|
|
|
|
#pragma omp atomic compare release
|
|
sx = sx > se ? se : sx;
|
|
#pragma omp atomic compare release
|
|
sx = sx < se ? se : sx;
|
|
#pragma omp atomic compare release
|
|
sx = se > sx ? se : sx;
|
|
#pragma omp atomic compare release
|
|
sx = se < sx ? se : sx;
|
|
#pragma omp atomic compare release
|
|
if (sx > se)
|
|
sx = se;
|
|
#pragma omp atomic compare release
|
|
if (sx < se)
|
|
sx = se;
|
|
#pragma omp atomic compare release
|
|
if (se > sx)
|
|
sx = se;
|
|
#pragma omp atomic compare release
|
|
if (se < sx)
|
|
sx = se;
|
|
|
|
#pragma omp atomic compare release
|
|
sx = sx == se ? sd : sx;
|
|
#pragma omp atomic compare release
|
|
sx = se == sx ? sd : sx;
|
|
#pragma omp atomic compare release
|
|
if (sx == se)
|
|
sx = sd;
|
|
#pragma omp atomic compare release
|
|
if (se == sx)
|
|
sx = sd;
|
|
|
|
#pragma omp atomic compare release
|
|
usx = usx > use ? use : usx;
|
|
#pragma omp atomic compare release
|
|
usx = usx < use ? use : usx;
|
|
#pragma omp atomic compare release
|
|
usx = use > usx ? use : usx;
|
|
#pragma omp atomic compare release
|
|
usx = use < usx ? use : usx;
|
|
#pragma omp atomic compare release
|
|
if (usx > use)
|
|
usx = use;
|
|
#pragma omp atomic compare release
|
|
if (usx < use)
|
|
usx = use;
|
|
#pragma omp atomic compare release
|
|
if (use > usx)
|
|
usx = use;
|
|
#pragma omp atomic compare release
|
|
if (use < usx)
|
|
usx = use;
|
|
|
|
#pragma omp atomic compare release
|
|
usx = usx == use ? usd : usx;
|
|
#pragma omp atomic compare release
|
|
usx = use == usx ? usd : usx;
|
|
#pragma omp atomic compare release
|
|
if (usx == use)
|
|
usx = usd;
|
|
#pragma omp atomic compare release
|
|
if (use == usx)
|
|
usx = usd;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
sx = sx > se ? se : sx;
|
|
#pragma omp atomic compare seq_cst
|
|
sx = sx < se ? se : sx;
|
|
#pragma omp atomic compare seq_cst
|
|
sx = se > sx ? se : sx;
|
|
#pragma omp atomic compare seq_cst
|
|
sx = se < sx ? se : sx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (sx > se)
|
|
sx = se;
|
|
#pragma omp atomic compare seq_cst
|
|
if (sx < se)
|
|
sx = se;
|
|
#pragma omp atomic compare seq_cst
|
|
if (se > sx)
|
|
sx = se;
|
|
#pragma omp atomic compare seq_cst
|
|
if (se < sx)
|
|
sx = se;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
sx = sx == se ? sd : sx;
|
|
#pragma omp atomic compare seq_cst
|
|
sx = se == sx ? sd : sx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (sx == se)
|
|
sx = sd;
|
|
#pragma omp atomic compare seq_cst
|
|
if (se == sx)
|
|
sx = sd;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
usx = usx > use ? use : usx;
|
|
#pragma omp atomic compare seq_cst
|
|
usx = usx < use ? use : usx;
|
|
#pragma omp atomic compare seq_cst
|
|
usx = use > usx ? use : usx;
|
|
#pragma omp atomic compare seq_cst
|
|
usx = use < usx ? use : usx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (usx > use)
|
|
usx = use;
|
|
#pragma omp atomic compare seq_cst
|
|
if (usx < use)
|
|
usx = use;
|
|
#pragma omp atomic compare seq_cst
|
|
if (use > usx)
|
|
usx = use;
|
|
#pragma omp atomic compare seq_cst
|
|
if (use < usx)
|
|
usx = use;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
usx = usx == use ? usd : usx;
|
|
#pragma omp atomic compare seq_cst
|
|
usx = use == usx ? usd : usx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (usx == use)
|
|
usx = usd;
|
|
#pragma omp atomic compare seq_cst
|
|
if (use == usx)
|
|
usx = usd;
|
|
|
|
#pragma omp atomic compare
|
|
ix = ix > ie ? ie : ix;
|
|
#pragma omp atomic compare
|
|
ix = ix < ie ? ie : ix;
|
|
#pragma omp atomic compare
|
|
ix = ie > ix ? ie : ix;
|
|
#pragma omp atomic compare
|
|
ix = ie < ix ? ie : ix;
|
|
#pragma omp atomic compare
|
|
if (ix > ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare
|
|
if (ix < ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare
|
|
if (ie > ix)
|
|
ix = ie;
|
|
#pragma omp atomic compare
|
|
if (ie < ix)
|
|
ix = ie;
|
|
|
|
#pragma omp atomic compare
|
|
ix = ix == ie ? id : ix;
|
|
#pragma omp atomic compare
|
|
ix = ie == ix ? id : ix;
|
|
#pragma omp atomic compare
|
|
if (ix == ie)
|
|
ix = id;
|
|
#pragma omp atomic compare
|
|
if (ie == ix)
|
|
ix = id;
|
|
|
|
#pragma omp atomic compare
|
|
uix = uix > uie ? uie : uix;
|
|
#pragma omp atomic compare
|
|
uix = uix < uie ? uie : uix;
|
|
#pragma omp atomic compare
|
|
uix = uie > uix ? uie : uix;
|
|
#pragma omp atomic compare
|
|
uix = uie < uix ? uie : uix;
|
|
#pragma omp atomic compare
|
|
if (uix > uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare
|
|
if (uix < uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare
|
|
if (uie > uix)
|
|
uix = uie;
|
|
#pragma omp atomic compare
|
|
if (uie < uix)
|
|
uix = uie;
|
|
|
|
#pragma omp atomic compare
|
|
uix = uix == uie ? uid : uix;
|
|
#pragma omp atomic compare
|
|
uix = uie == uix ? uid : uix;
|
|
#pragma omp atomic compare
|
|
if (uix == uie)
|
|
uix = uid;
|
|
#pragma omp atomic compare
|
|
if (uie == uix)
|
|
uix = uid;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
ix = ix > ie ? ie : ix;
|
|
#pragma omp atomic compare acq_rel
|
|
ix = ix < ie ? ie : ix;
|
|
#pragma omp atomic compare acq_rel
|
|
ix = ie > ix ? ie : ix;
|
|
#pragma omp atomic compare acq_rel
|
|
ix = ie < ix ? ie : ix;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ix > ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ix < ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ie > ix)
|
|
ix = ie;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ie < ix)
|
|
ix = ie;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
ix = ix == ie ? id : ix;
|
|
#pragma omp atomic compare acq_rel
|
|
ix = ie == ix ? id : ix;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ix == ie)
|
|
ix = id;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ie == ix)
|
|
ix = id;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
uix = uix > uie ? uie : uix;
|
|
#pragma omp atomic compare acq_rel
|
|
uix = uix < uie ? uie : uix;
|
|
#pragma omp atomic compare acq_rel
|
|
uix = uie > uix ? uie : uix;
|
|
#pragma omp atomic compare acq_rel
|
|
uix = uie < uix ? uie : uix;
|
|
#pragma omp atomic compare acq_rel
|
|
if (uix > uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare acq_rel
|
|
if (uix < uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare acq_rel
|
|
if (uie > uix)
|
|
uix = uie;
|
|
#pragma omp atomic compare acq_rel
|
|
if (uie < uix)
|
|
uix = uie;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
uix = uix == uie ? uid : uix;
|
|
#pragma omp atomic compare acq_rel
|
|
uix = uie == uix ? uid : uix;
|
|
#pragma omp atomic compare acq_rel
|
|
if (uix == uie)
|
|
uix = uid;
|
|
#pragma omp atomic compare acq_rel
|
|
if (uie == uix)
|
|
uix = uid;
|
|
|
|
#pragma omp atomic compare acquire
|
|
ix = ix > ie ? ie : ix;
|
|
#pragma omp atomic compare acquire
|
|
ix = ix < ie ? ie : ix;
|
|
#pragma omp atomic compare acquire
|
|
ix = ie > ix ? ie : ix;
|
|
#pragma omp atomic compare acquire
|
|
ix = ie < ix ? ie : ix;
|
|
#pragma omp atomic compare acquire
|
|
if (ix > ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare acquire
|
|
if (ix < ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare acquire
|
|
if (ie > ix)
|
|
ix = ie;
|
|
#pragma omp atomic compare acquire
|
|
if (ie < ix)
|
|
ix = ie;
|
|
|
|
#pragma omp atomic compare acquire
|
|
ix = ix == ie ? id : ix;
|
|
#pragma omp atomic compare acquire
|
|
ix = ie == ix ? id : ix;
|
|
#pragma omp atomic compare acquire
|
|
if (ix == ie)
|
|
ix = id;
|
|
#pragma omp atomic compare acquire
|
|
if (ie == ix)
|
|
ix = id;
|
|
|
|
#pragma omp atomic compare acquire
|
|
uix = uix > uie ? uie : uix;
|
|
#pragma omp atomic compare acquire
|
|
uix = uix < uie ? uie : uix;
|
|
#pragma omp atomic compare acquire
|
|
uix = uie > uix ? uie : uix;
|
|
#pragma omp atomic compare acquire
|
|
uix = uie < uix ? uie : uix;
|
|
#pragma omp atomic compare acquire
|
|
if (uix > uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare acquire
|
|
if (uix < uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare acquire
|
|
if (uie > uix)
|
|
uix = uie;
|
|
#pragma omp atomic compare acquire
|
|
if (uie < uix)
|
|
uix = uie;
|
|
|
|
#pragma omp atomic compare acquire
|
|
uix = uix == uie ? uid : uix;
|
|
#pragma omp atomic compare acquire
|
|
uix = uie == uix ? uid : uix;
|
|
#pragma omp atomic compare acquire
|
|
if (uix == uie)
|
|
uix = uid;
|
|
#pragma omp atomic compare acquire
|
|
if (uie == uix)
|
|
uix = uid;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
ix = ix > ie ? ie : ix;
|
|
#pragma omp atomic compare relaxed
|
|
ix = ix < ie ? ie : ix;
|
|
#pragma omp atomic compare relaxed
|
|
ix = ie > ix ? ie : ix;
|
|
#pragma omp atomic compare relaxed
|
|
ix = ie < ix ? ie : ix;
|
|
#pragma omp atomic compare relaxed
|
|
if (ix > ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare relaxed
|
|
if (ix < ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare relaxed
|
|
if (ie > ix)
|
|
ix = ie;
|
|
#pragma omp atomic compare relaxed
|
|
if (ie < ix)
|
|
ix = ie;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
ix = ix == ie ? id : ix;
|
|
#pragma omp atomic compare relaxed
|
|
ix = ie == ix ? id : ix;
|
|
#pragma omp atomic compare relaxed
|
|
if (ix == ie)
|
|
ix = id;
|
|
#pragma omp atomic compare relaxed
|
|
if (ie == ix)
|
|
ix = id;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
uix = uix > uie ? uie : uix;
|
|
#pragma omp atomic compare relaxed
|
|
uix = uix < uie ? uie : uix;
|
|
#pragma omp atomic compare relaxed
|
|
uix = uie > uix ? uie : uix;
|
|
#pragma omp atomic compare relaxed
|
|
uix = uie < uix ? uie : uix;
|
|
#pragma omp atomic compare relaxed
|
|
if (uix > uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare relaxed
|
|
if (uix < uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare relaxed
|
|
if (uie > uix)
|
|
uix = uie;
|
|
#pragma omp atomic compare relaxed
|
|
if (uie < uix)
|
|
uix = uie;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
uix = uix == uie ? uid : uix;
|
|
#pragma omp atomic compare relaxed
|
|
uix = uie == uix ? uid : uix;
|
|
#pragma omp atomic compare relaxed
|
|
if (uix == uie)
|
|
uix = uid;
|
|
#pragma omp atomic compare relaxed
|
|
if (uie == uix)
|
|
uix = uid;
|
|
|
|
#pragma omp atomic compare release
|
|
ix = ix > ie ? ie : ix;
|
|
#pragma omp atomic compare release
|
|
ix = ix < ie ? ie : ix;
|
|
#pragma omp atomic compare release
|
|
ix = ie > ix ? ie : ix;
|
|
#pragma omp atomic compare release
|
|
ix = ie < ix ? ie : ix;
|
|
#pragma omp atomic compare release
|
|
if (ix > ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare release
|
|
if (ix < ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare release
|
|
if (ie > ix)
|
|
ix = ie;
|
|
#pragma omp atomic compare release
|
|
if (ie < ix)
|
|
ix = ie;
|
|
|
|
#pragma omp atomic compare release
|
|
ix = ix == ie ? id : ix;
|
|
#pragma omp atomic compare release
|
|
ix = ie == ix ? id : ix;
|
|
#pragma omp atomic compare release
|
|
if (ix == ie)
|
|
ix = id;
|
|
#pragma omp atomic compare release
|
|
if (ie == ix)
|
|
ix = id;
|
|
|
|
#pragma omp atomic compare release
|
|
uix = uix > uie ? uie : uix;
|
|
#pragma omp atomic compare release
|
|
uix = uix < uie ? uie : uix;
|
|
#pragma omp atomic compare release
|
|
uix = uie > uix ? uie : uix;
|
|
#pragma omp atomic compare release
|
|
uix = uie < uix ? uie : uix;
|
|
#pragma omp atomic compare release
|
|
if (uix > uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare release
|
|
if (uix < uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare release
|
|
if (uie > uix)
|
|
uix = uie;
|
|
#pragma omp atomic compare release
|
|
if (uie < uix)
|
|
uix = uie;
|
|
|
|
#pragma omp atomic compare release
|
|
uix = uix == uie ? uid : uix;
|
|
#pragma omp atomic compare release
|
|
uix = uie == uix ? uid : uix;
|
|
#pragma omp atomic compare release
|
|
if (uix == uie)
|
|
uix = uid;
|
|
#pragma omp atomic compare release
|
|
if (uie == uix)
|
|
uix = uid;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
ix = ix > ie ? ie : ix;
|
|
#pragma omp atomic compare seq_cst
|
|
ix = ix < ie ? ie : ix;
|
|
#pragma omp atomic compare seq_cst
|
|
ix = ie > ix ? ie : ix;
|
|
#pragma omp atomic compare seq_cst
|
|
ix = ie < ix ? ie : ix;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ix > ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ix < ie)
|
|
ix = ie;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ie > ix)
|
|
ix = ie;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ie < ix)
|
|
ix = ie;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
ix = ix == ie ? id : ix;
|
|
#pragma omp atomic compare seq_cst
|
|
ix = ie == ix ? id : ix;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ix == ie)
|
|
ix = id;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ie == ix)
|
|
ix = id;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
uix = uix > uie ? uie : uix;
|
|
#pragma omp atomic compare seq_cst
|
|
uix = uix < uie ? uie : uix;
|
|
#pragma omp atomic compare seq_cst
|
|
uix = uie > uix ? uie : uix;
|
|
#pragma omp atomic compare seq_cst
|
|
uix = uie < uix ? uie : uix;
|
|
#pragma omp atomic compare seq_cst
|
|
if (uix > uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare seq_cst
|
|
if (uix < uie)
|
|
uix = uie;
|
|
#pragma omp atomic compare seq_cst
|
|
if (uie > uix)
|
|
uix = uie;
|
|
#pragma omp atomic compare seq_cst
|
|
if (uie < uix)
|
|
uix = uie;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
uix = uix == uie ? uid : uix;
|
|
#pragma omp atomic compare seq_cst
|
|
uix = uie == uix ? uid : uix;
|
|
#pragma omp atomic compare seq_cst
|
|
if (uix == uie)
|
|
uix = uid;
|
|
#pragma omp atomic compare seq_cst
|
|
if (uie == uix)
|
|
uix = uid;
|
|
|
|
#pragma omp atomic compare
|
|
lx = lx > le ? le : lx;
|
|
#pragma omp atomic compare
|
|
lx = lx < le ? le : lx;
|
|
#pragma omp atomic compare
|
|
lx = le > lx ? le : lx;
|
|
#pragma omp atomic compare
|
|
lx = le < lx ? le : lx;
|
|
#pragma omp atomic compare
|
|
if (lx > le)
|
|
lx = le;
|
|
#pragma omp atomic compare
|
|
if (lx < le)
|
|
lx = le;
|
|
#pragma omp atomic compare
|
|
if (le > lx)
|
|
lx = le;
|
|
#pragma omp atomic compare
|
|
if (le < lx)
|
|
lx = le;
|
|
|
|
#pragma omp atomic compare
|
|
lx = lx == le ? ld : lx;
|
|
#pragma omp atomic compare
|
|
lx = le == lx ? ld : lx;
|
|
#pragma omp atomic compare
|
|
if (lx == le)
|
|
lx = ld;
|
|
#pragma omp atomic compare
|
|
if (le == lx)
|
|
lx = ld;
|
|
|
|
#pragma omp atomic compare
|
|
ulx = ulx > ule ? ule : ulx;
|
|
#pragma omp atomic compare
|
|
ulx = ulx < ule ? ule : ulx;
|
|
#pragma omp atomic compare
|
|
ulx = ule > ulx ? ule : ulx;
|
|
#pragma omp atomic compare
|
|
ulx = ule < ulx ? ule : ulx;
|
|
#pragma omp atomic compare
|
|
if (ulx > ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare
|
|
if (ulx < ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare
|
|
if (ule > ulx)
|
|
ulx = ule;
|
|
#pragma omp atomic compare
|
|
if (ule < ulx)
|
|
ulx = ule;
|
|
|
|
#pragma omp atomic compare
|
|
ulx = ulx == ule ? uld : ulx;
|
|
#pragma omp atomic compare
|
|
ulx = ule == ulx ? uld : ulx;
|
|
#pragma omp atomic compare
|
|
if (ulx == ule)
|
|
ulx = uld;
|
|
#pragma omp atomic compare
|
|
if (ule == ulx)
|
|
ulx = uld;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
lx = lx > le ? le : lx;
|
|
#pragma omp atomic compare acq_rel
|
|
lx = lx < le ? le : lx;
|
|
#pragma omp atomic compare acq_rel
|
|
lx = le > lx ? le : lx;
|
|
#pragma omp atomic compare acq_rel
|
|
lx = le < lx ? le : lx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (lx > le)
|
|
lx = le;
|
|
#pragma omp atomic compare acq_rel
|
|
if (lx < le)
|
|
lx = le;
|
|
#pragma omp atomic compare acq_rel
|
|
if (le > lx)
|
|
lx = le;
|
|
#pragma omp atomic compare acq_rel
|
|
if (le < lx)
|
|
lx = le;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
lx = lx == le ? ld : lx;
|
|
#pragma omp atomic compare acq_rel
|
|
lx = le == lx ? ld : lx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (lx == le)
|
|
lx = ld;
|
|
#pragma omp atomic compare acq_rel
|
|
if (le == lx)
|
|
lx = ld;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
ulx = ulx > ule ? ule : ulx;
|
|
#pragma omp atomic compare acq_rel
|
|
ulx = ulx < ule ? ule : ulx;
|
|
#pragma omp atomic compare acq_rel
|
|
ulx = ule > ulx ? ule : ulx;
|
|
#pragma omp atomic compare acq_rel
|
|
ulx = ule < ulx ? ule : ulx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ulx > ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ulx < ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ule > ulx)
|
|
ulx = ule;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ule < ulx)
|
|
ulx = ule;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
ulx = ulx == ule ? uld : ulx;
|
|
#pragma omp atomic compare acq_rel
|
|
ulx = ule == ulx ? uld : ulx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ulx == ule)
|
|
ulx = uld;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ule == ulx)
|
|
ulx = uld;
|
|
|
|
#pragma omp atomic compare acquire
|
|
lx = lx > le ? le : lx;
|
|
#pragma omp atomic compare acquire
|
|
lx = lx < le ? le : lx;
|
|
#pragma omp atomic compare acquire
|
|
lx = le > lx ? le : lx;
|
|
#pragma omp atomic compare acquire
|
|
lx = le < lx ? le : lx;
|
|
#pragma omp atomic compare acquire
|
|
if (lx > le)
|
|
lx = le;
|
|
#pragma omp atomic compare acquire
|
|
if (lx < le)
|
|
lx = le;
|
|
#pragma omp atomic compare acquire
|
|
if (le > lx)
|
|
lx = le;
|
|
#pragma omp atomic compare acquire
|
|
if (le < lx)
|
|
lx = le;
|
|
|
|
#pragma omp atomic compare acquire
|
|
lx = lx == le ? ld : lx;
|
|
#pragma omp atomic compare acquire
|
|
lx = le == lx ? ld : lx;
|
|
#pragma omp atomic compare acquire
|
|
if (lx == le)
|
|
lx = ld;
|
|
#pragma omp atomic compare acquire
|
|
if (le == lx)
|
|
lx = ld;
|
|
|
|
#pragma omp atomic compare acquire
|
|
ulx = ulx > ule ? ule : ulx;
|
|
#pragma omp atomic compare acquire
|
|
ulx = ulx < ule ? ule : ulx;
|
|
#pragma omp atomic compare acquire
|
|
ulx = ule > ulx ? ule : ulx;
|
|
#pragma omp atomic compare acquire
|
|
ulx = ule < ulx ? ule : ulx;
|
|
#pragma omp atomic compare acquire
|
|
if (ulx > ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare acquire
|
|
if (ulx < ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare acquire
|
|
if (ule > ulx)
|
|
ulx = ule;
|
|
#pragma omp atomic compare acquire
|
|
if (ule < ulx)
|
|
ulx = ule;
|
|
|
|
#pragma omp atomic compare acquire
|
|
ulx = ulx == ule ? uld : ulx;
|
|
#pragma omp atomic compare acquire
|
|
ulx = ule == ulx ? uld : ulx;
|
|
#pragma omp atomic compare acquire
|
|
if (ulx == ule)
|
|
ulx = uld;
|
|
#pragma omp atomic compare acquire
|
|
if (ule == ulx)
|
|
ulx = uld;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
lx = lx > le ? le : lx;
|
|
#pragma omp atomic compare relaxed
|
|
lx = lx < le ? le : lx;
|
|
#pragma omp atomic compare relaxed
|
|
lx = le > lx ? le : lx;
|
|
#pragma omp atomic compare relaxed
|
|
lx = le < lx ? le : lx;
|
|
#pragma omp atomic compare relaxed
|
|
if (lx > le)
|
|
lx = le;
|
|
#pragma omp atomic compare relaxed
|
|
if (lx < le)
|
|
lx = le;
|
|
#pragma omp atomic compare relaxed
|
|
if (le > lx)
|
|
lx = le;
|
|
#pragma omp atomic compare relaxed
|
|
if (le < lx)
|
|
lx = le;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
lx = lx == le ? ld : lx;
|
|
#pragma omp atomic compare relaxed
|
|
lx = le == lx ? ld : lx;
|
|
#pragma omp atomic compare relaxed
|
|
if (lx == le)
|
|
lx = ld;
|
|
#pragma omp atomic compare relaxed
|
|
if (le == lx)
|
|
lx = ld;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
ulx = ulx > ule ? ule : ulx;
|
|
#pragma omp atomic compare relaxed
|
|
ulx = ulx < ule ? ule : ulx;
|
|
#pragma omp atomic compare relaxed
|
|
ulx = ule > ulx ? ule : ulx;
|
|
#pragma omp atomic compare relaxed
|
|
ulx = ule < ulx ? ule : ulx;
|
|
#pragma omp atomic compare relaxed
|
|
if (ulx > ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare relaxed
|
|
if (ulx < ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare relaxed
|
|
if (ule > ulx)
|
|
ulx = ule;
|
|
#pragma omp atomic compare relaxed
|
|
if (ule < ulx)
|
|
ulx = ule;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
ulx = ulx == ule ? uld : ulx;
|
|
#pragma omp atomic compare relaxed
|
|
ulx = ule == ulx ? uld : ulx;
|
|
#pragma omp atomic compare relaxed
|
|
if (ulx == ule)
|
|
ulx = uld;
|
|
#pragma omp atomic compare relaxed
|
|
if (ule == ulx)
|
|
ulx = uld;
|
|
|
|
#pragma omp atomic compare release
|
|
lx = lx > le ? le : lx;
|
|
#pragma omp atomic compare release
|
|
lx = lx < le ? le : lx;
|
|
#pragma omp atomic compare release
|
|
lx = le > lx ? le : lx;
|
|
#pragma omp atomic compare release
|
|
lx = le < lx ? le : lx;
|
|
#pragma omp atomic compare release
|
|
if (lx > le)
|
|
lx = le;
|
|
#pragma omp atomic compare release
|
|
if (lx < le)
|
|
lx = le;
|
|
#pragma omp atomic compare release
|
|
if (le > lx)
|
|
lx = le;
|
|
#pragma omp atomic compare release
|
|
if (le < lx)
|
|
lx = le;
|
|
|
|
#pragma omp atomic compare release
|
|
lx = lx == le ? ld : lx;
|
|
#pragma omp atomic compare release
|
|
lx = le == lx ? ld : lx;
|
|
#pragma omp atomic compare release
|
|
if (lx == le)
|
|
lx = ld;
|
|
#pragma omp atomic compare release
|
|
if (le == lx)
|
|
lx = ld;
|
|
|
|
#pragma omp atomic compare release
|
|
ulx = ulx > ule ? ule : ulx;
|
|
#pragma omp atomic compare release
|
|
ulx = ulx < ule ? ule : ulx;
|
|
#pragma omp atomic compare release
|
|
ulx = ule > ulx ? ule : ulx;
|
|
#pragma omp atomic compare release
|
|
ulx = ule < ulx ? ule : ulx;
|
|
#pragma omp atomic compare release
|
|
if (ulx > ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare release
|
|
if (ulx < ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare release
|
|
if (ule > ulx)
|
|
ulx = ule;
|
|
#pragma omp atomic compare release
|
|
if (ule < ulx)
|
|
ulx = ule;
|
|
|
|
#pragma omp atomic compare release
|
|
ulx = ulx == ule ? uld : ulx;
|
|
#pragma omp atomic compare release
|
|
ulx = ule == ulx ? uld : ulx;
|
|
#pragma omp atomic compare release
|
|
if (ulx == ule)
|
|
ulx = uld;
|
|
#pragma omp atomic compare release
|
|
if (ule == ulx)
|
|
ulx = uld;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
lx = lx > le ? le : lx;
|
|
#pragma omp atomic compare seq_cst
|
|
lx = lx < le ? le : lx;
|
|
#pragma omp atomic compare seq_cst
|
|
lx = le > lx ? le : lx;
|
|
#pragma omp atomic compare seq_cst
|
|
lx = le < lx ? le : lx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (lx > le)
|
|
lx = le;
|
|
#pragma omp atomic compare seq_cst
|
|
if (lx < le)
|
|
lx = le;
|
|
#pragma omp atomic compare seq_cst
|
|
if (le > lx)
|
|
lx = le;
|
|
#pragma omp atomic compare seq_cst
|
|
if (le < lx)
|
|
lx = le;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
lx = lx == le ? ld : lx;
|
|
#pragma omp atomic compare seq_cst
|
|
lx = le == lx ? ld : lx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (lx == le)
|
|
lx = ld;
|
|
#pragma omp atomic compare seq_cst
|
|
if (le == lx)
|
|
lx = ld;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
ulx = ulx > ule ? ule : ulx;
|
|
#pragma omp atomic compare seq_cst
|
|
ulx = ulx < ule ? ule : ulx;
|
|
#pragma omp atomic compare seq_cst
|
|
ulx = ule > ulx ? ule : ulx;
|
|
#pragma omp atomic compare seq_cst
|
|
ulx = ule < ulx ? ule : ulx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ulx > ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ulx < ule)
|
|
ulx = ule;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ule > ulx)
|
|
ulx = ule;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ule < ulx)
|
|
ulx = ule;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
ulx = ulx == ule ? uld : ulx;
|
|
#pragma omp atomic compare seq_cst
|
|
ulx = ule == ulx ? uld : ulx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ulx == ule)
|
|
ulx = uld;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ule == ulx)
|
|
ulx = uld;
|
|
|
|
#pragma omp atomic compare
|
|
llx = llx > lle ? lle : llx;
|
|
#pragma omp atomic compare
|
|
llx = llx < lle ? lle : llx;
|
|
#pragma omp atomic compare
|
|
llx = lle > llx ? lle : llx;
|
|
#pragma omp atomic compare
|
|
llx = lle < llx ? lle : llx;
|
|
#pragma omp atomic compare
|
|
if (llx > lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare
|
|
if (llx < lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare
|
|
if (lle > llx)
|
|
llx = lle;
|
|
#pragma omp atomic compare
|
|
if (lle < llx)
|
|
llx = lle;
|
|
|
|
#pragma omp atomic compare
|
|
llx = llx == lle ? lld : llx;
|
|
#pragma omp atomic compare
|
|
llx = lle == llx ? lld : llx;
|
|
#pragma omp atomic compare
|
|
if (llx == lle)
|
|
llx = lld;
|
|
#pragma omp atomic compare
|
|
if (lle == llx)
|
|
llx = lld;
|
|
|
|
#pragma omp atomic compare
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
#pragma omp atomic compare
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
#pragma omp atomic compare
|
|
ullx = ulle > ullx ? ulle : ullx;
|
|
#pragma omp atomic compare
|
|
ullx = ulle < ullx ? ulle : ullx;
|
|
#pragma omp atomic compare
|
|
if (ullx > ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare
|
|
if (ullx < ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare
|
|
if (ulle > ullx)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare
|
|
if (ulle < ullx)
|
|
ullx = ulle;
|
|
|
|
#pragma omp atomic compare
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
#pragma omp atomic compare
|
|
ullx = ulle == ullx ? ulld : ullx;
|
|
#pragma omp atomic compare
|
|
if (ullx == ulle)
|
|
ullx = ulld;
|
|
#pragma omp atomic compare
|
|
if (ulle == ullx)
|
|
ullx = ulld;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
llx = llx > lle ? lle : llx;
|
|
#pragma omp atomic compare acq_rel
|
|
llx = llx < lle ? lle : llx;
|
|
#pragma omp atomic compare acq_rel
|
|
llx = lle > llx ? lle : llx;
|
|
#pragma omp atomic compare acq_rel
|
|
llx = lle < llx ? lle : llx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (llx > lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare acq_rel
|
|
if (llx < lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare acq_rel
|
|
if (lle > llx)
|
|
llx = lle;
|
|
#pragma omp atomic compare acq_rel
|
|
if (lle < llx)
|
|
llx = lle;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
llx = llx == lle ? lld : llx;
|
|
#pragma omp atomic compare acq_rel
|
|
llx = lle == llx ? lld : llx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (llx == lle)
|
|
llx = lld;
|
|
#pragma omp atomic compare acq_rel
|
|
if (lle == llx)
|
|
llx = lld;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
#pragma omp atomic compare acq_rel
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
#pragma omp atomic compare acq_rel
|
|
ullx = ulle > ullx ? ulle : ullx;
|
|
#pragma omp atomic compare acq_rel
|
|
ullx = ulle < ullx ? ulle : ullx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ullx > ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ullx < ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ulle > ullx)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ulle < ullx)
|
|
ullx = ulle;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
#pragma omp atomic compare acq_rel
|
|
ullx = ulle == ullx ? ulld : ullx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ullx == ulle)
|
|
ullx = ulld;
|
|
#pragma omp atomic compare acq_rel
|
|
if (ulle == ullx)
|
|
ullx = ulld;
|
|
|
|
#pragma omp atomic compare acquire
|
|
llx = llx > lle ? lle : llx;
|
|
#pragma omp atomic compare acquire
|
|
llx = llx < lle ? lle : llx;
|
|
#pragma omp atomic compare acquire
|
|
llx = lle > llx ? lle : llx;
|
|
#pragma omp atomic compare acquire
|
|
llx = lle < llx ? lle : llx;
|
|
#pragma omp atomic compare acquire
|
|
if (llx > lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare acquire
|
|
if (llx < lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare acquire
|
|
if (lle > llx)
|
|
llx = lle;
|
|
#pragma omp atomic compare acquire
|
|
if (lle < llx)
|
|
llx = lle;
|
|
|
|
#pragma omp atomic compare acquire
|
|
llx = llx == lle ? lld : llx;
|
|
#pragma omp atomic compare acquire
|
|
llx = lle == llx ? lld : llx;
|
|
#pragma omp atomic compare acquire
|
|
if (llx == lle)
|
|
llx = lld;
|
|
#pragma omp atomic compare acquire
|
|
if (lle == llx)
|
|
llx = lld;
|
|
|
|
#pragma omp atomic compare acquire
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
#pragma omp atomic compare acquire
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
#pragma omp atomic compare acquire
|
|
ullx = ulle > ullx ? ulle : ullx;
|
|
#pragma omp atomic compare acquire
|
|
ullx = ulle < ullx ? ulle : ullx;
|
|
#pragma omp atomic compare acquire
|
|
if (ullx > ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare acquire
|
|
if (ullx < ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare acquire
|
|
if (ulle > ullx)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare acquire
|
|
if (ulle < ullx)
|
|
ullx = ulle;
|
|
|
|
#pragma omp atomic compare acquire
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
#pragma omp atomic compare acquire
|
|
ullx = ulle == ullx ? ulld : ullx;
|
|
#pragma omp atomic compare acquire
|
|
if (ullx == ulle)
|
|
ullx = ulld;
|
|
#pragma omp atomic compare acquire
|
|
if (ulle == ullx)
|
|
ullx = ulld;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
llx = llx > lle ? lle : llx;
|
|
#pragma omp atomic compare relaxed
|
|
llx = llx < lle ? lle : llx;
|
|
#pragma omp atomic compare relaxed
|
|
llx = lle > llx ? lle : llx;
|
|
#pragma omp atomic compare relaxed
|
|
llx = lle < llx ? lle : llx;
|
|
#pragma omp atomic compare relaxed
|
|
if (llx > lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare relaxed
|
|
if (llx < lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare relaxed
|
|
if (lle > llx)
|
|
llx = lle;
|
|
#pragma omp atomic compare relaxed
|
|
if (lle < llx)
|
|
llx = lle;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
llx = llx == lle ? lld : llx;
|
|
#pragma omp atomic compare relaxed
|
|
llx = lle == llx ? lld : llx;
|
|
#pragma omp atomic compare relaxed
|
|
if (llx == lle)
|
|
llx = lld;
|
|
#pragma omp atomic compare relaxed
|
|
if (lle == llx)
|
|
llx = lld;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
#pragma omp atomic compare relaxed
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
#pragma omp atomic compare relaxed
|
|
ullx = ulle > ullx ? ulle : ullx;
|
|
#pragma omp atomic compare relaxed
|
|
ullx = ulle < ullx ? ulle : ullx;
|
|
#pragma omp atomic compare relaxed
|
|
if (ullx > ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare relaxed
|
|
if (ullx < ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare relaxed
|
|
if (ulle > ullx)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare relaxed
|
|
if (ulle < ullx)
|
|
ullx = ulle;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
#pragma omp atomic compare relaxed
|
|
ullx = ulle == ullx ? ulld : ullx;
|
|
#pragma omp atomic compare relaxed
|
|
if (ullx == ulle)
|
|
ullx = ulld;
|
|
#pragma omp atomic compare relaxed
|
|
if (ulle == ullx)
|
|
ullx = ulld;
|
|
|
|
#pragma omp atomic compare release
|
|
llx = llx > lle ? lle : llx;
|
|
#pragma omp atomic compare release
|
|
llx = llx < lle ? lle : llx;
|
|
#pragma omp atomic compare release
|
|
llx = lle > llx ? lle : llx;
|
|
#pragma omp atomic compare release
|
|
llx = lle < llx ? lle : llx;
|
|
#pragma omp atomic compare release
|
|
if (llx > lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare release
|
|
if (llx < lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare release
|
|
if (lle > llx)
|
|
llx = lle;
|
|
#pragma omp atomic compare release
|
|
if (lle < llx)
|
|
llx = lle;
|
|
|
|
#pragma omp atomic compare release
|
|
llx = llx == lle ? lld : llx;
|
|
#pragma omp atomic compare release
|
|
llx = lle == llx ? lld : llx;
|
|
#pragma omp atomic compare release
|
|
if (llx == lle)
|
|
llx = lld;
|
|
#pragma omp atomic compare release
|
|
if (lle == llx)
|
|
llx = lld;
|
|
|
|
#pragma omp atomic compare release
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
#pragma omp atomic compare release
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
#pragma omp atomic compare release
|
|
ullx = ulle > ullx ? ulle : ullx;
|
|
#pragma omp atomic compare release
|
|
ullx = ulle < ullx ? ulle : ullx;
|
|
#pragma omp atomic compare release
|
|
if (ullx > ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare release
|
|
if (ullx < ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare release
|
|
if (ulle > ullx)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare release
|
|
if (ulle < ullx)
|
|
ullx = ulle;
|
|
|
|
#pragma omp atomic compare release
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
#pragma omp atomic compare release
|
|
ullx = ulle == ullx ? ulld : ullx;
|
|
#pragma omp atomic compare release
|
|
if (ullx == ulle)
|
|
ullx = ulld;
|
|
#pragma omp atomic compare release
|
|
if (ulle == ullx)
|
|
ullx = ulld;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
llx = llx > lle ? lle : llx;
|
|
#pragma omp atomic compare seq_cst
|
|
llx = llx < lle ? lle : llx;
|
|
#pragma omp atomic compare seq_cst
|
|
llx = lle > llx ? lle : llx;
|
|
#pragma omp atomic compare seq_cst
|
|
llx = lle < llx ? lle : llx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (llx > lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare seq_cst
|
|
if (llx < lle)
|
|
llx = lle;
|
|
#pragma omp atomic compare seq_cst
|
|
if (lle > llx)
|
|
llx = lle;
|
|
#pragma omp atomic compare seq_cst
|
|
if (lle < llx)
|
|
llx = lle;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
llx = llx == lle ? lld : llx;
|
|
#pragma omp atomic compare seq_cst
|
|
llx = lle == llx ? lld : llx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (llx == lle)
|
|
llx = lld;
|
|
#pragma omp atomic compare seq_cst
|
|
if (lle == llx)
|
|
llx = lld;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
#pragma omp atomic compare seq_cst
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
#pragma omp atomic compare seq_cst
|
|
ullx = ulle > ullx ? ulle : ullx;
|
|
#pragma omp atomic compare seq_cst
|
|
ullx = ulle < ullx ? ulle : ullx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ullx > ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ullx < ulle)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ulle > ullx)
|
|
ullx = ulle;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ulle < ullx)
|
|
ullx = ulle;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
#pragma omp atomic compare seq_cst
|
|
ullx = ulle == ullx ? ulld : ullx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ullx == ulle)
|
|
ullx = ulld;
|
|
#pragma omp atomic compare seq_cst
|
|
if (ulle == ullx)
|
|
ullx = ulld;
|
|
|
|
#pragma omp atomic compare
|
|
fx = fx > fe ? fe : fx;
|
|
#pragma omp atomic compare
|
|
fx = fx < fe ? fe : fx;
|
|
#pragma omp atomic compare
|
|
fx = fe > fx ? fe : fx;
|
|
#pragma omp atomic compare
|
|
fx = fe < fx ? fe : fx;
|
|
#pragma omp atomic compare
|
|
if (fx > fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare
|
|
if (fx < fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare
|
|
if (fe > fx)
|
|
fx = fe;
|
|
#pragma omp atomic compare
|
|
if (fe < fx)
|
|
fx = fe;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
fx = fx > fe ? fe : fx;
|
|
#pragma omp atomic compare acq_rel
|
|
fx = fx < fe ? fe : fx;
|
|
#pragma omp atomic compare acq_rel
|
|
fx = fe > fx ? fe : fx;
|
|
#pragma omp atomic compare acq_rel
|
|
fx = fe < fx ? fe : fx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (fx > fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare acq_rel
|
|
if (fx < fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare acq_rel
|
|
if (fe > fx)
|
|
fx = fe;
|
|
#pragma omp atomic compare acq_rel
|
|
if (fe < fx)
|
|
fx = fe;
|
|
|
|
#pragma omp atomic compare acquire
|
|
fx = fx > fe ? fe : fx;
|
|
#pragma omp atomic compare acquire
|
|
fx = fx < fe ? fe : fx;
|
|
#pragma omp atomic compare acquire
|
|
fx = fe > fx ? fe : fx;
|
|
#pragma omp atomic compare acquire
|
|
fx = fe < fx ? fe : fx;
|
|
#pragma omp atomic compare acquire
|
|
if (fx > fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare acquire
|
|
if (fx < fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare acquire
|
|
if (fe > fx)
|
|
fx = fe;
|
|
#pragma omp atomic compare acquire
|
|
if (fe < fx)
|
|
fx = fe;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
fx = fx > fe ? fe : fx;
|
|
#pragma omp atomic compare relaxed
|
|
fx = fx < fe ? fe : fx;
|
|
#pragma omp atomic compare relaxed
|
|
fx = fe > fx ? fe : fx;
|
|
#pragma omp atomic compare relaxed
|
|
fx = fe < fx ? fe : fx;
|
|
#pragma omp atomic compare relaxed
|
|
if (fx > fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare relaxed
|
|
if (fx < fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare relaxed
|
|
if (fe > fx)
|
|
fx = fe;
|
|
#pragma omp atomic compare relaxed
|
|
if (fe < fx)
|
|
fx = fe;
|
|
|
|
#pragma omp atomic compare release
|
|
fx = fx > fe ? fe : fx;
|
|
#pragma omp atomic compare release
|
|
fx = fx < fe ? fe : fx;
|
|
#pragma omp atomic compare release
|
|
fx = fe > fx ? fe : fx;
|
|
#pragma omp atomic compare release
|
|
fx = fe < fx ? fe : fx;
|
|
#pragma omp atomic compare release
|
|
if (fx > fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare release
|
|
if (fx < fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare release
|
|
if (fe > fx)
|
|
fx = fe;
|
|
#pragma omp atomic compare release
|
|
if (fe < fx)
|
|
fx = fe;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
fx = fx > fe ? fe : fx;
|
|
#pragma omp atomic compare seq_cst
|
|
fx = fx < fe ? fe : fx;
|
|
#pragma omp atomic compare seq_cst
|
|
fx = fe > fx ? fe : fx;
|
|
#pragma omp atomic compare seq_cst
|
|
fx = fe < fx ? fe : fx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (fx > fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare seq_cst
|
|
if (fx < fe)
|
|
fx = fe;
|
|
#pragma omp atomic compare seq_cst
|
|
if (fe > fx)
|
|
fx = fe;
|
|
#pragma omp atomic compare seq_cst
|
|
if (fe < fx)
|
|
fx = fe;
|
|
|
|
#pragma omp atomic compare
|
|
dx = dx > de ? de : dx;
|
|
#pragma omp atomic compare
|
|
dx = dx < de ? de : dx;
|
|
#pragma omp atomic compare
|
|
dx = de > dx ? de : dx;
|
|
#pragma omp atomic compare
|
|
dx = de < dx ? de : dx;
|
|
#pragma omp atomic compare
|
|
if (dx > de)
|
|
dx = de;
|
|
#pragma omp atomic compare
|
|
if (dx < de)
|
|
dx = de;
|
|
#pragma omp atomic compare
|
|
if (de > dx)
|
|
dx = de;
|
|
#pragma omp atomic compare
|
|
if (de < dx)
|
|
dx = de;
|
|
|
|
#pragma omp atomic compare acq_rel
|
|
dx = dx > de ? de : dx;
|
|
#pragma omp atomic compare acq_rel
|
|
dx = dx < de ? de : dx;
|
|
#pragma omp atomic compare acq_rel
|
|
dx = de > dx ? de : dx;
|
|
#pragma omp atomic compare acq_rel
|
|
dx = de < dx ? de : dx;
|
|
#pragma omp atomic compare acq_rel
|
|
if (dx > de)
|
|
dx = de;
|
|
#pragma omp atomic compare acq_rel
|
|
if (dx < de)
|
|
dx = de;
|
|
#pragma omp atomic compare acq_rel
|
|
if (de > dx)
|
|
dx = de;
|
|
#pragma omp atomic compare acq_rel
|
|
if (de < dx)
|
|
dx = de;
|
|
|
|
#pragma omp atomic compare acquire
|
|
dx = dx > de ? de : dx;
|
|
#pragma omp atomic compare acquire
|
|
dx = dx < de ? de : dx;
|
|
#pragma omp atomic compare acquire
|
|
dx = de > dx ? de : dx;
|
|
#pragma omp atomic compare acquire
|
|
dx = de < dx ? de : dx;
|
|
#pragma omp atomic compare acquire
|
|
if (dx > de)
|
|
dx = de;
|
|
#pragma omp atomic compare acquire
|
|
if (dx < de)
|
|
dx = de;
|
|
#pragma omp atomic compare acquire
|
|
if (de > dx)
|
|
dx = de;
|
|
#pragma omp atomic compare acquire
|
|
if (de < dx)
|
|
dx = de;
|
|
|
|
#pragma omp atomic compare relaxed
|
|
dx = dx > de ? de : dx;
|
|
#pragma omp atomic compare relaxed
|
|
dx = dx < de ? de : dx;
|
|
#pragma omp atomic compare relaxed
|
|
dx = de > dx ? de : dx;
|
|
#pragma omp atomic compare relaxed
|
|
dx = de < dx ? de : dx;
|
|
#pragma omp atomic compare relaxed
|
|
if (dx > de)
|
|
dx = de;
|
|
#pragma omp atomic compare relaxed
|
|
if (dx < de)
|
|
dx = de;
|
|
#pragma omp atomic compare relaxed
|
|
if (de > dx)
|
|
dx = de;
|
|
#pragma omp atomic compare relaxed
|
|
if (de < dx)
|
|
dx = de;
|
|
|
|
#pragma omp atomic compare release
|
|
dx = dx > de ? de : dx;
|
|
#pragma omp atomic compare release
|
|
dx = dx < de ? de : dx;
|
|
#pragma omp atomic compare release
|
|
dx = de > dx ? de : dx;
|
|
#pragma omp atomic compare release
|
|
dx = de < dx ? de : dx;
|
|
#pragma omp atomic compare release
|
|
if (dx > de)
|
|
dx = de;
|
|
#pragma omp atomic compare release
|
|
if (dx < de)
|
|
dx = de;
|
|
#pragma omp atomic compare release
|
|
if (de > dx)
|
|
dx = de;
|
|
#pragma omp atomic compare release
|
|
if (de < dx)
|
|
dx = de;
|
|
|
|
#pragma omp atomic compare seq_cst
|
|
dx = dx > de ? de : dx;
|
|
#pragma omp atomic compare seq_cst
|
|
dx = dx < de ? de : dx;
|
|
#pragma omp atomic compare seq_cst
|
|
dx = de > dx ? de : dx;
|
|
#pragma omp atomic compare seq_cst
|
|
dx = de < dx ? de : dx;
|
|
#pragma omp atomic compare seq_cst
|
|
if (dx > de)
|
|
dx = de;
|
|
#pragma omp atomic compare seq_cst
|
|
if (dx < de)
|
|
dx = de;
|
|
#pragma omp atomic compare seq_cst
|
|
if (de > dx)
|
|
dx = de;
|
|
#pragma omp atomic compare seq_cst
|
|
if (de < dx)
|
|
dx = de;
|
|
}
|
|
|
|
void bar() {
|
|
char cx, cv, cr, ce, cd;
|
|
unsigned char ucx, ucv, ucr, uce, ucd;
|
|
short sx, sv, sr, se, sd;
|
|
unsigned short usx, usv, usr, use, usd;
|
|
int ix, iv, ir, ie, id;
|
|
unsigned int uix, uiv, uir, uie, uid;
|
|
long lx, lv, lr, le, ld;
|
|
unsigned long ulx, ulv, ulr, ule, uld;
|
|
long long llx, llv, llr, lle, lld;
|
|
unsigned long long ullx, ullv, ullr, ulle, ulld;
|
|
float fx, fv, fe, fd;
|
|
double dx, dv, de, dd;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cv = cx;
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cv = cx;
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cv = cx;
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cv = cx;
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cv = cx;
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cv = cx;
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cv = cx;
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cv = cx;
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cv = cx;
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cv = cx;
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cv = cx;
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cv = cx;
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cv = cx;
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cv = cx;
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cv = cx;
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cv = cx;
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cv = cx;
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cv = cx;
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cv = cx;
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cv = cx;
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cv = cx;
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cv = cx;
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cv = cx;
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cv = cx;
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cv = cx;
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cv = cx;
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cv = cx;
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cv = cx;
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cv = cx;
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cv = cx;
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cv = cx;
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cv = cx;
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cv = cx;
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cv = cx;
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cv = cx;
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cv = cx;
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ce > cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (cx > ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ce < cx) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (cx < ce) {
|
|
cx = ce;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
}
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (cx == ce) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (ce == cx) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cr = cx == ce;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cr = ce == cx;
|
|
if (cr) {
|
|
cx = cd;
|
|
} else {
|
|
cv = cx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucv = ucx;
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucv = ucx;
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucv = ucx;
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucv = ucx;
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucv = ucx;
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucv = ucx;
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucv = ucx;
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucv = ucx;
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucv = ucx;
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucv = ucx;
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucv = ucx;
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucv = ucx;
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucv = ucx;
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucv = ucx;
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucv = ucx;
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucv = ucx;
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucv = ucx;
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucv = ucx;
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucv = ucx;
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucv = ucx;
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucv = ucx;
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucv = ucx;
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucv = ucx;
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucv = ucx;
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucv = ucx;
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucv = ucx;
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucv = ucx;
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucv = ucx;
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucv = ucx;
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucv = ucx;
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucv = ucx;
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucv = ucx;
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucv = ucx;
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucv = ucx;
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucv = ucx;
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucv = ucx;
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (uce > ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ucx > uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (uce < ucx) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ucx < uce) {
|
|
ucx = uce;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
}
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (ucx == uce) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (uce == ucx) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucr = ucx == uce;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucr = uce == ucx;
|
|
if (ucr) {
|
|
ucx = ucd;
|
|
} else {
|
|
ucv = ucx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sv = sx;
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sv = sx;
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sv = sx;
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sv = sx;
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sv = sx;
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sv = sx;
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (sx == se) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (se == sx) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sv = sx;
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sv = sx;
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sv = sx;
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sv = sx;
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sv = sx;
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sv = sx;
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (sx == se) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (se == sx) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sv = sx;
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sv = sx;
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sv = sx;
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sv = sx;
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sv = sx;
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sv = sx;
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (sx == se) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (se == sx) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sv = sx;
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sv = sx;
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sv = sx;
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sv = sx;
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sv = sx;
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sv = sx;
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (sx == se) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (se == sx) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sv = sx;
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sv = sx;
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sv = sx;
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sv = sx;
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sv = sx;
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sv = sx;
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (sx == se) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (se == sx) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sv = sx;
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sv = sx;
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sv = sx;
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sv = sx;
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sv = sx;
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sv = sx;
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (se > sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (sx > se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (se < sx) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (sx < se) {
|
|
sx = se;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (sx == se) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (se == sx) {
|
|
sx = sd;
|
|
}
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (sx == se) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (se == sx) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sr = sx == se;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sr = se == sx;
|
|
if (sr) {
|
|
sx = sd;
|
|
} else {
|
|
sv = sx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usv = usx;
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usv = usx;
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usv = usx;
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usv = usx;
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usv = usx;
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usv = usx;
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (usx == use) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (use == usx) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usv = usx;
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usv = usx;
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usv = usx;
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usv = usx;
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usv = usx;
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usv = usx;
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (usx == use) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (use == usx) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usv = usx;
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usv = usx;
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usv = usx;
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usv = usx;
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usv = usx;
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usv = usx;
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (usx == use) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (use == usx) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usv = usx;
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usv = usx;
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usv = usx;
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usv = usx;
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usv = usx;
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usv = usx;
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (usx == use) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (use == usx) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usv = usx;
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usv = usx;
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usv = usx;
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usv = usx;
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usv = usx;
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usv = usx;
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (usx == use) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (use == usx) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usv = usx;
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usv = usx;
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usv = usx;
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usv = usx;
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usv = usx;
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usv = usx;
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (use > usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (usx > use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (use < usx) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (usx < use) {
|
|
usx = use;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (usx == use) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (use == usx) {
|
|
usx = usd;
|
|
}
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (usx == use) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (use == usx) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usr = usx == use;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usr = use == usx;
|
|
if (usr) {
|
|
usx = usd;
|
|
} else {
|
|
usv = usx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
iv = ix;
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
iv = ix;
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
iv = ix;
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
iv = ix;
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
iv = ix;
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
iv = ix;
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (ix == ie) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (ie == ix) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
iv = ix;
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
iv = ix;
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
iv = ix;
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
iv = ix;
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
iv = ix;
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
iv = ix;
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (ix == ie) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (ie == ix) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
iv = ix;
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
iv = ix;
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
iv = ix;
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
iv = ix;
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
iv = ix;
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
iv = ix;
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (ix == ie) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (ie == ix) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
iv = ix;
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
iv = ix;
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
iv = ix;
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
iv = ix;
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
iv = ix;
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
iv = ix;
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (ix == ie) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (ie == ix) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
iv = ix;
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
iv = ix;
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
iv = ix;
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
iv = ix;
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
iv = ix;
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
iv = ix;
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (ix == ie) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (ie == ix) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
iv = ix;
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
iv = ix;
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
iv = ix;
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
iv = ix;
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
iv = ix;
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
iv = ix;
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ie > ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ix > ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ie < ix) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ix < ie) {
|
|
ix = ie;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ix == ie) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ie == ix) {
|
|
ix = id;
|
|
}
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (ix == ie) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (ie == ix) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = ix == ie;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = ie == ix;
|
|
if (ir) {
|
|
ix = id;
|
|
} else {
|
|
iv = ix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uiv = uix;
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uiv = uix;
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uiv = uix;
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uiv = uix;
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uiv = uix;
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uiv = uix;
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uiv = uix;
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uiv = uix;
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uiv = uix;
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uiv = uix;
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uiv = uix;
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uiv = uix;
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uiv = uix;
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uiv = uix;
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uiv = uix;
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uiv = uix;
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uiv = uix;
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uiv = uix;
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uiv = uix;
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uiv = uix;
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uiv = uix;
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uiv = uix;
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uiv = uix;
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uiv = uix;
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uiv = uix;
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uiv = uix;
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uiv = uix;
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uiv = uix;
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uiv = uix;
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uiv = uix;
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uiv = uix;
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uiv = uix;
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uiv = uix;
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uiv = uix;
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uiv = uix;
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uiv = uix;
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (uie > uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (uix > uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (uie < uix) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (uix < uie) {
|
|
uix = uie;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
}
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (uix == uie) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (uie == uix) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uir = uix == uie;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uir = uie == uix;
|
|
if (uir) {
|
|
uix = uid;
|
|
} else {
|
|
uiv = uix;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lv = lx;
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lv = lx;
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lv = lx;
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lv = lx;
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lv = lx;
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lv = lx;
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (lx == le) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (le == lx) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lv = lx;
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lv = lx;
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lv = lx;
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lv = lx;
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lv = lx;
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lv = lx;
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (lx == le) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (le == lx) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lv = lx;
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lv = lx;
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lv = lx;
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lv = lx;
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lv = lx;
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lv = lx;
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (lx == le) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (le == lx) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lv = lx;
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lv = lx;
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lv = lx;
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lv = lx;
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lv = lx;
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lv = lx;
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (lx == le) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (le == lx) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lv = lx;
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lv = lx;
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lv = lx;
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lv = lx;
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lv = lx;
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lv = lx;
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (lx == le) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (le == lx) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lv = lx;
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lv = lx;
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lv = lx;
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lv = lx;
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lv = lx;
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lv = lx;
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (le > lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (lx > le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (le < lx) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (lx < le) {
|
|
lx = le;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (lx == le) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (le == lx) {
|
|
lx = ld;
|
|
}
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (lx == le) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (le == lx) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lr = lx == le;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lr = le == lx;
|
|
if (lr) {
|
|
lx = ld;
|
|
} else {
|
|
lv = lx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulv = ulx;
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulv = ulx;
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulv = ulx;
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulv = ulx;
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulv = ulx;
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulv = ulx;
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulv = ulx;
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulv = ulx;
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulv = ulx;
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulv = ulx;
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulv = ulx;
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulv = ulx;
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulv = ulx;
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulv = ulx;
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulv = ulx;
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulv = ulx;
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulv = ulx;
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulv = ulx;
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulv = ulx;
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulv = ulx;
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulv = ulx;
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulv = ulx;
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulv = ulx;
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulv = ulx;
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulv = ulx;
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulv = ulx;
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulv = ulx;
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulv = ulx;
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulv = ulx;
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulv = ulx;
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulv = ulx;
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulv = ulx;
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulv = ulx;
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulv = ulx;
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulv = ulx;
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulv = ulx;
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ule > ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ulx > ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ule < ulx) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ulx < ule) {
|
|
ulx = ule;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
}
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (ulx == ule) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (ule == ulx) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulr = ulx == ule;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulr = ule == ulx;
|
|
if (ulr) {
|
|
ulx = uld;
|
|
} else {
|
|
ulv = ulx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llv = llx;
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llv = llx;
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llv = llx;
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llv = llx;
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llv = llx;
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llv = llx;
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llv = llx;
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llv = llx;
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llv = llx;
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llv = llx;
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llv = llx;
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llv = llx;
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llv = llx;
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llv = llx;
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llv = llx;
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llv = llx;
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llv = llx;
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llv = llx;
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llv = llx;
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llv = llx;
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llv = llx;
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llv = llx;
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llv = llx;
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llv = llx;
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llv = llx;
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llv = llx;
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llv = llx;
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llv = llx;
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llv = llx;
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llv = llx;
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llv = llx;
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llv = llx;
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llv = llx;
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llv = llx;
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llv = llx;
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llv = llx;
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (lle > llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (llx > lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (lle < llx) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (llx < lle) {
|
|
llx = lle;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
}
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (llx == lle) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (lle == llx) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llr = llx == lle;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llr = lle == llx;
|
|
if (llr) {
|
|
llx = lld;
|
|
} else {
|
|
llv = llx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullv = ullx;
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullv = ullx;
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullv = ullx;
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullv = ullx;
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullv = ullx;
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullv = ullx;
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullv = ullx;
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullv = ullx;
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullv = ullx;
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullv = ullx;
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullv = ullx;
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullv = ullx;
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullv = ullx;
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullv = ullx;
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullv = ullx;
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullv = ullx;
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullv = ullx;
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullv = ullx;
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullv = ullx;
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullv = ullx;
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullv = ullx;
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullv = ullx;
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullv = ullx;
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullv = ullx;
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullv = ullx;
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullv = ullx;
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullv = ullx;
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullv = ullx;
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullv = ullx;
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullv = ullx;
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullv = ullx;
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullv = ullx;
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullv = ullx;
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullv = ullx;
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullv = ullx;
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullv = ullx;
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ulle > ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ullx > ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ulle < ullx) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ullx < ulle) {
|
|
ullx = ulle;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
}
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (ullx == ulle) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (ulle == ullx) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullr = ullx == ulle;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullr = ulle == ullx;
|
|
if (ullr) {
|
|
ullx = ulld;
|
|
} else {
|
|
ullv = ullx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fv = fx;
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fv = fx;
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fv = fx;
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fv = fx;
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fv = fx;
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fv = fx;
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fv = fx;
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fv = fx;
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fv = fx;
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fv = fx;
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fv = fx;
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fv = fx;
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fv = fx;
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fv = fx;
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fv = fx;
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fv = fx;
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fv = fx;
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fv = fx;
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fv = fx;
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fv = fx;
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fv = fx;
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fv = fx;
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fv = fx;
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fv = fx;
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fv = fx;
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fv = fx;
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fv = fx;
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fv = fx;
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fv = fx;
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fv = fx;
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fv = fx;
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fv = fx;
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fv = fx;
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fv = fx;
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fv = fx;
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fv = fx;
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (fe > fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (fx > fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (fe < fx) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (fx < fe) {
|
|
fx = fe;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
}
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (fx == fe) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (fe == fx) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = fx == fe;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = fe == fx;
|
|
if (ir) {
|
|
fx = fd;
|
|
} else {
|
|
fv = fx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dv = dx;
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dv = dx;
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dv = dx;
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dv = dx;
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dv = dx;
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dv = dx;
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (dx == de) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
if (de == dx) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dv = dx;
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dv = dx;
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dv = dx;
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dv = dx;
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dv = dx;
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dv = dx;
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (dx == de) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
if (de == dx) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dv = dx;
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dv = dx;
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dv = dx;
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dv = dx;
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dv = dx;
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dv = dx;
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (dx == de) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
if (de == dx) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dv = dx;
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dv = dx;
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dv = dx;
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dv = dx;
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dv = dx;
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dv = dx;
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (dx == de) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
if (de == dx) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dv = dx;
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dv = dx;
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dv = dx;
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dv = dx;
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dv = dx;
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dv = dx;
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (dx == de) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
if (de == dx) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dv = dx;
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dv = dx;
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dv = dx;
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dv = dx;
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dv = dx;
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dv = dx;
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (de > dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (dx > de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (de < dx) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (dx < de) {
|
|
dx = de;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (dx == de) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
if (de == dx) {
|
|
dx = dd;
|
|
}
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (dx == de) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
if (de == dx) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = dx == de;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ir = de == dx;
|
|
if (ir) {
|
|
dx = dd;
|
|
} else {
|
|
dv = dx;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
char cxevd() {
|
|
char cx, cv, ce, cd;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cv = cx;
|
|
cx = cx > ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cv = cx;
|
|
cx = cx < ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cv = cx;
|
|
cx = cx == ce ? cd : cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cx = cx > ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cx = cx < ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
cx = cx == ce ? cd : cx;
|
|
cv = cx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cv = cx;
|
|
cx = cx > ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cv = cx;
|
|
cx = cx < ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cv = cx;
|
|
cx = cx == ce ? cd : cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cx = cx > ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cx = cx < ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
cx = cx == ce ? cd : cx;
|
|
cv = cx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cv = cx;
|
|
cx = cx > ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cv = cx;
|
|
cx = cx < ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cv = cx;
|
|
cx = cx == ce ? cd : cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cx = cx > ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cx = cx < ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
cx = cx == ce ? cd : cx;
|
|
cv = cx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cv = cx;
|
|
cx = cx > ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cv = cx;
|
|
cx = cx < ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cv = cx;
|
|
cx = cx == ce ? cd : cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cx = cx > ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cx = cx < ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
cx = cx == ce ? cd : cx;
|
|
cv = cx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cv = cx;
|
|
cx = cx > ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cv = cx;
|
|
cx = cx < ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cv = cx;
|
|
cx = cx == ce ? cd : cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cx = cx > ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cx = cx < ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
cx = cx == ce ? cd : cx;
|
|
cv = cx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cv = cx;
|
|
cx = cx > ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cv = cx;
|
|
cx = cx < ce ? ce : cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cv = cx;
|
|
cx = cx == ce ? cd : cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cx = cx > ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cx = cx < ce ? ce : cx;
|
|
cv = cx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
cx = cx == ce ? cd : cx;
|
|
cv = cx;
|
|
}
|
|
|
|
return cv;
|
|
}
|
|
|
|
unsigned char ucxevd() {
|
|
unsigned char ucx, ucv, uce, ucd;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx > uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx < uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucx = ucx > uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucx = ucx < uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
ucv = ucx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx > uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx < uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucx = ucx > uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucx = ucx < uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
ucv = ucx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx > uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx < uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucx = ucx > uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucx = ucx < uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
ucv = ucx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx > uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx < uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucx = ucx > uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucx = ucx < uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
ucv = ucx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx > uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx < uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucx = ucx > uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucx = ucx < uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
ucv = ucx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx > uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx < uce ? uce : ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucv = ucx;
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucx = ucx > uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucx = ucx < uce ? uce : ucx;
|
|
ucv = ucx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ucx = ucx == uce ? ucd : ucx;
|
|
ucv = ucx;
|
|
}
|
|
|
|
return ucv;
|
|
}
|
|
|
|
short sxevd() {
|
|
short sx, sv, se, sd;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sv = sx;
|
|
sx = sx > se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sv = sx;
|
|
sx = sx < se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sv = sx;
|
|
sx = sx == se ? sd : sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sx = sx > se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sx = sx < se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
sx = sx == se ? sd : sx;
|
|
sv = sx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sv = sx;
|
|
sx = sx > se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sv = sx;
|
|
sx = sx < se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sv = sx;
|
|
sx = sx == se ? sd : sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sx = sx > se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sx = sx < se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
sx = sx == se ? sd : sx;
|
|
sv = sx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sv = sx;
|
|
sx = sx > se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sv = sx;
|
|
sx = sx < se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sv = sx;
|
|
sx = sx == se ? sd : sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sx = sx > se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sx = sx < se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
sx = sx == se ? sd : sx;
|
|
sv = sx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sv = sx;
|
|
sx = sx > se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sv = sx;
|
|
sx = sx < se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sv = sx;
|
|
sx = sx == se ? sd : sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sx = sx > se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sx = sx < se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
sx = sx == se ? sd : sx;
|
|
sv = sx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sv = sx;
|
|
sx = sx > se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sv = sx;
|
|
sx = sx < se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sv = sx;
|
|
sx = sx == se ? sd : sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sx = sx > se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sx = sx < se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
sx = sx == se ? sd : sx;
|
|
sv = sx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sv = sx;
|
|
sx = sx > se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sv = sx;
|
|
sx = sx < se ? se : sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sv = sx;
|
|
sx = sx == se ? sd : sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sx = sx > se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sx = sx < se ? se : sx;
|
|
sv = sx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
sx = sx == se ? sd : sx;
|
|
sv = sx;
|
|
}
|
|
|
|
return sv;
|
|
}
|
|
|
|
unsigned short usxevd() {
|
|
unsigned short usx, usv, use, usd;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usv = usx;
|
|
usx = usx > use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usv = usx;
|
|
usx = usx < use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usv = usx;
|
|
usx = usx == use ? usd : usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usx = usx > use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usx = usx < use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
usx = usx == use ? usd : usx;
|
|
usv = usx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usv = usx;
|
|
usx = usx > use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usv = usx;
|
|
usx = usx < use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usv = usx;
|
|
usx = usx == use ? usd : usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usx = usx > use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usx = usx < use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
usx = usx == use ? usd : usx;
|
|
usv = usx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usv = usx;
|
|
usx = usx > use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usv = usx;
|
|
usx = usx < use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usv = usx;
|
|
usx = usx == use ? usd : usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usx = usx > use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usx = usx < use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
usx = usx == use ? usd : usx;
|
|
usv = usx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usv = usx;
|
|
usx = usx > use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usv = usx;
|
|
usx = usx < use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usv = usx;
|
|
usx = usx == use ? usd : usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usx = usx > use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usx = usx < use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
usx = usx == use ? usd : usx;
|
|
usv = usx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usv = usx;
|
|
usx = usx > use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usv = usx;
|
|
usx = usx < use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usv = usx;
|
|
usx = usx == use ? usd : usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usx = usx > use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usx = usx < use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
usx = usx == use ? usd : usx;
|
|
usv = usx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usv = usx;
|
|
usx = usx > use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usv = usx;
|
|
usx = usx < use ? use : usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usv = usx;
|
|
usx = usx == use ? usd : usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usx = usx > use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usx = usx < use ? use : usx;
|
|
usv = usx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
usx = usx == use ? usd : usx;
|
|
usv = usx;
|
|
}
|
|
|
|
return usv;
|
|
}
|
|
|
|
int ixevd() {
|
|
int ix, iv, ie, id;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
iv = ix;
|
|
ix = ix > ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
iv = ix;
|
|
ix = ix < ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
iv = ix;
|
|
ix = ix == ie ? id : ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ix = ix > ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ix = ix < ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ix = ix == ie ? id : ix;
|
|
iv = ix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
iv = ix;
|
|
ix = ix > ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
iv = ix;
|
|
ix = ix < ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
iv = ix;
|
|
ix = ix == ie ? id : ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ix = ix > ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ix = ix < ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ix = ix == ie ? id : ix;
|
|
iv = ix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
iv = ix;
|
|
ix = ix > ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
iv = ix;
|
|
ix = ix < ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
iv = ix;
|
|
ix = ix == ie ? id : ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ix = ix > ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ix = ix < ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ix = ix == ie ? id : ix;
|
|
iv = ix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
iv = ix;
|
|
ix = ix > ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
iv = ix;
|
|
ix = ix < ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
iv = ix;
|
|
ix = ix == ie ? id : ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ix = ix > ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ix = ix < ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ix = ix == ie ? id : ix;
|
|
iv = ix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
iv = ix;
|
|
ix = ix > ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
iv = ix;
|
|
ix = ix < ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
iv = ix;
|
|
ix = ix == ie ? id : ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ix = ix > ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ix = ix < ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ix = ix == ie ? id : ix;
|
|
iv = ix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
iv = ix;
|
|
ix = ix > ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
iv = ix;
|
|
ix = ix < ie ? ie : ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
iv = ix;
|
|
ix = ix == ie ? id : ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ix = ix > ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ix = ix < ie ? ie : ix;
|
|
iv = ix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ix = ix == ie ? id : ix;
|
|
iv = ix;
|
|
}
|
|
|
|
return iv;
|
|
}
|
|
|
|
unsigned int uixevd() {
|
|
unsigned int uix, uiv, uie, uid;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uiv = uix;
|
|
uix = uix > uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uiv = uix;
|
|
uix = uix < uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uiv = uix;
|
|
uix = uix == uie ? uid : uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uix = uix > uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uix = uix < uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
uix = uix == uie ? uid : uix;
|
|
uiv = uix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uiv = uix;
|
|
uix = uix > uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uiv = uix;
|
|
uix = uix < uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uiv = uix;
|
|
uix = uix == uie ? uid : uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uix = uix > uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uix = uix < uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
uix = uix == uie ? uid : uix;
|
|
uiv = uix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uiv = uix;
|
|
uix = uix > uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uiv = uix;
|
|
uix = uix < uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uiv = uix;
|
|
uix = uix == uie ? uid : uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uix = uix > uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uix = uix < uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
uix = uix == uie ? uid : uix;
|
|
uiv = uix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uiv = uix;
|
|
uix = uix > uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uiv = uix;
|
|
uix = uix < uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uiv = uix;
|
|
uix = uix == uie ? uid : uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uix = uix > uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uix = uix < uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
uix = uix == uie ? uid : uix;
|
|
uiv = uix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uiv = uix;
|
|
uix = uix > uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uiv = uix;
|
|
uix = uix < uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uiv = uix;
|
|
uix = uix == uie ? uid : uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uix = uix > uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uix = uix < uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
uix = uix == uie ? uid : uix;
|
|
uiv = uix;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uiv = uix;
|
|
uix = uix > uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uiv = uix;
|
|
uix = uix < uie ? uie : uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uiv = uix;
|
|
uix = uix == uie ? uid : uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uix = uix > uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uix = uix < uie ? uie : uix;
|
|
uiv = uix;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
uix = uix == uie ? uid : uix;
|
|
uiv = uix;
|
|
}
|
|
|
|
return uiv;
|
|
}
|
|
|
|
long lxevd() {
|
|
long lx, lv, le, ld;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lv = lx;
|
|
lx = lx > le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lv = lx;
|
|
lx = lx < le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lv = lx;
|
|
lx = lx == le ? ld : lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lx = lx > le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lx = lx < le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
lx = lx == le ? ld : lx;
|
|
lv = lx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lv = lx;
|
|
lx = lx > le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lv = lx;
|
|
lx = lx < le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lv = lx;
|
|
lx = lx == le ? ld : lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lx = lx > le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lx = lx < le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
lx = lx == le ? ld : lx;
|
|
lv = lx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lv = lx;
|
|
lx = lx > le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lv = lx;
|
|
lx = lx < le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lv = lx;
|
|
lx = lx == le ? ld : lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lx = lx > le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lx = lx < le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
lx = lx == le ? ld : lx;
|
|
lv = lx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lv = lx;
|
|
lx = lx > le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lv = lx;
|
|
lx = lx < le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lv = lx;
|
|
lx = lx == le ? ld : lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lx = lx > le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lx = lx < le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
lx = lx == le ? ld : lx;
|
|
lv = lx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lv = lx;
|
|
lx = lx > le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lv = lx;
|
|
lx = lx < le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lv = lx;
|
|
lx = lx == le ? ld : lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lx = lx > le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lx = lx < le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
lx = lx == le ? ld : lx;
|
|
lv = lx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lv = lx;
|
|
lx = lx > le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lv = lx;
|
|
lx = lx < le ? le : lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lv = lx;
|
|
lx = lx == le ? ld : lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lx = lx > le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lx = lx < le ? le : lx;
|
|
lv = lx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
lx = lx == le ? ld : lx;
|
|
lv = lx;
|
|
}
|
|
|
|
return lv;
|
|
}
|
|
|
|
unsigned long ulxevd() {
|
|
unsigned long ulx, ulv, ule, uld;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx > ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx < ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx == ule ? uld : ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulx = ulx > ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulx = ulx < ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ulx = ulx == ule ? uld : ulx;
|
|
ulv = ulx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx > ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx < ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx == ule ? uld : ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulx = ulx > ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulx = ulx < ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ulx = ulx == ule ? uld : ulx;
|
|
ulv = ulx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx > ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx < ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx == ule ? uld : ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulx = ulx > ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulx = ulx < ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ulx = ulx == ule ? uld : ulx;
|
|
ulv = ulx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx > ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx < ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx == ule ? uld : ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulx = ulx > ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulx = ulx < ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ulx = ulx == ule ? uld : ulx;
|
|
ulv = ulx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx > ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx < ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx == ule ? uld : ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulx = ulx > ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulx = ulx < ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ulx = ulx == ule ? uld : ulx;
|
|
ulv = ulx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx > ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx < ule ? ule : ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulv = ulx;
|
|
ulx = ulx == ule ? uld : ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulx = ulx > ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulx = ulx < ule ? ule : ulx;
|
|
ulv = ulx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ulx = ulx == ule ? uld : ulx;
|
|
ulv = ulx;
|
|
}
|
|
|
|
return ulv;
|
|
}
|
|
|
|
long long llxevd() {
|
|
long long llx, llv, lle, lld;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llv = llx;
|
|
llx = llx > lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llv = llx;
|
|
llx = llx < lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llv = llx;
|
|
llx = llx == lle ? lld : llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llx = llx > lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llx = llx < lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
llx = llx == lle ? lld : llx;
|
|
llv = llx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llv = llx;
|
|
llx = llx > lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llv = llx;
|
|
llx = llx < lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llv = llx;
|
|
llx = llx == lle ? lld : llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llx = llx > lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llx = llx < lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
llx = llx == lle ? lld : llx;
|
|
llv = llx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llv = llx;
|
|
llx = llx > lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llv = llx;
|
|
llx = llx < lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llv = llx;
|
|
llx = llx == lle ? lld : llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llx = llx > lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llx = llx < lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
llx = llx == lle ? lld : llx;
|
|
llv = llx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llv = llx;
|
|
llx = llx > lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llv = llx;
|
|
llx = llx < lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llv = llx;
|
|
llx = llx == lle ? lld : llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llx = llx > lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llx = llx < lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
llx = llx == lle ? lld : llx;
|
|
llv = llx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llv = llx;
|
|
llx = llx > lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llv = llx;
|
|
llx = llx < lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llv = llx;
|
|
llx = llx == lle ? lld : llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llx = llx > lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llx = llx < lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
llx = llx == lle ? lld : llx;
|
|
llv = llx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llv = llx;
|
|
llx = llx > lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llv = llx;
|
|
llx = llx < lle ? lle : llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llv = llx;
|
|
llx = llx == lle ? lld : llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llx = llx > lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llx = llx < lle ? lle : llx;
|
|
llv = llx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
llx = llx == lle ? lld : llx;
|
|
llv = llx;
|
|
}
|
|
|
|
return llv;
|
|
}
|
|
|
|
unsigned long long ullxevd() {
|
|
unsigned long long ullx, ullv, ulle, ulld;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
ullv = ullx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
ullv = ullx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
ullv = ullx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
ullv = ullx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
ullv = ullx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullv = ullx;
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullx = ullx > ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullx = ullx < ulle ? ulle : ullx;
|
|
ullv = ullx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
ullx = ullx == ulle ? ulld : ullx;
|
|
ullv = ullx;
|
|
}
|
|
|
|
return ullv;
|
|
}
|
|
|
|
float fxevd() {
|
|
float fx, fv, fe, fd;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fv = fx;
|
|
fx = fx > fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fv = fx;
|
|
fx = fx < fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fv = fx;
|
|
fx = fx == fe ? fd : fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fx = fx > fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fx = fx < fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
fx = fx == fe ? fd : fx;
|
|
fv = fx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fv = fx;
|
|
fx = fx > fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fv = fx;
|
|
fx = fx < fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fv = fx;
|
|
fx = fx == fe ? fd : fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fx = fx > fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fx = fx < fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
fx = fx == fe ? fd : fx;
|
|
fv = fx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fv = fx;
|
|
fx = fx > fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fv = fx;
|
|
fx = fx < fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fv = fx;
|
|
fx = fx == fe ? fd : fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fx = fx > fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fx = fx < fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
fx = fx == fe ? fd : fx;
|
|
fv = fx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fv = fx;
|
|
fx = fx > fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fv = fx;
|
|
fx = fx < fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fv = fx;
|
|
fx = fx == fe ? fd : fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fx = fx > fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fx = fx < fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
fx = fx == fe ? fd : fx;
|
|
fv = fx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fv = fx;
|
|
fx = fx > fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fv = fx;
|
|
fx = fx < fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fv = fx;
|
|
fx = fx == fe ? fd : fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fx = fx > fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fx = fx < fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
fx = fx == fe ? fd : fx;
|
|
fv = fx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fv = fx;
|
|
fx = fx > fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fv = fx;
|
|
fx = fx < fe ? fe : fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fv = fx;
|
|
fx = fx == fe ? fd : fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fx = fx > fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fx = fx < fe ? fe : fx;
|
|
fv = fx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
fx = fx == fe ? fd : fx;
|
|
fv = fx;
|
|
}
|
|
|
|
return fv;
|
|
}
|
|
|
|
double dxevd() {
|
|
double dx, dv, de, dd;
|
|
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dv = dx;
|
|
dx = dx > de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dv = dx;
|
|
dx = dx < de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dv = dx;
|
|
dx = dx == de ? dd : dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dx = dx > de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dx = dx < de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture
|
|
{
|
|
dx = dx == de ? dd : dx;
|
|
dv = dx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dv = dx;
|
|
dx = dx > de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dv = dx;
|
|
dx = dx < de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dv = dx;
|
|
dx = dx == de ? dd : dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dx = dx > de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dx = dx < de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acq_rel
|
|
{
|
|
dx = dx == de ? dd : dx;
|
|
dv = dx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dv = dx;
|
|
dx = dx > de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dv = dx;
|
|
dx = dx < de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dv = dx;
|
|
dx = dx == de ? dd : dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dx = dx > de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dx = dx < de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture acquire
|
|
{
|
|
dx = dx == de ? dd : dx;
|
|
dv = dx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dv = dx;
|
|
dx = dx > de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dv = dx;
|
|
dx = dx < de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dv = dx;
|
|
dx = dx == de ? dd : dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dx = dx > de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dx = dx < de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture relaxed
|
|
{
|
|
dx = dx == de ? dd : dx;
|
|
dv = dx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dv = dx;
|
|
dx = dx > de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dv = dx;
|
|
dx = dx < de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dv = dx;
|
|
dx = dx == de ? dd : dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dx = dx > de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dx = dx < de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture release
|
|
{
|
|
dx = dx == de ? dd : dx;
|
|
dv = dx;
|
|
}
|
|
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dv = dx;
|
|
dx = dx > de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dv = dx;
|
|
dx = dx < de ? de : dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dv = dx;
|
|
dx = dx == de ? dd : dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dx = dx > de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dx = dx < de ? de : dx;
|
|
dv = dx;
|
|
}
|
|
#pragma omp atomic compare capture seq_cst
|
|
{
|
|
dx = dx == de ? dd : dx;
|
|
dv = dx;
|
|
}
|
|
|
|
return dv;
|
|
}
|
|
|
|
#endif
|
|
// CHECK-LABEL: @foo(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[CX:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[CE:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[CD:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCX:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCE:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCD:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[SX:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[SE:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[SD:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USX:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USE:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USD:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[IX:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[IE:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[ID:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UIX:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UIE:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UID:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[LX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[FX:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[FE:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[FD:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[DX:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[DE:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[DD:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP0]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP2]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP5:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP4]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP6]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP8]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP10]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP12]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP15:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP14]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP19]], i8 [[TMP20]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP23:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP24:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP22]], i8 [[TMP23]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP25:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP27:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP25]], i8 [[TMP26]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP28:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP29:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP28]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP30]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP32:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP32]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP34]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP37:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP36]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP38]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP40:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP41:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP40]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP42:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP42]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP45:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP46:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP44]], i8 [[TMP45]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP47:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP49:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP47]], i8 [[TMP48]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP50:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP51:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP52:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP50]], i8 [[TMP51]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP53:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP54:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP55:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP53]], i8 [[TMP54]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP56]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1:[0-9]+]])
|
|
// CHECK-NEXT: [[TMP58:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP58]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP61:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP60]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP62:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP63:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP62]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP64]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP66]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP68]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP70]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP72:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP73:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP74:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP72]], i8 [[TMP73]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP75:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP76:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP77:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP75]], i8 [[TMP76]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP79:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP80:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP78]], i8 [[TMP79]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP81:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP83:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP81]], i8 [[TMP82]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP84:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP85:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP84]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP86:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP86]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP88]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP90]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP93:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP92]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP94:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP95:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP94]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP96]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP98:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP99:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP98]] acq_rel, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP101:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP102:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP100]], i8 [[TMP101]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP103:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP105:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP103]], i8 [[TMP104]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP106:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP107:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP108:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP106]], i8 [[TMP107]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP109:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP111:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP109]], i8 [[TMP110]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP112]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP115:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP114]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP117:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP116]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP118]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP120:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP121:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP120]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP122]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP124:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP125:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP124]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP127:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP126]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP128:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP129:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP130:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP128]], i8 [[TMP129]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP133:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP131]], i8 [[TMP132]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP134:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP135:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP136:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP134]], i8 [[TMP135]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP137:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP138:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP139:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP137]], i8 [[TMP138]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP140:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP141:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP140]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP142:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP143:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP142]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP144:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP145:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP144]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP146:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP147:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP146]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP148:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP149:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP148]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP150:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP151:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP150]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP152:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP153:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP152]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP154:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP155:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP154]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP156:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP157:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP158:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP156]], i8 [[TMP157]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP159:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP160:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP161:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP159]], i8 [[TMP160]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP162:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP163:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP164:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP162]], i8 [[TMP163]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP165:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP166:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP167:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP165]], i8 [[TMP166]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP168:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP169:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP168]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP170:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP171:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP170]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP173:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP172]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP174:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP175:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP174]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP177:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP176]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP178:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP179:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP178]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP181:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP180]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP182:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP183:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP182]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP184:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP185:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP186:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP184]], i8 [[TMP185]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP187:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP188:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP189:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP187]], i8 [[TMP188]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP190:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP191:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP192:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP190]], i8 [[TMP191]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP193:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP194:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP195:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP193]], i8 [[TMP194]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP196:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP197:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP196]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP198:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP199:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP198]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP200:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP201:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP200]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP202:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP203:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP202]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP204:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP205:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP204]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP206:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP207:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP206]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP208:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP209:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP208]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP210:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP211:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP210]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP212:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP213:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP214:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP212]], i8 [[TMP213]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP215:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP216:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP217:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP215]], i8 [[TMP216]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP218:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP219:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP220:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP218]], i8 [[TMP219]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP221:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP222:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP223:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP221]], i8 [[TMP222]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP224:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP225:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP224]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP226:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP227:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP226]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP228:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP229:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP228]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP230:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP231:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP230]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP232:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP233:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP232]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP234:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP235:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP234]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP236:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP237:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP236]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP238:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP239:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP238]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP240:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP241:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP242:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP240]], i8 [[TMP241]] release monotonic, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP243:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP244:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP245:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP243]], i8 [[TMP244]] release monotonic, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP246:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP247:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP248:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP246]], i8 [[TMP247]] release monotonic, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP249:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP250:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP251:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP249]], i8 [[TMP250]] release monotonic, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP252:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP253:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP252]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP254:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP255:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP254]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP256:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP257:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP256]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP258:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP259:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP258]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP260:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP261:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP260]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP262:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP263:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP262]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP264:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP265:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP264]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP266:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP267:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP266]] release, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP268:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP269:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP270:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP268]], i8 [[TMP269]] release monotonic, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP271:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP272:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP273:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP271]], i8 [[TMP272]] release monotonic, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP274:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP275:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP276:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP274]], i8 [[TMP275]] release monotonic, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP277:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP278:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP279:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP277]], i8 [[TMP278]] release monotonic, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP280:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP281:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP280]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP282:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP283:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP282]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP284:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP285:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP284]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP286:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP287:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP286]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP288:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP289:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP288]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP290:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP291:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP290]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP292:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP293:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP292]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP294:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP295:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP294]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP296:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP297:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP298:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP296]], i8 [[TMP297]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP299:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP300:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP301:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP299]], i8 [[TMP300]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP302:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP303:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP304:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP302]], i8 [[TMP303]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP305:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP306:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP307:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP305]], i8 [[TMP306]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP308:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP309:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP308]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP310:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP311:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP310]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP312:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP313:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP312]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP314:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP315:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP314]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP316:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP317:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP316]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP318:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP319:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP318]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP320:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP321:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP320]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP322:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP323:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP322]] seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP324:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP325:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP326:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP324]], i8 [[TMP325]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP327:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP328:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP329:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP327]], i8 [[TMP328]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP330:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP331:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP332:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP330]], i8 [[TMP331]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP333:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP334:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP335:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP333]], i8 [[TMP334]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP336:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP337:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP336]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP338:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP339:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP338]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP340:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP341:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP340]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP342:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP343:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP342]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP344:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP345:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP344]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP346:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP347:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP346]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP348:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP349:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP348]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP350:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP351:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP350]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP352:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP353:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP354:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP352]], i16 [[TMP353]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP355:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP356:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP357:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP355]], i16 [[TMP356]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP358:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP359:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP360:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP358]], i16 [[TMP359]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP361:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP362:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP363:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP361]], i16 [[TMP362]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP364:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP365:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP364]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP366:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP367:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP366]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP368:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP369:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP368]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP370:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP371:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP370]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP372:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP373:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP372]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP374:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP375:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP374]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP376:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP377:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP376]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP378:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP379:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP378]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP380:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP381:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP382:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP380]], i16 [[TMP381]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP383:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP384:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP385:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP383]], i16 [[TMP384]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP386:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP387:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP388:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP386]], i16 [[TMP387]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP389:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP390:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP391:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP389]], i16 [[TMP390]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP392:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP393:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP392]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP394:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP395:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP394]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP396:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP397:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP396]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP398:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP399:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP398]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP400:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP401:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP400]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP402:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP403:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP402]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP404:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP405:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP404]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP406:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP407:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP406]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP408:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP409:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP410:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP408]], i16 [[TMP409]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP411:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP412:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP413:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP411]], i16 [[TMP412]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP414:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP415:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP416:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP414]], i16 [[TMP415]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP417:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP418:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP419:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP417]], i16 [[TMP418]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP420:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP421:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP420]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP422:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP423:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP422]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP424:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP425:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP424]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP426:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP427:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP426]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP428:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP429:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP428]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP430:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP431:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP430]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP432:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP433:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP432]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP434:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP435:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP434]] acq_rel, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP436:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP437:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP438:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP436]], i16 [[TMP437]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP439:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP440:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP441:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP439]], i16 [[TMP440]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP442:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP443:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP444:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP442]], i16 [[TMP443]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP445:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP446:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP447:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP445]], i16 [[TMP446]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP448:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP449:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP448]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP450:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP451:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP450]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP452:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP453:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP452]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP454:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP455:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP454]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP456:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP457:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP456]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP458:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP459:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP458]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP460:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP461:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP460]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP462:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP463:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP462]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP464:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP465:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP466:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP464]], i16 [[TMP465]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP467:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP468:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP469:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP467]], i16 [[TMP468]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP470:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP471:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP472:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP470]], i16 [[TMP471]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP473:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP474:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP475:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP473]], i16 [[TMP474]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP476:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP477:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP476]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP478:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP479:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP478]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP480:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP481:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP480]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP482:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP483:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP482]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP484:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP485:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP484]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP486:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP487:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP486]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP488:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP489:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP488]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP490:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP491:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP490]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP492:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP493:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP494:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP492]], i16 [[TMP493]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP495:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP496:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP497:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP495]], i16 [[TMP496]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP498:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP499:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP500:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP498]], i16 [[TMP499]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP501:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP502:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP503:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP501]], i16 [[TMP502]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP504:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP505:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP504]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP506:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP507:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP506]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP508:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP509:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP508]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP510:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP511:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP510]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP512:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP513:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP512]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP514:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP515:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP514]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP516:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP517:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP516]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP518:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP519:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP518]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP520:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP521:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP522:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP520]], i16 [[TMP521]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP523:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP524:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP525:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP523]], i16 [[TMP524]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP526:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP527:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP528:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP526]], i16 [[TMP527]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP529:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP530:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP531:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP529]], i16 [[TMP530]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP532:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP533:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP532]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP534:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP535:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP534]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP536:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP537:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP536]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP538:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP539:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP538]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP540:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP541:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP540]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP542:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP543:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP542]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP544:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP545:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP544]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP546:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP547:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP546]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP548:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP549:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP550:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP548]], i16 [[TMP549]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP551:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP552:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP553:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP551]], i16 [[TMP552]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP554:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP555:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP556:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP554]], i16 [[TMP555]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP557:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP558:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP559:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP557]], i16 [[TMP558]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP560:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP561:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP560]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP562:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP563:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP562]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP564:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP565:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP564]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP566:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP567:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP566]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP568:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP569:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP568]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP570:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP571:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP570]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP572:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP573:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP572]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP574:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP575:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP574]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP576:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP577:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP578:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP576]], i16 [[TMP577]] release monotonic, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP579:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP580:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP581:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP579]], i16 [[TMP580]] release monotonic, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP582:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP583:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP584:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP582]], i16 [[TMP583]] release monotonic, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP585:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP586:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP587:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP585]], i16 [[TMP586]] release monotonic, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP588:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP589:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP588]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP590:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP591:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP590]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP592:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP593:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP592]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP594:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP595:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP594]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP596:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP597:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP596]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP598:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP599:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP598]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP600:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP601:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP600]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP602:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP603:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP602]] release, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP604:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP605:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP606:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP604]], i16 [[TMP605]] release monotonic, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP607:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP608:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP609:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP607]], i16 [[TMP608]] release monotonic, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP610:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP611:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP612:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP610]], i16 [[TMP611]] release monotonic, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP613:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP614:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP615:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP613]], i16 [[TMP614]] release monotonic, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP616:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP617:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP616]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP618:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP619:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP618]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP620:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP621:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP620]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP622:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP623:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP622]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP624:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP625:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP624]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP626:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP627:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP626]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP628:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP629:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP628]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP630:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP631:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP630]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP632:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP633:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP634:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP632]], i16 [[TMP633]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP635:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP636:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP637:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP635]], i16 [[TMP636]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP638:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP639:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP640:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP638]], i16 [[TMP639]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP641:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP642:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP643:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP641]], i16 [[TMP642]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP644:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP645:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP644]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP646:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP647:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP646]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP648:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP649:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP648]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP650:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP651:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP650]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP652:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP653:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP652]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP654:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP655:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP654]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP656:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP657:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP656]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP658:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP659:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP658]] seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP660:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP661:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP662:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP660]], i16 [[TMP661]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP663:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP664:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP665:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP663]], i16 [[TMP664]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP666:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP667:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP668:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP666]], i16 [[TMP667]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP669:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP670:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP671:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP669]], i16 [[TMP670]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP672:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP673:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP672]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP674:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP675:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP674]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP676:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP677:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP676]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP678:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP679:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP678]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP680:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP681:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP680]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP682:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP683:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP682]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP684:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP685:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP684]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP686:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP687:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP686]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP688:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP689:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP690:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP688]], i32 [[TMP689]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP691:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP692:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP693:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP691]], i32 [[TMP692]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP694:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP695:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP696:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP694]], i32 [[TMP695]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP697:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP698:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP699:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP697]], i32 [[TMP698]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP700:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP701:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP700]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP702:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP703:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP702]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP704:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP705:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP704]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP706:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP707:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP706]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP708:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP709:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP708]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP710:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP711:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP710]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP712:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP713:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP712]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP714:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP715:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP714]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP716:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP717:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP718:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP716]], i32 [[TMP717]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP719:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP720:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP721:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP719]], i32 [[TMP720]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP722:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP723:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP724:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP722]], i32 [[TMP723]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP725:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP726:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP727:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP725]], i32 [[TMP726]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP728:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP729:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP728]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP730:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP731:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP730]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP732:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP733:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP732]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP734:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP735:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP734]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP736:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP737:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP736]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP738:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP739:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP738]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP740:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP741:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP740]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP742:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP743:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP742]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP744:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP745:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP746:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP744]], i32 [[TMP745]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP747:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP748:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP749:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP747]], i32 [[TMP748]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP750:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP751:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP752:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP750]], i32 [[TMP751]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP753:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP754:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP755:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP753]], i32 [[TMP754]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP756:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP757:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP756]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP758:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP759:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP758]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP760:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP761:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP760]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP762:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP763:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP762]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP764:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP765:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP764]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP766:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP767:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP766]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP768:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP769:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP768]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP770:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP771:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP770]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP772:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP773:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP774:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP772]], i32 [[TMP773]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP775:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP776:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP777:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP775]], i32 [[TMP776]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP778:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP779:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP780:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP778]], i32 [[TMP779]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP781:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP782:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP783:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP781]], i32 [[TMP782]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP784:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP785:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP784]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP786:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP787:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP786]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP788:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP789:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP788]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP790:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP791:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP790]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP792:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP793:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP792]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP794:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP795:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP794]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP796:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP797:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP796]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP798:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP799:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP798]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP800:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP801:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP802:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP800]], i32 [[TMP801]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP803:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP804:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP805:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP803]], i32 [[TMP804]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP806:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP807:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP808:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP806]], i32 [[TMP807]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP809:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP810:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP811:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP809]], i32 [[TMP810]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP812:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP813:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP812]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP814:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP815:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP814]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP816:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP817:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP816]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP818:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP819:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP818]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP820:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP821:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP820]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP822:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP823:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP822]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP824:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP825:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP824]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP826:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP827:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP826]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP828:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP829:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP830:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP828]], i32 [[TMP829]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP831:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP832:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP833:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP831]], i32 [[TMP832]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP834:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP835:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP836:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP834]], i32 [[TMP835]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP837:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP838:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP839:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP837]], i32 [[TMP838]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP840:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP841:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP840]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP842:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP843:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP842]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP844:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP845:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP844]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP846:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP847:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP846]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP848:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP849:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP848]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP850:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP851:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP850]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP852:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP853:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP852]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP854:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP855:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP854]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP856:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP857:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP858:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP856]], i32 [[TMP857]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP859:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP860:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP861:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP859]], i32 [[TMP860]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP862:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP863:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP864:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP862]], i32 [[TMP863]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP865:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP866:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP867:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP865]], i32 [[TMP866]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP868:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP869:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP868]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP870:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP871:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP870]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP872:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP873:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP872]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP874:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP875:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP874]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP876:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP877:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP876]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP878:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP879:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP878]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP880:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP881:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP880]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP882:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP883:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP882]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP884:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP885:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP886:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP884]], i32 [[TMP885]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP887:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP888:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP889:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP887]], i32 [[TMP888]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP890:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP891:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP892:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP890]], i32 [[TMP891]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP893:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP894:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP895:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP893]], i32 [[TMP894]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP896:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP897:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP896]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP898:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP899:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP898]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP900:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP901:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP900]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP902:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP903:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP902]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP904:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP905:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP904]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP906:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP907:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP906]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP908:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP909:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP908]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP910:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP911:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP910]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP912:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP913:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP914:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP912]], i32 [[TMP913]] release monotonic, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP915:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP916:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP917:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP915]], i32 [[TMP916]] release monotonic, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP918:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP919:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP920:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP918]], i32 [[TMP919]] release monotonic, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP921:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP922:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP923:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP921]], i32 [[TMP922]] release monotonic, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP924:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP925:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP924]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP926:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP927:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP926]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP928:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP929:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP928]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP930:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP931:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP930]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP932:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP933:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP932]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP934:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP935:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP934]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP936:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP937:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP936]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP938:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP939:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP938]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP940:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP941:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP942:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP940]], i32 [[TMP941]] release monotonic, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP943:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP944:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP945:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP943]], i32 [[TMP944]] release monotonic, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP946:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP947:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP948:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP946]], i32 [[TMP947]] release monotonic, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP949:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP950:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP951:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP949]], i32 [[TMP950]] release monotonic, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP952:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP953:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP952]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP954:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP955:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP954]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP956:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP957:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP956]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP958:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP959:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP958]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP960:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP961:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP960]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP962:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP963:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP962]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP964:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP965:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP964]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP966:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP967:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP966]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP968:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP969:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP970:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP968]], i32 [[TMP969]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP971:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP972:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP973:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP971]], i32 [[TMP972]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP974:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP975:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP976:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP974]], i32 [[TMP975]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP977:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP978:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP979:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP977]], i32 [[TMP978]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP980:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP981:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP980]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP982:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP983:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP982]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP984:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP985:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP984]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP986:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP987:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP986]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP988:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP989:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP988]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP990:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP991:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP990]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP992:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP993:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP992]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP994:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP995:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP994]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP996:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP997:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP998:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP996]], i32 [[TMP997]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP999:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP1000:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP1001:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP999]], i32 [[TMP1000]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1002:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP1003:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP1004:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP1002]], i32 [[TMP1003]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1005:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP1006:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP1007:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP1005]], i32 [[TMP1006]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1008:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1009:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1008]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1010:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1011:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1010]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1012:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1013:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1012]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1014:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1015:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1014]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1016:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1017:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1016]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1018:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1019:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1018]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1020:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1021:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1020]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1022:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1023:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1022]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1024:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1025:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1026:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1024]], i64 [[TMP1025]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1027:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1028:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1029:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1027]], i64 [[TMP1028]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1030:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1031:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1032:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1030]], i64 [[TMP1031]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1033:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1034:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1035:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1033]], i64 [[TMP1034]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1036:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1037:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1036]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1038:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1039:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1038]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1040:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1041:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1040]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1042:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1043:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1042]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1044:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1045:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1044]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1046:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1047:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1046]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1048:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1049:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1048]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1050:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1051:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1050]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1052:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1053:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1054:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1052]], i64 [[TMP1053]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1055:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1056:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1057:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1055]], i64 [[TMP1056]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1058:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1059:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1060:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1058]], i64 [[TMP1059]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1061:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1062:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1063:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1061]], i64 [[TMP1062]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1064:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1065:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1064]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1066:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1067:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1066]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1068:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1069:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1068]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1070:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1071:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1070]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1072:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1073:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1072]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1074:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1075:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1074]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1076:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1077:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1076]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1078:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1079:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1078]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1080:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1081:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1082:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1080]], i64 [[TMP1081]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1083:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1084:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1085:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1083]], i64 [[TMP1084]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1086:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1087:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1088:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1086]], i64 [[TMP1087]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1089:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1090:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1091:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1089]], i64 [[TMP1090]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1092:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1093:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1092]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1094:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1095:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1094]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1096:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1097:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1096]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1098:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1099:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1098]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1100:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1101:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1100]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1102:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1103:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1102]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1104:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1105:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1104]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1106:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1107:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1106]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1108:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1109:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1110:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1108]], i64 [[TMP1109]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1111:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1112:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1113:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1111]], i64 [[TMP1112]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1114:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1115:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1116:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1114]], i64 [[TMP1115]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1117:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1118:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1119:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1117]], i64 [[TMP1118]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1120:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1121:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1120]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1122:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1123:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1122]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1124:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1125:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1124]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1126:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1127:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1126]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1128:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1129:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1128]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1130:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1131:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1130]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1132:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1133:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1132]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1134:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1135:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1134]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1136:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1137:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1138:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1136]], i64 [[TMP1137]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1139:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1140:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1141:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1139]], i64 [[TMP1140]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1142:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1143:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1144:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1142]], i64 [[TMP1143]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1145:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1146:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1147:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1145]], i64 [[TMP1146]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1148:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1149:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1148]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1150:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1151:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1150]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1152:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1153:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1152]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1154:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1155:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1154]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1156:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1157:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1156]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1158:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1159:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1158]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1160:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1161:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1160]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1162:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1163:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1162]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1164:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1165:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1166:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1164]], i64 [[TMP1165]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1167:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1168:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1169:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1167]], i64 [[TMP1168]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1170:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1171:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1172:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1170]], i64 [[TMP1171]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1173:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1174:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1175:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1173]], i64 [[TMP1174]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1176:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1177:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1176]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1178:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1179:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1178]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1180:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1181:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1180]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1182:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1183:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1182]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1184:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1185:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1184]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1186:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1187:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1186]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1188:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1189:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1188]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1190:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1191:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1190]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1192:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1193:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1194:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1192]], i64 [[TMP1193]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1195:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1196:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1197:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1195]], i64 [[TMP1196]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1198:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1199:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1200:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1198]], i64 [[TMP1199]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1201:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1202:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1203:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1201]], i64 [[TMP1202]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1204:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1205:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1204]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1206:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1207:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1206]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1208:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1209:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1208]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1210:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1211:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1210]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1212:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1213:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1212]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1214:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1215:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1214]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1216:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1217:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1216]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1218:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1219:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1218]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1220:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1221:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1222:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1220]], i64 [[TMP1221]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1223:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1224:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1225:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1223]], i64 [[TMP1224]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1226:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1227:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1228:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1226]], i64 [[TMP1227]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1229:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1230:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1231:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1229]], i64 [[TMP1230]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1232:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1233:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1232]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1234:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1235:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1234]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1236:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1237:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1236]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1238:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1239:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1238]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1240:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1241:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1240]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1242:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1243:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1242]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1244:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1245:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1244]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1246:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1247:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1246]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1248:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1249:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1250:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1248]], i64 [[TMP1249]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1251:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1252:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1253:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1251]], i64 [[TMP1252]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1254:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1255:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1256:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1254]], i64 [[TMP1255]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1257:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1258:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1259:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1257]], i64 [[TMP1258]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1260:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1261:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1260]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1262:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1263:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1262]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1264:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1265:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1264]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1266:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1267:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1266]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1268:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1269:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1268]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1270:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1271:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1270]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1272:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1273:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1272]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1274:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1275:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1274]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1276:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1277:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1278:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1276]], i64 [[TMP1277]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1279:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1280:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1281:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1279]], i64 [[TMP1280]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1282:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1283:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1284:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1282]], i64 [[TMP1283]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1285:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1286:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1287:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1285]], i64 [[TMP1286]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1288:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1289:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1288]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1290:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1291:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1290]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1292:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1293:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1292]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1294:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1295:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1294]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1296:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1297:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1296]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1298:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1299:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1298]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1300:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1301:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1300]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1302:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1303:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1302]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1304:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1305:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1306:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1304]], i64 [[TMP1305]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1307:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1308:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1309:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1307]], i64 [[TMP1308]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1310:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1311:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1312:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1310]], i64 [[TMP1311]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1313:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1314:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP1315:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1313]], i64 [[TMP1314]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1316:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1317:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1316]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1318:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1319:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1318]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1320:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1321:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1320]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1322:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1323:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1322]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1324:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1325:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1324]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1326:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1327:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1326]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1328:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1329:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1328]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1330:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1331:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1330]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1332:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1333:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1334:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1332]], i64 [[TMP1333]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1335:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1336:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1337:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1335]], i64 [[TMP1336]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1338:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1339:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1340:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1338]], i64 [[TMP1339]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1341:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1342:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP1343:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1341]], i64 [[TMP1342]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1344:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1345:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1344]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1346:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1347:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1346]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1348:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1349:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1348]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1350:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1351:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1350]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1352:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1353:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1352]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1354:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1355:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1354]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1356:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1357:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1356]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1358:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1359:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1358]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1360:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1361:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1362:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1360]], i64 [[TMP1361]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1363:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1364:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1365:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1363]], i64 [[TMP1364]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1366:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1367:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1368:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1366]], i64 [[TMP1367]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1369:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1370:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1371:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1369]], i64 [[TMP1370]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1372:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1373:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1372]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1374:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1375:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1374]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1376:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1377:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1376]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1378:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1379:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1378]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1380:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1381:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1380]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1382:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1383:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1382]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1384:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1385:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1384]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1386:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1387:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1386]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1388:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1389:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1390:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1388]], i64 [[TMP1389]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1391:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1392:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1393:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1391]], i64 [[TMP1392]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1394:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1395:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1396:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1394]], i64 [[TMP1395]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1397:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1398:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1399:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1397]], i64 [[TMP1398]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1400:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1401:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1400]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1402:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1403:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1402]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1404:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1405:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1404]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1406:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1407:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1406]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1408:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1409:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1408]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1410:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1411:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1410]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1412:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1413:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1412]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1414:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1415:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1414]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1416:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1417:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1418:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1416]], i64 [[TMP1417]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1419:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1420:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1421:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1419]], i64 [[TMP1420]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1422:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1423:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1424:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1422]], i64 [[TMP1423]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1425:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1426:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1427:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1425]], i64 [[TMP1426]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1428:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1429:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1428]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1430:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1431:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1430]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1432:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1433:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1432]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1434:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1435:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1434]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1436:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1437:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1436]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1438:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1439:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1438]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1440:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1441:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1440]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1442:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1443:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1442]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1444:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1445:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1446:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1444]], i64 [[TMP1445]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1447:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1448:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1449:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1447]], i64 [[TMP1448]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1450:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1451:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1452:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1450]], i64 [[TMP1451]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1453:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1454:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1455:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1453]], i64 [[TMP1454]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1456:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1457:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1456]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1458:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1459:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1458]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1460:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1461:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1460]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1462:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1463:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1462]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1464:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1465:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1464]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1466:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1467:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1466]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1468:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1469:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1468]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1470:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1471:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1470]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1472:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1473:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1474:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1472]], i64 [[TMP1473]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1475:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1476:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1477:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1475]], i64 [[TMP1476]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1478:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1479:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1480:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1478]], i64 [[TMP1479]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1481:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1482:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1483:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1481]], i64 [[TMP1482]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1484:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1485:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1484]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1486:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1487:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1486]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1488:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1489:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1488]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1490:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1491:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1490]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1492:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1493:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1492]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1494:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1495:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1494]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1496:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1497:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1496]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1498:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1499:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1498]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1500:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1501:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1502:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1500]], i64 [[TMP1501]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1503:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1504:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1505:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1503]], i64 [[TMP1504]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1506:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1507:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1508:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1506]], i64 [[TMP1507]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1509:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1510:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1511:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1509]], i64 [[TMP1510]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP1512:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1513:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1512]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1514:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1515:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1514]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1516:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1517:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1516]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1518:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1519:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1518]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1520:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1521:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1520]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1522:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1523:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1522]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1524:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1525:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1524]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1526:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1527:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1526]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1528:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1529:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1530:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1528]], i64 [[TMP1529]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1531:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1532:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1533:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1531]], i64 [[TMP1532]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1534:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1535:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1536:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1534]], i64 [[TMP1535]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1537:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1538:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1539:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1537]], i64 [[TMP1538]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1540:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1541:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1540]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1542:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1543:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1542]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1544:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1545:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1544]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1546:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1547:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1546]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1548:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1549:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1548]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1550:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1551:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1550]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1552:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1553:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1552]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1554:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1555:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1554]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1556:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1557:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1558:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1556]], i64 [[TMP1557]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1559:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1560:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1561:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1559]], i64 [[TMP1560]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1562:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1563:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1564:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1562]], i64 [[TMP1563]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1565:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1566:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1567:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1565]], i64 [[TMP1566]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1568:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1569:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1568]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1570:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1571:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1570]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1572:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1573:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1572]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1574:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1575:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1574]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1576:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1577:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1576]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1578:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1579:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1578]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1580:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1581:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1580]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1582:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1583:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1582]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1584:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1585:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1586:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1584]], i64 [[TMP1585]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1587:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1588:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1589:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1587]], i64 [[TMP1588]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1590:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1591:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1592:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1590]], i64 [[TMP1591]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1593:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1594:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1595:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1593]], i64 [[TMP1594]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1596:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1597:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1596]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1598:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1599:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1598]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1600:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1601:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1600]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1602:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1603:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1602]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1604:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1605:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1604]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1606:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1607:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1606]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1608:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1609:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1608]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1610:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1611:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1610]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1612:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1613:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1614:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1612]], i64 [[TMP1613]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1615:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1616:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1617:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1615]], i64 [[TMP1616]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1618:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1619:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1620:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1618]], i64 [[TMP1619]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1621:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1622:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1623:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1621]], i64 [[TMP1622]] release monotonic, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1624:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1625:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1624]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1626:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1627:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1626]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1628:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1629:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1628]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1630:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1631:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1630]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1632:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1633:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1632]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1634:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1635:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1634]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1636:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1637:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1636]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1638:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1639:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1638]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1640:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1641:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1642:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1640]], i64 [[TMP1641]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1643:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1644:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1645:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1643]], i64 [[TMP1644]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1646:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1647:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1648:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1646]], i64 [[TMP1647]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1649:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1650:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP1651:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1649]], i64 [[TMP1650]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1652:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1653:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1652]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1654:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1655:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1654]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1656:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1657:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1656]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1658:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1659:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1658]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1660:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1661:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1660]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1662:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1663:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1662]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1664:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1665:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1664]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1666:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1667:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1666]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1668:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1669:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1670:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1668]], i64 [[TMP1669]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1671:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1672:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1673:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1671]], i64 [[TMP1672]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1674:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1675:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1676:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1674]], i64 [[TMP1675]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1677:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1678:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP1679:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1677]], i64 [[TMP1678]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1680:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1681:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1680]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1682:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1683:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1682]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1684:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1685:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1684]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1686:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1687:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1686]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1688:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1689:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1688]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1690:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1691:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1690]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1692:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1693:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1692]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1694:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1695:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1694]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1696:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1697:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1696]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1698:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1699:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1698]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1700:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1701:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1700]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1702:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1703:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1702]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1704:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1705:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1704]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1706:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1707:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1706]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1708:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1709:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1708]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1710:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1711:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1710]] acq_rel, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1712:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1713:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1712]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP1714:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1715:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1714]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP1716:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1717:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1716]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP1718:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1719:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1718]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP1720:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1721:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1720]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP1722:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1723:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1722]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP1724:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1725:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1724]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP1726:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1727:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1726]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP1728:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1729:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1728]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1730:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1731:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1730]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1732:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1733:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1732]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1734:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1735:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1734]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1736:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1737:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1736]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1738:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1739:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1738]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1740:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1741:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1740]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1742:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1743:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1742]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1744:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1745:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1744]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1746:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1747:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1746]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1748:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1749:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1748]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1750:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1751:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1750]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1752:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1753:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1752]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1754:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1755:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1754]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1756:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1757:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1756]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1758:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1759:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1758]] release, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1760:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1761:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1760]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1762:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1763:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1762]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1764:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1765:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1764]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1766:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1767:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1766]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1768:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1769:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1768]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1770:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1771:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1770]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1772:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1773:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1772]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1774:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1775:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1774]] seq_cst, align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1776:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1777:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1776]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1778:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1779:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1778]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1780:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1781:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1780]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1782:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1783:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1782]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1784:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1785:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1784]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1786:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1787:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1786]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1788:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1789:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1788]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1790:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1791:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1790]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1792:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1793:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1792]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1794:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1795:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1794]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1796:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1797:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1796]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1798:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1799:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1798]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1800:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1801:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1800]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1802:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1803:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1802]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1804:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1805:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1804]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1806:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1807:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1806]] acq_rel, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1808:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1809:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1808]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1810:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1811:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1810]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1812:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1813:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1812]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1814:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1815:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1814]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1816:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1817:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1816]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1818:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1819:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1818]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1820:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1821:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1820]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1822:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1823:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1822]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP1824:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1825:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1824]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1826:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1827:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1826]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1828:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1829:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1828]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1830:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1831:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1830]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1832:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1833:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1832]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1834:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1835:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1834]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1836:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1837:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1836]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1838:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1839:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1838]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP1840:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1841:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1840]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1842:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1843:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1842]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1844:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1845:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1844]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1846:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1847:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1846]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1848:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1849:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1848]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1850:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1851:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1850]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1852:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1853:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1852]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1854:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1855:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1854]] release, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1856:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1857:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1856]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1858:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1859:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1858]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1860:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1861:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1860]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1862:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1863:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1862]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1864:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1865:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1864]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1866:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1867:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1866]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1868:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1869:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1868]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1870:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1871:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1870]] seq_cst, align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK-LABEL: @bar(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[CX:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[CV:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[CR:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[CE:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[CD:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCX:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCV:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCR:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCE:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCD:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[SX:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[SV:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[SR:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[SE:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[SD:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USX:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USV:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USR:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USE:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USD:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[IX:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[IV:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[IR:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[IE:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[ID:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UIX:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UIV:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UIR:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UIE:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UID:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[LX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LV:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LR:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULV:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULR:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLV:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLR:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLV:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLR:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[FX:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[FV:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[FE:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[FD:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[DX:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[DV:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[DE:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[DD:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP0]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP1]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP2]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP3]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP5:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP4]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP5]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP6]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP7]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP10:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP8]], i8 [[TMP9]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP11:%.*]] = extractvalue { i8, i1 } [[TMP10]], 0
|
|
// CHECK-NEXT: store i8 [[TMP11]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP14:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP12]], i8 [[TMP13]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP15:%.*]] = extractvalue { i8, i1 } [[TMP14]], 0
|
|
// CHECK-NEXT: store i8 [[TMP15]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP16]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP18:%.*]] = icmp sgt i8 [[TMP17]], [[TMP16]]
|
|
// CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i8 [[TMP16]], i8 [[TMP17]]
|
|
// CHECK-NEXT: store i8 [[TMP19]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP20]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP22:%.*]] = icmp slt i8 [[TMP21]], [[TMP20]]
|
|
// CHECK-NEXT: [[TMP23:%.*]] = select i1 [[TMP22]], i8 [[TMP20]], i8 [[TMP21]]
|
|
// CHECK-NEXT: store i8 [[TMP23]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP24]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP26:%.*]] = icmp slt i8 [[TMP25]], [[TMP24]]
|
|
// CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP26]], i8 [[TMP24]], i8 [[TMP25]]
|
|
// CHECK-NEXT: store i8 [[TMP27]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP28:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP29:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP28]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP30:%.*]] = icmp sgt i8 [[TMP29]], [[TMP28]]
|
|
// CHECK-NEXT: [[TMP31:%.*]] = select i1 [[TMP30]], i8 [[TMP28]], i8 [[TMP29]]
|
|
// CHECK-NEXT: store i8 [[TMP31]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP33:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP34:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP32]], i8 [[TMP33]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP35:%.*]] = extractvalue { i8, i1 } [[TMP34]], 0
|
|
// CHECK-NEXT: [[TMP36:%.*]] = extractvalue { i8, i1 } [[TMP34]], 1
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP32]], i8 [[TMP35]]
|
|
// CHECK-NEXT: store i8 [[TMP37]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP38]], i8 [[TMP39]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
|
|
// CHECK-NEXT: store i8 [[TMP43]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP45:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP46:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP44]], i8 [[TMP45]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP47:%.*]] = extractvalue { i8, i1 } [[TMP46]], 0
|
|
// CHECK-NEXT: [[TMP48:%.*]] = extractvalue { i8, i1 } [[TMP46]], 1
|
|
// CHECK-NEXT: br i1 [[TMP48]], label [[CX_ATOMIC_EXIT:%.*]], label [[CX_ATOMIC_CONT:%.*]]
|
|
// CHECK: cx.atomic.cont:
|
|
// CHECK-NEXT: store i8 [[TMP47]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT]]
|
|
// CHECK: cx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP50:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP51:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP49]], i8 [[TMP50]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP52:%.*]] = extractvalue { i8, i1 } [[TMP51]], 0
|
|
// CHECK-NEXT: [[TMP53:%.*]] = extractvalue { i8, i1 } [[TMP51]], 1
|
|
// CHECK-NEXT: br i1 [[TMP53]], label [[CX_ATOMIC_EXIT1:%.*]], label [[CX_ATOMIC_CONT2:%.*]]
|
|
// CHECK: cx.atomic.cont2:
|
|
// CHECK-NEXT: store i8 [[TMP52]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT1]]
|
|
// CHECK: cx.atomic.exit1:
|
|
// CHECK-NEXT: [[TMP54:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP55:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP56:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP54]], i8 [[TMP55]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP57:%.*]] = extractvalue { i8, i1 } [[TMP56]], 1
|
|
// CHECK-NEXT: [[TMP58:%.*]] = sext i1 [[TMP57]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP58]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP59:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP61:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP59]], i8 [[TMP60]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP62:%.*]] = extractvalue { i8, i1 } [[TMP61]], 1
|
|
// CHECK-NEXT: [[TMP63:%.*]] = sext i1 [[TMP62]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP63]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP66:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP64]], i8 [[TMP65]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP67:%.*]] = extractvalue { i8, i1 } [[TMP66]], 0
|
|
// CHECK-NEXT: [[TMP68:%.*]] = extractvalue { i8, i1 } [[TMP66]], 1
|
|
// CHECK-NEXT: br i1 [[TMP68]], label [[CX_ATOMIC_EXIT3:%.*]], label [[CX_ATOMIC_CONT4:%.*]]
|
|
// CHECK: cx.atomic.cont4:
|
|
// CHECK-NEXT: store i8 [[TMP67]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT3]]
|
|
// CHECK: cx.atomic.exit3:
|
|
// CHECK-NEXT: [[TMP69:%.*]] = extractvalue { i8, i1 } [[TMP66]], 1
|
|
// CHECK-NEXT: [[TMP70:%.*]] = sext i1 [[TMP69]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP70]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP72:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP73:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP71]], i8 [[TMP72]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP74:%.*]] = extractvalue { i8, i1 } [[TMP73]], 0
|
|
// CHECK-NEXT: [[TMP75:%.*]] = extractvalue { i8, i1 } [[TMP73]], 1
|
|
// CHECK-NEXT: br i1 [[TMP75]], label [[CX_ATOMIC_EXIT5:%.*]], label [[CX_ATOMIC_CONT6:%.*]]
|
|
// CHECK: cx.atomic.cont6:
|
|
// CHECK-NEXT: store i8 [[TMP74]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT5]]
|
|
// CHECK: cx.atomic.exit5:
|
|
// CHECK-NEXT: [[TMP76:%.*]] = extractvalue { i8, i1 } [[TMP73]], 1
|
|
// CHECK-NEXT: [[TMP77:%.*]] = sext i1 [[TMP76]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP77]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP78]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP79]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP80:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP80]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP81]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP82]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP83]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP84:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP85:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP84]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP85]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP86:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP88:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP86]], i8 [[TMP87]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP89:%.*]] = extractvalue { i8, i1 } [[TMP88]], 0
|
|
// CHECK-NEXT: store i8 [[TMP89]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP91:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP92:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP90]], i8 [[TMP91]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP93:%.*]] = extractvalue { i8, i1 } [[TMP92]], 0
|
|
// CHECK-NEXT: store i8 [[TMP93]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP94:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP95:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP94]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP96:%.*]] = icmp sgt i8 [[TMP95]], [[TMP94]]
|
|
// CHECK-NEXT: [[TMP97:%.*]] = select i1 [[TMP96]], i8 [[TMP94]], i8 [[TMP95]]
|
|
// CHECK-NEXT: store i8 [[TMP97]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP99:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP98]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP100:%.*]] = icmp slt i8 [[TMP99]], [[TMP98]]
|
|
// CHECK-NEXT: [[TMP101:%.*]] = select i1 [[TMP100]], i8 [[TMP98]], i8 [[TMP99]]
|
|
// CHECK-NEXT: store i8 [[TMP101]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP102:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP103:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP102]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP104:%.*]] = icmp slt i8 [[TMP103]], [[TMP102]]
|
|
// CHECK-NEXT: [[TMP105:%.*]] = select i1 [[TMP104]], i8 [[TMP102]], i8 [[TMP103]]
|
|
// CHECK-NEXT: store i8 [[TMP105]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP107:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP106]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP108:%.*]] = icmp sgt i8 [[TMP107]], [[TMP106]]
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP106]], i8 [[TMP107]]
|
|
// CHECK-NEXT: store i8 [[TMP109]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP111:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP112:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP110]], i8 [[TMP111]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP113:%.*]] = extractvalue { i8, i1 } [[TMP112]], 0
|
|
// CHECK-NEXT: [[TMP114:%.*]] = extractvalue { i8, i1 } [[TMP112]], 1
|
|
// CHECK-NEXT: [[TMP115:%.*]] = select i1 [[TMP114]], i8 [[TMP110]], i8 [[TMP113]]
|
|
// CHECK-NEXT: store i8 [[TMP115]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP117:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP118:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP116]], i8 [[TMP117]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP119:%.*]] = extractvalue { i8, i1 } [[TMP118]], 0
|
|
// CHECK-NEXT: [[TMP120:%.*]] = extractvalue { i8, i1 } [[TMP118]], 1
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP116]], i8 [[TMP119]]
|
|
// CHECK-NEXT: store i8 [[TMP121]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP123:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP124:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP122]], i8 [[TMP123]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP125:%.*]] = extractvalue { i8, i1 } [[TMP124]], 0
|
|
// CHECK-NEXT: [[TMP126:%.*]] = extractvalue { i8, i1 } [[TMP124]], 1
|
|
// CHECK-NEXT: br i1 [[TMP126]], label [[CX_ATOMIC_EXIT7:%.*]], label [[CX_ATOMIC_CONT8:%.*]]
|
|
// CHECK: cx.atomic.cont8:
|
|
// CHECK-NEXT: store i8 [[TMP125]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT7]]
|
|
// CHECK: cx.atomic.exit7:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP128:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP129:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP127]], i8 [[TMP128]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP129]], 0
|
|
// CHECK-NEXT: [[TMP131:%.*]] = extractvalue { i8, i1 } [[TMP129]], 1
|
|
// CHECK-NEXT: br i1 [[TMP131]], label [[CX_ATOMIC_EXIT9:%.*]], label [[CX_ATOMIC_CONT10:%.*]]
|
|
// CHECK: cx.atomic.cont10:
|
|
// CHECK-NEXT: store i8 [[TMP130]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT9]]
|
|
// CHECK: cx.atomic.exit9:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP133:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP134:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP132]], i8 [[TMP133]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP135:%.*]] = extractvalue { i8, i1 } [[TMP134]], 1
|
|
// CHECK-NEXT: [[TMP136:%.*]] = sext i1 [[TMP135]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP136]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP137:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP138:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP139:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP137]], i8 [[TMP138]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP140:%.*]] = extractvalue { i8, i1 } [[TMP139]], 1
|
|
// CHECK-NEXT: [[TMP141:%.*]] = sext i1 [[TMP140]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP141]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP142:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP143:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP144:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP142]], i8 [[TMP143]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP145:%.*]] = extractvalue { i8, i1 } [[TMP144]], 0
|
|
// CHECK-NEXT: [[TMP146:%.*]] = extractvalue { i8, i1 } [[TMP144]], 1
|
|
// CHECK-NEXT: br i1 [[TMP146]], label [[CX_ATOMIC_EXIT11:%.*]], label [[CX_ATOMIC_CONT12:%.*]]
|
|
// CHECK: cx.atomic.cont12:
|
|
// CHECK-NEXT: store i8 [[TMP145]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT11]]
|
|
// CHECK: cx.atomic.exit11:
|
|
// CHECK-NEXT: [[TMP147:%.*]] = extractvalue { i8, i1 } [[TMP144]], 1
|
|
// CHECK-NEXT: [[TMP148:%.*]] = sext i1 [[TMP147]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP148]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP149:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP150:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP151:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP149]], i8 [[TMP150]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP152:%.*]] = extractvalue { i8, i1 } [[TMP151]], 0
|
|
// CHECK-NEXT: [[TMP153:%.*]] = extractvalue { i8, i1 } [[TMP151]], 1
|
|
// CHECK-NEXT: br i1 [[TMP153]], label [[CX_ATOMIC_EXIT13:%.*]], label [[CX_ATOMIC_CONT14:%.*]]
|
|
// CHECK: cx.atomic.cont14:
|
|
// CHECK-NEXT: store i8 [[TMP152]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT13]]
|
|
// CHECK: cx.atomic.exit13:
|
|
// CHECK-NEXT: [[TMP154:%.*]] = extractvalue { i8, i1 } [[TMP151]], 1
|
|
// CHECK-NEXT: [[TMP155:%.*]] = sext i1 [[TMP154]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP155]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP156:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP157:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP156]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP157]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP158:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP159:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP158]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP159]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP160:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP161:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP160]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP161]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP162:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP163:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP162]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP163]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP164:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP165:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP166:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP164]], i8 [[TMP165]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP167:%.*]] = extractvalue { i8, i1 } [[TMP166]], 0
|
|
// CHECK-NEXT: store i8 [[TMP167]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP168:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP169:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP170:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP168]], i8 [[TMP169]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP171:%.*]] = extractvalue { i8, i1 } [[TMP170]], 0
|
|
// CHECK-NEXT: store i8 [[TMP171]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP173:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP172]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP174:%.*]] = icmp sgt i8 [[TMP173]], [[TMP172]]
|
|
// CHECK-NEXT: [[TMP175:%.*]] = select i1 [[TMP174]], i8 [[TMP172]], i8 [[TMP173]]
|
|
// CHECK-NEXT: store i8 [[TMP175]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP177:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP176]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP178:%.*]] = icmp slt i8 [[TMP177]], [[TMP176]]
|
|
// CHECK-NEXT: [[TMP179:%.*]] = select i1 [[TMP178]], i8 [[TMP176]], i8 [[TMP177]]
|
|
// CHECK-NEXT: store i8 [[TMP179]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP181:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP180]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP182:%.*]] = icmp slt i8 [[TMP181]], [[TMP180]]
|
|
// CHECK-NEXT: [[TMP183:%.*]] = select i1 [[TMP182]], i8 [[TMP180]], i8 [[TMP181]]
|
|
// CHECK-NEXT: store i8 [[TMP183]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP184:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP185:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP184]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP186:%.*]] = icmp sgt i8 [[TMP185]], [[TMP184]]
|
|
// CHECK-NEXT: [[TMP187:%.*]] = select i1 [[TMP186]], i8 [[TMP184]], i8 [[TMP185]]
|
|
// CHECK-NEXT: store i8 [[TMP187]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP188:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP189:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP190:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP188]], i8 [[TMP189]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP191:%.*]] = extractvalue { i8, i1 } [[TMP190]], 0
|
|
// CHECK-NEXT: [[TMP192:%.*]] = extractvalue { i8, i1 } [[TMP190]], 1
|
|
// CHECK-NEXT: [[TMP193:%.*]] = select i1 [[TMP192]], i8 [[TMP188]], i8 [[TMP191]]
|
|
// CHECK-NEXT: store i8 [[TMP193]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP194:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP195:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP196:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP194]], i8 [[TMP195]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP197:%.*]] = extractvalue { i8, i1 } [[TMP196]], 0
|
|
// CHECK-NEXT: [[TMP198:%.*]] = extractvalue { i8, i1 } [[TMP196]], 1
|
|
// CHECK-NEXT: [[TMP199:%.*]] = select i1 [[TMP198]], i8 [[TMP194]], i8 [[TMP197]]
|
|
// CHECK-NEXT: store i8 [[TMP199]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP200:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP201:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP202:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP200]], i8 [[TMP201]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP203:%.*]] = extractvalue { i8, i1 } [[TMP202]], 0
|
|
// CHECK-NEXT: [[TMP204:%.*]] = extractvalue { i8, i1 } [[TMP202]], 1
|
|
// CHECK-NEXT: br i1 [[TMP204]], label [[CX_ATOMIC_EXIT15:%.*]], label [[CX_ATOMIC_CONT16:%.*]]
|
|
// CHECK: cx.atomic.cont16:
|
|
// CHECK-NEXT: store i8 [[TMP203]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT15]]
|
|
// CHECK: cx.atomic.exit15:
|
|
// CHECK-NEXT: [[TMP205:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP206:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP207:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP205]], i8 [[TMP206]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP208:%.*]] = extractvalue { i8, i1 } [[TMP207]], 0
|
|
// CHECK-NEXT: [[TMP209:%.*]] = extractvalue { i8, i1 } [[TMP207]], 1
|
|
// CHECK-NEXT: br i1 [[TMP209]], label [[CX_ATOMIC_EXIT17:%.*]], label [[CX_ATOMIC_CONT18:%.*]]
|
|
// CHECK: cx.atomic.cont18:
|
|
// CHECK-NEXT: store i8 [[TMP208]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT17]]
|
|
// CHECK: cx.atomic.exit17:
|
|
// CHECK-NEXT: [[TMP210:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP211:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP212:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP210]], i8 [[TMP211]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP213:%.*]] = extractvalue { i8, i1 } [[TMP212]], 1
|
|
// CHECK-NEXT: [[TMP214:%.*]] = sext i1 [[TMP213]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP214]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP215:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP216:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP217:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP215]], i8 [[TMP216]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP218:%.*]] = extractvalue { i8, i1 } [[TMP217]], 1
|
|
// CHECK-NEXT: [[TMP219:%.*]] = sext i1 [[TMP218]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP219]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP220:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP221:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP222:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP220]], i8 [[TMP221]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP223:%.*]] = extractvalue { i8, i1 } [[TMP222]], 0
|
|
// CHECK-NEXT: [[TMP224:%.*]] = extractvalue { i8, i1 } [[TMP222]], 1
|
|
// CHECK-NEXT: br i1 [[TMP224]], label [[CX_ATOMIC_EXIT19:%.*]], label [[CX_ATOMIC_CONT20:%.*]]
|
|
// CHECK: cx.atomic.cont20:
|
|
// CHECK-NEXT: store i8 [[TMP223]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT19]]
|
|
// CHECK: cx.atomic.exit19:
|
|
// CHECK-NEXT: [[TMP225:%.*]] = extractvalue { i8, i1 } [[TMP222]], 1
|
|
// CHECK-NEXT: [[TMP226:%.*]] = sext i1 [[TMP225]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP226]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP227:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP228:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP229:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP227]], i8 [[TMP228]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP230:%.*]] = extractvalue { i8, i1 } [[TMP229]], 0
|
|
// CHECK-NEXT: [[TMP231:%.*]] = extractvalue { i8, i1 } [[TMP229]], 1
|
|
// CHECK-NEXT: br i1 [[TMP231]], label [[CX_ATOMIC_EXIT21:%.*]], label [[CX_ATOMIC_CONT22:%.*]]
|
|
// CHECK: cx.atomic.cont22:
|
|
// CHECK-NEXT: store i8 [[TMP230]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT21]]
|
|
// CHECK: cx.atomic.exit21:
|
|
// CHECK-NEXT: [[TMP232:%.*]] = extractvalue { i8, i1 } [[TMP229]], 1
|
|
// CHECK-NEXT: [[TMP233:%.*]] = sext i1 [[TMP232]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP233]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP234:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP235:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP234]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP235]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP236:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP237:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP236]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP237]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP238:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP239:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP238]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP239]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP240:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP241:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP240]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP241]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP242:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP243:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP244:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP242]], i8 [[TMP243]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP245:%.*]] = extractvalue { i8, i1 } [[TMP244]], 0
|
|
// CHECK-NEXT: store i8 [[TMP245]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP246:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP247:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP248:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP246]], i8 [[TMP247]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP249:%.*]] = extractvalue { i8, i1 } [[TMP248]], 0
|
|
// CHECK-NEXT: store i8 [[TMP249]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP250:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP251:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP250]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP252:%.*]] = icmp sgt i8 [[TMP251]], [[TMP250]]
|
|
// CHECK-NEXT: [[TMP253:%.*]] = select i1 [[TMP252]], i8 [[TMP250]], i8 [[TMP251]]
|
|
// CHECK-NEXT: store i8 [[TMP253]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP254:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP255:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP254]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP256:%.*]] = icmp slt i8 [[TMP255]], [[TMP254]]
|
|
// CHECK-NEXT: [[TMP257:%.*]] = select i1 [[TMP256]], i8 [[TMP254]], i8 [[TMP255]]
|
|
// CHECK-NEXT: store i8 [[TMP257]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP258:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP259:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP258]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP260:%.*]] = icmp slt i8 [[TMP259]], [[TMP258]]
|
|
// CHECK-NEXT: [[TMP261:%.*]] = select i1 [[TMP260]], i8 [[TMP258]], i8 [[TMP259]]
|
|
// CHECK-NEXT: store i8 [[TMP261]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP262:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP263:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP262]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP264:%.*]] = icmp sgt i8 [[TMP263]], [[TMP262]]
|
|
// CHECK-NEXT: [[TMP265:%.*]] = select i1 [[TMP264]], i8 [[TMP262]], i8 [[TMP263]]
|
|
// CHECK-NEXT: store i8 [[TMP265]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP266:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP267:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP268:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP266]], i8 [[TMP267]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP269:%.*]] = extractvalue { i8, i1 } [[TMP268]], 0
|
|
// CHECK-NEXT: [[TMP270:%.*]] = extractvalue { i8, i1 } [[TMP268]], 1
|
|
// CHECK-NEXT: [[TMP271:%.*]] = select i1 [[TMP270]], i8 [[TMP266]], i8 [[TMP269]]
|
|
// CHECK-NEXT: store i8 [[TMP271]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP272:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP273:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP274:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP272]], i8 [[TMP273]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP275:%.*]] = extractvalue { i8, i1 } [[TMP274]], 0
|
|
// CHECK-NEXT: [[TMP276:%.*]] = extractvalue { i8, i1 } [[TMP274]], 1
|
|
// CHECK-NEXT: [[TMP277:%.*]] = select i1 [[TMP276]], i8 [[TMP272]], i8 [[TMP275]]
|
|
// CHECK-NEXT: store i8 [[TMP277]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP278:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP279:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP280:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP278]], i8 [[TMP279]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP281:%.*]] = extractvalue { i8, i1 } [[TMP280]], 0
|
|
// CHECK-NEXT: [[TMP282:%.*]] = extractvalue { i8, i1 } [[TMP280]], 1
|
|
// CHECK-NEXT: br i1 [[TMP282]], label [[CX_ATOMIC_EXIT23:%.*]], label [[CX_ATOMIC_CONT24:%.*]]
|
|
// CHECK: cx.atomic.cont24:
|
|
// CHECK-NEXT: store i8 [[TMP281]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT23]]
|
|
// CHECK: cx.atomic.exit23:
|
|
// CHECK-NEXT: [[TMP283:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP284:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP285:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP283]], i8 [[TMP284]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP286:%.*]] = extractvalue { i8, i1 } [[TMP285]], 0
|
|
// CHECK-NEXT: [[TMP287:%.*]] = extractvalue { i8, i1 } [[TMP285]], 1
|
|
// CHECK-NEXT: br i1 [[TMP287]], label [[CX_ATOMIC_EXIT25:%.*]], label [[CX_ATOMIC_CONT26:%.*]]
|
|
// CHECK: cx.atomic.cont26:
|
|
// CHECK-NEXT: store i8 [[TMP286]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT25]]
|
|
// CHECK: cx.atomic.exit25:
|
|
// CHECK-NEXT: [[TMP288:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP289:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP290:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP288]], i8 [[TMP289]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP291:%.*]] = extractvalue { i8, i1 } [[TMP290]], 1
|
|
// CHECK-NEXT: [[TMP292:%.*]] = sext i1 [[TMP291]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP292]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP293:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP294:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP295:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP293]], i8 [[TMP294]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP296:%.*]] = extractvalue { i8, i1 } [[TMP295]], 1
|
|
// CHECK-NEXT: [[TMP297:%.*]] = sext i1 [[TMP296]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP297]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP298:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP299:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP300:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP298]], i8 [[TMP299]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP301:%.*]] = extractvalue { i8, i1 } [[TMP300]], 0
|
|
// CHECK-NEXT: [[TMP302:%.*]] = extractvalue { i8, i1 } [[TMP300]], 1
|
|
// CHECK-NEXT: br i1 [[TMP302]], label [[CX_ATOMIC_EXIT27:%.*]], label [[CX_ATOMIC_CONT28:%.*]]
|
|
// CHECK: cx.atomic.cont28:
|
|
// CHECK-NEXT: store i8 [[TMP301]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT27]]
|
|
// CHECK: cx.atomic.exit27:
|
|
// CHECK-NEXT: [[TMP303:%.*]] = extractvalue { i8, i1 } [[TMP300]], 1
|
|
// CHECK-NEXT: [[TMP304:%.*]] = sext i1 [[TMP303]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP304]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP305:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP306:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP307:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP305]], i8 [[TMP306]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP308:%.*]] = extractvalue { i8, i1 } [[TMP307]], 0
|
|
// CHECK-NEXT: [[TMP309:%.*]] = extractvalue { i8, i1 } [[TMP307]], 1
|
|
// CHECK-NEXT: br i1 [[TMP309]], label [[CX_ATOMIC_EXIT29:%.*]], label [[CX_ATOMIC_CONT30:%.*]]
|
|
// CHECK: cx.atomic.cont30:
|
|
// CHECK-NEXT: store i8 [[TMP308]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT29]]
|
|
// CHECK: cx.atomic.exit29:
|
|
// CHECK-NEXT: [[TMP310:%.*]] = extractvalue { i8, i1 } [[TMP307]], 1
|
|
// CHECK-NEXT: [[TMP311:%.*]] = sext i1 [[TMP310]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP311]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: [[TMP312:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP313:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP312]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP313]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP314:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP315:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP314]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP315]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP316:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP317:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP316]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP317]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP318:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP319:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP318]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP319]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP320:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP321:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP322:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP320]], i8 [[TMP321]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP323:%.*]] = extractvalue { i8, i1 } [[TMP322]], 0
|
|
// CHECK-NEXT: store i8 [[TMP323]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP324:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP325:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP326:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP324]], i8 [[TMP325]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP327:%.*]] = extractvalue { i8, i1 } [[TMP326]], 0
|
|
// CHECK-NEXT: store i8 [[TMP327]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP328:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP329:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP328]] release, align 1
|
|
// CHECK-NEXT: [[TMP330:%.*]] = icmp sgt i8 [[TMP329]], [[TMP328]]
|
|
// CHECK-NEXT: [[TMP331:%.*]] = select i1 [[TMP330]], i8 [[TMP328]], i8 [[TMP329]]
|
|
// CHECK-NEXT: store i8 [[TMP331]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP332:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP333:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP332]] release, align 1
|
|
// CHECK-NEXT: [[TMP334:%.*]] = icmp slt i8 [[TMP333]], [[TMP332]]
|
|
// CHECK-NEXT: [[TMP335:%.*]] = select i1 [[TMP334]], i8 [[TMP332]], i8 [[TMP333]]
|
|
// CHECK-NEXT: store i8 [[TMP335]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP336:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP337:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP336]] release, align 1
|
|
// CHECK-NEXT: [[TMP338:%.*]] = icmp slt i8 [[TMP337]], [[TMP336]]
|
|
// CHECK-NEXT: [[TMP339:%.*]] = select i1 [[TMP338]], i8 [[TMP336]], i8 [[TMP337]]
|
|
// CHECK-NEXT: store i8 [[TMP339]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP340:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP341:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP340]] release, align 1
|
|
// CHECK-NEXT: [[TMP342:%.*]] = icmp sgt i8 [[TMP341]], [[TMP340]]
|
|
// CHECK-NEXT: [[TMP343:%.*]] = select i1 [[TMP342]], i8 [[TMP340]], i8 [[TMP341]]
|
|
// CHECK-NEXT: store i8 [[TMP343]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP344:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP345:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP346:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP344]], i8 [[TMP345]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP347:%.*]] = extractvalue { i8, i1 } [[TMP346]], 0
|
|
// CHECK-NEXT: [[TMP348:%.*]] = extractvalue { i8, i1 } [[TMP346]], 1
|
|
// CHECK-NEXT: [[TMP349:%.*]] = select i1 [[TMP348]], i8 [[TMP344]], i8 [[TMP347]]
|
|
// CHECK-NEXT: store i8 [[TMP349]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP350:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP351:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP352:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP350]], i8 [[TMP351]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP353:%.*]] = extractvalue { i8, i1 } [[TMP352]], 0
|
|
// CHECK-NEXT: [[TMP354:%.*]] = extractvalue { i8, i1 } [[TMP352]], 1
|
|
// CHECK-NEXT: [[TMP355:%.*]] = select i1 [[TMP354]], i8 [[TMP350]], i8 [[TMP353]]
|
|
// CHECK-NEXT: store i8 [[TMP355]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP356:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP357:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP358:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP356]], i8 [[TMP357]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP359:%.*]] = extractvalue { i8, i1 } [[TMP358]], 0
|
|
// CHECK-NEXT: [[TMP360:%.*]] = extractvalue { i8, i1 } [[TMP358]], 1
|
|
// CHECK-NEXT: br i1 [[TMP360]], label [[CX_ATOMIC_EXIT31:%.*]], label [[CX_ATOMIC_CONT32:%.*]]
|
|
// CHECK: cx.atomic.cont32:
|
|
// CHECK-NEXT: store i8 [[TMP359]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT31]]
|
|
// CHECK: cx.atomic.exit31:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP361:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP362:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP363:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP361]], i8 [[TMP362]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP364:%.*]] = extractvalue { i8, i1 } [[TMP363]], 0
|
|
// CHECK-NEXT: [[TMP365:%.*]] = extractvalue { i8, i1 } [[TMP363]], 1
|
|
// CHECK-NEXT: br i1 [[TMP365]], label [[CX_ATOMIC_EXIT33:%.*]], label [[CX_ATOMIC_CONT34:%.*]]
|
|
// CHECK: cx.atomic.cont34:
|
|
// CHECK-NEXT: store i8 [[TMP364]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT33]]
|
|
// CHECK: cx.atomic.exit33:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP366:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP367:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP368:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP366]], i8 [[TMP367]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP369:%.*]] = extractvalue { i8, i1 } [[TMP368]], 1
|
|
// CHECK-NEXT: [[TMP370:%.*]] = sext i1 [[TMP369]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP370]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP371:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP372:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP373:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP371]], i8 [[TMP372]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP374:%.*]] = extractvalue { i8, i1 } [[TMP373]], 1
|
|
// CHECK-NEXT: [[TMP375:%.*]] = sext i1 [[TMP374]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP375]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP376:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP377:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP378:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP376]], i8 [[TMP377]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP379:%.*]] = extractvalue { i8, i1 } [[TMP378]], 0
|
|
// CHECK-NEXT: [[TMP380:%.*]] = extractvalue { i8, i1 } [[TMP378]], 1
|
|
// CHECK-NEXT: br i1 [[TMP380]], label [[CX_ATOMIC_EXIT35:%.*]], label [[CX_ATOMIC_CONT36:%.*]]
|
|
// CHECK: cx.atomic.cont36:
|
|
// CHECK-NEXT: store i8 [[TMP379]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT35]]
|
|
// CHECK: cx.atomic.exit35:
|
|
// CHECK-NEXT: [[TMP381:%.*]] = extractvalue { i8, i1 } [[TMP378]], 1
|
|
// CHECK-NEXT: [[TMP382:%.*]] = sext i1 [[TMP381]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP382]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP383:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP384:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP385:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP383]], i8 [[TMP384]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP386:%.*]] = extractvalue { i8, i1 } [[TMP385]], 0
|
|
// CHECK-NEXT: [[TMP387:%.*]] = extractvalue { i8, i1 } [[TMP385]], 1
|
|
// CHECK-NEXT: br i1 [[TMP387]], label [[CX_ATOMIC_EXIT37:%.*]], label [[CX_ATOMIC_CONT38:%.*]]
|
|
// CHECK: cx.atomic.cont38:
|
|
// CHECK-NEXT: store i8 [[TMP386]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT37]]
|
|
// CHECK: cx.atomic.exit37:
|
|
// CHECK-NEXT: [[TMP388:%.*]] = extractvalue { i8, i1 } [[TMP385]], 1
|
|
// CHECK-NEXT: [[TMP389:%.*]] = sext i1 [[TMP388]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP389]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP390:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP391:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP390]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP391]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP392:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP393:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP392]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP393]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP394:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP395:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP394]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP395]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP396:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP397:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP396]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP397]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP398:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP399:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP400:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP398]], i8 [[TMP399]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP401:%.*]] = extractvalue { i8, i1 } [[TMP400]], 0
|
|
// CHECK-NEXT: store i8 [[TMP401]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP402:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP403:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP404:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP402]], i8 [[TMP403]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP405:%.*]] = extractvalue { i8, i1 } [[TMP404]], 0
|
|
// CHECK-NEXT: store i8 [[TMP405]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP406:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP407:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP406]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP408:%.*]] = icmp sgt i8 [[TMP407]], [[TMP406]]
|
|
// CHECK-NEXT: [[TMP409:%.*]] = select i1 [[TMP408]], i8 [[TMP406]], i8 [[TMP407]]
|
|
// CHECK-NEXT: store i8 [[TMP409]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP410:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP411:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP410]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP412:%.*]] = icmp slt i8 [[TMP411]], [[TMP410]]
|
|
// CHECK-NEXT: [[TMP413:%.*]] = select i1 [[TMP412]], i8 [[TMP410]], i8 [[TMP411]]
|
|
// CHECK-NEXT: store i8 [[TMP413]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP414:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP415:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP414]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP416:%.*]] = icmp slt i8 [[TMP415]], [[TMP414]]
|
|
// CHECK-NEXT: [[TMP417:%.*]] = select i1 [[TMP416]], i8 [[TMP414]], i8 [[TMP415]]
|
|
// CHECK-NEXT: store i8 [[TMP417]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP418:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP419:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP418]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP420:%.*]] = icmp sgt i8 [[TMP419]], [[TMP418]]
|
|
// CHECK-NEXT: [[TMP421:%.*]] = select i1 [[TMP420]], i8 [[TMP418]], i8 [[TMP419]]
|
|
// CHECK-NEXT: store i8 [[TMP421]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP422:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP423:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP424:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP422]], i8 [[TMP423]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP425:%.*]] = extractvalue { i8, i1 } [[TMP424]], 0
|
|
// CHECK-NEXT: [[TMP426:%.*]] = extractvalue { i8, i1 } [[TMP424]], 1
|
|
// CHECK-NEXT: [[TMP427:%.*]] = select i1 [[TMP426]], i8 [[TMP422]], i8 [[TMP425]]
|
|
// CHECK-NEXT: store i8 [[TMP427]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP428:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP429:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP430:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP428]], i8 [[TMP429]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP431:%.*]] = extractvalue { i8, i1 } [[TMP430]], 0
|
|
// CHECK-NEXT: [[TMP432:%.*]] = extractvalue { i8, i1 } [[TMP430]], 1
|
|
// CHECK-NEXT: [[TMP433:%.*]] = select i1 [[TMP432]], i8 [[TMP428]], i8 [[TMP431]]
|
|
// CHECK-NEXT: store i8 [[TMP433]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP434:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP435:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP436:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP434]], i8 [[TMP435]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP437:%.*]] = extractvalue { i8, i1 } [[TMP436]], 0
|
|
// CHECK-NEXT: [[TMP438:%.*]] = extractvalue { i8, i1 } [[TMP436]], 1
|
|
// CHECK-NEXT: br i1 [[TMP438]], label [[CX_ATOMIC_EXIT39:%.*]], label [[CX_ATOMIC_CONT40:%.*]]
|
|
// CHECK: cx.atomic.cont40:
|
|
// CHECK-NEXT: store i8 [[TMP437]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT39]]
|
|
// CHECK: cx.atomic.exit39:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP439:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP440:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP441:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP439]], i8 [[TMP440]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP442:%.*]] = extractvalue { i8, i1 } [[TMP441]], 0
|
|
// CHECK-NEXT: [[TMP443:%.*]] = extractvalue { i8, i1 } [[TMP441]], 1
|
|
// CHECK-NEXT: br i1 [[TMP443]], label [[CX_ATOMIC_EXIT41:%.*]], label [[CX_ATOMIC_CONT42:%.*]]
|
|
// CHECK: cx.atomic.cont42:
|
|
// CHECK-NEXT: store i8 [[TMP442]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT41]]
|
|
// CHECK: cx.atomic.exit41:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP444:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP445:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP446:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP444]], i8 [[TMP445]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP447:%.*]] = extractvalue { i8, i1 } [[TMP446]], 1
|
|
// CHECK-NEXT: [[TMP448:%.*]] = sext i1 [[TMP447]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP448]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP449:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP450:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP451:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP449]], i8 [[TMP450]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP452:%.*]] = extractvalue { i8, i1 } [[TMP451]], 1
|
|
// CHECK-NEXT: [[TMP453:%.*]] = sext i1 [[TMP452]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP453]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP454:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP455:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP456:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP454]], i8 [[TMP455]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP457:%.*]] = extractvalue { i8, i1 } [[TMP456]], 0
|
|
// CHECK-NEXT: [[TMP458:%.*]] = extractvalue { i8, i1 } [[TMP456]], 1
|
|
// CHECK-NEXT: br i1 [[TMP458]], label [[CX_ATOMIC_EXIT43:%.*]], label [[CX_ATOMIC_CONT44:%.*]]
|
|
// CHECK: cx.atomic.cont44:
|
|
// CHECK-NEXT: store i8 [[TMP457]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT43]]
|
|
// CHECK: cx.atomic.exit43:
|
|
// CHECK-NEXT: [[TMP459:%.*]] = extractvalue { i8, i1 } [[TMP456]], 1
|
|
// CHECK-NEXT: [[TMP460:%.*]] = sext i1 [[TMP459]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP460]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP461:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP462:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP463:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP461]], i8 [[TMP462]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP464:%.*]] = extractvalue { i8, i1 } [[TMP463]], 0
|
|
// CHECK-NEXT: [[TMP465:%.*]] = extractvalue { i8, i1 } [[TMP463]], 1
|
|
// CHECK-NEXT: br i1 [[TMP465]], label [[CX_ATOMIC_EXIT45:%.*]], label [[CX_ATOMIC_CONT46:%.*]]
|
|
// CHECK: cx.atomic.cont46:
|
|
// CHECK-NEXT: store i8 [[TMP464]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT45]]
|
|
// CHECK: cx.atomic.exit45:
|
|
// CHECK-NEXT: [[TMP466:%.*]] = extractvalue { i8, i1 } [[TMP463]], 1
|
|
// CHECK-NEXT: [[TMP467:%.*]] = sext i1 [[TMP466]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP467]], ptr [[CR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP468:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP469:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP468]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP469]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP470:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP471:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP470]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP471]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP472:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP473:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP472]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP473]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP474:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP475:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP474]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP475]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP476:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP477:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP478:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP476]], i8 [[TMP477]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP479:%.*]] = extractvalue { i8, i1 } [[TMP478]], 0
|
|
// CHECK-NEXT: store i8 [[TMP479]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP480:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP481:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP482:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP480]], i8 [[TMP481]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP483:%.*]] = extractvalue { i8, i1 } [[TMP482]], 0
|
|
// CHECK-NEXT: store i8 [[TMP483]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP484:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP485:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP484]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP486:%.*]] = icmp ugt i8 [[TMP485]], [[TMP484]]
|
|
// CHECK-NEXT: [[TMP487:%.*]] = select i1 [[TMP486]], i8 [[TMP484]], i8 [[TMP485]]
|
|
// CHECK-NEXT: store i8 [[TMP487]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP488:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP489:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP488]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP490:%.*]] = icmp ult i8 [[TMP489]], [[TMP488]]
|
|
// CHECK-NEXT: [[TMP491:%.*]] = select i1 [[TMP490]], i8 [[TMP488]], i8 [[TMP489]]
|
|
// CHECK-NEXT: store i8 [[TMP491]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP492:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP493:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP492]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP494:%.*]] = icmp ult i8 [[TMP493]], [[TMP492]]
|
|
// CHECK-NEXT: [[TMP495:%.*]] = select i1 [[TMP494]], i8 [[TMP492]], i8 [[TMP493]]
|
|
// CHECK-NEXT: store i8 [[TMP495]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP496:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP497:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP496]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP498:%.*]] = icmp ugt i8 [[TMP497]], [[TMP496]]
|
|
// CHECK-NEXT: [[TMP499:%.*]] = select i1 [[TMP498]], i8 [[TMP496]], i8 [[TMP497]]
|
|
// CHECK-NEXT: store i8 [[TMP499]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP500:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP501:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP502:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP500]], i8 [[TMP501]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP503:%.*]] = extractvalue { i8, i1 } [[TMP502]], 0
|
|
// CHECK-NEXT: [[TMP504:%.*]] = extractvalue { i8, i1 } [[TMP502]], 1
|
|
// CHECK-NEXT: [[TMP505:%.*]] = select i1 [[TMP504]], i8 [[TMP500]], i8 [[TMP503]]
|
|
// CHECK-NEXT: store i8 [[TMP505]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP506:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP507:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP508:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP506]], i8 [[TMP507]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP509:%.*]] = extractvalue { i8, i1 } [[TMP508]], 0
|
|
// CHECK-NEXT: [[TMP510:%.*]] = extractvalue { i8, i1 } [[TMP508]], 1
|
|
// CHECK-NEXT: [[TMP511:%.*]] = select i1 [[TMP510]], i8 [[TMP506]], i8 [[TMP509]]
|
|
// CHECK-NEXT: store i8 [[TMP511]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP512:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP513:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP514:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP512]], i8 [[TMP513]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP515:%.*]] = extractvalue { i8, i1 } [[TMP514]], 0
|
|
// CHECK-NEXT: [[TMP516:%.*]] = extractvalue { i8, i1 } [[TMP514]], 1
|
|
// CHECK-NEXT: br i1 [[TMP516]], label [[UCX_ATOMIC_EXIT:%.*]], label [[UCX_ATOMIC_CONT:%.*]]
|
|
// CHECK: ucx.atomic.cont:
|
|
// CHECK-NEXT: store i8 [[TMP515]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT]]
|
|
// CHECK: ucx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP517:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP518:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP519:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP517]], i8 [[TMP518]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP520:%.*]] = extractvalue { i8, i1 } [[TMP519]], 0
|
|
// CHECK-NEXT: [[TMP521:%.*]] = extractvalue { i8, i1 } [[TMP519]], 1
|
|
// CHECK-NEXT: br i1 [[TMP521]], label [[UCX_ATOMIC_EXIT47:%.*]], label [[UCX_ATOMIC_CONT48:%.*]]
|
|
// CHECK: ucx.atomic.cont48:
|
|
// CHECK-NEXT: store i8 [[TMP520]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT47]]
|
|
// CHECK: ucx.atomic.exit47:
|
|
// CHECK-NEXT: [[TMP522:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP523:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP524:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP522]], i8 [[TMP523]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP525:%.*]] = extractvalue { i8, i1 } [[TMP524]], 1
|
|
// CHECK-NEXT: [[TMP526:%.*]] = zext i1 [[TMP525]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP526]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP527:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP528:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP529:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP527]], i8 [[TMP528]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP530:%.*]] = extractvalue { i8, i1 } [[TMP529]], 1
|
|
// CHECK-NEXT: [[TMP531:%.*]] = zext i1 [[TMP530]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP531]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP532:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP533:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP534:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP532]], i8 [[TMP533]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP535:%.*]] = extractvalue { i8, i1 } [[TMP534]], 0
|
|
// CHECK-NEXT: [[TMP536:%.*]] = extractvalue { i8, i1 } [[TMP534]], 1
|
|
// CHECK-NEXT: br i1 [[TMP536]], label [[UCX_ATOMIC_EXIT49:%.*]], label [[UCX_ATOMIC_CONT50:%.*]]
|
|
// CHECK: ucx.atomic.cont50:
|
|
// CHECK-NEXT: store i8 [[TMP535]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT49]]
|
|
// CHECK: ucx.atomic.exit49:
|
|
// CHECK-NEXT: [[TMP537:%.*]] = extractvalue { i8, i1 } [[TMP534]], 1
|
|
// CHECK-NEXT: [[TMP538:%.*]] = zext i1 [[TMP537]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP538]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP539:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP540:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP541:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP539]], i8 [[TMP540]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP542:%.*]] = extractvalue { i8, i1 } [[TMP541]], 0
|
|
// CHECK-NEXT: [[TMP543:%.*]] = extractvalue { i8, i1 } [[TMP541]], 1
|
|
// CHECK-NEXT: br i1 [[TMP543]], label [[UCX_ATOMIC_EXIT51:%.*]], label [[UCX_ATOMIC_CONT52:%.*]]
|
|
// CHECK: ucx.atomic.cont52:
|
|
// CHECK-NEXT: store i8 [[TMP542]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT51]]
|
|
// CHECK: ucx.atomic.exit51:
|
|
// CHECK-NEXT: [[TMP544:%.*]] = extractvalue { i8, i1 } [[TMP541]], 1
|
|
// CHECK-NEXT: [[TMP545:%.*]] = zext i1 [[TMP544]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP545]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP546:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP547:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP546]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP547]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP548:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP549:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP548]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP549]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP550:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP551:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP550]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP551]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP552:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP553:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP552]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP553]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP554:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP555:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP556:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP554]], i8 [[TMP555]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP557:%.*]] = extractvalue { i8, i1 } [[TMP556]], 0
|
|
// CHECK-NEXT: store i8 [[TMP557]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP558:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP559:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP560:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP558]], i8 [[TMP559]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP561:%.*]] = extractvalue { i8, i1 } [[TMP560]], 0
|
|
// CHECK-NEXT: store i8 [[TMP561]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP562:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP563:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP562]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP564:%.*]] = icmp ugt i8 [[TMP563]], [[TMP562]]
|
|
// CHECK-NEXT: [[TMP565:%.*]] = select i1 [[TMP564]], i8 [[TMP562]], i8 [[TMP563]]
|
|
// CHECK-NEXT: store i8 [[TMP565]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP566:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP567:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP566]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP568:%.*]] = icmp ult i8 [[TMP567]], [[TMP566]]
|
|
// CHECK-NEXT: [[TMP569:%.*]] = select i1 [[TMP568]], i8 [[TMP566]], i8 [[TMP567]]
|
|
// CHECK-NEXT: store i8 [[TMP569]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP570:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP571:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP570]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP572:%.*]] = icmp ult i8 [[TMP571]], [[TMP570]]
|
|
// CHECK-NEXT: [[TMP573:%.*]] = select i1 [[TMP572]], i8 [[TMP570]], i8 [[TMP571]]
|
|
// CHECK-NEXT: store i8 [[TMP573]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP574:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP575:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP574]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP576:%.*]] = icmp ugt i8 [[TMP575]], [[TMP574]]
|
|
// CHECK-NEXT: [[TMP577:%.*]] = select i1 [[TMP576]], i8 [[TMP574]], i8 [[TMP575]]
|
|
// CHECK-NEXT: store i8 [[TMP577]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP578:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP579:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP580:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP578]], i8 [[TMP579]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP581:%.*]] = extractvalue { i8, i1 } [[TMP580]], 0
|
|
// CHECK-NEXT: [[TMP582:%.*]] = extractvalue { i8, i1 } [[TMP580]], 1
|
|
// CHECK-NEXT: [[TMP583:%.*]] = select i1 [[TMP582]], i8 [[TMP578]], i8 [[TMP581]]
|
|
// CHECK-NEXT: store i8 [[TMP583]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP584:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP585:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP586:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP584]], i8 [[TMP585]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP587:%.*]] = extractvalue { i8, i1 } [[TMP586]], 0
|
|
// CHECK-NEXT: [[TMP588:%.*]] = extractvalue { i8, i1 } [[TMP586]], 1
|
|
// CHECK-NEXT: [[TMP589:%.*]] = select i1 [[TMP588]], i8 [[TMP584]], i8 [[TMP587]]
|
|
// CHECK-NEXT: store i8 [[TMP589]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP590:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP591:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP592:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP590]], i8 [[TMP591]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP593:%.*]] = extractvalue { i8, i1 } [[TMP592]], 0
|
|
// CHECK-NEXT: [[TMP594:%.*]] = extractvalue { i8, i1 } [[TMP592]], 1
|
|
// CHECK-NEXT: br i1 [[TMP594]], label [[UCX_ATOMIC_EXIT53:%.*]], label [[UCX_ATOMIC_CONT54:%.*]]
|
|
// CHECK: ucx.atomic.cont54:
|
|
// CHECK-NEXT: store i8 [[TMP593]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT53]]
|
|
// CHECK: ucx.atomic.exit53:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP595:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP596:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP597:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP595]], i8 [[TMP596]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP598:%.*]] = extractvalue { i8, i1 } [[TMP597]], 0
|
|
// CHECK-NEXT: [[TMP599:%.*]] = extractvalue { i8, i1 } [[TMP597]], 1
|
|
// CHECK-NEXT: br i1 [[TMP599]], label [[UCX_ATOMIC_EXIT55:%.*]], label [[UCX_ATOMIC_CONT56:%.*]]
|
|
// CHECK: ucx.atomic.cont56:
|
|
// CHECK-NEXT: store i8 [[TMP598]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT55]]
|
|
// CHECK: ucx.atomic.exit55:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP600:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP601:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP602:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP600]], i8 [[TMP601]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP603:%.*]] = extractvalue { i8, i1 } [[TMP602]], 1
|
|
// CHECK-NEXT: [[TMP604:%.*]] = zext i1 [[TMP603]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP604]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP605:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP606:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP607:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP605]], i8 [[TMP606]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP608:%.*]] = extractvalue { i8, i1 } [[TMP607]], 1
|
|
// CHECK-NEXT: [[TMP609:%.*]] = zext i1 [[TMP608]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP609]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP610:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP611:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP612:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP610]], i8 [[TMP611]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP613:%.*]] = extractvalue { i8, i1 } [[TMP612]], 0
|
|
// CHECK-NEXT: [[TMP614:%.*]] = extractvalue { i8, i1 } [[TMP612]], 1
|
|
// CHECK-NEXT: br i1 [[TMP614]], label [[UCX_ATOMIC_EXIT57:%.*]], label [[UCX_ATOMIC_CONT58:%.*]]
|
|
// CHECK: ucx.atomic.cont58:
|
|
// CHECK-NEXT: store i8 [[TMP613]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT57]]
|
|
// CHECK: ucx.atomic.exit57:
|
|
// CHECK-NEXT: [[TMP615:%.*]] = extractvalue { i8, i1 } [[TMP612]], 1
|
|
// CHECK-NEXT: [[TMP616:%.*]] = zext i1 [[TMP615]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP616]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP617:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP618:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP619:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP617]], i8 [[TMP618]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP620:%.*]] = extractvalue { i8, i1 } [[TMP619]], 0
|
|
// CHECK-NEXT: [[TMP621:%.*]] = extractvalue { i8, i1 } [[TMP619]], 1
|
|
// CHECK-NEXT: br i1 [[TMP621]], label [[UCX_ATOMIC_EXIT59:%.*]], label [[UCX_ATOMIC_CONT60:%.*]]
|
|
// CHECK: ucx.atomic.cont60:
|
|
// CHECK-NEXT: store i8 [[TMP620]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT59]]
|
|
// CHECK: ucx.atomic.exit59:
|
|
// CHECK-NEXT: [[TMP622:%.*]] = extractvalue { i8, i1 } [[TMP619]], 1
|
|
// CHECK-NEXT: [[TMP623:%.*]] = zext i1 [[TMP622]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP623]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP624:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP625:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP624]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP625]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP626:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP627:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP626]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP627]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP628:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP629:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP628]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP629]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP630:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP631:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP630]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP631]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP632:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP633:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP634:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP632]], i8 [[TMP633]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP635:%.*]] = extractvalue { i8, i1 } [[TMP634]], 0
|
|
// CHECK-NEXT: store i8 [[TMP635]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP636:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP637:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP638:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP636]], i8 [[TMP637]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP639:%.*]] = extractvalue { i8, i1 } [[TMP638]], 0
|
|
// CHECK-NEXT: store i8 [[TMP639]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP640:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP641:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP640]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP642:%.*]] = icmp ugt i8 [[TMP641]], [[TMP640]]
|
|
// CHECK-NEXT: [[TMP643:%.*]] = select i1 [[TMP642]], i8 [[TMP640]], i8 [[TMP641]]
|
|
// CHECK-NEXT: store i8 [[TMP643]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP644:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP645:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP644]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP646:%.*]] = icmp ult i8 [[TMP645]], [[TMP644]]
|
|
// CHECK-NEXT: [[TMP647:%.*]] = select i1 [[TMP646]], i8 [[TMP644]], i8 [[TMP645]]
|
|
// CHECK-NEXT: store i8 [[TMP647]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP648:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP649:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP648]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP650:%.*]] = icmp ult i8 [[TMP649]], [[TMP648]]
|
|
// CHECK-NEXT: [[TMP651:%.*]] = select i1 [[TMP650]], i8 [[TMP648]], i8 [[TMP649]]
|
|
// CHECK-NEXT: store i8 [[TMP651]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP652:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP653:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP652]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP654:%.*]] = icmp ugt i8 [[TMP653]], [[TMP652]]
|
|
// CHECK-NEXT: [[TMP655:%.*]] = select i1 [[TMP654]], i8 [[TMP652]], i8 [[TMP653]]
|
|
// CHECK-NEXT: store i8 [[TMP655]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP656:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP657:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP658:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP656]], i8 [[TMP657]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP659:%.*]] = extractvalue { i8, i1 } [[TMP658]], 0
|
|
// CHECK-NEXT: [[TMP660:%.*]] = extractvalue { i8, i1 } [[TMP658]], 1
|
|
// CHECK-NEXT: [[TMP661:%.*]] = select i1 [[TMP660]], i8 [[TMP656]], i8 [[TMP659]]
|
|
// CHECK-NEXT: store i8 [[TMP661]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP662:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP663:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP664:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP662]], i8 [[TMP663]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP665:%.*]] = extractvalue { i8, i1 } [[TMP664]], 0
|
|
// CHECK-NEXT: [[TMP666:%.*]] = extractvalue { i8, i1 } [[TMP664]], 1
|
|
// CHECK-NEXT: [[TMP667:%.*]] = select i1 [[TMP666]], i8 [[TMP662]], i8 [[TMP665]]
|
|
// CHECK-NEXT: store i8 [[TMP667]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP668:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP669:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP670:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP668]], i8 [[TMP669]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP671:%.*]] = extractvalue { i8, i1 } [[TMP670]], 0
|
|
// CHECK-NEXT: [[TMP672:%.*]] = extractvalue { i8, i1 } [[TMP670]], 1
|
|
// CHECK-NEXT: br i1 [[TMP672]], label [[UCX_ATOMIC_EXIT61:%.*]], label [[UCX_ATOMIC_CONT62:%.*]]
|
|
// CHECK: ucx.atomic.cont62:
|
|
// CHECK-NEXT: store i8 [[TMP671]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT61]]
|
|
// CHECK: ucx.atomic.exit61:
|
|
// CHECK-NEXT: [[TMP673:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP674:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP675:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP673]], i8 [[TMP674]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP676:%.*]] = extractvalue { i8, i1 } [[TMP675]], 0
|
|
// CHECK-NEXT: [[TMP677:%.*]] = extractvalue { i8, i1 } [[TMP675]], 1
|
|
// CHECK-NEXT: br i1 [[TMP677]], label [[UCX_ATOMIC_EXIT63:%.*]], label [[UCX_ATOMIC_CONT64:%.*]]
|
|
// CHECK: ucx.atomic.cont64:
|
|
// CHECK-NEXT: store i8 [[TMP676]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT63]]
|
|
// CHECK: ucx.atomic.exit63:
|
|
// CHECK-NEXT: [[TMP678:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP679:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP680:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP678]], i8 [[TMP679]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP681:%.*]] = extractvalue { i8, i1 } [[TMP680]], 1
|
|
// CHECK-NEXT: [[TMP682:%.*]] = zext i1 [[TMP681]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP682]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP683:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP684:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP685:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP683]], i8 [[TMP684]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP686:%.*]] = extractvalue { i8, i1 } [[TMP685]], 1
|
|
// CHECK-NEXT: [[TMP687:%.*]] = zext i1 [[TMP686]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP687]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP688:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP689:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP690:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP688]], i8 [[TMP689]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP691:%.*]] = extractvalue { i8, i1 } [[TMP690]], 0
|
|
// CHECK-NEXT: [[TMP692:%.*]] = extractvalue { i8, i1 } [[TMP690]], 1
|
|
// CHECK-NEXT: br i1 [[TMP692]], label [[UCX_ATOMIC_EXIT65:%.*]], label [[UCX_ATOMIC_CONT66:%.*]]
|
|
// CHECK: ucx.atomic.cont66:
|
|
// CHECK-NEXT: store i8 [[TMP691]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT65]]
|
|
// CHECK: ucx.atomic.exit65:
|
|
// CHECK-NEXT: [[TMP693:%.*]] = extractvalue { i8, i1 } [[TMP690]], 1
|
|
// CHECK-NEXT: [[TMP694:%.*]] = zext i1 [[TMP693]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP694]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP695:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP696:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP697:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP695]], i8 [[TMP696]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP698:%.*]] = extractvalue { i8, i1 } [[TMP697]], 0
|
|
// CHECK-NEXT: [[TMP699:%.*]] = extractvalue { i8, i1 } [[TMP697]], 1
|
|
// CHECK-NEXT: br i1 [[TMP699]], label [[UCX_ATOMIC_EXIT67:%.*]], label [[UCX_ATOMIC_CONT68:%.*]]
|
|
// CHECK: ucx.atomic.cont68:
|
|
// CHECK-NEXT: store i8 [[TMP698]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT67]]
|
|
// CHECK: ucx.atomic.exit67:
|
|
// CHECK-NEXT: [[TMP700:%.*]] = extractvalue { i8, i1 } [[TMP697]], 1
|
|
// CHECK-NEXT: [[TMP701:%.*]] = zext i1 [[TMP700]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP701]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP702:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP703:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP702]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP703]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP704:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP705:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP704]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP705]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP706:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP707:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP706]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP707]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP708:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP709:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP708]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP709]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP710:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP711:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP712:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP710]], i8 [[TMP711]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP713:%.*]] = extractvalue { i8, i1 } [[TMP712]], 0
|
|
// CHECK-NEXT: store i8 [[TMP713]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP714:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP715:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP716:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP714]], i8 [[TMP715]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP717:%.*]] = extractvalue { i8, i1 } [[TMP716]], 0
|
|
// CHECK-NEXT: store i8 [[TMP717]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP718:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP719:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP718]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP720:%.*]] = icmp ugt i8 [[TMP719]], [[TMP718]]
|
|
// CHECK-NEXT: [[TMP721:%.*]] = select i1 [[TMP720]], i8 [[TMP718]], i8 [[TMP719]]
|
|
// CHECK-NEXT: store i8 [[TMP721]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP722:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP723:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP722]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP724:%.*]] = icmp ult i8 [[TMP723]], [[TMP722]]
|
|
// CHECK-NEXT: [[TMP725:%.*]] = select i1 [[TMP724]], i8 [[TMP722]], i8 [[TMP723]]
|
|
// CHECK-NEXT: store i8 [[TMP725]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP726:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP727:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP726]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP728:%.*]] = icmp ult i8 [[TMP727]], [[TMP726]]
|
|
// CHECK-NEXT: [[TMP729:%.*]] = select i1 [[TMP728]], i8 [[TMP726]], i8 [[TMP727]]
|
|
// CHECK-NEXT: store i8 [[TMP729]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP730:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP731:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP730]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP732:%.*]] = icmp ugt i8 [[TMP731]], [[TMP730]]
|
|
// CHECK-NEXT: [[TMP733:%.*]] = select i1 [[TMP732]], i8 [[TMP730]], i8 [[TMP731]]
|
|
// CHECK-NEXT: store i8 [[TMP733]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP734:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP735:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP736:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP734]], i8 [[TMP735]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP737:%.*]] = extractvalue { i8, i1 } [[TMP736]], 0
|
|
// CHECK-NEXT: [[TMP738:%.*]] = extractvalue { i8, i1 } [[TMP736]], 1
|
|
// CHECK-NEXT: [[TMP739:%.*]] = select i1 [[TMP738]], i8 [[TMP734]], i8 [[TMP737]]
|
|
// CHECK-NEXT: store i8 [[TMP739]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP740:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP741:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP742:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP740]], i8 [[TMP741]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP743:%.*]] = extractvalue { i8, i1 } [[TMP742]], 0
|
|
// CHECK-NEXT: [[TMP744:%.*]] = extractvalue { i8, i1 } [[TMP742]], 1
|
|
// CHECK-NEXT: [[TMP745:%.*]] = select i1 [[TMP744]], i8 [[TMP740]], i8 [[TMP743]]
|
|
// CHECK-NEXT: store i8 [[TMP745]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP746:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP747:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP748:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP746]], i8 [[TMP747]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP749:%.*]] = extractvalue { i8, i1 } [[TMP748]], 0
|
|
// CHECK-NEXT: [[TMP750:%.*]] = extractvalue { i8, i1 } [[TMP748]], 1
|
|
// CHECK-NEXT: br i1 [[TMP750]], label [[UCX_ATOMIC_EXIT69:%.*]], label [[UCX_ATOMIC_CONT70:%.*]]
|
|
// CHECK: ucx.atomic.cont70:
|
|
// CHECK-NEXT: store i8 [[TMP749]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT69]]
|
|
// CHECK: ucx.atomic.exit69:
|
|
// CHECK-NEXT: [[TMP751:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP752:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP753:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP751]], i8 [[TMP752]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP754:%.*]] = extractvalue { i8, i1 } [[TMP753]], 0
|
|
// CHECK-NEXT: [[TMP755:%.*]] = extractvalue { i8, i1 } [[TMP753]], 1
|
|
// CHECK-NEXT: br i1 [[TMP755]], label [[UCX_ATOMIC_EXIT71:%.*]], label [[UCX_ATOMIC_CONT72:%.*]]
|
|
// CHECK: ucx.atomic.cont72:
|
|
// CHECK-NEXT: store i8 [[TMP754]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT71]]
|
|
// CHECK: ucx.atomic.exit71:
|
|
// CHECK-NEXT: [[TMP756:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP757:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP758:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP756]], i8 [[TMP757]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP759:%.*]] = extractvalue { i8, i1 } [[TMP758]], 1
|
|
// CHECK-NEXT: [[TMP760:%.*]] = zext i1 [[TMP759]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP760]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP761:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP762:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP763:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP761]], i8 [[TMP762]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP764:%.*]] = extractvalue { i8, i1 } [[TMP763]], 1
|
|
// CHECK-NEXT: [[TMP765:%.*]] = zext i1 [[TMP764]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP765]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP766:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP767:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP768:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP766]], i8 [[TMP767]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP769:%.*]] = extractvalue { i8, i1 } [[TMP768]], 0
|
|
// CHECK-NEXT: [[TMP770:%.*]] = extractvalue { i8, i1 } [[TMP768]], 1
|
|
// CHECK-NEXT: br i1 [[TMP770]], label [[UCX_ATOMIC_EXIT73:%.*]], label [[UCX_ATOMIC_CONT74:%.*]]
|
|
// CHECK: ucx.atomic.cont74:
|
|
// CHECK-NEXT: store i8 [[TMP769]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT73]]
|
|
// CHECK: ucx.atomic.exit73:
|
|
// CHECK-NEXT: [[TMP771:%.*]] = extractvalue { i8, i1 } [[TMP768]], 1
|
|
// CHECK-NEXT: [[TMP772:%.*]] = zext i1 [[TMP771]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP772]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP773:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP774:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP775:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP773]], i8 [[TMP774]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP776:%.*]] = extractvalue { i8, i1 } [[TMP775]], 0
|
|
// CHECK-NEXT: [[TMP777:%.*]] = extractvalue { i8, i1 } [[TMP775]], 1
|
|
// CHECK-NEXT: br i1 [[TMP777]], label [[UCX_ATOMIC_EXIT75:%.*]], label [[UCX_ATOMIC_CONT76:%.*]]
|
|
// CHECK: ucx.atomic.cont76:
|
|
// CHECK-NEXT: store i8 [[TMP776]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT75]]
|
|
// CHECK: ucx.atomic.exit75:
|
|
// CHECK-NEXT: [[TMP778:%.*]] = extractvalue { i8, i1 } [[TMP775]], 1
|
|
// CHECK-NEXT: [[TMP779:%.*]] = zext i1 [[TMP778]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP779]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: [[TMP780:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP781:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP780]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP781]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP782:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP783:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP782]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP783]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP784:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP785:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP784]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP785]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP786:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP787:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP786]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP787]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP788:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP789:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP790:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP788]], i8 [[TMP789]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP791:%.*]] = extractvalue { i8, i1 } [[TMP790]], 0
|
|
// CHECK-NEXT: store i8 [[TMP791]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP792:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP793:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP794:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP792]], i8 [[TMP793]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP795:%.*]] = extractvalue { i8, i1 } [[TMP794]], 0
|
|
// CHECK-NEXT: store i8 [[TMP795]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP796:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP797:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP796]] release, align 1
|
|
// CHECK-NEXT: [[TMP798:%.*]] = icmp ugt i8 [[TMP797]], [[TMP796]]
|
|
// CHECK-NEXT: [[TMP799:%.*]] = select i1 [[TMP798]], i8 [[TMP796]], i8 [[TMP797]]
|
|
// CHECK-NEXT: store i8 [[TMP799]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP800:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP801:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP800]] release, align 1
|
|
// CHECK-NEXT: [[TMP802:%.*]] = icmp ult i8 [[TMP801]], [[TMP800]]
|
|
// CHECK-NEXT: [[TMP803:%.*]] = select i1 [[TMP802]], i8 [[TMP800]], i8 [[TMP801]]
|
|
// CHECK-NEXT: store i8 [[TMP803]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP804:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP805:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP804]] release, align 1
|
|
// CHECK-NEXT: [[TMP806:%.*]] = icmp ult i8 [[TMP805]], [[TMP804]]
|
|
// CHECK-NEXT: [[TMP807:%.*]] = select i1 [[TMP806]], i8 [[TMP804]], i8 [[TMP805]]
|
|
// CHECK-NEXT: store i8 [[TMP807]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP808:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP809:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP808]] release, align 1
|
|
// CHECK-NEXT: [[TMP810:%.*]] = icmp ugt i8 [[TMP809]], [[TMP808]]
|
|
// CHECK-NEXT: [[TMP811:%.*]] = select i1 [[TMP810]], i8 [[TMP808]], i8 [[TMP809]]
|
|
// CHECK-NEXT: store i8 [[TMP811]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP812:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP813:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP814:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP812]], i8 [[TMP813]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP815:%.*]] = extractvalue { i8, i1 } [[TMP814]], 0
|
|
// CHECK-NEXT: [[TMP816:%.*]] = extractvalue { i8, i1 } [[TMP814]], 1
|
|
// CHECK-NEXT: [[TMP817:%.*]] = select i1 [[TMP816]], i8 [[TMP812]], i8 [[TMP815]]
|
|
// CHECK-NEXT: store i8 [[TMP817]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP818:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP819:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP820:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP818]], i8 [[TMP819]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP821:%.*]] = extractvalue { i8, i1 } [[TMP820]], 0
|
|
// CHECK-NEXT: [[TMP822:%.*]] = extractvalue { i8, i1 } [[TMP820]], 1
|
|
// CHECK-NEXT: [[TMP823:%.*]] = select i1 [[TMP822]], i8 [[TMP818]], i8 [[TMP821]]
|
|
// CHECK-NEXT: store i8 [[TMP823]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP824:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP825:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP826:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP824]], i8 [[TMP825]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP827:%.*]] = extractvalue { i8, i1 } [[TMP826]], 0
|
|
// CHECK-NEXT: [[TMP828:%.*]] = extractvalue { i8, i1 } [[TMP826]], 1
|
|
// CHECK-NEXT: br i1 [[TMP828]], label [[UCX_ATOMIC_EXIT77:%.*]], label [[UCX_ATOMIC_CONT78:%.*]]
|
|
// CHECK: ucx.atomic.cont78:
|
|
// CHECK-NEXT: store i8 [[TMP827]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT77]]
|
|
// CHECK: ucx.atomic.exit77:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP829:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP830:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP831:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP829]], i8 [[TMP830]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP832:%.*]] = extractvalue { i8, i1 } [[TMP831]], 0
|
|
// CHECK-NEXT: [[TMP833:%.*]] = extractvalue { i8, i1 } [[TMP831]], 1
|
|
// CHECK-NEXT: br i1 [[TMP833]], label [[UCX_ATOMIC_EXIT79:%.*]], label [[UCX_ATOMIC_CONT80:%.*]]
|
|
// CHECK: ucx.atomic.cont80:
|
|
// CHECK-NEXT: store i8 [[TMP832]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT79]]
|
|
// CHECK: ucx.atomic.exit79:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP834:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP835:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP836:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP834]], i8 [[TMP835]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP837:%.*]] = extractvalue { i8, i1 } [[TMP836]], 1
|
|
// CHECK-NEXT: [[TMP838:%.*]] = zext i1 [[TMP837]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP838]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP839:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP840:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP841:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP839]], i8 [[TMP840]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP842:%.*]] = extractvalue { i8, i1 } [[TMP841]], 1
|
|
// CHECK-NEXT: [[TMP843:%.*]] = zext i1 [[TMP842]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP843]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP844:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP845:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP846:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP844]], i8 [[TMP845]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP847:%.*]] = extractvalue { i8, i1 } [[TMP846]], 0
|
|
// CHECK-NEXT: [[TMP848:%.*]] = extractvalue { i8, i1 } [[TMP846]], 1
|
|
// CHECK-NEXT: br i1 [[TMP848]], label [[UCX_ATOMIC_EXIT81:%.*]], label [[UCX_ATOMIC_CONT82:%.*]]
|
|
// CHECK: ucx.atomic.cont82:
|
|
// CHECK-NEXT: store i8 [[TMP847]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT81]]
|
|
// CHECK: ucx.atomic.exit81:
|
|
// CHECK-NEXT: [[TMP849:%.*]] = extractvalue { i8, i1 } [[TMP846]], 1
|
|
// CHECK-NEXT: [[TMP850:%.*]] = zext i1 [[TMP849]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP850]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP851:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP852:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP853:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP851]], i8 [[TMP852]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP854:%.*]] = extractvalue { i8, i1 } [[TMP853]], 0
|
|
// CHECK-NEXT: [[TMP855:%.*]] = extractvalue { i8, i1 } [[TMP853]], 1
|
|
// CHECK-NEXT: br i1 [[TMP855]], label [[UCX_ATOMIC_EXIT83:%.*]], label [[UCX_ATOMIC_CONT84:%.*]]
|
|
// CHECK: ucx.atomic.cont84:
|
|
// CHECK-NEXT: store i8 [[TMP854]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT83]]
|
|
// CHECK: ucx.atomic.exit83:
|
|
// CHECK-NEXT: [[TMP856:%.*]] = extractvalue { i8, i1 } [[TMP853]], 1
|
|
// CHECK-NEXT: [[TMP857:%.*]] = zext i1 [[TMP856]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP857]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP858:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP859:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP858]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP859]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP860:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP861:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP860]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP861]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP862:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP863:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP862]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP863]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP864:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP865:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP864]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP865]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP866:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP867:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP868:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP866]], i8 [[TMP867]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP869:%.*]] = extractvalue { i8, i1 } [[TMP868]], 0
|
|
// CHECK-NEXT: store i8 [[TMP869]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP870:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP871:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP872:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP870]], i8 [[TMP871]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP873:%.*]] = extractvalue { i8, i1 } [[TMP872]], 0
|
|
// CHECK-NEXT: store i8 [[TMP873]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP874:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP875:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP874]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP876:%.*]] = icmp ugt i8 [[TMP875]], [[TMP874]]
|
|
// CHECK-NEXT: [[TMP877:%.*]] = select i1 [[TMP876]], i8 [[TMP874]], i8 [[TMP875]]
|
|
// CHECK-NEXT: store i8 [[TMP877]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP878:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP879:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP878]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP880:%.*]] = icmp ult i8 [[TMP879]], [[TMP878]]
|
|
// CHECK-NEXT: [[TMP881:%.*]] = select i1 [[TMP880]], i8 [[TMP878]], i8 [[TMP879]]
|
|
// CHECK-NEXT: store i8 [[TMP881]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP882:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP883:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP882]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP884:%.*]] = icmp ult i8 [[TMP883]], [[TMP882]]
|
|
// CHECK-NEXT: [[TMP885:%.*]] = select i1 [[TMP884]], i8 [[TMP882]], i8 [[TMP883]]
|
|
// CHECK-NEXT: store i8 [[TMP885]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP886:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP887:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP886]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP888:%.*]] = icmp ugt i8 [[TMP887]], [[TMP886]]
|
|
// CHECK-NEXT: [[TMP889:%.*]] = select i1 [[TMP888]], i8 [[TMP886]], i8 [[TMP887]]
|
|
// CHECK-NEXT: store i8 [[TMP889]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP890:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP891:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP892:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP890]], i8 [[TMP891]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP893:%.*]] = extractvalue { i8, i1 } [[TMP892]], 0
|
|
// CHECK-NEXT: [[TMP894:%.*]] = extractvalue { i8, i1 } [[TMP892]], 1
|
|
// CHECK-NEXT: [[TMP895:%.*]] = select i1 [[TMP894]], i8 [[TMP890]], i8 [[TMP893]]
|
|
// CHECK-NEXT: store i8 [[TMP895]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP896:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP897:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP898:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP896]], i8 [[TMP897]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP899:%.*]] = extractvalue { i8, i1 } [[TMP898]], 0
|
|
// CHECK-NEXT: [[TMP900:%.*]] = extractvalue { i8, i1 } [[TMP898]], 1
|
|
// CHECK-NEXT: [[TMP901:%.*]] = select i1 [[TMP900]], i8 [[TMP896]], i8 [[TMP899]]
|
|
// CHECK-NEXT: store i8 [[TMP901]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP902:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP903:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP904:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP902]], i8 [[TMP903]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP905:%.*]] = extractvalue { i8, i1 } [[TMP904]], 0
|
|
// CHECK-NEXT: [[TMP906:%.*]] = extractvalue { i8, i1 } [[TMP904]], 1
|
|
// CHECK-NEXT: br i1 [[TMP906]], label [[UCX_ATOMIC_EXIT85:%.*]], label [[UCX_ATOMIC_CONT86:%.*]]
|
|
// CHECK: ucx.atomic.cont86:
|
|
// CHECK-NEXT: store i8 [[TMP905]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT85]]
|
|
// CHECK: ucx.atomic.exit85:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP907:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP908:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP909:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP907]], i8 [[TMP908]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP910:%.*]] = extractvalue { i8, i1 } [[TMP909]], 0
|
|
// CHECK-NEXT: [[TMP911:%.*]] = extractvalue { i8, i1 } [[TMP909]], 1
|
|
// CHECK-NEXT: br i1 [[TMP911]], label [[UCX_ATOMIC_EXIT87:%.*]], label [[UCX_ATOMIC_CONT88:%.*]]
|
|
// CHECK: ucx.atomic.cont88:
|
|
// CHECK-NEXT: store i8 [[TMP910]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT87]]
|
|
// CHECK: ucx.atomic.exit87:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP912:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP913:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP914:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP912]], i8 [[TMP913]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP915:%.*]] = extractvalue { i8, i1 } [[TMP914]], 1
|
|
// CHECK-NEXT: [[TMP916:%.*]] = zext i1 [[TMP915]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP916]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP917:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP918:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP919:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP917]], i8 [[TMP918]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP920:%.*]] = extractvalue { i8, i1 } [[TMP919]], 1
|
|
// CHECK-NEXT: [[TMP921:%.*]] = zext i1 [[TMP920]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP921]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP922:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP923:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP924:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP922]], i8 [[TMP923]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP925:%.*]] = extractvalue { i8, i1 } [[TMP924]], 0
|
|
// CHECK-NEXT: [[TMP926:%.*]] = extractvalue { i8, i1 } [[TMP924]], 1
|
|
// CHECK-NEXT: br i1 [[TMP926]], label [[UCX_ATOMIC_EXIT89:%.*]], label [[UCX_ATOMIC_CONT90:%.*]]
|
|
// CHECK: ucx.atomic.cont90:
|
|
// CHECK-NEXT: store i8 [[TMP925]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT89]]
|
|
// CHECK: ucx.atomic.exit89:
|
|
// CHECK-NEXT: [[TMP927:%.*]] = extractvalue { i8, i1 } [[TMP924]], 1
|
|
// CHECK-NEXT: [[TMP928:%.*]] = zext i1 [[TMP927]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP928]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP929:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP930:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP931:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP929]], i8 [[TMP930]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP932:%.*]] = extractvalue { i8, i1 } [[TMP931]], 0
|
|
// CHECK-NEXT: [[TMP933:%.*]] = extractvalue { i8, i1 } [[TMP931]], 1
|
|
// CHECK-NEXT: br i1 [[TMP933]], label [[UCX_ATOMIC_EXIT91:%.*]], label [[UCX_ATOMIC_CONT92:%.*]]
|
|
// CHECK: ucx.atomic.cont92:
|
|
// CHECK-NEXT: store i8 [[TMP932]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT91]]
|
|
// CHECK: ucx.atomic.exit91:
|
|
// CHECK-NEXT: [[TMP934:%.*]] = extractvalue { i8, i1 } [[TMP931]], 1
|
|
// CHECK-NEXT: [[TMP935:%.*]] = zext i1 [[TMP934]] to i8
|
|
// CHECK-NEXT: store i8 [[TMP935]], ptr [[UCR]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP936:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP937:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP936]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP937]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP938:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP939:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP938]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP939]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP940:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP941:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP940]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP941]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP942:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP943:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP942]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP943]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP944:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP945:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP946:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP944]], i16 [[TMP945]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP947:%.*]] = extractvalue { i16, i1 } [[TMP946]], 0
|
|
// CHECK-NEXT: store i16 [[TMP947]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP948:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP949:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP950:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP948]], i16 [[TMP949]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP951:%.*]] = extractvalue { i16, i1 } [[TMP950]], 0
|
|
// CHECK-NEXT: store i16 [[TMP951]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP952:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP953:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP952]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP954:%.*]] = icmp sgt i16 [[TMP953]], [[TMP952]]
|
|
// CHECK-NEXT: [[TMP955:%.*]] = select i1 [[TMP954]], i16 [[TMP952]], i16 [[TMP953]]
|
|
// CHECK-NEXT: store i16 [[TMP955]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP956:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP957:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP956]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP958:%.*]] = icmp slt i16 [[TMP957]], [[TMP956]]
|
|
// CHECK-NEXT: [[TMP959:%.*]] = select i1 [[TMP958]], i16 [[TMP956]], i16 [[TMP957]]
|
|
// CHECK-NEXT: store i16 [[TMP959]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP960:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP961:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP960]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP962:%.*]] = icmp slt i16 [[TMP961]], [[TMP960]]
|
|
// CHECK-NEXT: [[TMP963:%.*]] = select i1 [[TMP962]], i16 [[TMP960]], i16 [[TMP961]]
|
|
// CHECK-NEXT: store i16 [[TMP963]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP964:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP965:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP964]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP966:%.*]] = icmp sgt i16 [[TMP965]], [[TMP964]]
|
|
// CHECK-NEXT: [[TMP967:%.*]] = select i1 [[TMP966]], i16 [[TMP964]], i16 [[TMP965]]
|
|
// CHECK-NEXT: store i16 [[TMP967]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP968:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP969:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP970:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP968]], i16 [[TMP969]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP971:%.*]] = extractvalue { i16, i1 } [[TMP970]], 0
|
|
// CHECK-NEXT: [[TMP972:%.*]] = extractvalue { i16, i1 } [[TMP970]], 1
|
|
// CHECK-NEXT: [[TMP973:%.*]] = select i1 [[TMP972]], i16 [[TMP968]], i16 [[TMP971]]
|
|
// CHECK-NEXT: store i16 [[TMP973]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP974:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP975:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP976:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP974]], i16 [[TMP975]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP977:%.*]] = extractvalue { i16, i1 } [[TMP976]], 0
|
|
// CHECK-NEXT: [[TMP978:%.*]] = extractvalue { i16, i1 } [[TMP976]], 1
|
|
// CHECK-NEXT: [[TMP979:%.*]] = select i1 [[TMP978]], i16 [[TMP974]], i16 [[TMP977]]
|
|
// CHECK-NEXT: store i16 [[TMP979]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP980:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP981:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP982:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP980]], i16 [[TMP981]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP983:%.*]] = extractvalue { i16, i1 } [[TMP982]], 0
|
|
// CHECK-NEXT: [[TMP984:%.*]] = extractvalue { i16, i1 } [[TMP982]], 1
|
|
// CHECK-NEXT: br i1 [[TMP984]], label [[SX_ATOMIC_EXIT:%.*]], label [[SX_ATOMIC_CONT:%.*]]
|
|
// CHECK: sx.atomic.cont:
|
|
// CHECK-NEXT: store i16 [[TMP983]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT]]
|
|
// CHECK: sx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP985:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP986:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP987:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP985]], i16 [[TMP986]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP988:%.*]] = extractvalue { i16, i1 } [[TMP987]], 0
|
|
// CHECK-NEXT: [[TMP989:%.*]] = extractvalue { i16, i1 } [[TMP987]], 1
|
|
// CHECK-NEXT: br i1 [[TMP989]], label [[SX_ATOMIC_EXIT93:%.*]], label [[SX_ATOMIC_CONT94:%.*]]
|
|
// CHECK: sx.atomic.cont94:
|
|
// CHECK-NEXT: store i16 [[TMP988]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT93]]
|
|
// CHECK: sx.atomic.exit93:
|
|
// CHECK-NEXT: [[TMP990:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP991:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP992:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP990]], i16 [[TMP991]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP993:%.*]] = extractvalue { i16, i1 } [[TMP992]], 1
|
|
// CHECK-NEXT: [[TMP994:%.*]] = sext i1 [[TMP993]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP994]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP995:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP996:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP997:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP995]], i16 [[TMP996]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP998:%.*]] = extractvalue { i16, i1 } [[TMP997]], 1
|
|
// CHECK-NEXT: [[TMP999:%.*]] = sext i1 [[TMP998]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP999]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1000:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1001:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1002:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1000]], i16 [[TMP1001]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1003:%.*]] = extractvalue { i16, i1 } [[TMP1002]], 0
|
|
// CHECK-NEXT: [[TMP1004:%.*]] = extractvalue { i16, i1 } [[TMP1002]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1004]], label [[SX_ATOMIC_EXIT95:%.*]], label [[SX_ATOMIC_CONT96:%.*]]
|
|
// CHECK: sx.atomic.cont96:
|
|
// CHECK-NEXT: store i16 [[TMP1003]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT95]]
|
|
// CHECK: sx.atomic.exit95:
|
|
// CHECK-NEXT: [[TMP1005:%.*]] = extractvalue { i16, i1 } [[TMP1002]], 1
|
|
// CHECK-NEXT: [[TMP1006:%.*]] = sext i1 [[TMP1005]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1006]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1007:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1008:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1009:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1007]], i16 [[TMP1008]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1010:%.*]] = extractvalue { i16, i1 } [[TMP1009]], 0
|
|
// CHECK-NEXT: [[TMP1011:%.*]] = extractvalue { i16, i1 } [[TMP1009]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1011]], label [[SX_ATOMIC_EXIT97:%.*]], label [[SX_ATOMIC_CONT98:%.*]]
|
|
// CHECK: sx.atomic.cont98:
|
|
// CHECK-NEXT: store i16 [[TMP1010]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT97]]
|
|
// CHECK: sx.atomic.exit97:
|
|
// CHECK-NEXT: [[TMP1012:%.*]] = extractvalue { i16, i1 } [[TMP1009]], 1
|
|
// CHECK-NEXT: [[TMP1013:%.*]] = sext i1 [[TMP1012]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1013]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1014:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1015:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1014]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1015]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1016:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1017:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1016]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1017]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1018:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1019:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1018]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1019]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1020:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1021:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1020]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1021]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1022:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1023:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1024:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1022]], i16 [[TMP1023]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1025:%.*]] = extractvalue { i16, i1 } [[TMP1024]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1025]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1026:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1027:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1028:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1026]], i16 [[TMP1027]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1029:%.*]] = extractvalue { i16, i1 } [[TMP1028]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1029]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1030:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1031:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1030]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP1032:%.*]] = icmp sgt i16 [[TMP1031]], [[TMP1030]]
|
|
// CHECK-NEXT: [[TMP1033:%.*]] = select i1 [[TMP1032]], i16 [[TMP1030]], i16 [[TMP1031]]
|
|
// CHECK-NEXT: store i16 [[TMP1033]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1034:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1035:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1034]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP1036:%.*]] = icmp slt i16 [[TMP1035]], [[TMP1034]]
|
|
// CHECK-NEXT: [[TMP1037:%.*]] = select i1 [[TMP1036]], i16 [[TMP1034]], i16 [[TMP1035]]
|
|
// CHECK-NEXT: store i16 [[TMP1037]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1038:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1039:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1038]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP1040:%.*]] = icmp slt i16 [[TMP1039]], [[TMP1038]]
|
|
// CHECK-NEXT: [[TMP1041:%.*]] = select i1 [[TMP1040]], i16 [[TMP1038]], i16 [[TMP1039]]
|
|
// CHECK-NEXT: store i16 [[TMP1041]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1042:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1043:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1042]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP1044:%.*]] = icmp sgt i16 [[TMP1043]], [[TMP1042]]
|
|
// CHECK-NEXT: [[TMP1045:%.*]] = select i1 [[TMP1044]], i16 [[TMP1042]], i16 [[TMP1043]]
|
|
// CHECK-NEXT: store i16 [[TMP1045]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1046:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1047:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1048:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1046]], i16 [[TMP1047]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1049:%.*]] = extractvalue { i16, i1 } [[TMP1048]], 0
|
|
// CHECK-NEXT: [[TMP1050:%.*]] = extractvalue { i16, i1 } [[TMP1048]], 1
|
|
// CHECK-NEXT: [[TMP1051:%.*]] = select i1 [[TMP1050]], i16 [[TMP1046]], i16 [[TMP1049]]
|
|
// CHECK-NEXT: store i16 [[TMP1051]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1052:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1053:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1054:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1052]], i16 [[TMP1053]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1055:%.*]] = extractvalue { i16, i1 } [[TMP1054]], 0
|
|
// CHECK-NEXT: [[TMP1056:%.*]] = extractvalue { i16, i1 } [[TMP1054]], 1
|
|
// CHECK-NEXT: [[TMP1057:%.*]] = select i1 [[TMP1056]], i16 [[TMP1052]], i16 [[TMP1055]]
|
|
// CHECK-NEXT: store i16 [[TMP1057]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1058:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1059:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1060:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1058]], i16 [[TMP1059]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1061:%.*]] = extractvalue { i16, i1 } [[TMP1060]], 0
|
|
// CHECK-NEXT: [[TMP1062:%.*]] = extractvalue { i16, i1 } [[TMP1060]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1062]], label [[SX_ATOMIC_EXIT99:%.*]], label [[SX_ATOMIC_CONT100:%.*]]
|
|
// CHECK: sx.atomic.cont100:
|
|
// CHECK-NEXT: store i16 [[TMP1061]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT99]]
|
|
// CHECK: sx.atomic.exit99:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1063:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1064:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1065:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1063]], i16 [[TMP1064]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1066:%.*]] = extractvalue { i16, i1 } [[TMP1065]], 0
|
|
// CHECK-NEXT: [[TMP1067:%.*]] = extractvalue { i16, i1 } [[TMP1065]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1067]], label [[SX_ATOMIC_EXIT101:%.*]], label [[SX_ATOMIC_CONT102:%.*]]
|
|
// CHECK: sx.atomic.cont102:
|
|
// CHECK-NEXT: store i16 [[TMP1066]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT101]]
|
|
// CHECK: sx.atomic.exit101:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1068:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1069:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1070:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1068]], i16 [[TMP1069]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1071:%.*]] = extractvalue { i16, i1 } [[TMP1070]], 1
|
|
// CHECK-NEXT: [[TMP1072:%.*]] = sext i1 [[TMP1071]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1072]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1073:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1074:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1075:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1073]], i16 [[TMP1074]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1076:%.*]] = extractvalue { i16, i1 } [[TMP1075]], 1
|
|
// CHECK-NEXT: [[TMP1077:%.*]] = sext i1 [[TMP1076]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1077]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1078:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1079:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1080:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1078]], i16 [[TMP1079]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1081:%.*]] = extractvalue { i16, i1 } [[TMP1080]], 0
|
|
// CHECK-NEXT: [[TMP1082:%.*]] = extractvalue { i16, i1 } [[TMP1080]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1082]], label [[SX_ATOMIC_EXIT103:%.*]], label [[SX_ATOMIC_CONT104:%.*]]
|
|
// CHECK: sx.atomic.cont104:
|
|
// CHECK-NEXT: store i16 [[TMP1081]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT103]]
|
|
// CHECK: sx.atomic.exit103:
|
|
// CHECK-NEXT: [[TMP1083:%.*]] = extractvalue { i16, i1 } [[TMP1080]], 1
|
|
// CHECK-NEXT: [[TMP1084:%.*]] = sext i1 [[TMP1083]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1084]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1085:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1086:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1087:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1085]], i16 [[TMP1086]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1088:%.*]] = extractvalue { i16, i1 } [[TMP1087]], 0
|
|
// CHECK-NEXT: [[TMP1089:%.*]] = extractvalue { i16, i1 } [[TMP1087]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1089]], label [[SX_ATOMIC_EXIT105:%.*]], label [[SX_ATOMIC_CONT106:%.*]]
|
|
// CHECK: sx.atomic.cont106:
|
|
// CHECK-NEXT: store i16 [[TMP1088]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT105]]
|
|
// CHECK: sx.atomic.exit105:
|
|
// CHECK-NEXT: [[TMP1090:%.*]] = extractvalue { i16, i1 } [[TMP1087]], 1
|
|
// CHECK-NEXT: [[TMP1091:%.*]] = sext i1 [[TMP1090]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1091]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1092:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1093:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1092]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1093]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1094:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1095:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1094]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1095]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1096:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1097:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1096]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1097]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1098:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1099:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1098]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1099]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1100:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1101:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1102:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1100]], i16 [[TMP1101]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1103:%.*]] = extractvalue { i16, i1 } [[TMP1102]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1103]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1104:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1105:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1106:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1104]], i16 [[TMP1105]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1107:%.*]] = extractvalue { i16, i1 } [[TMP1106]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1107]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1108:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1109:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1108]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP1110:%.*]] = icmp sgt i16 [[TMP1109]], [[TMP1108]]
|
|
// CHECK-NEXT: [[TMP1111:%.*]] = select i1 [[TMP1110]], i16 [[TMP1108]], i16 [[TMP1109]]
|
|
// CHECK-NEXT: store i16 [[TMP1111]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1112:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1113:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1112]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP1114:%.*]] = icmp slt i16 [[TMP1113]], [[TMP1112]]
|
|
// CHECK-NEXT: [[TMP1115:%.*]] = select i1 [[TMP1114]], i16 [[TMP1112]], i16 [[TMP1113]]
|
|
// CHECK-NEXT: store i16 [[TMP1115]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1116:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1117:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1116]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP1118:%.*]] = icmp slt i16 [[TMP1117]], [[TMP1116]]
|
|
// CHECK-NEXT: [[TMP1119:%.*]] = select i1 [[TMP1118]], i16 [[TMP1116]], i16 [[TMP1117]]
|
|
// CHECK-NEXT: store i16 [[TMP1119]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1120:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1121:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1120]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP1122:%.*]] = icmp sgt i16 [[TMP1121]], [[TMP1120]]
|
|
// CHECK-NEXT: [[TMP1123:%.*]] = select i1 [[TMP1122]], i16 [[TMP1120]], i16 [[TMP1121]]
|
|
// CHECK-NEXT: store i16 [[TMP1123]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1124:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1125:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1126:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1124]], i16 [[TMP1125]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1127:%.*]] = extractvalue { i16, i1 } [[TMP1126]], 0
|
|
// CHECK-NEXT: [[TMP1128:%.*]] = extractvalue { i16, i1 } [[TMP1126]], 1
|
|
// CHECK-NEXT: [[TMP1129:%.*]] = select i1 [[TMP1128]], i16 [[TMP1124]], i16 [[TMP1127]]
|
|
// CHECK-NEXT: store i16 [[TMP1129]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1130:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1131:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1132:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1130]], i16 [[TMP1131]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1133:%.*]] = extractvalue { i16, i1 } [[TMP1132]], 0
|
|
// CHECK-NEXT: [[TMP1134:%.*]] = extractvalue { i16, i1 } [[TMP1132]], 1
|
|
// CHECK-NEXT: [[TMP1135:%.*]] = select i1 [[TMP1134]], i16 [[TMP1130]], i16 [[TMP1133]]
|
|
// CHECK-NEXT: store i16 [[TMP1135]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1136:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1137:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1138:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1136]], i16 [[TMP1137]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1139:%.*]] = extractvalue { i16, i1 } [[TMP1138]], 0
|
|
// CHECK-NEXT: [[TMP1140:%.*]] = extractvalue { i16, i1 } [[TMP1138]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1140]], label [[SX_ATOMIC_EXIT107:%.*]], label [[SX_ATOMIC_CONT108:%.*]]
|
|
// CHECK: sx.atomic.cont108:
|
|
// CHECK-NEXT: store i16 [[TMP1139]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT107]]
|
|
// CHECK: sx.atomic.exit107:
|
|
// CHECK-NEXT: [[TMP1141:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1142:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1143:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1141]], i16 [[TMP1142]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1144:%.*]] = extractvalue { i16, i1 } [[TMP1143]], 0
|
|
// CHECK-NEXT: [[TMP1145:%.*]] = extractvalue { i16, i1 } [[TMP1143]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1145]], label [[SX_ATOMIC_EXIT109:%.*]], label [[SX_ATOMIC_CONT110:%.*]]
|
|
// CHECK: sx.atomic.cont110:
|
|
// CHECK-NEXT: store i16 [[TMP1144]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT109]]
|
|
// CHECK: sx.atomic.exit109:
|
|
// CHECK-NEXT: [[TMP1146:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1147:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1148:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1146]], i16 [[TMP1147]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1149:%.*]] = extractvalue { i16, i1 } [[TMP1148]], 1
|
|
// CHECK-NEXT: [[TMP1150:%.*]] = sext i1 [[TMP1149]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1150]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1151:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1152:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1153:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1151]], i16 [[TMP1152]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1154:%.*]] = extractvalue { i16, i1 } [[TMP1153]], 1
|
|
// CHECK-NEXT: [[TMP1155:%.*]] = sext i1 [[TMP1154]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1155]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1156:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1157:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1158:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1156]], i16 [[TMP1157]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1159:%.*]] = extractvalue { i16, i1 } [[TMP1158]], 0
|
|
// CHECK-NEXT: [[TMP1160:%.*]] = extractvalue { i16, i1 } [[TMP1158]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1160]], label [[SX_ATOMIC_EXIT111:%.*]], label [[SX_ATOMIC_CONT112:%.*]]
|
|
// CHECK: sx.atomic.cont112:
|
|
// CHECK-NEXT: store i16 [[TMP1159]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT111]]
|
|
// CHECK: sx.atomic.exit111:
|
|
// CHECK-NEXT: [[TMP1161:%.*]] = extractvalue { i16, i1 } [[TMP1158]], 1
|
|
// CHECK-NEXT: [[TMP1162:%.*]] = sext i1 [[TMP1161]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1162]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1163:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1164:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1165:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1163]], i16 [[TMP1164]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1166:%.*]] = extractvalue { i16, i1 } [[TMP1165]], 0
|
|
// CHECK-NEXT: [[TMP1167:%.*]] = extractvalue { i16, i1 } [[TMP1165]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1167]], label [[SX_ATOMIC_EXIT113:%.*]], label [[SX_ATOMIC_CONT114:%.*]]
|
|
// CHECK: sx.atomic.cont114:
|
|
// CHECK-NEXT: store i16 [[TMP1166]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT113]]
|
|
// CHECK: sx.atomic.exit113:
|
|
// CHECK-NEXT: [[TMP1168:%.*]] = extractvalue { i16, i1 } [[TMP1165]], 1
|
|
// CHECK-NEXT: [[TMP1169:%.*]] = sext i1 [[TMP1168]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1169]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1170:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1171:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1170]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1171]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1172:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1173:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1172]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1173]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1174:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1175:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1174]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1175]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1176:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1177:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1176]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1177]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1178:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1179:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1180:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1178]], i16 [[TMP1179]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1181:%.*]] = extractvalue { i16, i1 } [[TMP1180]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1181]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1182:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1183:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1184:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1182]], i16 [[TMP1183]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1185:%.*]] = extractvalue { i16, i1 } [[TMP1184]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1185]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1186:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1187:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1186]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1188:%.*]] = icmp sgt i16 [[TMP1187]], [[TMP1186]]
|
|
// CHECK-NEXT: [[TMP1189:%.*]] = select i1 [[TMP1188]], i16 [[TMP1186]], i16 [[TMP1187]]
|
|
// CHECK-NEXT: store i16 [[TMP1189]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1190:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1191:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1190]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1192:%.*]] = icmp slt i16 [[TMP1191]], [[TMP1190]]
|
|
// CHECK-NEXT: [[TMP1193:%.*]] = select i1 [[TMP1192]], i16 [[TMP1190]], i16 [[TMP1191]]
|
|
// CHECK-NEXT: store i16 [[TMP1193]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1194:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1195:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1194]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1196:%.*]] = icmp slt i16 [[TMP1195]], [[TMP1194]]
|
|
// CHECK-NEXT: [[TMP1197:%.*]] = select i1 [[TMP1196]], i16 [[TMP1194]], i16 [[TMP1195]]
|
|
// CHECK-NEXT: store i16 [[TMP1197]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1198:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1199:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1198]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1200:%.*]] = icmp sgt i16 [[TMP1199]], [[TMP1198]]
|
|
// CHECK-NEXT: [[TMP1201:%.*]] = select i1 [[TMP1200]], i16 [[TMP1198]], i16 [[TMP1199]]
|
|
// CHECK-NEXT: store i16 [[TMP1201]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1202:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1203:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1204:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1202]], i16 [[TMP1203]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1205:%.*]] = extractvalue { i16, i1 } [[TMP1204]], 0
|
|
// CHECK-NEXT: [[TMP1206:%.*]] = extractvalue { i16, i1 } [[TMP1204]], 1
|
|
// CHECK-NEXT: [[TMP1207:%.*]] = select i1 [[TMP1206]], i16 [[TMP1202]], i16 [[TMP1205]]
|
|
// CHECK-NEXT: store i16 [[TMP1207]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1208:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1209:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1210:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1208]], i16 [[TMP1209]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1211:%.*]] = extractvalue { i16, i1 } [[TMP1210]], 0
|
|
// CHECK-NEXT: [[TMP1212:%.*]] = extractvalue { i16, i1 } [[TMP1210]], 1
|
|
// CHECK-NEXT: [[TMP1213:%.*]] = select i1 [[TMP1212]], i16 [[TMP1208]], i16 [[TMP1211]]
|
|
// CHECK-NEXT: store i16 [[TMP1213]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP1214:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1215:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1216:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1214]], i16 [[TMP1215]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1217:%.*]] = extractvalue { i16, i1 } [[TMP1216]], 0
|
|
// CHECK-NEXT: [[TMP1218:%.*]] = extractvalue { i16, i1 } [[TMP1216]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1218]], label [[SX_ATOMIC_EXIT115:%.*]], label [[SX_ATOMIC_CONT116:%.*]]
|
|
// CHECK: sx.atomic.cont116:
|
|
// CHECK-NEXT: store i16 [[TMP1217]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT115]]
|
|
// CHECK: sx.atomic.exit115:
|
|
// CHECK-NEXT: [[TMP1219:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1220:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1221:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1219]], i16 [[TMP1220]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1222:%.*]] = extractvalue { i16, i1 } [[TMP1221]], 0
|
|
// CHECK-NEXT: [[TMP1223:%.*]] = extractvalue { i16, i1 } [[TMP1221]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1223]], label [[SX_ATOMIC_EXIT117:%.*]], label [[SX_ATOMIC_CONT118:%.*]]
|
|
// CHECK: sx.atomic.cont118:
|
|
// CHECK-NEXT: store i16 [[TMP1222]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT117]]
|
|
// CHECK: sx.atomic.exit117:
|
|
// CHECK-NEXT: [[TMP1224:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1225:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1226:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1224]], i16 [[TMP1225]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1227:%.*]] = extractvalue { i16, i1 } [[TMP1226]], 1
|
|
// CHECK-NEXT: [[TMP1228:%.*]] = sext i1 [[TMP1227]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1228]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1229:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1230:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1231:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1229]], i16 [[TMP1230]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1232:%.*]] = extractvalue { i16, i1 } [[TMP1231]], 1
|
|
// CHECK-NEXT: [[TMP1233:%.*]] = sext i1 [[TMP1232]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1233]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1234:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1235:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1236:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1234]], i16 [[TMP1235]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1237:%.*]] = extractvalue { i16, i1 } [[TMP1236]], 0
|
|
// CHECK-NEXT: [[TMP1238:%.*]] = extractvalue { i16, i1 } [[TMP1236]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1238]], label [[SX_ATOMIC_EXIT119:%.*]], label [[SX_ATOMIC_CONT120:%.*]]
|
|
// CHECK: sx.atomic.cont120:
|
|
// CHECK-NEXT: store i16 [[TMP1237]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT119]]
|
|
// CHECK: sx.atomic.exit119:
|
|
// CHECK-NEXT: [[TMP1239:%.*]] = extractvalue { i16, i1 } [[TMP1236]], 1
|
|
// CHECK-NEXT: [[TMP1240:%.*]] = sext i1 [[TMP1239]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1240]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1241:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1242:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1243:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1241]], i16 [[TMP1242]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1244:%.*]] = extractvalue { i16, i1 } [[TMP1243]], 0
|
|
// CHECK-NEXT: [[TMP1245:%.*]] = extractvalue { i16, i1 } [[TMP1243]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1245]], label [[SX_ATOMIC_EXIT121:%.*]], label [[SX_ATOMIC_CONT122:%.*]]
|
|
// CHECK: sx.atomic.cont122:
|
|
// CHECK-NEXT: store i16 [[TMP1244]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT121]]
|
|
// CHECK: sx.atomic.exit121:
|
|
// CHECK-NEXT: [[TMP1246:%.*]] = extractvalue { i16, i1 } [[TMP1243]], 1
|
|
// CHECK-NEXT: [[TMP1247:%.*]] = sext i1 [[TMP1246]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1247]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: [[TMP1248:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1249:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1248]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1249]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1250:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1251:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1250]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1251]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1252:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1253:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1252]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1253]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1254:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1255:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1254]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1255]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1256:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1257:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1258:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1256]], i16 [[TMP1257]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1259:%.*]] = extractvalue { i16, i1 } [[TMP1258]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1259]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1260:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1261:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1262:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1260]], i16 [[TMP1261]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1263:%.*]] = extractvalue { i16, i1 } [[TMP1262]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1263]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1264:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1265:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1264]] release, align 2
|
|
// CHECK-NEXT: [[TMP1266:%.*]] = icmp sgt i16 [[TMP1265]], [[TMP1264]]
|
|
// CHECK-NEXT: [[TMP1267:%.*]] = select i1 [[TMP1266]], i16 [[TMP1264]], i16 [[TMP1265]]
|
|
// CHECK-NEXT: store i16 [[TMP1267]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1268:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1269:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1268]] release, align 2
|
|
// CHECK-NEXT: [[TMP1270:%.*]] = icmp slt i16 [[TMP1269]], [[TMP1268]]
|
|
// CHECK-NEXT: [[TMP1271:%.*]] = select i1 [[TMP1270]], i16 [[TMP1268]], i16 [[TMP1269]]
|
|
// CHECK-NEXT: store i16 [[TMP1271]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1272:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1273:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1272]] release, align 2
|
|
// CHECK-NEXT: [[TMP1274:%.*]] = icmp slt i16 [[TMP1273]], [[TMP1272]]
|
|
// CHECK-NEXT: [[TMP1275:%.*]] = select i1 [[TMP1274]], i16 [[TMP1272]], i16 [[TMP1273]]
|
|
// CHECK-NEXT: store i16 [[TMP1275]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1276:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1277:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1276]] release, align 2
|
|
// CHECK-NEXT: [[TMP1278:%.*]] = icmp sgt i16 [[TMP1277]], [[TMP1276]]
|
|
// CHECK-NEXT: [[TMP1279:%.*]] = select i1 [[TMP1278]], i16 [[TMP1276]], i16 [[TMP1277]]
|
|
// CHECK-NEXT: store i16 [[TMP1279]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1280:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1281:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1282:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1280]], i16 [[TMP1281]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1283:%.*]] = extractvalue { i16, i1 } [[TMP1282]], 0
|
|
// CHECK-NEXT: [[TMP1284:%.*]] = extractvalue { i16, i1 } [[TMP1282]], 1
|
|
// CHECK-NEXT: [[TMP1285:%.*]] = select i1 [[TMP1284]], i16 [[TMP1280]], i16 [[TMP1283]]
|
|
// CHECK-NEXT: store i16 [[TMP1285]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1286:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1287:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1288:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1286]], i16 [[TMP1287]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1289:%.*]] = extractvalue { i16, i1 } [[TMP1288]], 0
|
|
// CHECK-NEXT: [[TMP1290:%.*]] = extractvalue { i16, i1 } [[TMP1288]], 1
|
|
// CHECK-NEXT: [[TMP1291:%.*]] = select i1 [[TMP1290]], i16 [[TMP1286]], i16 [[TMP1289]]
|
|
// CHECK-NEXT: store i16 [[TMP1291]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1292:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1293:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1294:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1292]], i16 [[TMP1293]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1295:%.*]] = extractvalue { i16, i1 } [[TMP1294]], 0
|
|
// CHECK-NEXT: [[TMP1296:%.*]] = extractvalue { i16, i1 } [[TMP1294]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1296]], label [[SX_ATOMIC_EXIT123:%.*]], label [[SX_ATOMIC_CONT124:%.*]]
|
|
// CHECK: sx.atomic.cont124:
|
|
// CHECK-NEXT: store i16 [[TMP1295]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT123]]
|
|
// CHECK: sx.atomic.exit123:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1297:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1298:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1299:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1297]], i16 [[TMP1298]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1300:%.*]] = extractvalue { i16, i1 } [[TMP1299]], 0
|
|
// CHECK-NEXT: [[TMP1301:%.*]] = extractvalue { i16, i1 } [[TMP1299]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1301]], label [[SX_ATOMIC_EXIT125:%.*]], label [[SX_ATOMIC_CONT126:%.*]]
|
|
// CHECK: sx.atomic.cont126:
|
|
// CHECK-NEXT: store i16 [[TMP1300]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT125]]
|
|
// CHECK: sx.atomic.exit125:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1302:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1303:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1304:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1302]], i16 [[TMP1303]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1305:%.*]] = extractvalue { i16, i1 } [[TMP1304]], 1
|
|
// CHECK-NEXT: [[TMP1306:%.*]] = sext i1 [[TMP1305]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1306]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1307:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1308:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1309:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1307]], i16 [[TMP1308]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1310:%.*]] = extractvalue { i16, i1 } [[TMP1309]], 1
|
|
// CHECK-NEXT: [[TMP1311:%.*]] = sext i1 [[TMP1310]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1311]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1312:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1313:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1314:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1312]], i16 [[TMP1313]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1315:%.*]] = extractvalue { i16, i1 } [[TMP1314]], 0
|
|
// CHECK-NEXT: [[TMP1316:%.*]] = extractvalue { i16, i1 } [[TMP1314]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1316]], label [[SX_ATOMIC_EXIT127:%.*]], label [[SX_ATOMIC_CONT128:%.*]]
|
|
// CHECK: sx.atomic.cont128:
|
|
// CHECK-NEXT: store i16 [[TMP1315]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT127]]
|
|
// CHECK: sx.atomic.exit127:
|
|
// CHECK-NEXT: [[TMP1317:%.*]] = extractvalue { i16, i1 } [[TMP1314]], 1
|
|
// CHECK-NEXT: [[TMP1318:%.*]] = sext i1 [[TMP1317]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1318]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1319:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1320:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1321:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1319]], i16 [[TMP1320]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1322:%.*]] = extractvalue { i16, i1 } [[TMP1321]], 0
|
|
// CHECK-NEXT: [[TMP1323:%.*]] = extractvalue { i16, i1 } [[TMP1321]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1323]], label [[SX_ATOMIC_EXIT129:%.*]], label [[SX_ATOMIC_CONT130:%.*]]
|
|
// CHECK: sx.atomic.cont130:
|
|
// CHECK-NEXT: store i16 [[TMP1322]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT129]]
|
|
// CHECK: sx.atomic.exit129:
|
|
// CHECK-NEXT: [[TMP1324:%.*]] = extractvalue { i16, i1 } [[TMP1321]], 1
|
|
// CHECK-NEXT: [[TMP1325:%.*]] = sext i1 [[TMP1324]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1325]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1326:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1327:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1326]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1327]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1328:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1329:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1328]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1329]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1330:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1331:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1330]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1331]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1332:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1333:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1332]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1333]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1334:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1335:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1336:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1334]], i16 [[TMP1335]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1337:%.*]] = extractvalue { i16, i1 } [[TMP1336]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1337]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1338:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1339:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1340:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1338]], i16 [[TMP1339]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1341:%.*]] = extractvalue { i16, i1 } [[TMP1340]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1341]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1342:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1343:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1342]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1344:%.*]] = icmp sgt i16 [[TMP1343]], [[TMP1342]]
|
|
// CHECK-NEXT: [[TMP1345:%.*]] = select i1 [[TMP1344]], i16 [[TMP1342]], i16 [[TMP1343]]
|
|
// CHECK-NEXT: store i16 [[TMP1345]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1346:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1347:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1346]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1348:%.*]] = icmp slt i16 [[TMP1347]], [[TMP1346]]
|
|
// CHECK-NEXT: [[TMP1349:%.*]] = select i1 [[TMP1348]], i16 [[TMP1346]], i16 [[TMP1347]]
|
|
// CHECK-NEXT: store i16 [[TMP1349]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1350:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1351:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1350]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1352:%.*]] = icmp slt i16 [[TMP1351]], [[TMP1350]]
|
|
// CHECK-NEXT: [[TMP1353:%.*]] = select i1 [[TMP1352]], i16 [[TMP1350]], i16 [[TMP1351]]
|
|
// CHECK-NEXT: store i16 [[TMP1353]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1354:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1355:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1354]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1356:%.*]] = icmp sgt i16 [[TMP1355]], [[TMP1354]]
|
|
// CHECK-NEXT: [[TMP1357:%.*]] = select i1 [[TMP1356]], i16 [[TMP1354]], i16 [[TMP1355]]
|
|
// CHECK-NEXT: store i16 [[TMP1357]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1358:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1359:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1360:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1358]], i16 [[TMP1359]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1361:%.*]] = extractvalue { i16, i1 } [[TMP1360]], 0
|
|
// CHECK-NEXT: [[TMP1362:%.*]] = extractvalue { i16, i1 } [[TMP1360]], 1
|
|
// CHECK-NEXT: [[TMP1363:%.*]] = select i1 [[TMP1362]], i16 [[TMP1358]], i16 [[TMP1361]]
|
|
// CHECK-NEXT: store i16 [[TMP1363]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1364:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1365:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1366:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1364]], i16 [[TMP1365]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1367:%.*]] = extractvalue { i16, i1 } [[TMP1366]], 0
|
|
// CHECK-NEXT: [[TMP1368:%.*]] = extractvalue { i16, i1 } [[TMP1366]], 1
|
|
// CHECK-NEXT: [[TMP1369:%.*]] = select i1 [[TMP1368]], i16 [[TMP1364]], i16 [[TMP1367]]
|
|
// CHECK-NEXT: store i16 [[TMP1369]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1370:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1371:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1372:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1370]], i16 [[TMP1371]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1373:%.*]] = extractvalue { i16, i1 } [[TMP1372]], 0
|
|
// CHECK-NEXT: [[TMP1374:%.*]] = extractvalue { i16, i1 } [[TMP1372]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1374]], label [[SX_ATOMIC_EXIT131:%.*]], label [[SX_ATOMIC_CONT132:%.*]]
|
|
// CHECK: sx.atomic.cont132:
|
|
// CHECK-NEXT: store i16 [[TMP1373]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT131]]
|
|
// CHECK: sx.atomic.exit131:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1375:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1376:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1377:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1375]], i16 [[TMP1376]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1378:%.*]] = extractvalue { i16, i1 } [[TMP1377]], 0
|
|
// CHECK-NEXT: [[TMP1379:%.*]] = extractvalue { i16, i1 } [[TMP1377]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1379]], label [[SX_ATOMIC_EXIT133:%.*]], label [[SX_ATOMIC_CONT134:%.*]]
|
|
// CHECK: sx.atomic.cont134:
|
|
// CHECK-NEXT: store i16 [[TMP1378]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT133]]
|
|
// CHECK: sx.atomic.exit133:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1380:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1381:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1382:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1380]], i16 [[TMP1381]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1383:%.*]] = extractvalue { i16, i1 } [[TMP1382]], 1
|
|
// CHECK-NEXT: [[TMP1384:%.*]] = sext i1 [[TMP1383]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1384]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1385:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1386:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1387:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1385]], i16 [[TMP1386]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1388:%.*]] = extractvalue { i16, i1 } [[TMP1387]], 1
|
|
// CHECK-NEXT: [[TMP1389:%.*]] = sext i1 [[TMP1388]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1389]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1390:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1391:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1392:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1390]], i16 [[TMP1391]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1393:%.*]] = extractvalue { i16, i1 } [[TMP1392]], 0
|
|
// CHECK-NEXT: [[TMP1394:%.*]] = extractvalue { i16, i1 } [[TMP1392]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1394]], label [[SX_ATOMIC_EXIT135:%.*]], label [[SX_ATOMIC_CONT136:%.*]]
|
|
// CHECK: sx.atomic.cont136:
|
|
// CHECK-NEXT: store i16 [[TMP1393]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT135]]
|
|
// CHECK: sx.atomic.exit135:
|
|
// CHECK-NEXT: [[TMP1395:%.*]] = extractvalue { i16, i1 } [[TMP1392]], 1
|
|
// CHECK-NEXT: [[TMP1396:%.*]] = sext i1 [[TMP1395]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1396]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1397:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1398:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP1399:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1397]], i16 [[TMP1398]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1400:%.*]] = extractvalue { i16, i1 } [[TMP1399]], 0
|
|
// CHECK-NEXT: [[TMP1401:%.*]] = extractvalue { i16, i1 } [[TMP1399]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1401]], label [[SX_ATOMIC_EXIT137:%.*]], label [[SX_ATOMIC_CONT138:%.*]]
|
|
// CHECK: sx.atomic.cont138:
|
|
// CHECK-NEXT: store i16 [[TMP1400]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT137]]
|
|
// CHECK: sx.atomic.exit137:
|
|
// CHECK-NEXT: [[TMP1402:%.*]] = extractvalue { i16, i1 } [[TMP1399]], 1
|
|
// CHECK-NEXT: [[TMP1403:%.*]] = sext i1 [[TMP1402]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1403]], ptr [[SR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1404:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1405:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1404]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1405]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1406:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1407:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1406]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1407]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1408:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1409:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1408]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1409]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1410:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1411:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1410]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1411]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1412:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1413:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1414:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1412]], i16 [[TMP1413]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1415:%.*]] = extractvalue { i16, i1 } [[TMP1414]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1415]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1416:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1417:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1418:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1416]], i16 [[TMP1417]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1419:%.*]] = extractvalue { i16, i1 } [[TMP1418]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1419]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1420:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1421:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1420]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1422:%.*]] = icmp ugt i16 [[TMP1421]], [[TMP1420]]
|
|
// CHECK-NEXT: [[TMP1423:%.*]] = select i1 [[TMP1422]], i16 [[TMP1420]], i16 [[TMP1421]]
|
|
// CHECK-NEXT: store i16 [[TMP1423]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1424:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1425:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1424]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1426:%.*]] = icmp ult i16 [[TMP1425]], [[TMP1424]]
|
|
// CHECK-NEXT: [[TMP1427:%.*]] = select i1 [[TMP1426]], i16 [[TMP1424]], i16 [[TMP1425]]
|
|
// CHECK-NEXT: store i16 [[TMP1427]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1428:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1429:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1428]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1430:%.*]] = icmp ult i16 [[TMP1429]], [[TMP1428]]
|
|
// CHECK-NEXT: [[TMP1431:%.*]] = select i1 [[TMP1430]], i16 [[TMP1428]], i16 [[TMP1429]]
|
|
// CHECK-NEXT: store i16 [[TMP1431]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1432:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1433:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1432]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1434:%.*]] = icmp ugt i16 [[TMP1433]], [[TMP1432]]
|
|
// CHECK-NEXT: [[TMP1435:%.*]] = select i1 [[TMP1434]], i16 [[TMP1432]], i16 [[TMP1433]]
|
|
// CHECK-NEXT: store i16 [[TMP1435]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1436:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1437:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1438:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1436]], i16 [[TMP1437]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1439:%.*]] = extractvalue { i16, i1 } [[TMP1438]], 0
|
|
// CHECK-NEXT: [[TMP1440:%.*]] = extractvalue { i16, i1 } [[TMP1438]], 1
|
|
// CHECK-NEXT: [[TMP1441:%.*]] = select i1 [[TMP1440]], i16 [[TMP1436]], i16 [[TMP1439]]
|
|
// CHECK-NEXT: store i16 [[TMP1441]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1442:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1443:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1444:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1442]], i16 [[TMP1443]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1445:%.*]] = extractvalue { i16, i1 } [[TMP1444]], 0
|
|
// CHECK-NEXT: [[TMP1446:%.*]] = extractvalue { i16, i1 } [[TMP1444]], 1
|
|
// CHECK-NEXT: [[TMP1447:%.*]] = select i1 [[TMP1446]], i16 [[TMP1442]], i16 [[TMP1445]]
|
|
// CHECK-NEXT: store i16 [[TMP1447]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1448:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1449:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1450:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1448]], i16 [[TMP1449]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1451:%.*]] = extractvalue { i16, i1 } [[TMP1450]], 0
|
|
// CHECK-NEXT: [[TMP1452:%.*]] = extractvalue { i16, i1 } [[TMP1450]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1452]], label [[USX_ATOMIC_EXIT:%.*]], label [[USX_ATOMIC_CONT:%.*]]
|
|
// CHECK: usx.atomic.cont:
|
|
// CHECK-NEXT: store i16 [[TMP1451]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT]]
|
|
// CHECK: usx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP1453:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1454:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1455:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1453]], i16 [[TMP1454]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1456:%.*]] = extractvalue { i16, i1 } [[TMP1455]], 0
|
|
// CHECK-NEXT: [[TMP1457:%.*]] = extractvalue { i16, i1 } [[TMP1455]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1457]], label [[USX_ATOMIC_EXIT139:%.*]], label [[USX_ATOMIC_CONT140:%.*]]
|
|
// CHECK: usx.atomic.cont140:
|
|
// CHECK-NEXT: store i16 [[TMP1456]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT139]]
|
|
// CHECK: usx.atomic.exit139:
|
|
// CHECK-NEXT: [[TMP1458:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1459:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1460:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1458]], i16 [[TMP1459]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1461:%.*]] = extractvalue { i16, i1 } [[TMP1460]], 1
|
|
// CHECK-NEXT: [[TMP1462:%.*]] = zext i1 [[TMP1461]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1462]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1463:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1464:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1465:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1463]], i16 [[TMP1464]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1466:%.*]] = extractvalue { i16, i1 } [[TMP1465]], 1
|
|
// CHECK-NEXT: [[TMP1467:%.*]] = zext i1 [[TMP1466]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1467]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1468:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1469:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1470:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1468]], i16 [[TMP1469]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1471:%.*]] = extractvalue { i16, i1 } [[TMP1470]], 0
|
|
// CHECK-NEXT: [[TMP1472:%.*]] = extractvalue { i16, i1 } [[TMP1470]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1472]], label [[USX_ATOMIC_EXIT141:%.*]], label [[USX_ATOMIC_CONT142:%.*]]
|
|
// CHECK: usx.atomic.cont142:
|
|
// CHECK-NEXT: store i16 [[TMP1471]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT141]]
|
|
// CHECK: usx.atomic.exit141:
|
|
// CHECK-NEXT: [[TMP1473:%.*]] = extractvalue { i16, i1 } [[TMP1470]], 1
|
|
// CHECK-NEXT: [[TMP1474:%.*]] = zext i1 [[TMP1473]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1474]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1475:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1476:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1477:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1475]], i16 [[TMP1476]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1478:%.*]] = extractvalue { i16, i1 } [[TMP1477]], 0
|
|
// CHECK-NEXT: [[TMP1479:%.*]] = extractvalue { i16, i1 } [[TMP1477]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1479]], label [[USX_ATOMIC_EXIT143:%.*]], label [[USX_ATOMIC_CONT144:%.*]]
|
|
// CHECK: usx.atomic.cont144:
|
|
// CHECK-NEXT: store i16 [[TMP1478]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT143]]
|
|
// CHECK: usx.atomic.exit143:
|
|
// CHECK-NEXT: [[TMP1480:%.*]] = extractvalue { i16, i1 } [[TMP1477]], 1
|
|
// CHECK-NEXT: [[TMP1481:%.*]] = zext i1 [[TMP1480]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1481]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1482:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1483:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1482]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1483]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1484:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1485:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1484]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1485]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1486:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1487:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1486]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1487]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1488:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1489:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1488]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1489]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1490:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1491:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1492:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1490]], i16 [[TMP1491]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1493:%.*]] = extractvalue { i16, i1 } [[TMP1492]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1493]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1494:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1495:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1496:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1494]], i16 [[TMP1495]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1497:%.*]] = extractvalue { i16, i1 } [[TMP1496]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1497]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1498:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1499:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1498]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP1500:%.*]] = icmp ugt i16 [[TMP1499]], [[TMP1498]]
|
|
// CHECK-NEXT: [[TMP1501:%.*]] = select i1 [[TMP1500]], i16 [[TMP1498]], i16 [[TMP1499]]
|
|
// CHECK-NEXT: store i16 [[TMP1501]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1502:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1503:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1502]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP1504:%.*]] = icmp ult i16 [[TMP1503]], [[TMP1502]]
|
|
// CHECK-NEXT: [[TMP1505:%.*]] = select i1 [[TMP1504]], i16 [[TMP1502]], i16 [[TMP1503]]
|
|
// CHECK-NEXT: store i16 [[TMP1505]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1506:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1507:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1506]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP1508:%.*]] = icmp ult i16 [[TMP1507]], [[TMP1506]]
|
|
// CHECK-NEXT: [[TMP1509:%.*]] = select i1 [[TMP1508]], i16 [[TMP1506]], i16 [[TMP1507]]
|
|
// CHECK-NEXT: store i16 [[TMP1509]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1510:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1511:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1510]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP1512:%.*]] = icmp ugt i16 [[TMP1511]], [[TMP1510]]
|
|
// CHECK-NEXT: [[TMP1513:%.*]] = select i1 [[TMP1512]], i16 [[TMP1510]], i16 [[TMP1511]]
|
|
// CHECK-NEXT: store i16 [[TMP1513]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1514:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1515:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1516:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1514]], i16 [[TMP1515]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1517:%.*]] = extractvalue { i16, i1 } [[TMP1516]], 0
|
|
// CHECK-NEXT: [[TMP1518:%.*]] = extractvalue { i16, i1 } [[TMP1516]], 1
|
|
// CHECK-NEXT: [[TMP1519:%.*]] = select i1 [[TMP1518]], i16 [[TMP1514]], i16 [[TMP1517]]
|
|
// CHECK-NEXT: store i16 [[TMP1519]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1520:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1521:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1522:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1520]], i16 [[TMP1521]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1523:%.*]] = extractvalue { i16, i1 } [[TMP1522]], 0
|
|
// CHECK-NEXT: [[TMP1524:%.*]] = extractvalue { i16, i1 } [[TMP1522]], 1
|
|
// CHECK-NEXT: [[TMP1525:%.*]] = select i1 [[TMP1524]], i16 [[TMP1520]], i16 [[TMP1523]]
|
|
// CHECK-NEXT: store i16 [[TMP1525]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1526:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1527:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1528:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1526]], i16 [[TMP1527]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1529:%.*]] = extractvalue { i16, i1 } [[TMP1528]], 0
|
|
// CHECK-NEXT: [[TMP1530:%.*]] = extractvalue { i16, i1 } [[TMP1528]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1530]], label [[USX_ATOMIC_EXIT145:%.*]], label [[USX_ATOMIC_CONT146:%.*]]
|
|
// CHECK: usx.atomic.cont146:
|
|
// CHECK-NEXT: store i16 [[TMP1529]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT145]]
|
|
// CHECK: usx.atomic.exit145:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1531:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1532:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1533:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1531]], i16 [[TMP1532]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1534:%.*]] = extractvalue { i16, i1 } [[TMP1533]], 0
|
|
// CHECK-NEXT: [[TMP1535:%.*]] = extractvalue { i16, i1 } [[TMP1533]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1535]], label [[USX_ATOMIC_EXIT147:%.*]], label [[USX_ATOMIC_CONT148:%.*]]
|
|
// CHECK: usx.atomic.cont148:
|
|
// CHECK-NEXT: store i16 [[TMP1534]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT147]]
|
|
// CHECK: usx.atomic.exit147:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1536:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1537:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1538:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1536]], i16 [[TMP1537]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1539:%.*]] = extractvalue { i16, i1 } [[TMP1538]], 1
|
|
// CHECK-NEXT: [[TMP1540:%.*]] = zext i1 [[TMP1539]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1540]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1541:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1542:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1543:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1541]], i16 [[TMP1542]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1544:%.*]] = extractvalue { i16, i1 } [[TMP1543]], 1
|
|
// CHECK-NEXT: [[TMP1545:%.*]] = zext i1 [[TMP1544]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1545]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1546:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1547:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1548:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1546]], i16 [[TMP1547]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1549:%.*]] = extractvalue { i16, i1 } [[TMP1548]], 0
|
|
// CHECK-NEXT: [[TMP1550:%.*]] = extractvalue { i16, i1 } [[TMP1548]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1550]], label [[USX_ATOMIC_EXIT149:%.*]], label [[USX_ATOMIC_CONT150:%.*]]
|
|
// CHECK: usx.atomic.cont150:
|
|
// CHECK-NEXT: store i16 [[TMP1549]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT149]]
|
|
// CHECK: usx.atomic.exit149:
|
|
// CHECK-NEXT: [[TMP1551:%.*]] = extractvalue { i16, i1 } [[TMP1548]], 1
|
|
// CHECK-NEXT: [[TMP1552:%.*]] = zext i1 [[TMP1551]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1552]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1553:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1554:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1555:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1553]], i16 [[TMP1554]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP1556:%.*]] = extractvalue { i16, i1 } [[TMP1555]], 0
|
|
// CHECK-NEXT: [[TMP1557:%.*]] = extractvalue { i16, i1 } [[TMP1555]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1557]], label [[USX_ATOMIC_EXIT151:%.*]], label [[USX_ATOMIC_CONT152:%.*]]
|
|
// CHECK: usx.atomic.cont152:
|
|
// CHECK-NEXT: store i16 [[TMP1556]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT151]]
|
|
// CHECK: usx.atomic.exit151:
|
|
// CHECK-NEXT: [[TMP1558:%.*]] = extractvalue { i16, i1 } [[TMP1555]], 1
|
|
// CHECK-NEXT: [[TMP1559:%.*]] = zext i1 [[TMP1558]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1559]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1560:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1561:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1560]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1561]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1562:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1563:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1562]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1563]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1564:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1565:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1564]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1565]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1566:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1567:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1566]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1567]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1568:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1569:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1570:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1568]], i16 [[TMP1569]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1571:%.*]] = extractvalue { i16, i1 } [[TMP1570]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1571]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1572:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1573:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1574:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1572]], i16 [[TMP1573]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1575:%.*]] = extractvalue { i16, i1 } [[TMP1574]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1575]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1576:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1577:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1576]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP1578:%.*]] = icmp ugt i16 [[TMP1577]], [[TMP1576]]
|
|
// CHECK-NEXT: [[TMP1579:%.*]] = select i1 [[TMP1578]], i16 [[TMP1576]], i16 [[TMP1577]]
|
|
// CHECK-NEXT: store i16 [[TMP1579]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1580:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1581:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1580]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP1582:%.*]] = icmp ult i16 [[TMP1581]], [[TMP1580]]
|
|
// CHECK-NEXT: [[TMP1583:%.*]] = select i1 [[TMP1582]], i16 [[TMP1580]], i16 [[TMP1581]]
|
|
// CHECK-NEXT: store i16 [[TMP1583]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1584:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1585:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1584]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP1586:%.*]] = icmp ult i16 [[TMP1585]], [[TMP1584]]
|
|
// CHECK-NEXT: [[TMP1587:%.*]] = select i1 [[TMP1586]], i16 [[TMP1584]], i16 [[TMP1585]]
|
|
// CHECK-NEXT: store i16 [[TMP1587]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1588:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1589:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1588]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP1590:%.*]] = icmp ugt i16 [[TMP1589]], [[TMP1588]]
|
|
// CHECK-NEXT: [[TMP1591:%.*]] = select i1 [[TMP1590]], i16 [[TMP1588]], i16 [[TMP1589]]
|
|
// CHECK-NEXT: store i16 [[TMP1591]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1592:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1593:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1594:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1592]], i16 [[TMP1593]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1595:%.*]] = extractvalue { i16, i1 } [[TMP1594]], 0
|
|
// CHECK-NEXT: [[TMP1596:%.*]] = extractvalue { i16, i1 } [[TMP1594]], 1
|
|
// CHECK-NEXT: [[TMP1597:%.*]] = select i1 [[TMP1596]], i16 [[TMP1592]], i16 [[TMP1595]]
|
|
// CHECK-NEXT: store i16 [[TMP1597]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1598:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1599:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1600:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1598]], i16 [[TMP1599]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1601:%.*]] = extractvalue { i16, i1 } [[TMP1600]], 0
|
|
// CHECK-NEXT: [[TMP1602:%.*]] = extractvalue { i16, i1 } [[TMP1600]], 1
|
|
// CHECK-NEXT: [[TMP1603:%.*]] = select i1 [[TMP1602]], i16 [[TMP1598]], i16 [[TMP1601]]
|
|
// CHECK-NEXT: store i16 [[TMP1603]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1604:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1605:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1606:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1604]], i16 [[TMP1605]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1607:%.*]] = extractvalue { i16, i1 } [[TMP1606]], 0
|
|
// CHECK-NEXT: [[TMP1608:%.*]] = extractvalue { i16, i1 } [[TMP1606]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1608]], label [[USX_ATOMIC_EXIT153:%.*]], label [[USX_ATOMIC_CONT154:%.*]]
|
|
// CHECK: usx.atomic.cont154:
|
|
// CHECK-NEXT: store i16 [[TMP1607]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT153]]
|
|
// CHECK: usx.atomic.exit153:
|
|
// CHECK-NEXT: [[TMP1609:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1610:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1611:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1609]], i16 [[TMP1610]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1612:%.*]] = extractvalue { i16, i1 } [[TMP1611]], 0
|
|
// CHECK-NEXT: [[TMP1613:%.*]] = extractvalue { i16, i1 } [[TMP1611]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1613]], label [[USX_ATOMIC_EXIT155:%.*]], label [[USX_ATOMIC_CONT156:%.*]]
|
|
// CHECK: usx.atomic.cont156:
|
|
// CHECK-NEXT: store i16 [[TMP1612]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT155]]
|
|
// CHECK: usx.atomic.exit155:
|
|
// CHECK-NEXT: [[TMP1614:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1615:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1616:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1614]], i16 [[TMP1615]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1617:%.*]] = extractvalue { i16, i1 } [[TMP1616]], 1
|
|
// CHECK-NEXT: [[TMP1618:%.*]] = zext i1 [[TMP1617]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1618]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1619:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1620:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1621:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1619]], i16 [[TMP1620]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1622:%.*]] = extractvalue { i16, i1 } [[TMP1621]], 1
|
|
// CHECK-NEXT: [[TMP1623:%.*]] = zext i1 [[TMP1622]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1623]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1624:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1625:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1626:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1624]], i16 [[TMP1625]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1627:%.*]] = extractvalue { i16, i1 } [[TMP1626]], 0
|
|
// CHECK-NEXT: [[TMP1628:%.*]] = extractvalue { i16, i1 } [[TMP1626]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1628]], label [[USX_ATOMIC_EXIT157:%.*]], label [[USX_ATOMIC_CONT158:%.*]]
|
|
// CHECK: usx.atomic.cont158:
|
|
// CHECK-NEXT: store i16 [[TMP1627]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT157]]
|
|
// CHECK: usx.atomic.exit157:
|
|
// CHECK-NEXT: [[TMP1629:%.*]] = extractvalue { i16, i1 } [[TMP1626]], 1
|
|
// CHECK-NEXT: [[TMP1630:%.*]] = zext i1 [[TMP1629]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1630]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1631:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1632:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1633:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1631]], i16 [[TMP1632]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP1634:%.*]] = extractvalue { i16, i1 } [[TMP1633]], 0
|
|
// CHECK-NEXT: [[TMP1635:%.*]] = extractvalue { i16, i1 } [[TMP1633]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1635]], label [[USX_ATOMIC_EXIT159:%.*]], label [[USX_ATOMIC_CONT160:%.*]]
|
|
// CHECK: usx.atomic.cont160:
|
|
// CHECK-NEXT: store i16 [[TMP1634]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT159]]
|
|
// CHECK: usx.atomic.exit159:
|
|
// CHECK-NEXT: [[TMP1636:%.*]] = extractvalue { i16, i1 } [[TMP1633]], 1
|
|
// CHECK-NEXT: [[TMP1637:%.*]] = zext i1 [[TMP1636]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1637]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1638:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1639:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1638]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1639]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1640:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1641:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1640]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1641]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1642:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1643:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1642]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1643]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1644:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1645:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1644]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1645]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1646:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1647:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1648:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1646]], i16 [[TMP1647]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1649:%.*]] = extractvalue { i16, i1 } [[TMP1648]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1649]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1650:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1651:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1652:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1650]], i16 [[TMP1651]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1653:%.*]] = extractvalue { i16, i1 } [[TMP1652]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1653]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1654:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1655:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1654]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1656:%.*]] = icmp ugt i16 [[TMP1655]], [[TMP1654]]
|
|
// CHECK-NEXT: [[TMP1657:%.*]] = select i1 [[TMP1656]], i16 [[TMP1654]], i16 [[TMP1655]]
|
|
// CHECK-NEXT: store i16 [[TMP1657]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1658:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1659:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1658]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1660:%.*]] = icmp ult i16 [[TMP1659]], [[TMP1658]]
|
|
// CHECK-NEXT: [[TMP1661:%.*]] = select i1 [[TMP1660]], i16 [[TMP1658]], i16 [[TMP1659]]
|
|
// CHECK-NEXT: store i16 [[TMP1661]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1662:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1663:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1662]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1664:%.*]] = icmp ult i16 [[TMP1663]], [[TMP1662]]
|
|
// CHECK-NEXT: [[TMP1665:%.*]] = select i1 [[TMP1664]], i16 [[TMP1662]], i16 [[TMP1663]]
|
|
// CHECK-NEXT: store i16 [[TMP1665]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1666:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1667:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1666]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1668:%.*]] = icmp ugt i16 [[TMP1667]], [[TMP1666]]
|
|
// CHECK-NEXT: [[TMP1669:%.*]] = select i1 [[TMP1668]], i16 [[TMP1666]], i16 [[TMP1667]]
|
|
// CHECK-NEXT: store i16 [[TMP1669]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1670:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1671:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1672:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1670]], i16 [[TMP1671]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1673:%.*]] = extractvalue { i16, i1 } [[TMP1672]], 0
|
|
// CHECK-NEXT: [[TMP1674:%.*]] = extractvalue { i16, i1 } [[TMP1672]], 1
|
|
// CHECK-NEXT: [[TMP1675:%.*]] = select i1 [[TMP1674]], i16 [[TMP1670]], i16 [[TMP1673]]
|
|
// CHECK-NEXT: store i16 [[TMP1675]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1676:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1677:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1678:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1676]], i16 [[TMP1677]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1679:%.*]] = extractvalue { i16, i1 } [[TMP1678]], 0
|
|
// CHECK-NEXT: [[TMP1680:%.*]] = extractvalue { i16, i1 } [[TMP1678]], 1
|
|
// CHECK-NEXT: [[TMP1681:%.*]] = select i1 [[TMP1680]], i16 [[TMP1676]], i16 [[TMP1679]]
|
|
// CHECK-NEXT: store i16 [[TMP1681]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP1682:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1683:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1684:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1682]], i16 [[TMP1683]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1685:%.*]] = extractvalue { i16, i1 } [[TMP1684]], 0
|
|
// CHECK-NEXT: [[TMP1686:%.*]] = extractvalue { i16, i1 } [[TMP1684]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1686]], label [[USX_ATOMIC_EXIT161:%.*]], label [[USX_ATOMIC_CONT162:%.*]]
|
|
// CHECK: usx.atomic.cont162:
|
|
// CHECK-NEXT: store i16 [[TMP1685]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT161]]
|
|
// CHECK: usx.atomic.exit161:
|
|
// CHECK-NEXT: [[TMP1687:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1688:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1689:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1687]], i16 [[TMP1688]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1690:%.*]] = extractvalue { i16, i1 } [[TMP1689]], 0
|
|
// CHECK-NEXT: [[TMP1691:%.*]] = extractvalue { i16, i1 } [[TMP1689]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1691]], label [[USX_ATOMIC_EXIT163:%.*]], label [[USX_ATOMIC_CONT164:%.*]]
|
|
// CHECK: usx.atomic.cont164:
|
|
// CHECK-NEXT: store i16 [[TMP1690]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT163]]
|
|
// CHECK: usx.atomic.exit163:
|
|
// CHECK-NEXT: [[TMP1692:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1693:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1694:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1692]], i16 [[TMP1693]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1695:%.*]] = extractvalue { i16, i1 } [[TMP1694]], 1
|
|
// CHECK-NEXT: [[TMP1696:%.*]] = zext i1 [[TMP1695]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1696]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1697:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1698:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1699:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1697]], i16 [[TMP1698]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1700:%.*]] = extractvalue { i16, i1 } [[TMP1699]], 1
|
|
// CHECK-NEXT: [[TMP1701:%.*]] = zext i1 [[TMP1700]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1701]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1702:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1703:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1704:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1702]], i16 [[TMP1703]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1705:%.*]] = extractvalue { i16, i1 } [[TMP1704]], 0
|
|
// CHECK-NEXT: [[TMP1706:%.*]] = extractvalue { i16, i1 } [[TMP1704]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1706]], label [[USX_ATOMIC_EXIT165:%.*]], label [[USX_ATOMIC_CONT166:%.*]]
|
|
// CHECK: usx.atomic.cont166:
|
|
// CHECK-NEXT: store i16 [[TMP1705]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT165]]
|
|
// CHECK: usx.atomic.exit165:
|
|
// CHECK-NEXT: [[TMP1707:%.*]] = extractvalue { i16, i1 } [[TMP1704]], 1
|
|
// CHECK-NEXT: [[TMP1708:%.*]] = zext i1 [[TMP1707]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1708]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1709:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1710:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1711:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1709]], i16 [[TMP1710]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1712:%.*]] = extractvalue { i16, i1 } [[TMP1711]], 0
|
|
// CHECK-NEXT: [[TMP1713:%.*]] = extractvalue { i16, i1 } [[TMP1711]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1713]], label [[USX_ATOMIC_EXIT167:%.*]], label [[USX_ATOMIC_CONT168:%.*]]
|
|
// CHECK: usx.atomic.cont168:
|
|
// CHECK-NEXT: store i16 [[TMP1712]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT167]]
|
|
// CHECK: usx.atomic.exit167:
|
|
// CHECK-NEXT: [[TMP1714:%.*]] = extractvalue { i16, i1 } [[TMP1711]], 1
|
|
// CHECK-NEXT: [[TMP1715:%.*]] = zext i1 [[TMP1714]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1715]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: [[TMP1716:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1717:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1716]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1717]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1718:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1719:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1718]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1719]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1720:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1721:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1720]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1721]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1722:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1723:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1722]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1723]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1724:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1725:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1726:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1724]], i16 [[TMP1725]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1727:%.*]] = extractvalue { i16, i1 } [[TMP1726]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1727]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1728:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1729:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1730:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1728]], i16 [[TMP1729]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1731:%.*]] = extractvalue { i16, i1 } [[TMP1730]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1731]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1732:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1733:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1732]] release, align 2
|
|
// CHECK-NEXT: [[TMP1734:%.*]] = icmp ugt i16 [[TMP1733]], [[TMP1732]]
|
|
// CHECK-NEXT: [[TMP1735:%.*]] = select i1 [[TMP1734]], i16 [[TMP1732]], i16 [[TMP1733]]
|
|
// CHECK-NEXT: store i16 [[TMP1735]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1736:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1737:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1736]] release, align 2
|
|
// CHECK-NEXT: [[TMP1738:%.*]] = icmp ult i16 [[TMP1737]], [[TMP1736]]
|
|
// CHECK-NEXT: [[TMP1739:%.*]] = select i1 [[TMP1738]], i16 [[TMP1736]], i16 [[TMP1737]]
|
|
// CHECK-NEXT: store i16 [[TMP1739]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1740:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1741:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1740]] release, align 2
|
|
// CHECK-NEXT: [[TMP1742:%.*]] = icmp ult i16 [[TMP1741]], [[TMP1740]]
|
|
// CHECK-NEXT: [[TMP1743:%.*]] = select i1 [[TMP1742]], i16 [[TMP1740]], i16 [[TMP1741]]
|
|
// CHECK-NEXT: store i16 [[TMP1743]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1744:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1745:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1744]] release, align 2
|
|
// CHECK-NEXT: [[TMP1746:%.*]] = icmp ugt i16 [[TMP1745]], [[TMP1744]]
|
|
// CHECK-NEXT: [[TMP1747:%.*]] = select i1 [[TMP1746]], i16 [[TMP1744]], i16 [[TMP1745]]
|
|
// CHECK-NEXT: store i16 [[TMP1747]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1748:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1749:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1750:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1748]], i16 [[TMP1749]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1751:%.*]] = extractvalue { i16, i1 } [[TMP1750]], 0
|
|
// CHECK-NEXT: [[TMP1752:%.*]] = extractvalue { i16, i1 } [[TMP1750]], 1
|
|
// CHECK-NEXT: [[TMP1753:%.*]] = select i1 [[TMP1752]], i16 [[TMP1748]], i16 [[TMP1751]]
|
|
// CHECK-NEXT: store i16 [[TMP1753]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1754:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1755:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1756:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1754]], i16 [[TMP1755]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1757:%.*]] = extractvalue { i16, i1 } [[TMP1756]], 0
|
|
// CHECK-NEXT: [[TMP1758:%.*]] = extractvalue { i16, i1 } [[TMP1756]], 1
|
|
// CHECK-NEXT: [[TMP1759:%.*]] = select i1 [[TMP1758]], i16 [[TMP1754]], i16 [[TMP1757]]
|
|
// CHECK-NEXT: store i16 [[TMP1759]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1760:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1761:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1762:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1760]], i16 [[TMP1761]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1763:%.*]] = extractvalue { i16, i1 } [[TMP1762]], 0
|
|
// CHECK-NEXT: [[TMP1764:%.*]] = extractvalue { i16, i1 } [[TMP1762]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1764]], label [[USX_ATOMIC_EXIT169:%.*]], label [[USX_ATOMIC_CONT170:%.*]]
|
|
// CHECK: usx.atomic.cont170:
|
|
// CHECK-NEXT: store i16 [[TMP1763]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT169]]
|
|
// CHECK: usx.atomic.exit169:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1765:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1766:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1767:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1765]], i16 [[TMP1766]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1768:%.*]] = extractvalue { i16, i1 } [[TMP1767]], 0
|
|
// CHECK-NEXT: [[TMP1769:%.*]] = extractvalue { i16, i1 } [[TMP1767]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1769]], label [[USX_ATOMIC_EXIT171:%.*]], label [[USX_ATOMIC_CONT172:%.*]]
|
|
// CHECK: usx.atomic.cont172:
|
|
// CHECK-NEXT: store i16 [[TMP1768]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT171]]
|
|
// CHECK: usx.atomic.exit171:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1770:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1771:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1772:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1770]], i16 [[TMP1771]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1773:%.*]] = extractvalue { i16, i1 } [[TMP1772]], 1
|
|
// CHECK-NEXT: [[TMP1774:%.*]] = zext i1 [[TMP1773]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1774]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1775:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1776:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1777:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1775]], i16 [[TMP1776]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1778:%.*]] = extractvalue { i16, i1 } [[TMP1777]], 1
|
|
// CHECK-NEXT: [[TMP1779:%.*]] = zext i1 [[TMP1778]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1779]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1780:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1781:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1782:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1780]], i16 [[TMP1781]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1783:%.*]] = extractvalue { i16, i1 } [[TMP1782]], 0
|
|
// CHECK-NEXT: [[TMP1784:%.*]] = extractvalue { i16, i1 } [[TMP1782]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1784]], label [[USX_ATOMIC_EXIT173:%.*]], label [[USX_ATOMIC_CONT174:%.*]]
|
|
// CHECK: usx.atomic.cont174:
|
|
// CHECK-NEXT: store i16 [[TMP1783]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT173]]
|
|
// CHECK: usx.atomic.exit173:
|
|
// CHECK-NEXT: [[TMP1785:%.*]] = extractvalue { i16, i1 } [[TMP1782]], 1
|
|
// CHECK-NEXT: [[TMP1786:%.*]] = zext i1 [[TMP1785]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1786]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1787:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1788:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1789:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1787]], i16 [[TMP1788]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP1790:%.*]] = extractvalue { i16, i1 } [[TMP1789]], 0
|
|
// CHECK-NEXT: [[TMP1791:%.*]] = extractvalue { i16, i1 } [[TMP1789]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1791]], label [[USX_ATOMIC_EXIT175:%.*]], label [[USX_ATOMIC_CONT176:%.*]]
|
|
// CHECK: usx.atomic.cont176:
|
|
// CHECK-NEXT: store i16 [[TMP1790]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT175]]
|
|
// CHECK: usx.atomic.exit175:
|
|
// CHECK-NEXT: [[TMP1792:%.*]] = extractvalue { i16, i1 } [[TMP1789]], 1
|
|
// CHECK-NEXT: [[TMP1793:%.*]] = zext i1 [[TMP1792]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1793]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1794:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1795:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1794]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1795]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1796:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1797:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1796]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1797]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1798:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1799:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1798]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1799]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1800:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1801:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1800]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1801]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1802:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1803:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1804:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1802]], i16 [[TMP1803]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1805:%.*]] = extractvalue { i16, i1 } [[TMP1804]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1805]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1806:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1807:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1808:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1806]], i16 [[TMP1807]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1809:%.*]] = extractvalue { i16, i1 } [[TMP1808]], 0
|
|
// CHECK-NEXT: store i16 [[TMP1809]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1810:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1811:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1810]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1812:%.*]] = icmp ugt i16 [[TMP1811]], [[TMP1810]]
|
|
// CHECK-NEXT: [[TMP1813:%.*]] = select i1 [[TMP1812]], i16 [[TMP1810]], i16 [[TMP1811]]
|
|
// CHECK-NEXT: store i16 [[TMP1813]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1814:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1815:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1814]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1816:%.*]] = icmp ult i16 [[TMP1815]], [[TMP1814]]
|
|
// CHECK-NEXT: [[TMP1817:%.*]] = select i1 [[TMP1816]], i16 [[TMP1814]], i16 [[TMP1815]]
|
|
// CHECK-NEXT: store i16 [[TMP1817]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1818:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1819:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1818]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1820:%.*]] = icmp ult i16 [[TMP1819]], [[TMP1818]]
|
|
// CHECK-NEXT: [[TMP1821:%.*]] = select i1 [[TMP1820]], i16 [[TMP1818]], i16 [[TMP1819]]
|
|
// CHECK-NEXT: store i16 [[TMP1821]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1822:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1823:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1822]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1824:%.*]] = icmp ugt i16 [[TMP1823]], [[TMP1822]]
|
|
// CHECK-NEXT: [[TMP1825:%.*]] = select i1 [[TMP1824]], i16 [[TMP1822]], i16 [[TMP1823]]
|
|
// CHECK-NEXT: store i16 [[TMP1825]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1826:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1827:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1828:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1826]], i16 [[TMP1827]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1829:%.*]] = extractvalue { i16, i1 } [[TMP1828]], 0
|
|
// CHECK-NEXT: [[TMP1830:%.*]] = extractvalue { i16, i1 } [[TMP1828]], 1
|
|
// CHECK-NEXT: [[TMP1831:%.*]] = select i1 [[TMP1830]], i16 [[TMP1826]], i16 [[TMP1829]]
|
|
// CHECK-NEXT: store i16 [[TMP1831]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1832:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1833:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1834:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1832]], i16 [[TMP1833]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1835:%.*]] = extractvalue { i16, i1 } [[TMP1834]], 0
|
|
// CHECK-NEXT: [[TMP1836:%.*]] = extractvalue { i16, i1 } [[TMP1834]], 1
|
|
// CHECK-NEXT: [[TMP1837:%.*]] = select i1 [[TMP1836]], i16 [[TMP1832]], i16 [[TMP1835]]
|
|
// CHECK-NEXT: store i16 [[TMP1837]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1838:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1839:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1840:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1838]], i16 [[TMP1839]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1841:%.*]] = extractvalue { i16, i1 } [[TMP1840]], 0
|
|
// CHECK-NEXT: [[TMP1842:%.*]] = extractvalue { i16, i1 } [[TMP1840]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1842]], label [[USX_ATOMIC_EXIT177:%.*]], label [[USX_ATOMIC_CONT178:%.*]]
|
|
// CHECK: usx.atomic.cont178:
|
|
// CHECK-NEXT: store i16 [[TMP1841]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT177]]
|
|
// CHECK: usx.atomic.exit177:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1843:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1844:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1845:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1843]], i16 [[TMP1844]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1846:%.*]] = extractvalue { i16, i1 } [[TMP1845]], 0
|
|
// CHECK-NEXT: [[TMP1847:%.*]] = extractvalue { i16, i1 } [[TMP1845]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1847]], label [[USX_ATOMIC_EXIT179:%.*]], label [[USX_ATOMIC_CONT180:%.*]]
|
|
// CHECK: usx.atomic.cont180:
|
|
// CHECK-NEXT: store i16 [[TMP1846]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT179]]
|
|
// CHECK: usx.atomic.exit179:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1848:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1849:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1850:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1848]], i16 [[TMP1849]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1851:%.*]] = extractvalue { i16, i1 } [[TMP1850]], 1
|
|
// CHECK-NEXT: [[TMP1852:%.*]] = zext i1 [[TMP1851]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1852]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1853:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1854:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1855:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1853]], i16 [[TMP1854]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1856:%.*]] = extractvalue { i16, i1 } [[TMP1855]], 1
|
|
// CHECK-NEXT: [[TMP1857:%.*]] = zext i1 [[TMP1856]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1857]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1858:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1859:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1860:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1858]], i16 [[TMP1859]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1861:%.*]] = extractvalue { i16, i1 } [[TMP1860]], 0
|
|
// CHECK-NEXT: [[TMP1862:%.*]] = extractvalue { i16, i1 } [[TMP1860]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1862]], label [[USX_ATOMIC_EXIT181:%.*]], label [[USX_ATOMIC_CONT182:%.*]]
|
|
// CHECK: usx.atomic.cont182:
|
|
// CHECK-NEXT: store i16 [[TMP1861]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT181]]
|
|
// CHECK: usx.atomic.exit181:
|
|
// CHECK-NEXT: [[TMP1863:%.*]] = extractvalue { i16, i1 } [[TMP1860]], 1
|
|
// CHECK-NEXT: [[TMP1864:%.*]] = zext i1 [[TMP1863]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1864]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1865:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1866:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP1867:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1865]], i16 [[TMP1866]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP1868:%.*]] = extractvalue { i16, i1 } [[TMP1867]], 0
|
|
// CHECK-NEXT: [[TMP1869:%.*]] = extractvalue { i16, i1 } [[TMP1867]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1869]], label [[USX_ATOMIC_EXIT183:%.*]], label [[USX_ATOMIC_CONT184:%.*]]
|
|
// CHECK: usx.atomic.cont184:
|
|
// CHECK-NEXT: store i16 [[TMP1868]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT183]]
|
|
// CHECK: usx.atomic.exit183:
|
|
// CHECK-NEXT: [[TMP1870:%.*]] = extractvalue { i16, i1 } [[TMP1867]], 1
|
|
// CHECK-NEXT: [[TMP1871:%.*]] = zext i1 [[TMP1870]] to i16
|
|
// CHECK-NEXT: store i16 [[TMP1871]], ptr [[USR]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1872:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1873:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1872]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1873]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1874:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1875:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1874]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1875]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1876:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1877:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1876]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1877]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1878:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1879:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1878]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1879]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1880:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1881:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1882:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1880]], i32 [[TMP1881]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1883:%.*]] = extractvalue { i32, i1 } [[TMP1882]], 0
|
|
// CHECK-NEXT: store i32 [[TMP1883]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1884:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1885:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1886:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1884]], i32 [[TMP1885]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1887:%.*]] = extractvalue { i32, i1 } [[TMP1886]], 0
|
|
// CHECK-NEXT: store i32 [[TMP1887]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1888:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1889:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1888]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1890:%.*]] = icmp sgt i32 [[TMP1889]], [[TMP1888]]
|
|
// CHECK-NEXT: [[TMP1891:%.*]] = select i1 [[TMP1890]], i32 [[TMP1888]], i32 [[TMP1889]]
|
|
// CHECK-NEXT: store i32 [[TMP1891]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1892:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1893:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1892]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1894:%.*]] = icmp slt i32 [[TMP1893]], [[TMP1892]]
|
|
// CHECK-NEXT: [[TMP1895:%.*]] = select i1 [[TMP1894]], i32 [[TMP1892]], i32 [[TMP1893]]
|
|
// CHECK-NEXT: store i32 [[TMP1895]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1896:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1897:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1896]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1898:%.*]] = icmp slt i32 [[TMP1897]], [[TMP1896]]
|
|
// CHECK-NEXT: [[TMP1899:%.*]] = select i1 [[TMP1898]], i32 [[TMP1896]], i32 [[TMP1897]]
|
|
// CHECK-NEXT: store i32 [[TMP1899]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1900:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1901:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1900]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1902:%.*]] = icmp sgt i32 [[TMP1901]], [[TMP1900]]
|
|
// CHECK-NEXT: [[TMP1903:%.*]] = select i1 [[TMP1902]], i32 [[TMP1900]], i32 [[TMP1901]]
|
|
// CHECK-NEXT: store i32 [[TMP1903]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1904:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1905:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1906:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1904]], i32 [[TMP1905]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1907:%.*]] = extractvalue { i32, i1 } [[TMP1906]], 0
|
|
// CHECK-NEXT: [[TMP1908:%.*]] = extractvalue { i32, i1 } [[TMP1906]], 1
|
|
// CHECK-NEXT: [[TMP1909:%.*]] = select i1 [[TMP1908]], i32 [[TMP1904]], i32 [[TMP1907]]
|
|
// CHECK-NEXT: store i32 [[TMP1909]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1910:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1911:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1912:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1910]], i32 [[TMP1911]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1913:%.*]] = extractvalue { i32, i1 } [[TMP1912]], 0
|
|
// CHECK-NEXT: [[TMP1914:%.*]] = extractvalue { i32, i1 } [[TMP1912]], 1
|
|
// CHECK-NEXT: [[TMP1915:%.*]] = select i1 [[TMP1914]], i32 [[TMP1910]], i32 [[TMP1913]]
|
|
// CHECK-NEXT: store i32 [[TMP1915]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP1916:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1917:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1918:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1916]], i32 [[TMP1917]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1919:%.*]] = extractvalue { i32, i1 } [[TMP1918]], 0
|
|
// CHECK-NEXT: [[TMP1920:%.*]] = extractvalue { i32, i1 } [[TMP1918]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1920]], label [[IX_ATOMIC_EXIT:%.*]], label [[IX_ATOMIC_CONT:%.*]]
|
|
// CHECK: ix.atomic.cont:
|
|
// CHECK-NEXT: store i32 [[TMP1919]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT]]
|
|
// CHECK: ix.atomic.exit:
|
|
// CHECK-NEXT: [[TMP1921:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1922:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1923:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1921]], i32 [[TMP1922]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1924:%.*]] = extractvalue { i32, i1 } [[TMP1923]], 0
|
|
// CHECK-NEXT: [[TMP1925:%.*]] = extractvalue { i32, i1 } [[TMP1923]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1925]], label [[IX_ATOMIC_EXIT185:%.*]], label [[IX_ATOMIC_CONT186:%.*]]
|
|
// CHECK: ix.atomic.cont186:
|
|
// CHECK-NEXT: store i32 [[TMP1924]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT185]]
|
|
// CHECK: ix.atomic.exit185:
|
|
// CHECK-NEXT: [[TMP1926:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1927:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1928:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1926]], i32 [[TMP1927]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1929:%.*]] = extractvalue { i32, i1 } [[TMP1928]], 1
|
|
// CHECK-NEXT: [[TMP1930:%.*]] = sext i1 [[TMP1929]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP1930]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP1931:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1932:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1933:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1931]], i32 [[TMP1932]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1934:%.*]] = extractvalue { i32, i1 } [[TMP1933]], 1
|
|
// CHECK-NEXT: [[TMP1935:%.*]] = sext i1 [[TMP1934]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP1935]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP1936:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1937:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1938:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1936]], i32 [[TMP1937]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1939:%.*]] = extractvalue { i32, i1 } [[TMP1938]], 0
|
|
// CHECK-NEXT: [[TMP1940:%.*]] = extractvalue { i32, i1 } [[TMP1938]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1940]], label [[IX_ATOMIC_EXIT187:%.*]], label [[IX_ATOMIC_CONT188:%.*]]
|
|
// CHECK: ix.atomic.cont188:
|
|
// CHECK-NEXT: store i32 [[TMP1939]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT187]]
|
|
// CHECK: ix.atomic.exit187:
|
|
// CHECK-NEXT: [[TMP1941:%.*]] = extractvalue { i32, i1 } [[TMP1938]], 1
|
|
// CHECK-NEXT: [[TMP1942:%.*]] = sext i1 [[TMP1941]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP1942]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP1943:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1944:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1945:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1943]], i32 [[TMP1944]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP1946:%.*]] = extractvalue { i32, i1 } [[TMP1945]], 0
|
|
// CHECK-NEXT: [[TMP1947:%.*]] = extractvalue { i32, i1 } [[TMP1945]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1947]], label [[IX_ATOMIC_EXIT189:%.*]], label [[IX_ATOMIC_CONT190:%.*]]
|
|
// CHECK: ix.atomic.cont190:
|
|
// CHECK-NEXT: store i32 [[TMP1946]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT189]]
|
|
// CHECK: ix.atomic.exit189:
|
|
// CHECK-NEXT: [[TMP1948:%.*]] = extractvalue { i32, i1 } [[TMP1945]], 1
|
|
// CHECK-NEXT: [[TMP1949:%.*]] = sext i1 [[TMP1948]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP1949]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP1950:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1951:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1950]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1951]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1952:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1953:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1952]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1953]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1954:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1955:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1954]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1955]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1956:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1957:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1956]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1957]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1958:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1959:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1960:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1958]], i32 [[TMP1959]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP1961:%.*]] = extractvalue { i32, i1 } [[TMP1960]], 0
|
|
// CHECK-NEXT: store i32 [[TMP1961]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1962:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1963:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1964:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1962]], i32 [[TMP1963]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP1965:%.*]] = extractvalue { i32, i1 } [[TMP1964]], 0
|
|
// CHECK-NEXT: store i32 [[TMP1965]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1966:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1967:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1966]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP1968:%.*]] = icmp sgt i32 [[TMP1967]], [[TMP1966]]
|
|
// CHECK-NEXT: [[TMP1969:%.*]] = select i1 [[TMP1968]], i32 [[TMP1966]], i32 [[TMP1967]]
|
|
// CHECK-NEXT: store i32 [[TMP1969]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1970:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1971:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1970]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP1972:%.*]] = icmp slt i32 [[TMP1971]], [[TMP1970]]
|
|
// CHECK-NEXT: [[TMP1973:%.*]] = select i1 [[TMP1972]], i32 [[TMP1970]], i32 [[TMP1971]]
|
|
// CHECK-NEXT: store i32 [[TMP1973]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1974:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1975:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1974]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP1976:%.*]] = icmp slt i32 [[TMP1975]], [[TMP1974]]
|
|
// CHECK-NEXT: [[TMP1977:%.*]] = select i1 [[TMP1976]], i32 [[TMP1974]], i32 [[TMP1975]]
|
|
// CHECK-NEXT: store i32 [[TMP1977]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1978:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1979:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1978]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP1980:%.*]] = icmp sgt i32 [[TMP1979]], [[TMP1978]]
|
|
// CHECK-NEXT: [[TMP1981:%.*]] = select i1 [[TMP1980]], i32 [[TMP1978]], i32 [[TMP1979]]
|
|
// CHECK-NEXT: store i32 [[TMP1981]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1982:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1983:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1984:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1982]], i32 [[TMP1983]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP1985:%.*]] = extractvalue { i32, i1 } [[TMP1984]], 0
|
|
// CHECK-NEXT: [[TMP1986:%.*]] = extractvalue { i32, i1 } [[TMP1984]], 1
|
|
// CHECK-NEXT: [[TMP1987:%.*]] = select i1 [[TMP1986]], i32 [[TMP1982]], i32 [[TMP1985]]
|
|
// CHECK-NEXT: store i32 [[TMP1987]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1988:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1989:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1990:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1988]], i32 [[TMP1989]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP1991:%.*]] = extractvalue { i32, i1 } [[TMP1990]], 0
|
|
// CHECK-NEXT: [[TMP1992:%.*]] = extractvalue { i32, i1 } [[TMP1990]], 1
|
|
// CHECK-NEXT: [[TMP1993:%.*]] = select i1 [[TMP1992]], i32 [[TMP1988]], i32 [[TMP1991]]
|
|
// CHECK-NEXT: store i32 [[TMP1993]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1994:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1995:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP1996:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1994]], i32 [[TMP1995]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP1997:%.*]] = extractvalue { i32, i1 } [[TMP1996]], 0
|
|
// CHECK-NEXT: [[TMP1998:%.*]] = extractvalue { i32, i1 } [[TMP1996]], 1
|
|
// CHECK-NEXT: br i1 [[TMP1998]], label [[IX_ATOMIC_EXIT191:%.*]], label [[IX_ATOMIC_CONT192:%.*]]
|
|
// CHECK: ix.atomic.cont192:
|
|
// CHECK-NEXT: store i32 [[TMP1997]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT191]]
|
|
// CHECK: ix.atomic.exit191:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP1999:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2000:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2001:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1999]], i32 [[TMP2000]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2002:%.*]] = extractvalue { i32, i1 } [[TMP2001]], 0
|
|
// CHECK-NEXT: [[TMP2003:%.*]] = extractvalue { i32, i1 } [[TMP2001]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2003]], label [[IX_ATOMIC_EXIT193:%.*]], label [[IX_ATOMIC_CONT194:%.*]]
|
|
// CHECK: ix.atomic.cont194:
|
|
// CHECK-NEXT: store i32 [[TMP2002]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT193]]
|
|
// CHECK: ix.atomic.exit193:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2004:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2005:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2006:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2004]], i32 [[TMP2005]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2007:%.*]] = extractvalue { i32, i1 } [[TMP2006]], 1
|
|
// CHECK-NEXT: [[TMP2008:%.*]] = sext i1 [[TMP2007]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2008]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2009:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2010:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2011:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2009]], i32 [[TMP2010]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2012:%.*]] = extractvalue { i32, i1 } [[TMP2011]], 1
|
|
// CHECK-NEXT: [[TMP2013:%.*]] = sext i1 [[TMP2012]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2013]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2014:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2015:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2016:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2014]], i32 [[TMP2015]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2017:%.*]] = extractvalue { i32, i1 } [[TMP2016]], 0
|
|
// CHECK-NEXT: [[TMP2018:%.*]] = extractvalue { i32, i1 } [[TMP2016]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2018]], label [[IX_ATOMIC_EXIT195:%.*]], label [[IX_ATOMIC_CONT196:%.*]]
|
|
// CHECK: ix.atomic.cont196:
|
|
// CHECK-NEXT: store i32 [[TMP2017]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT195]]
|
|
// CHECK: ix.atomic.exit195:
|
|
// CHECK-NEXT: [[TMP2019:%.*]] = extractvalue { i32, i1 } [[TMP2016]], 1
|
|
// CHECK-NEXT: [[TMP2020:%.*]] = sext i1 [[TMP2019]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2020]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2021:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2022:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2023:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2021]], i32 [[TMP2022]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2024:%.*]] = extractvalue { i32, i1 } [[TMP2023]], 0
|
|
// CHECK-NEXT: [[TMP2025:%.*]] = extractvalue { i32, i1 } [[TMP2023]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2025]], label [[IX_ATOMIC_EXIT197:%.*]], label [[IX_ATOMIC_CONT198:%.*]]
|
|
// CHECK: ix.atomic.cont198:
|
|
// CHECK-NEXT: store i32 [[TMP2024]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT197]]
|
|
// CHECK: ix.atomic.exit197:
|
|
// CHECK-NEXT: [[TMP2026:%.*]] = extractvalue { i32, i1 } [[TMP2023]], 1
|
|
// CHECK-NEXT: [[TMP2027:%.*]] = sext i1 [[TMP2026]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2027]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2028:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2029:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2028]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2029]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2030:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2031:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2030]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2031]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2032:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2033:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2032]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2033]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2034:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2035:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2034]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2035]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2036:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2037:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2038:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2036]], i32 [[TMP2037]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2039:%.*]] = extractvalue { i32, i1 } [[TMP2038]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2039]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2040:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2041:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2042:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2040]], i32 [[TMP2041]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2043:%.*]] = extractvalue { i32, i1 } [[TMP2042]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2043]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2044:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2045:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2044]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP2046:%.*]] = icmp sgt i32 [[TMP2045]], [[TMP2044]]
|
|
// CHECK-NEXT: [[TMP2047:%.*]] = select i1 [[TMP2046]], i32 [[TMP2044]], i32 [[TMP2045]]
|
|
// CHECK-NEXT: store i32 [[TMP2047]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2048:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2049:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2048]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP2050:%.*]] = icmp slt i32 [[TMP2049]], [[TMP2048]]
|
|
// CHECK-NEXT: [[TMP2051:%.*]] = select i1 [[TMP2050]], i32 [[TMP2048]], i32 [[TMP2049]]
|
|
// CHECK-NEXT: store i32 [[TMP2051]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2052:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2053:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2052]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP2054:%.*]] = icmp slt i32 [[TMP2053]], [[TMP2052]]
|
|
// CHECK-NEXT: [[TMP2055:%.*]] = select i1 [[TMP2054]], i32 [[TMP2052]], i32 [[TMP2053]]
|
|
// CHECK-NEXT: store i32 [[TMP2055]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2056:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2057:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2056]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP2058:%.*]] = icmp sgt i32 [[TMP2057]], [[TMP2056]]
|
|
// CHECK-NEXT: [[TMP2059:%.*]] = select i1 [[TMP2058]], i32 [[TMP2056]], i32 [[TMP2057]]
|
|
// CHECK-NEXT: store i32 [[TMP2059]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2060:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2061:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2062:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2060]], i32 [[TMP2061]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2063:%.*]] = extractvalue { i32, i1 } [[TMP2062]], 0
|
|
// CHECK-NEXT: [[TMP2064:%.*]] = extractvalue { i32, i1 } [[TMP2062]], 1
|
|
// CHECK-NEXT: [[TMP2065:%.*]] = select i1 [[TMP2064]], i32 [[TMP2060]], i32 [[TMP2063]]
|
|
// CHECK-NEXT: store i32 [[TMP2065]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2066:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2067:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2068:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2066]], i32 [[TMP2067]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2069:%.*]] = extractvalue { i32, i1 } [[TMP2068]], 0
|
|
// CHECK-NEXT: [[TMP2070:%.*]] = extractvalue { i32, i1 } [[TMP2068]], 1
|
|
// CHECK-NEXT: [[TMP2071:%.*]] = select i1 [[TMP2070]], i32 [[TMP2066]], i32 [[TMP2069]]
|
|
// CHECK-NEXT: store i32 [[TMP2071]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2072:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2073:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2074:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2072]], i32 [[TMP2073]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2075:%.*]] = extractvalue { i32, i1 } [[TMP2074]], 0
|
|
// CHECK-NEXT: [[TMP2076:%.*]] = extractvalue { i32, i1 } [[TMP2074]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2076]], label [[IX_ATOMIC_EXIT199:%.*]], label [[IX_ATOMIC_CONT200:%.*]]
|
|
// CHECK: ix.atomic.cont200:
|
|
// CHECK-NEXT: store i32 [[TMP2075]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT199]]
|
|
// CHECK: ix.atomic.exit199:
|
|
// CHECK-NEXT: [[TMP2077:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2078:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2079:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2077]], i32 [[TMP2078]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2080:%.*]] = extractvalue { i32, i1 } [[TMP2079]], 0
|
|
// CHECK-NEXT: [[TMP2081:%.*]] = extractvalue { i32, i1 } [[TMP2079]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2081]], label [[IX_ATOMIC_EXIT201:%.*]], label [[IX_ATOMIC_CONT202:%.*]]
|
|
// CHECK: ix.atomic.cont202:
|
|
// CHECK-NEXT: store i32 [[TMP2080]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT201]]
|
|
// CHECK: ix.atomic.exit201:
|
|
// CHECK-NEXT: [[TMP2082:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2083:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2084:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2082]], i32 [[TMP2083]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2085:%.*]] = extractvalue { i32, i1 } [[TMP2084]], 1
|
|
// CHECK-NEXT: [[TMP2086:%.*]] = sext i1 [[TMP2085]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2086]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP2087:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2088:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2089:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2087]], i32 [[TMP2088]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2090:%.*]] = extractvalue { i32, i1 } [[TMP2089]], 1
|
|
// CHECK-NEXT: [[TMP2091:%.*]] = sext i1 [[TMP2090]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2091]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP2092:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2093:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2094:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2092]], i32 [[TMP2093]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2095:%.*]] = extractvalue { i32, i1 } [[TMP2094]], 0
|
|
// CHECK-NEXT: [[TMP2096:%.*]] = extractvalue { i32, i1 } [[TMP2094]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2096]], label [[IX_ATOMIC_EXIT203:%.*]], label [[IX_ATOMIC_CONT204:%.*]]
|
|
// CHECK: ix.atomic.cont204:
|
|
// CHECK-NEXT: store i32 [[TMP2095]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT203]]
|
|
// CHECK: ix.atomic.exit203:
|
|
// CHECK-NEXT: [[TMP2097:%.*]] = extractvalue { i32, i1 } [[TMP2094]], 1
|
|
// CHECK-NEXT: [[TMP2098:%.*]] = sext i1 [[TMP2097]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2098]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP2099:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2100:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2101:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2099]], i32 [[TMP2100]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2102:%.*]] = extractvalue { i32, i1 } [[TMP2101]], 0
|
|
// CHECK-NEXT: [[TMP2103:%.*]] = extractvalue { i32, i1 } [[TMP2101]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2103]], label [[IX_ATOMIC_EXIT205:%.*]], label [[IX_ATOMIC_CONT206:%.*]]
|
|
// CHECK: ix.atomic.cont206:
|
|
// CHECK-NEXT: store i32 [[TMP2102]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT205]]
|
|
// CHECK: ix.atomic.exit205:
|
|
// CHECK-NEXT: [[TMP2104:%.*]] = extractvalue { i32, i1 } [[TMP2101]], 1
|
|
// CHECK-NEXT: [[TMP2105:%.*]] = sext i1 [[TMP2104]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2105]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP2106:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2107:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2106]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2107]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2108:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2109:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2108]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2109]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2110:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2111:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2110]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2111]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2112:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2113:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2112]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2113]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2114:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2115:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2116:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2114]], i32 [[TMP2115]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2117:%.*]] = extractvalue { i32, i1 } [[TMP2116]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2117]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2118:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2119:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2120:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2118]], i32 [[TMP2119]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2121:%.*]] = extractvalue { i32, i1 } [[TMP2120]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2121]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2122:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2123:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2122]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2124:%.*]] = icmp sgt i32 [[TMP2123]], [[TMP2122]]
|
|
// CHECK-NEXT: [[TMP2125:%.*]] = select i1 [[TMP2124]], i32 [[TMP2122]], i32 [[TMP2123]]
|
|
// CHECK-NEXT: store i32 [[TMP2125]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2126:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2127:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2126]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2128:%.*]] = icmp slt i32 [[TMP2127]], [[TMP2126]]
|
|
// CHECK-NEXT: [[TMP2129:%.*]] = select i1 [[TMP2128]], i32 [[TMP2126]], i32 [[TMP2127]]
|
|
// CHECK-NEXT: store i32 [[TMP2129]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2130:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2131:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2130]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2132:%.*]] = icmp slt i32 [[TMP2131]], [[TMP2130]]
|
|
// CHECK-NEXT: [[TMP2133:%.*]] = select i1 [[TMP2132]], i32 [[TMP2130]], i32 [[TMP2131]]
|
|
// CHECK-NEXT: store i32 [[TMP2133]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2134:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2135:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2134]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2136:%.*]] = icmp sgt i32 [[TMP2135]], [[TMP2134]]
|
|
// CHECK-NEXT: [[TMP2137:%.*]] = select i1 [[TMP2136]], i32 [[TMP2134]], i32 [[TMP2135]]
|
|
// CHECK-NEXT: store i32 [[TMP2137]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2138:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2139:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2140:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2138]], i32 [[TMP2139]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2141:%.*]] = extractvalue { i32, i1 } [[TMP2140]], 0
|
|
// CHECK-NEXT: [[TMP2142:%.*]] = extractvalue { i32, i1 } [[TMP2140]], 1
|
|
// CHECK-NEXT: [[TMP2143:%.*]] = select i1 [[TMP2142]], i32 [[TMP2138]], i32 [[TMP2141]]
|
|
// CHECK-NEXT: store i32 [[TMP2143]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2144:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2145:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2146:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2144]], i32 [[TMP2145]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2147:%.*]] = extractvalue { i32, i1 } [[TMP2146]], 0
|
|
// CHECK-NEXT: [[TMP2148:%.*]] = extractvalue { i32, i1 } [[TMP2146]], 1
|
|
// CHECK-NEXT: [[TMP2149:%.*]] = select i1 [[TMP2148]], i32 [[TMP2144]], i32 [[TMP2147]]
|
|
// CHECK-NEXT: store i32 [[TMP2149]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2150:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2151:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2152:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2150]], i32 [[TMP2151]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2153:%.*]] = extractvalue { i32, i1 } [[TMP2152]], 0
|
|
// CHECK-NEXT: [[TMP2154:%.*]] = extractvalue { i32, i1 } [[TMP2152]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2154]], label [[IX_ATOMIC_EXIT207:%.*]], label [[IX_ATOMIC_CONT208:%.*]]
|
|
// CHECK: ix.atomic.cont208:
|
|
// CHECK-NEXT: store i32 [[TMP2153]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT207]]
|
|
// CHECK: ix.atomic.exit207:
|
|
// CHECK-NEXT: [[TMP2155:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2156:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2157:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2155]], i32 [[TMP2156]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2158:%.*]] = extractvalue { i32, i1 } [[TMP2157]], 0
|
|
// CHECK-NEXT: [[TMP2159:%.*]] = extractvalue { i32, i1 } [[TMP2157]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2159]], label [[IX_ATOMIC_EXIT209:%.*]], label [[IX_ATOMIC_CONT210:%.*]]
|
|
// CHECK: ix.atomic.cont210:
|
|
// CHECK-NEXT: store i32 [[TMP2158]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT209]]
|
|
// CHECK: ix.atomic.exit209:
|
|
// CHECK-NEXT: [[TMP2160:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2161:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2162:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2160]], i32 [[TMP2161]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2163:%.*]] = extractvalue { i32, i1 } [[TMP2162]], 1
|
|
// CHECK-NEXT: [[TMP2164:%.*]] = sext i1 [[TMP2163]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2164]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP2165:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2166:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2167:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2165]], i32 [[TMP2166]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2168:%.*]] = extractvalue { i32, i1 } [[TMP2167]], 1
|
|
// CHECK-NEXT: [[TMP2169:%.*]] = sext i1 [[TMP2168]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2169]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP2170:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2171:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2172:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2170]], i32 [[TMP2171]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2173:%.*]] = extractvalue { i32, i1 } [[TMP2172]], 0
|
|
// CHECK-NEXT: [[TMP2174:%.*]] = extractvalue { i32, i1 } [[TMP2172]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2174]], label [[IX_ATOMIC_EXIT211:%.*]], label [[IX_ATOMIC_CONT212:%.*]]
|
|
// CHECK: ix.atomic.cont212:
|
|
// CHECK-NEXT: store i32 [[TMP2173]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT211]]
|
|
// CHECK: ix.atomic.exit211:
|
|
// CHECK-NEXT: [[TMP2175:%.*]] = extractvalue { i32, i1 } [[TMP2172]], 1
|
|
// CHECK-NEXT: [[TMP2176:%.*]] = sext i1 [[TMP2175]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2176]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP2177:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2178:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2179:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2177]], i32 [[TMP2178]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2180:%.*]] = extractvalue { i32, i1 } [[TMP2179]], 0
|
|
// CHECK-NEXT: [[TMP2181:%.*]] = extractvalue { i32, i1 } [[TMP2179]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2181]], label [[IX_ATOMIC_EXIT213:%.*]], label [[IX_ATOMIC_CONT214:%.*]]
|
|
// CHECK: ix.atomic.cont214:
|
|
// CHECK-NEXT: store i32 [[TMP2180]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT213]]
|
|
// CHECK: ix.atomic.exit213:
|
|
// CHECK-NEXT: [[TMP2182:%.*]] = extractvalue { i32, i1 } [[TMP2179]], 1
|
|
// CHECK-NEXT: [[TMP2183:%.*]] = sext i1 [[TMP2182]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2183]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP2184:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2185:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2184]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2185]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2186:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2187:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2186]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2187]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2188:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2189:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2188]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2189]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2190:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2191:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2190]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2191]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2192:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2193:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2194:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2192]], i32 [[TMP2193]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2195:%.*]] = extractvalue { i32, i1 } [[TMP2194]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2195]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2196:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2197:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2198:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2196]], i32 [[TMP2197]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2199:%.*]] = extractvalue { i32, i1 } [[TMP2198]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2199]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2200:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2201:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2200]] release, align 4
|
|
// CHECK-NEXT: [[TMP2202:%.*]] = icmp sgt i32 [[TMP2201]], [[TMP2200]]
|
|
// CHECK-NEXT: [[TMP2203:%.*]] = select i1 [[TMP2202]], i32 [[TMP2200]], i32 [[TMP2201]]
|
|
// CHECK-NEXT: store i32 [[TMP2203]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2204:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2205:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2204]] release, align 4
|
|
// CHECK-NEXT: [[TMP2206:%.*]] = icmp slt i32 [[TMP2205]], [[TMP2204]]
|
|
// CHECK-NEXT: [[TMP2207:%.*]] = select i1 [[TMP2206]], i32 [[TMP2204]], i32 [[TMP2205]]
|
|
// CHECK-NEXT: store i32 [[TMP2207]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2208:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2209:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2208]] release, align 4
|
|
// CHECK-NEXT: [[TMP2210:%.*]] = icmp slt i32 [[TMP2209]], [[TMP2208]]
|
|
// CHECK-NEXT: [[TMP2211:%.*]] = select i1 [[TMP2210]], i32 [[TMP2208]], i32 [[TMP2209]]
|
|
// CHECK-NEXT: store i32 [[TMP2211]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2212:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2213:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2212]] release, align 4
|
|
// CHECK-NEXT: [[TMP2214:%.*]] = icmp sgt i32 [[TMP2213]], [[TMP2212]]
|
|
// CHECK-NEXT: [[TMP2215:%.*]] = select i1 [[TMP2214]], i32 [[TMP2212]], i32 [[TMP2213]]
|
|
// CHECK-NEXT: store i32 [[TMP2215]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2216:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2217:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2218:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2216]], i32 [[TMP2217]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2219:%.*]] = extractvalue { i32, i1 } [[TMP2218]], 0
|
|
// CHECK-NEXT: [[TMP2220:%.*]] = extractvalue { i32, i1 } [[TMP2218]], 1
|
|
// CHECK-NEXT: [[TMP2221:%.*]] = select i1 [[TMP2220]], i32 [[TMP2216]], i32 [[TMP2219]]
|
|
// CHECK-NEXT: store i32 [[TMP2221]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2222:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2223:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2224:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2222]], i32 [[TMP2223]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2225:%.*]] = extractvalue { i32, i1 } [[TMP2224]], 0
|
|
// CHECK-NEXT: [[TMP2226:%.*]] = extractvalue { i32, i1 } [[TMP2224]], 1
|
|
// CHECK-NEXT: [[TMP2227:%.*]] = select i1 [[TMP2226]], i32 [[TMP2222]], i32 [[TMP2225]]
|
|
// CHECK-NEXT: store i32 [[TMP2227]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2228:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2229:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2230:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2228]], i32 [[TMP2229]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2231:%.*]] = extractvalue { i32, i1 } [[TMP2230]], 0
|
|
// CHECK-NEXT: [[TMP2232:%.*]] = extractvalue { i32, i1 } [[TMP2230]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2232]], label [[IX_ATOMIC_EXIT215:%.*]], label [[IX_ATOMIC_CONT216:%.*]]
|
|
// CHECK: ix.atomic.cont216:
|
|
// CHECK-NEXT: store i32 [[TMP2231]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT215]]
|
|
// CHECK: ix.atomic.exit215:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2233:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2234:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2235:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2233]], i32 [[TMP2234]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2236:%.*]] = extractvalue { i32, i1 } [[TMP2235]], 0
|
|
// CHECK-NEXT: [[TMP2237:%.*]] = extractvalue { i32, i1 } [[TMP2235]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2237]], label [[IX_ATOMIC_EXIT217:%.*]], label [[IX_ATOMIC_CONT218:%.*]]
|
|
// CHECK: ix.atomic.cont218:
|
|
// CHECK-NEXT: store i32 [[TMP2236]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT217]]
|
|
// CHECK: ix.atomic.exit217:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2238:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2239:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2240:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2238]], i32 [[TMP2239]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2241:%.*]] = extractvalue { i32, i1 } [[TMP2240]], 1
|
|
// CHECK-NEXT: [[TMP2242:%.*]] = sext i1 [[TMP2241]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2242]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2243:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2244:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2245:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2243]], i32 [[TMP2244]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2246:%.*]] = extractvalue { i32, i1 } [[TMP2245]], 1
|
|
// CHECK-NEXT: [[TMP2247:%.*]] = sext i1 [[TMP2246]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2247]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2248:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2249:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2250:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2248]], i32 [[TMP2249]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2251:%.*]] = extractvalue { i32, i1 } [[TMP2250]], 0
|
|
// CHECK-NEXT: [[TMP2252:%.*]] = extractvalue { i32, i1 } [[TMP2250]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2252]], label [[IX_ATOMIC_EXIT219:%.*]], label [[IX_ATOMIC_CONT220:%.*]]
|
|
// CHECK: ix.atomic.cont220:
|
|
// CHECK-NEXT: store i32 [[TMP2251]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT219]]
|
|
// CHECK: ix.atomic.exit219:
|
|
// CHECK-NEXT: [[TMP2253:%.*]] = extractvalue { i32, i1 } [[TMP2250]], 1
|
|
// CHECK-NEXT: [[TMP2254:%.*]] = sext i1 [[TMP2253]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2254]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2255:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2256:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2257:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2255]], i32 [[TMP2256]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2258:%.*]] = extractvalue { i32, i1 } [[TMP2257]], 0
|
|
// CHECK-NEXT: [[TMP2259:%.*]] = extractvalue { i32, i1 } [[TMP2257]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2259]], label [[IX_ATOMIC_EXIT221:%.*]], label [[IX_ATOMIC_CONT222:%.*]]
|
|
// CHECK: ix.atomic.cont222:
|
|
// CHECK-NEXT: store i32 [[TMP2258]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT221]]
|
|
// CHECK: ix.atomic.exit221:
|
|
// CHECK-NEXT: [[TMP2260:%.*]] = extractvalue { i32, i1 } [[TMP2257]], 1
|
|
// CHECK-NEXT: [[TMP2261:%.*]] = sext i1 [[TMP2260]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2261]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2262:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2263:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2262]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2263]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2264:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2265:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2264]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2265]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2266:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2267:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2266]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2267]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2268:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2269:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2268]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2269]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2270:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2271:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2272:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2270]], i32 [[TMP2271]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2273:%.*]] = extractvalue { i32, i1 } [[TMP2272]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2273]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2274:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2275:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2276:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2274]], i32 [[TMP2275]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2277:%.*]] = extractvalue { i32, i1 } [[TMP2276]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2277]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2278:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2279:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2278]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2280:%.*]] = icmp sgt i32 [[TMP2279]], [[TMP2278]]
|
|
// CHECK-NEXT: [[TMP2281:%.*]] = select i1 [[TMP2280]], i32 [[TMP2278]], i32 [[TMP2279]]
|
|
// CHECK-NEXT: store i32 [[TMP2281]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2282:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2283:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2282]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2284:%.*]] = icmp slt i32 [[TMP2283]], [[TMP2282]]
|
|
// CHECK-NEXT: [[TMP2285:%.*]] = select i1 [[TMP2284]], i32 [[TMP2282]], i32 [[TMP2283]]
|
|
// CHECK-NEXT: store i32 [[TMP2285]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2286:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2287:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2286]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2288:%.*]] = icmp slt i32 [[TMP2287]], [[TMP2286]]
|
|
// CHECK-NEXT: [[TMP2289:%.*]] = select i1 [[TMP2288]], i32 [[TMP2286]], i32 [[TMP2287]]
|
|
// CHECK-NEXT: store i32 [[TMP2289]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2290:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2291:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2290]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2292:%.*]] = icmp sgt i32 [[TMP2291]], [[TMP2290]]
|
|
// CHECK-NEXT: [[TMP2293:%.*]] = select i1 [[TMP2292]], i32 [[TMP2290]], i32 [[TMP2291]]
|
|
// CHECK-NEXT: store i32 [[TMP2293]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2294:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2295:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2296:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2294]], i32 [[TMP2295]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2297:%.*]] = extractvalue { i32, i1 } [[TMP2296]], 0
|
|
// CHECK-NEXT: [[TMP2298:%.*]] = extractvalue { i32, i1 } [[TMP2296]], 1
|
|
// CHECK-NEXT: [[TMP2299:%.*]] = select i1 [[TMP2298]], i32 [[TMP2294]], i32 [[TMP2297]]
|
|
// CHECK-NEXT: store i32 [[TMP2299]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2300:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2301:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2302:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2300]], i32 [[TMP2301]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2303:%.*]] = extractvalue { i32, i1 } [[TMP2302]], 0
|
|
// CHECK-NEXT: [[TMP2304:%.*]] = extractvalue { i32, i1 } [[TMP2302]], 1
|
|
// CHECK-NEXT: [[TMP2305:%.*]] = select i1 [[TMP2304]], i32 [[TMP2300]], i32 [[TMP2303]]
|
|
// CHECK-NEXT: store i32 [[TMP2305]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2306:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2307:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2308:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2306]], i32 [[TMP2307]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2309:%.*]] = extractvalue { i32, i1 } [[TMP2308]], 0
|
|
// CHECK-NEXT: [[TMP2310:%.*]] = extractvalue { i32, i1 } [[TMP2308]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2310]], label [[IX_ATOMIC_EXIT223:%.*]], label [[IX_ATOMIC_CONT224:%.*]]
|
|
// CHECK: ix.atomic.cont224:
|
|
// CHECK-NEXT: store i32 [[TMP2309]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT223]]
|
|
// CHECK: ix.atomic.exit223:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2311:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2312:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2313:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2311]], i32 [[TMP2312]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2314:%.*]] = extractvalue { i32, i1 } [[TMP2313]], 0
|
|
// CHECK-NEXT: [[TMP2315:%.*]] = extractvalue { i32, i1 } [[TMP2313]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2315]], label [[IX_ATOMIC_EXIT225:%.*]], label [[IX_ATOMIC_CONT226:%.*]]
|
|
// CHECK: ix.atomic.cont226:
|
|
// CHECK-NEXT: store i32 [[TMP2314]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT225]]
|
|
// CHECK: ix.atomic.exit225:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2316:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2317:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2318:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2316]], i32 [[TMP2317]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2319:%.*]] = extractvalue { i32, i1 } [[TMP2318]], 1
|
|
// CHECK-NEXT: [[TMP2320:%.*]] = sext i1 [[TMP2319]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2320]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2321:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2322:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2323:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2321]], i32 [[TMP2322]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2324:%.*]] = extractvalue { i32, i1 } [[TMP2323]], 1
|
|
// CHECK-NEXT: [[TMP2325:%.*]] = sext i1 [[TMP2324]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2325]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2326:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2327:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2328:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2326]], i32 [[TMP2327]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2329:%.*]] = extractvalue { i32, i1 } [[TMP2328]], 0
|
|
// CHECK-NEXT: [[TMP2330:%.*]] = extractvalue { i32, i1 } [[TMP2328]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2330]], label [[IX_ATOMIC_EXIT227:%.*]], label [[IX_ATOMIC_CONT228:%.*]]
|
|
// CHECK: ix.atomic.cont228:
|
|
// CHECK-NEXT: store i32 [[TMP2329]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT227]]
|
|
// CHECK: ix.atomic.exit227:
|
|
// CHECK-NEXT: [[TMP2331:%.*]] = extractvalue { i32, i1 } [[TMP2328]], 1
|
|
// CHECK-NEXT: [[TMP2332:%.*]] = sext i1 [[TMP2331]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2332]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2333:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP2334:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP2335:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2333]], i32 [[TMP2334]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2336:%.*]] = extractvalue { i32, i1 } [[TMP2335]], 0
|
|
// CHECK-NEXT: [[TMP2337:%.*]] = extractvalue { i32, i1 } [[TMP2335]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2337]], label [[IX_ATOMIC_EXIT229:%.*]], label [[IX_ATOMIC_CONT230:%.*]]
|
|
// CHECK: ix.atomic.cont230:
|
|
// CHECK-NEXT: store i32 [[TMP2336]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT229]]
|
|
// CHECK: ix.atomic.exit229:
|
|
// CHECK-NEXT: [[TMP2338:%.*]] = extractvalue { i32, i1 } [[TMP2335]], 1
|
|
// CHECK-NEXT: [[TMP2339:%.*]] = sext i1 [[TMP2338]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2339]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2340:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2341:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2340]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2341]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2342:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2343:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2342]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2343]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2344:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2345:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2344]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2345]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2346:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2347:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2346]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2347]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2348:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2349:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2350:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2348]], i32 [[TMP2349]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2351:%.*]] = extractvalue { i32, i1 } [[TMP2350]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2351]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2352:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2353:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2354:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2352]], i32 [[TMP2353]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2355:%.*]] = extractvalue { i32, i1 } [[TMP2354]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2355]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2356:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2357:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2356]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2358:%.*]] = icmp ugt i32 [[TMP2357]], [[TMP2356]]
|
|
// CHECK-NEXT: [[TMP2359:%.*]] = select i1 [[TMP2358]], i32 [[TMP2356]], i32 [[TMP2357]]
|
|
// CHECK-NEXT: store i32 [[TMP2359]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2360:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2361:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2360]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2362:%.*]] = icmp ult i32 [[TMP2361]], [[TMP2360]]
|
|
// CHECK-NEXT: [[TMP2363:%.*]] = select i1 [[TMP2362]], i32 [[TMP2360]], i32 [[TMP2361]]
|
|
// CHECK-NEXT: store i32 [[TMP2363]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2364:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2365:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2364]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2366:%.*]] = icmp ult i32 [[TMP2365]], [[TMP2364]]
|
|
// CHECK-NEXT: [[TMP2367:%.*]] = select i1 [[TMP2366]], i32 [[TMP2364]], i32 [[TMP2365]]
|
|
// CHECK-NEXT: store i32 [[TMP2367]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2368:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2369:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2368]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2370:%.*]] = icmp ugt i32 [[TMP2369]], [[TMP2368]]
|
|
// CHECK-NEXT: [[TMP2371:%.*]] = select i1 [[TMP2370]], i32 [[TMP2368]], i32 [[TMP2369]]
|
|
// CHECK-NEXT: store i32 [[TMP2371]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2372:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2373:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2374:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2372]], i32 [[TMP2373]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2375:%.*]] = extractvalue { i32, i1 } [[TMP2374]], 0
|
|
// CHECK-NEXT: [[TMP2376:%.*]] = extractvalue { i32, i1 } [[TMP2374]], 1
|
|
// CHECK-NEXT: [[TMP2377:%.*]] = select i1 [[TMP2376]], i32 [[TMP2372]], i32 [[TMP2375]]
|
|
// CHECK-NEXT: store i32 [[TMP2377]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2378:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2379:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2380:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2378]], i32 [[TMP2379]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2381:%.*]] = extractvalue { i32, i1 } [[TMP2380]], 0
|
|
// CHECK-NEXT: [[TMP2382:%.*]] = extractvalue { i32, i1 } [[TMP2380]], 1
|
|
// CHECK-NEXT: [[TMP2383:%.*]] = select i1 [[TMP2382]], i32 [[TMP2378]], i32 [[TMP2381]]
|
|
// CHECK-NEXT: store i32 [[TMP2383]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2384:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2385:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2386:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2384]], i32 [[TMP2385]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2387:%.*]] = extractvalue { i32, i1 } [[TMP2386]], 0
|
|
// CHECK-NEXT: [[TMP2388:%.*]] = extractvalue { i32, i1 } [[TMP2386]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2388]], label [[UIX_ATOMIC_EXIT:%.*]], label [[UIX_ATOMIC_CONT:%.*]]
|
|
// CHECK: uix.atomic.cont:
|
|
// CHECK-NEXT: store i32 [[TMP2387]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT]]
|
|
// CHECK: uix.atomic.exit:
|
|
// CHECK-NEXT: [[TMP2389:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2390:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2391:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2389]], i32 [[TMP2390]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2392:%.*]] = extractvalue { i32, i1 } [[TMP2391]], 0
|
|
// CHECK-NEXT: [[TMP2393:%.*]] = extractvalue { i32, i1 } [[TMP2391]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2393]], label [[UIX_ATOMIC_EXIT231:%.*]], label [[UIX_ATOMIC_CONT232:%.*]]
|
|
// CHECK: uix.atomic.cont232:
|
|
// CHECK-NEXT: store i32 [[TMP2392]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT231]]
|
|
// CHECK: uix.atomic.exit231:
|
|
// CHECK-NEXT: [[TMP2394:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2395:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2396:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2394]], i32 [[TMP2395]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2397:%.*]] = extractvalue { i32, i1 } [[TMP2396]], 1
|
|
// CHECK-NEXT: [[TMP2398:%.*]] = zext i1 [[TMP2397]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2398]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2399:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2400:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2401:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2399]], i32 [[TMP2400]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2402:%.*]] = extractvalue { i32, i1 } [[TMP2401]], 1
|
|
// CHECK-NEXT: [[TMP2403:%.*]] = zext i1 [[TMP2402]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2403]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2404:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2405:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2406:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2404]], i32 [[TMP2405]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2407:%.*]] = extractvalue { i32, i1 } [[TMP2406]], 0
|
|
// CHECK-NEXT: [[TMP2408:%.*]] = extractvalue { i32, i1 } [[TMP2406]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2408]], label [[UIX_ATOMIC_EXIT233:%.*]], label [[UIX_ATOMIC_CONT234:%.*]]
|
|
// CHECK: uix.atomic.cont234:
|
|
// CHECK-NEXT: store i32 [[TMP2407]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT233]]
|
|
// CHECK: uix.atomic.exit233:
|
|
// CHECK-NEXT: [[TMP2409:%.*]] = extractvalue { i32, i1 } [[TMP2406]], 1
|
|
// CHECK-NEXT: [[TMP2410:%.*]] = zext i1 [[TMP2409]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2410]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2411:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2412:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2413:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2411]], i32 [[TMP2412]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2414:%.*]] = extractvalue { i32, i1 } [[TMP2413]], 0
|
|
// CHECK-NEXT: [[TMP2415:%.*]] = extractvalue { i32, i1 } [[TMP2413]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2415]], label [[UIX_ATOMIC_EXIT235:%.*]], label [[UIX_ATOMIC_CONT236:%.*]]
|
|
// CHECK: uix.atomic.cont236:
|
|
// CHECK-NEXT: store i32 [[TMP2414]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT235]]
|
|
// CHECK: uix.atomic.exit235:
|
|
// CHECK-NEXT: [[TMP2416:%.*]] = extractvalue { i32, i1 } [[TMP2413]], 1
|
|
// CHECK-NEXT: [[TMP2417:%.*]] = zext i1 [[TMP2416]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2417]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2418:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2419:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2418]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2419]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2420:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2421:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2420]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2421]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2422:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2423:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2422]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2423]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2424:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2425:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2424]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2425]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2426:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2427:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2428:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2426]], i32 [[TMP2427]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2429:%.*]] = extractvalue { i32, i1 } [[TMP2428]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2429]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2430:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2431:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2432:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2430]], i32 [[TMP2431]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2433:%.*]] = extractvalue { i32, i1 } [[TMP2432]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2433]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2434:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2435:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2434]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP2436:%.*]] = icmp ugt i32 [[TMP2435]], [[TMP2434]]
|
|
// CHECK-NEXT: [[TMP2437:%.*]] = select i1 [[TMP2436]], i32 [[TMP2434]], i32 [[TMP2435]]
|
|
// CHECK-NEXT: store i32 [[TMP2437]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2438:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2439:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2438]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP2440:%.*]] = icmp ult i32 [[TMP2439]], [[TMP2438]]
|
|
// CHECK-NEXT: [[TMP2441:%.*]] = select i1 [[TMP2440]], i32 [[TMP2438]], i32 [[TMP2439]]
|
|
// CHECK-NEXT: store i32 [[TMP2441]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2442:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2443:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2442]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP2444:%.*]] = icmp ult i32 [[TMP2443]], [[TMP2442]]
|
|
// CHECK-NEXT: [[TMP2445:%.*]] = select i1 [[TMP2444]], i32 [[TMP2442]], i32 [[TMP2443]]
|
|
// CHECK-NEXT: store i32 [[TMP2445]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2446:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2447:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2446]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP2448:%.*]] = icmp ugt i32 [[TMP2447]], [[TMP2446]]
|
|
// CHECK-NEXT: [[TMP2449:%.*]] = select i1 [[TMP2448]], i32 [[TMP2446]], i32 [[TMP2447]]
|
|
// CHECK-NEXT: store i32 [[TMP2449]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2450:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2451:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2452:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2450]], i32 [[TMP2451]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2453:%.*]] = extractvalue { i32, i1 } [[TMP2452]], 0
|
|
// CHECK-NEXT: [[TMP2454:%.*]] = extractvalue { i32, i1 } [[TMP2452]], 1
|
|
// CHECK-NEXT: [[TMP2455:%.*]] = select i1 [[TMP2454]], i32 [[TMP2450]], i32 [[TMP2453]]
|
|
// CHECK-NEXT: store i32 [[TMP2455]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2456:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2457:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2458:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2456]], i32 [[TMP2457]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2459:%.*]] = extractvalue { i32, i1 } [[TMP2458]], 0
|
|
// CHECK-NEXT: [[TMP2460:%.*]] = extractvalue { i32, i1 } [[TMP2458]], 1
|
|
// CHECK-NEXT: [[TMP2461:%.*]] = select i1 [[TMP2460]], i32 [[TMP2456]], i32 [[TMP2459]]
|
|
// CHECK-NEXT: store i32 [[TMP2461]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2462:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2463:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2464:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2462]], i32 [[TMP2463]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2465:%.*]] = extractvalue { i32, i1 } [[TMP2464]], 0
|
|
// CHECK-NEXT: [[TMP2466:%.*]] = extractvalue { i32, i1 } [[TMP2464]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2466]], label [[UIX_ATOMIC_EXIT237:%.*]], label [[UIX_ATOMIC_CONT238:%.*]]
|
|
// CHECK: uix.atomic.cont238:
|
|
// CHECK-NEXT: store i32 [[TMP2465]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT237]]
|
|
// CHECK: uix.atomic.exit237:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2467:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2468:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2469:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2467]], i32 [[TMP2468]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2470:%.*]] = extractvalue { i32, i1 } [[TMP2469]], 0
|
|
// CHECK-NEXT: [[TMP2471:%.*]] = extractvalue { i32, i1 } [[TMP2469]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2471]], label [[UIX_ATOMIC_EXIT239:%.*]], label [[UIX_ATOMIC_CONT240:%.*]]
|
|
// CHECK: uix.atomic.cont240:
|
|
// CHECK-NEXT: store i32 [[TMP2470]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT239]]
|
|
// CHECK: uix.atomic.exit239:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2472:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2473:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2474:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2472]], i32 [[TMP2473]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2475:%.*]] = extractvalue { i32, i1 } [[TMP2474]], 1
|
|
// CHECK-NEXT: [[TMP2476:%.*]] = zext i1 [[TMP2475]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2476]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2477:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2478:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2479:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2477]], i32 [[TMP2478]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2480:%.*]] = extractvalue { i32, i1 } [[TMP2479]], 1
|
|
// CHECK-NEXT: [[TMP2481:%.*]] = zext i1 [[TMP2480]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2481]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2482:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2483:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2484:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2482]], i32 [[TMP2483]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2485:%.*]] = extractvalue { i32, i1 } [[TMP2484]], 0
|
|
// CHECK-NEXT: [[TMP2486:%.*]] = extractvalue { i32, i1 } [[TMP2484]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2486]], label [[UIX_ATOMIC_EXIT241:%.*]], label [[UIX_ATOMIC_CONT242:%.*]]
|
|
// CHECK: uix.atomic.cont242:
|
|
// CHECK-NEXT: store i32 [[TMP2485]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT241]]
|
|
// CHECK: uix.atomic.exit241:
|
|
// CHECK-NEXT: [[TMP2487:%.*]] = extractvalue { i32, i1 } [[TMP2484]], 1
|
|
// CHECK-NEXT: [[TMP2488:%.*]] = zext i1 [[TMP2487]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2488]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2489:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2490:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2491:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2489]], i32 [[TMP2490]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP2492:%.*]] = extractvalue { i32, i1 } [[TMP2491]], 0
|
|
// CHECK-NEXT: [[TMP2493:%.*]] = extractvalue { i32, i1 } [[TMP2491]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2493]], label [[UIX_ATOMIC_EXIT243:%.*]], label [[UIX_ATOMIC_CONT244:%.*]]
|
|
// CHECK: uix.atomic.cont244:
|
|
// CHECK-NEXT: store i32 [[TMP2492]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT243]]
|
|
// CHECK: uix.atomic.exit243:
|
|
// CHECK-NEXT: [[TMP2494:%.*]] = extractvalue { i32, i1 } [[TMP2491]], 1
|
|
// CHECK-NEXT: [[TMP2495:%.*]] = zext i1 [[TMP2494]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2495]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2496:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2497:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2496]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2497]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2498:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2499:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2498]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2499]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2500:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2501:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2500]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2501]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2502:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2503:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2502]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2503]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2504:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2505:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2506:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2504]], i32 [[TMP2505]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2507:%.*]] = extractvalue { i32, i1 } [[TMP2506]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2507]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2508:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2509:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2510:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2508]], i32 [[TMP2509]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2511:%.*]] = extractvalue { i32, i1 } [[TMP2510]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2511]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2512:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2513:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2512]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP2514:%.*]] = icmp ugt i32 [[TMP2513]], [[TMP2512]]
|
|
// CHECK-NEXT: [[TMP2515:%.*]] = select i1 [[TMP2514]], i32 [[TMP2512]], i32 [[TMP2513]]
|
|
// CHECK-NEXT: store i32 [[TMP2515]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2516:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2517:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2516]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP2518:%.*]] = icmp ult i32 [[TMP2517]], [[TMP2516]]
|
|
// CHECK-NEXT: [[TMP2519:%.*]] = select i1 [[TMP2518]], i32 [[TMP2516]], i32 [[TMP2517]]
|
|
// CHECK-NEXT: store i32 [[TMP2519]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2520:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2521:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2520]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP2522:%.*]] = icmp ult i32 [[TMP2521]], [[TMP2520]]
|
|
// CHECK-NEXT: [[TMP2523:%.*]] = select i1 [[TMP2522]], i32 [[TMP2520]], i32 [[TMP2521]]
|
|
// CHECK-NEXT: store i32 [[TMP2523]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2524:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2525:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2524]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP2526:%.*]] = icmp ugt i32 [[TMP2525]], [[TMP2524]]
|
|
// CHECK-NEXT: [[TMP2527:%.*]] = select i1 [[TMP2526]], i32 [[TMP2524]], i32 [[TMP2525]]
|
|
// CHECK-NEXT: store i32 [[TMP2527]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2528:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2529:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2530:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2528]], i32 [[TMP2529]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2531:%.*]] = extractvalue { i32, i1 } [[TMP2530]], 0
|
|
// CHECK-NEXT: [[TMP2532:%.*]] = extractvalue { i32, i1 } [[TMP2530]], 1
|
|
// CHECK-NEXT: [[TMP2533:%.*]] = select i1 [[TMP2532]], i32 [[TMP2528]], i32 [[TMP2531]]
|
|
// CHECK-NEXT: store i32 [[TMP2533]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2534:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2535:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2536:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2534]], i32 [[TMP2535]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2537:%.*]] = extractvalue { i32, i1 } [[TMP2536]], 0
|
|
// CHECK-NEXT: [[TMP2538:%.*]] = extractvalue { i32, i1 } [[TMP2536]], 1
|
|
// CHECK-NEXT: [[TMP2539:%.*]] = select i1 [[TMP2538]], i32 [[TMP2534]], i32 [[TMP2537]]
|
|
// CHECK-NEXT: store i32 [[TMP2539]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2540:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2541:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2542:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2540]], i32 [[TMP2541]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2543:%.*]] = extractvalue { i32, i1 } [[TMP2542]], 0
|
|
// CHECK-NEXT: [[TMP2544:%.*]] = extractvalue { i32, i1 } [[TMP2542]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2544]], label [[UIX_ATOMIC_EXIT245:%.*]], label [[UIX_ATOMIC_CONT246:%.*]]
|
|
// CHECK: uix.atomic.cont246:
|
|
// CHECK-NEXT: store i32 [[TMP2543]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT245]]
|
|
// CHECK: uix.atomic.exit245:
|
|
// CHECK-NEXT: [[TMP2545:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2546:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2547:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2545]], i32 [[TMP2546]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2548:%.*]] = extractvalue { i32, i1 } [[TMP2547]], 0
|
|
// CHECK-NEXT: [[TMP2549:%.*]] = extractvalue { i32, i1 } [[TMP2547]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2549]], label [[UIX_ATOMIC_EXIT247:%.*]], label [[UIX_ATOMIC_CONT248:%.*]]
|
|
// CHECK: uix.atomic.cont248:
|
|
// CHECK-NEXT: store i32 [[TMP2548]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT247]]
|
|
// CHECK: uix.atomic.exit247:
|
|
// CHECK-NEXT: [[TMP2550:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2551:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2552:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2550]], i32 [[TMP2551]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2553:%.*]] = extractvalue { i32, i1 } [[TMP2552]], 1
|
|
// CHECK-NEXT: [[TMP2554:%.*]] = zext i1 [[TMP2553]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2554]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2555:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2556:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2557:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2555]], i32 [[TMP2556]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2558:%.*]] = extractvalue { i32, i1 } [[TMP2557]], 1
|
|
// CHECK-NEXT: [[TMP2559:%.*]] = zext i1 [[TMP2558]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2559]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2560:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2561:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2562:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2560]], i32 [[TMP2561]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2563:%.*]] = extractvalue { i32, i1 } [[TMP2562]], 0
|
|
// CHECK-NEXT: [[TMP2564:%.*]] = extractvalue { i32, i1 } [[TMP2562]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2564]], label [[UIX_ATOMIC_EXIT249:%.*]], label [[UIX_ATOMIC_CONT250:%.*]]
|
|
// CHECK: uix.atomic.cont250:
|
|
// CHECK-NEXT: store i32 [[TMP2563]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT249]]
|
|
// CHECK: uix.atomic.exit249:
|
|
// CHECK-NEXT: [[TMP2565:%.*]] = extractvalue { i32, i1 } [[TMP2562]], 1
|
|
// CHECK-NEXT: [[TMP2566:%.*]] = zext i1 [[TMP2565]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2566]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2567:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2568:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2569:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2567]], i32 [[TMP2568]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP2570:%.*]] = extractvalue { i32, i1 } [[TMP2569]], 0
|
|
// CHECK-NEXT: [[TMP2571:%.*]] = extractvalue { i32, i1 } [[TMP2569]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2571]], label [[UIX_ATOMIC_EXIT251:%.*]], label [[UIX_ATOMIC_CONT252:%.*]]
|
|
// CHECK: uix.atomic.cont252:
|
|
// CHECK-NEXT: store i32 [[TMP2570]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT251]]
|
|
// CHECK: uix.atomic.exit251:
|
|
// CHECK-NEXT: [[TMP2572:%.*]] = extractvalue { i32, i1 } [[TMP2569]], 1
|
|
// CHECK-NEXT: [[TMP2573:%.*]] = zext i1 [[TMP2572]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2573]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2574:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2575:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2574]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2575]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2576:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2577:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2576]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2577]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2578:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2579:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2578]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2579]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2580:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2581:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2580]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2581]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2582:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2583:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2584:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2582]], i32 [[TMP2583]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2585:%.*]] = extractvalue { i32, i1 } [[TMP2584]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2585]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2586:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2587:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2588:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2586]], i32 [[TMP2587]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2589:%.*]] = extractvalue { i32, i1 } [[TMP2588]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2589]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2590:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2591:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2590]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2592:%.*]] = icmp ugt i32 [[TMP2591]], [[TMP2590]]
|
|
// CHECK-NEXT: [[TMP2593:%.*]] = select i1 [[TMP2592]], i32 [[TMP2590]], i32 [[TMP2591]]
|
|
// CHECK-NEXT: store i32 [[TMP2593]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2594:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2595:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2594]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2596:%.*]] = icmp ult i32 [[TMP2595]], [[TMP2594]]
|
|
// CHECK-NEXT: [[TMP2597:%.*]] = select i1 [[TMP2596]], i32 [[TMP2594]], i32 [[TMP2595]]
|
|
// CHECK-NEXT: store i32 [[TMP2597]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2598:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2599:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2598]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2600:%.*]] = icmp ult i32 [[TMP2599]], [[TMP2598]]
|
|
// CHECK-NEXT: [[TMP2601:%.*]] = select i1 [[TMP2600]], i32 [[TMP2598]], i32 [[TMP2599]]
|
|
// CHECK-NEXT: store i32 [[TMP2601]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2602:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2603:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2602]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2604:%.*]] = icmp ugt i32 [[TMP2603]], [[TMP2602]]
|
|
// CHECK-NEXT: [[TMP2605:%.*]] = select i1 [[TMP2604]], i32 [[TMP2602]], i32 [[TMP2603]]
|
|
// CHECK-NEXT: store i32 [[TMP2605]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2606:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2607:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2608:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2606]], i32 [[TMP2607]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2609:%.*]] = extractvalue { i32, i1 } [[TMP2608]], 0
|
|
// CHECK-NEXT: [[TMP2610:%.*]] = extractvalue { i32, i1 } [[TMP2608]], 1
|
|
// CHECK-NEXT: [[TMP2611:%.*]] = select i1 [[TMP2610]], i32 [[TMP2606]], i32 [[TMP2609]]
|
|
// CHECK-NEXT: store i32 [[TMP2611]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2612:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2613:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2614:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2612]], i32 [[TMP2613]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2615:%.*]] = extractvalue { i32, i1 } [[TMP2614]], 0
|
|
// CHECK-NEXT: [[TMP2616:%.*]] = extractvalue { i32, i1 } [[TMP2614]], 1
|
|
// CHECK-NEXT: [[TMP2617:%.*]] = select i1 [[TMP2616]], i32 [[TMP2612]], i32 [[TMP2615]]
|
|
// CHECK-NEXT: store i32 [[TMP2617]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2618:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2619:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2620:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2618]], i32 [[TMP2619]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2621:%.*]] = extractvalue { i32, i1 } [[TMP2620]], 0
|
|
// CHECK-NEXT: [[TMP2622:%.*]] = extractvalue { i32, i1 } [[TMP2620]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2622]], label [[UIX_ATOMIC_EXIT253:%.*]], label [[UIX_ATOMIC_CONT254:%.*]]
|
|
// CHECK: uix.atomic.cont254:
|
|
// CHECK-NEXT: store i32 [[TMP2621]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT253]]
|
|
// CHECK: uix.atomic.exit253:
|
|
// CHECK-NEXT: [[TMP2623:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2624:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2625:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2623]], i32 [[TMP2624]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2626:%.*]] = extractvalue { i32, i1 } [[TMP2625]], 0
|
|
// CHECK-NEXT: [[TMP2627:%.*]] = extractvalue { i32, i1 } [[TMP2625]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2627]], label [[UIX_ATOMIC_EXIT255:%.*]], label [[UIX_ATOMIC_CONT256:%.*]]
|
|
// CHECK: uix.atomic.cont256:
|
|
// CHECK-NEXT: store i32 [[TMP2626]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT255]]
|
|
// CHECK: uix.atomic.exit255:
|
|
// CHECK-NEXT: [[TMP2628:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2629:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2630:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2628]], i32 [[TMP2629]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2631:%.*]] = extractvalue { i32, i1 } [[TMP2630]], 1
|
|
// CHECK-NEXT: [[TMP2632:%.*]] = zext i1 [[TMP2631]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2632]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2633:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2634:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2635:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2633]], i32 [[TMP2634]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2636:%.*]] = extractvalue { i32, i1 } [[TMP2635]], 1
|
|
// CHECK-NEXT: [[TMP2637:%.*]] = zext i1 [[TMP2636]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2637]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2638:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2639:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2640:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2638]], i32 [[TMP2639]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2641:%.*]] = extractvalue { i32, i1 } [[TMP2640]], 0
|
|
// CHECK-NEXT: [[TMP2642:%.*]] = extractvalue { i32, i1 } [[TMP2640]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2642]], label [[UIX_ATOMIC_EXIT257:%.*]], label [[UIX_ATOMIC_CONT258:%.*]]
|
|
// CHECK: uix.atomic.cont258:
|
|
// CHECK-NEXT: store i32 [[TMP2641]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT257]]
|
|
// CHECK: uix.atomic.exit257:
|
|
// CHECK-NEXT: [[TMP2643:%.*]] = extractvalue { i32, i1 } [[TMP2640]], 1
|
|
// CHECK-NEXT: [[TMP2644:%.*]] = zext i1 [[TMP2643]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2644]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2645:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2646:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2647:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2645]], i32 [[TMP2646]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2648:%.*]] = extractvalue { i32, i1 } [[TMP2647]], 0
|
|
// CHECK-NEXT: [[TMP2649:%.*]] = extractvalue { i32, i1 } [[TMP2647]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2649]], label [[UIX_ATOMIC_EXIT259:%.*]], label [[UIX_ATOMIC_CONT260:%.*]]
|
|
// CHECK: uix.atomic.cont260:
|
|
// CHECK-NEXT: store i32 [[TMP2648]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT259]]
|
|
// CHECK: uix.atomic.exit259:
|
|
// CHECK-NEXT: [[TMP2650:%.*]] = extractvalue { i32, i1 } [[TMP2647]], 1
|
|
// CHECK-NEXT: [[TMP2651:%.*]] = zext i1 [[TMP2650]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2651]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: [[TMP2652:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2653:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2652]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2653]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2654:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2655:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2654]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2655]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2656:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2657:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2656]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2657]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2658:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2659:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2658]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2659]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2660:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2661:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2662:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2660]], i32 [[TMP2661]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2663:%.*]] = extractvalue { i32, i1 } [[TMP2662]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2663]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2664:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2665:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2666:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2664]], i32 [[TMP2665]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2667:%.*]] = extractvalue { i32, i1 } [[TMP2666]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2667]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2668:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2669:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2668]] release, align 4
|
|
// CHECK-NEXT: [[TMP2670:%.*]] = icmp ugt i32 [[TMP2669]], [[TMP2668]]
|
|
// CHECK-NEXT: [[TMP2671:%.*]] = select i1 [[TMP2670]], i32 [[TMP2668]], i32 [[TMP2669]]
|
|
// CHECK-NEXT: store i32 [[TMP2671]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2672:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2673:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2672]] release, align 4
|
|
// CHECK-NEXT: [[TMP2674:%.*]] = icmp ult i32 [[TMP2673]], [[TMP2672]]
|
|
// CHECK-NEXT: [[TMP2675:%.*]] = select i1 [[TMP2674]], i32 [[TMP2672]], i32 [[TMP2673]]
|
|
// CHECK-NEXT: store i32 [[TMP2675]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2676:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2677:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2676]] release, align 4
|
|
// CHECK-NEXT: [[TMP2678:%.*]] = icmp ult i32 [[TMP2677]], [[TMP2676]]
|
|
// CHECK-NEXT: [[TMP2679:%.*]] = select i1 [[TMP2678]], i32 [[TMP2676]], i32 [[TMP2677]]
|
|
// CHECK-NEXT: store i32 [[TMP2679]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2680:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2681:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2680]] release, align 4
|
|
// CHECK-NEXT: [[TMP2682:%.*]] = icmp ugt i32 [[TMP2681]], [[TMP2680]]
|
|
// CHECK-NEXT: [[TMP2683:%.*]] = select i1 [[TMP2682]], i32 [[TMP2680]], i32 [[TMP2681]]
|
|
// CHECK-NEXT: store i32 [[TMP2683]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2684:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2685:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2686:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2684]], i32 [[TMP2685]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2687:%.*]] = extractvalue { i32, i1 } [[TMP2686]], 0
|
|
// CHECK-NEXT: [[TMP2688:%.*]] = extractvalue { i32, i1 } [[TMP2686]], 1
|
|
// CHECK-NEXT: [[TMP2689:%.*]] = select i1 [[TMP2688]], i32 [[TMP2684]], i32 [[TMP2687]]
|
|
// CHECK-NEXT: store i32 [[TMP2689]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2690:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2691:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2692:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2690]], i32 [[TMP2691]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2693:%.*]] = extractvalue { i32, i1 } [[TMP2692]], 0
|
|
// CHECK-NEXT: [[TMP2694:%.*]] = extractvalue { i32, i1 } [[TMP2692]], 1
|
|
// CHECK-NEXT: [[TMP2695:%.*]] = select i1 [[TMP2694]], i32 [[TMP2690]], i32 [[TMP2693]]
|
|
// CHECK-NEXT: store i32 [[TMP2695]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2696:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2697:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2698:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2696]], i32 [[TMP2697]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2699:%.*]] = extractvalue { i32, i1 } [[TMP2698]], 0
|
|
// CHECK-NEXT: [[TMP2700:%.*]] = extractvalue { i32, i1 } [[TMP2698]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2700]], label [[UIX_ATOMIC_EXIT261:%.*]], label [[UIX_ATOMIC_CONT262:%.*]]
|
|
// CHECK: uix.atomic.cont262:
|
|
// CHECK-NEXT: store i32 [[TMP2699]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT261]]
|
|
// CHECK: uix.atomic.exit261:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2701:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2702:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2703:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2701]], i32 [[TMP2702]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2704:%.*]] = extractvalue { i32, i1 } [[TMP2703]], 0
|
|
// CHECK-NEXT: [[TMP2705:%.*]] = extractvalue { i32, i1 } [[TMP2703]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2705]], label [[UIX_ATOMIC_EXIT263:%.*]], label [[UIX_ATOMIC_CONT264:%.*]]
|
|
// CHECK: uix.atomic.cont264:
|
|
// CHECK-NEXT: store i32 [[TMP2704]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT263]]
|
|
// CHECK: uix.atomic.exit263:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2706:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2707:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2708:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2706]], i32 [[TMP2707]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2709:%.*]] = extractvalue { i32, i1 } [[TMP2708]], 1
|
|
// CHECK-NEXT: [[TMP2710:%.*]] = zext i1 [[TMP2709]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2710]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2711:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2712:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2713:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2711]], i32 [[TMP2712]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2714:%.*]] = extractvalue { i32, i1 } [[TMP2713]], 1
|
|
// CHECK-NEXT: [[TMP2715:%.*]] = zext i1 [[TMP2714]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2715]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2716:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2717:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2718:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2716]], i32 [[TMP2717]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2719:%.*]] = extractvalue { i32, i1 } [[TMP2718]], 0
|
|
// CHECK-NEXT: [[TMP2720:%.*]] = extractvalue { i32, i1 } [[TMP2718]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2720]], label [[UIX_ATOMIC_EXIT265:%.*]], label [[UIX_ATOMIC_CONT266:%.*]]
|
|
// CHECK: uix.atomic.cont266:
|
|
// CHECK-NEXT: store i32 [[TMP2719]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT265]]
|
|
// CHECK: uix.atomic.exit265:
|
|
// CHECK-NEXT: [[TMP2721:%.*]] = extractvalue { i32, i1 } [[TMP2718]], 1
|
|
// CHECK-NEXT: [[TMP2722:%.*]] = zext i1 [[TMP2721]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2722]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2723:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2724:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2725:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2723]], i32 [[TMP2724]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP2726:%.*]] = extractvalue { i32, i1 } [[TMP2725]], 0
|
|
// CHECK-NEXT: [[TMP2727:%.*]] = extractvalue { i32, i1 } [[TMP2725]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2727]], label [[UIX_ATOMIC_EXIT267:%.*]], label [[UIX_ATOMIC_CONT268:%.*]]
|
|
// CHECK: uix.atomic.cont268:
|
|
// CHECK-NEXT: store i32 [[TMP2726]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT267]]
|
|
// CHECK: uix.atomic.exit267:
|
|
// CHECK-NEXT: [[TMP2728:%.*]] = extractvalue { i32, i1 } [[TMP2725]], 1
|
|
// CHECK-NEXT: [[TMP2729:%.*]] = zext i1 [[TMP2728]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2729]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2730:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2731:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2730]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2731]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2732:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2733:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2732]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2733]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2734:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2735:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2734]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2735]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2736:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2737:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2736]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP2737]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2738:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2739:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2740:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2738]], i32 [[TMP2739]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2741:%.*]] = extractvalue { i32, i1 } [[TMP2740]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2741]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2742:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2743:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2744:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2742]], i32 [[TMP2743]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2745:%.*]] = extractvalue { i32, i1 } [[TMP2744]], 0
|
|
// CHECK-NEXT: store i32 [[TMP2745]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2746:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2747:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2746]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2748:%.*]] = icmp ugt i32 [[TMP2747]], [[TMP2746]]
|
|
// CHECK-NEXT: [[TMP2749:%.*]] = select i1 [[TMP2748]], i32 [[TMP2746]], i32 [[TMP2747]]
|
|
// CHECK-NEXT: store i32 [[TMP2749]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2750:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2751:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2750]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2752:%.*]] = icmp ult i32 [[TMP2751]], [[TMP2750]]
|
|
// CHECK-NEXT: [[TMP2753:%.*]] = select i1 [[TMP2752]], i32 [[TMP2750]], i32 [[TMP2751]]
|
|
// CHECK-NEXT: store i32 [[TMP2753]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2754:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2755:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2754]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2756:%.*]] = icmp ult i32 [[TMP2755]], [[TMP2754]]
|
|
// CHECK-NEXT: [[TMP2757:%.*]] = select i1 [[TMP2756]], i32 [[TMP2754]], i32 [[TMP2755]]
|
|
// CHECK-NEXT: store i32 [[TMP2757]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2758:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2759:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2758]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2760:%.*]] = icmp ugt i32 [[TMP2759]], [[TMP2758]]
|
|
// CHECK-NEXT: [[TMP2761:%.*]] = select i1 [[TMP2760]], i32 [[TMP2758]], i32 [[TMP2759]]
|
|
// CHECK-NEXT: store i32 [[TMP2761]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2762:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2763:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2764:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2762]], i32 [[TMP2763]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2765:%.*]] = extractvalue { i32, i1 } [[TMP2764]], 0
|
|
// CHECK-NEXT: [[TMP2766:%.*]] = extractvalue { i32, i1 } [[TMP2764]], 1
|
|
// CHECK-NEXT: [[TMP2767:%.*]] = select i1 [[TMP2766]], i32 [[TMP2762]], i32 [[TMP2765]]
|
|
// CHECK-NEXT: store i32 [[TMP2767]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2768:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2769:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2770:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2768]], i32 [[TMP2769]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2771:%.*]] = extractvalue { i32, i1 } [[TMP2770]], 0
|
|
// CHECK-NEXT: [[TMP2772:%.*]] = extractvalue { i32, i1 } [[TMP2770]], 1
|
|
// CHECK-NEXT: [[TMP2773:%.*]] = select i1 [[TMP2772]], i32 [[TMP2768]], i32 [[TMP2771]]
|
|
// CHECK-NEXT: store i32 [[TMP2773]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2774:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2775:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2776:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2774]], i32 [[TMP2775]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2777:%.*]] = extractvalue { i32, i1 } [[TMP2776]], 0
|
|
// CHECK-NEXT: [[TMP2778:%.*]] = extractvalue { i32, i1 } [[TMP2776]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2778]], label [[UIX_ATOMIC_EXIT269:%.*]], label [[UIX_ATOMIC_CONT270:%.*]]
|
|
// CHECK: uix.atomic.cont270:
|
|
// CHECK-NEXT: store i32 [[TMP2777]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT269]]
|
|
// CHECK: uix.atomic.exit269:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2779:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2780:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2781:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2779]], i32 [[TMP2780]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2782:%.*]] = extractvalue { i32, i1 } [[TMP2781]], 0
|
|
// CHECK-NEXT: [[TMP2783:%.*]] = extractvalue { i32, i1 } [[TMP2781]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2783]], label [[UIX_ATOMIC_EXIT271:%.*]], label [[UIX_ATOMIC_CONT272:%.*]]
|
|
// CHECK: uix.atomic.cont272:
|
|
// CHECK-NEXT: store i32 [[TMP2782]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT271]]
|
|
// CHECK: uix.atomic.exit271:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2784:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2785:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2786:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2784]], i32 [[TMP2785]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2787:%.*]] = extractvalue { i32, i1 } [[TMP2786]], 1
|
|
// CHECK-NEXT: [[TMP2788:%.*]] = zext i1 [[TMP2787]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2788]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2789:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2790:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2791:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2789]], i32 [[TMP2790]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2792:%.*]] = extractvalue { i32, i1 } [[TMP2791]], 1
|
|
// CHECK-NEXT: [[TMP2793:%.*]] = zext i1 [[TMP2792]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2793]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2794:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2795:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2796:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2794]], i32 [[TMP2795]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2797:%.*]] = extractvalue { i32, i1 } [[TMP2796]], 0
|
|
// CHECK-NEXT: [[TMP2798:%.*]] = extractvalue { i32, i1 } [[TMP2796]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2798]], label [[UIX_ATOMIC_EXIT273:%.*]], label [[UIX_ATOMIC_CONT274:%.*]]
|
|
// CHECK: uix.atomic.cont274:
|
|
// CHECK-NEXT: store i32 [[TMP2797]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT273]]
|
|
// CHECK: uix.atomic.exit273:
|
|
// CHECK-NEXT: [[TMP2799:%.*]] = extractvalue { i32, i1 } [[TMP2796]], 1
|
|
// CHECK-NEXT: [[TMP2800:%.*]] = zext i1 [[TMP2799]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2800]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2801:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP2802:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP2803:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2801]], i32 [[TMP2802]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP2804:%.*]] = extractvalue { i32, i1 } [[TMP2803]], 0
|
|
// CHECK-NEXT: [[TMP2805:%.*]] = extractvalue { i32, i1 } [[TMP2803]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2805]], label [[UIX_ATOMIC_EXIT275:%.*]], label [[UIX_ATOMIC_CONT276:%.*]]
|
|
// CHECK: uix.atomic.cont276:
|
|
// CHECK-NEXT: store i32 [[TMP2804]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT275]]
|
|
// CHECK: uix.atomic.exit275:
|
|
// CHECK-NEXT: [[TMP2806:%.*]] = extractvalue { i32, i1 } [[TMP2803]], 1
|
|
// CHECK-NEXT: [[TMP2807:%.*]] = zext i1 [[TMP2806]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP2807]], ptr [[UIR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2808:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2809:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2808]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2809]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2810:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2811:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2810]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2811]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2812:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2813:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2812]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2813]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2814:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2815:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2814]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2815]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2816:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2817:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2818:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2816]], i64 [[TMP2817]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2819:%.*]] = extractvalue { i64, i1 } [[TMP2818]], 0
|
|
// CHECK-NEXT: store i64 [[TMP2819]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2820:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2821:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2822:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2820]], i64 [[TMP2821]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2823:%.*]] = extractvalue { i64, i1 } [[TMP2822]], 0
|
|
// CHECK-NEXT: store i64 [[TMP2823]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2824:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2825:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2824]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2826:%.*]] = icmp sgt i64 [[TMP2825]], [[TMP2824]]
|
|
// CHECK-NEXT: [[TMP2827:%.*]] = select i1 [[TMP2826]], i64 [[TMP2824]], i64 [[TMP2825]]
|
|
// CHECK-NEXT: store i64 [[TMP2827]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2828:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2829:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2828]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2830:%.*]] = icmp slt i64 [[TMP2829]], [[TMP2828]]
|
|
// CHECK-NEXT: [[TMP2831:%.*]] = select i1 [[TMP2830]], i64 [[TMP2828]], i64 [[TMP2829]]
|
|
// CHECK-NEXT: store i64 [[TMP2831]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2832:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2833:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2832]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2834:%.*]] = icmp slt i64 [[TMP2833]], [[TMP2832]]
|
|
// CHECK-NEXT: [[TMP2835:%.*]] = select i1 [[TMP2834]], i64 [[TMP2832]], i64 [[TMP2833]]
|
|
// CHECK-NEXT: store i64 [[TMP2835]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2836:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2837:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2836]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2838:%.*]] = icmp sgt i64 [[TMP2837]], [[TMP2836]]
|
|
// CHECK-NEXT: [[TMP2839:%.*]] = select i1 [[TMP2838]], i64 [[TMP2836]], i64 [[TMP2837]]
|
|
// CHECK-NEXT: store i64 [[TMP2839]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2840:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2841:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2842:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2840]], i64 [[TMP2841]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2843:%.*]] = extractvalue { i64, i1 } [[TMP2842]], 0
|
|
// CHECK-NEXT: [[TMP2844:%.*]] = extractvalue { i64, i1 } [[TMP2842]], 1
|
|
// CHECK-NEXT: [[TMP2845:%.*]] = select i1 [[TMP2844]], i64 [[TMP2840]], i64 [[TMP2843]]
|
|
// CHECK-NEXT: store i64 [[TMP2845]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2846:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2847:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2848:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2846]], i64 [[TMP2847]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2849:%.*]] = extractvalue { i64, i1 } [[TMP2848]], 0
|
|
// CHECK-NEXT: [[TMP2850:%.*]] = extractvalue { i64, i1 } [[TMP2848]], 1
|
|
// CHECK-NEXT: [[TMP2851:%.*]] = select i1 [[TMP2850]], i64 [[TMP2846]], i64 [[TMP2849]]
|
|
// CHECK-NEXT: store i64 [[TMP2851]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2852:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2853:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2854:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2852]], i64 [[TMP2853]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2855:%.*]] = extractvalue { i64, i1 } [[TMP2854]], 0
|
|
// CHECK-NEXT: [[TMP2856:%.*]] = extractvalue { i64, i1 } [[TMP2854]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2856]], label [[LX_ATOMIC_EXIT:%.*]], label [[LX_ATOMIC_CONT:%.*]]
|
|
// CHECK: lx.atomic.cont:
|
|
// CHECK-NEXT: store i64 [[TMP2855]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT]]
|
|
// CHECK: lx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP2857:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2858:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2859:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2857]], i64 [[TMP2858]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2860:%.*]] = extractvalue { i64, i1 } [[TMP2859]], 0
|
|
// CHECK-NEXT: [[TMP2861:%.*]] = extractvalue { i64, i1 } [[TMP2859]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2861]], label [[LX_ATOMIC_EXIT277:%.*]], label [[LX_ATOMIC_CONT278:%.*]]
|
|
// CHECK: lx.atomic.cont278:
|
|
// CHECK-NEXT: store i64 [[TMP2860]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT277]]
|
|
// CHECK: lx.atomic.exit277:
|
|
// CHECK-NEXT: [[TMP2862:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2863:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2864:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2862]], i64 [[TMP2863]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2865:%.*]] = extractvalue { i64, i1 } [[TMP2864]], 1
|
|
// CHECK-NEXT: [[TMP2866:%.*]] = sext i1 [[TMP2865]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP2866]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP2867:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2868:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2869:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2867]], i64 [[TMP2868]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2870:%.*]] = extractvalue { i64, i1 } [[TMP2869]], 1
|
|
// CHECK-NEXT: [[TMP2871:%.*]] = sext i1 [[TMP2870]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP2871]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP2872:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2873:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2874:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2872]], i64 [[TMP2873]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2875:%.*]] = extractvalue { i64, i1 } [[TMP2874]], 0
|
|
// CHECK-NEXT: [[TMP2876:%.*]] = extractvalue { i64, i1 } [[TMP2874]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2876]], label [[LX_ATOMIC_EXIT279:%.*]], label [[LX_ATOMIC_CONT280:%.*]]
|
|
// CHECK: lx.atomic.cont280:
|
|
// CHECK-NEXT: store i64 [[TMP2875]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT279]]
|
|
// CHECK: lx.atomic.exit279:
|
|
// CHECK-NEXT: [[TMP2877:%.*]] = extractvalue { i64, i1 } [[TMP2874]], 1
|
|
// CHECK-NEXT: [[TMP2878:%.*]] = sext i1 [[TMP2877]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP2878]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP2879:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2880:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2881:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2879]], i64 [[TMP2880]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP2882:%.*]] = extractvalue { i64, i1 } [[TMP2881]], 0
|
|
// CHECK-NEXT: [[TMP2883:%.*]] = extractvalue { i64, i1 } [[TMP2881]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2883]], label [[LX_ATOMIC_EXIT281:%.*]], label [[LX_ATOMIC_CONT282:%.*]]
|
|
// CHECK: lx.atomic.cont282:
|
|
// CHECK-NEXT: store i64 [[TMP2882]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT281]]
|
|
// CHECK: lx.atomic.exit281:
|
|
// CHECK-NEXT: [[TMP2884:%.*]] = extractvalue { i64, i1 } [[TMP2881]], 1
|
|
// CHECK-NEXT: [[TMP2885:%.*]] = sext i1 [[TMP2884]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP2885]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP2886:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2887:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2886]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2887]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2888:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2889:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2888]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2889]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2890:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2891:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2890]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2891]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2892:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2893:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2892]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2893]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2894:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2895:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2896:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2894]], i64 [[TMP2895]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2897:%.*]] = extractvalue { i64, i1 } [[TMP2896]], 0
|
|
// CHECK-NEXT: store i64 [[TMP2897]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2898:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2899:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2900:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2898]], i64 [[TMP2899]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2901:%.*]] = extractvalue { i64, i1 } [[TMP2900]], 0
|
|
// CHECK-NEXT: store i64 [[TMP2901]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2902:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2903:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2902]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP2904:%.*]] = icmp sgt i64 [[TMP2903]], [[TMP2902]]
|
|
// CHECK-NEXT: [[TMP2905:%.*]] = select i1 [[TMP2904]], i64 [[TMP2902]], i64 [[TMP2903]]
|
|
// CHECK-NEXT: store i64 [[TMP2905]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2906:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2907:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2906]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP2908:%.*]] = icmp slt i64 [[TMP2907]], [[TMP2906]]
|
|
// CHECK-NEXT: [[TMP2909:%.*]] = select i1 [[TMP2908]], i64 [[TMP2906]], i64 [[TMP2907]]
|
|
// CHECK-NEXT: store i64 [[TMP2909]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2910:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2911:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2910]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP2912:%.*]] = icmp slt i64 [[TMP2911]], [[TMP2910]]
|
|
// CHECK-NEXT: [[TMP2913:%.*]] = select i1 [[TMP2912]], i64 [[TMP2910]], i64 [[TMP2911]]
|
|
// CHECK-NEXT: store i64 [[TMP2913]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2914:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2915:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2914]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP2916:%.*]] = icmp sgt i64 [[TMP2915]], [[TMP2914]]
|
|
// CHECK-NEXT: [[TMP2917:%.*]] = select i1 [[TMP2916]], i64 [[TMP2914]], i64 [[TMP2915]]
|
|
// CHECK-NEXT: store i64 [[TMP2917]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2918:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2919:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2920:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2918]], i64 [[TMP2919]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2921:%.*]] = extractvalue { i64, i1 } [[TMP2920]], 0
|
|
// CHECK-NEXT: [[TMP2922:%.*]] = extractvalue { i64, i1 } [[TMP2920]], 1
|
|
// CHECK-NEXT: [[TMP2923:%.*]] = select i1 [[TMP2922]], i64 [[TMP2918]], i64 [[TMP2921]]
|
|
// CHECK-NEXT: store i64 [[TMP2923]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2924:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2925:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2926:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2924]], i64 [[TMP2925]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2927:%.*]] = extractvalue { i64, i1 } [[TMP2926]], 0
|
|
// CHECK-NEXT: [[TMP2928:%.*]] = extractvalue { i64, i1 } [[TMP2926]], 1
|
|
// CHECK-NEXT: [[TMP2929:%.*]] = select i1 [[TMP2928]], i64 [[TMP2924]], i64 [[TMP2927]]
|
|
// CHECK-NEXT: store i64 [[TMP2929]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2930:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2931:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2932:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2930]], i64 [[TMP2931]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2933:%.*]] = extractvalue { i64, i1 } [[TMP2932]], 0
|
|
// CHECK-NEXT: [[TMP2934:%.*]] = extractvalue { i64, i1 } [[TMP2932]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2934]], label [[LX_ATOMIC_EXIT283:%.*]], label [[LX_ATOMIC_CONT284:%.*]]
|
|
// CHECK: lx.atomic.cont284:
|
|
// CHECK-NEXT: store i64 [[TMP2933]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT283]]
|
|
// CHECK: lx.atomic.exit283:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2935:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2936:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2937:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2935]], i64 [[TMP2936]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2938:%.*]] = extractvalue { i64, i1 } [[TMP2937]], 0
|
|
// CHECK-NEXT: [[TMP2939:%.*]] = extractvalue { i64, i1 } [[TMP2937]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2939]], label [[LX_ATOMIC_EXIT285:%.*]], label [[LX_ATOMIC_CONT286:%.*]]
|
|
// CHECK: lx.atomic.cont286:
|
|
// CHECK-NEXT: store i64 [[TMP2938]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT285]]
|
|
// CHECK: lx.atomic.exit285:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2940:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2941:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2942:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2940]], i64 [[TMP2941]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2943:%.*]] = extractvalue { i64, i1 } [[TMP2942]], 1
|
|
// CHECK-NEXT: [[TMP2944:%.*]] = sext i1 [[TMP2943]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP2944]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2945:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2946:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2947:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2945]], i64 [[TMP2946]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2948:%.*]] = extractvalue { i64, i1 } [[TMP2947]], 1
|
|
// CHECK-NEXT: [[TMP2949:%.*]] = sext i1 [[TMP2948]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP2949]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2950:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2951:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2952:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2950]], i64 [[TMP2951]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2953:%.*]] = extractvalue { i64, i1 } [[TMP2952]], 0
|
|
// CHECK-NEXT: [[TMP2954:%.*]] = extractvalue { i64, i1 } [[TMP2952]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2954]], label [[LX_ATOMIC_EXIT287:%.*]], label [[LX_ATOMIC_CONT288:%.*]]
|
|
// CHECK: lx.atomic.cont288:
|
|
// CHECK-NEXT: store i64 [[TMP2953]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT287]]
|
|
// CHECK: lx.atomic.exit287:
|
|
// CHECK-NEXT: [[TMP2955:%.*]] = extractvalue { i64, i1 } [[TMP2952]], 1
|
|
// CHECK-NEXT: [[TMP2956:%.*]] = sext i1 [[TMP2955]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP2956]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2957:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2958:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2959:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2957]], i64 [[TMP2958]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP2960:%.*]] = extractvalue { i64, i1 } [[TMP2959]], 0
|
|
// CHECK-NEXT: [[TMP2961:%.*]] = extractvalue { i64, i1 } [[TMP2959]], 1
|
|
// CHECK-NEXT: br i1 [[TMP2961]], label [[LX_ATOMIC_EXIT289:%.*]], label [[LX_ATOMIC_CONT290:%.*]]
|
|
// CHECK: lx.atomic.cont290:
|
|
// CHECK-NEXT: store i64 [[TMP2960]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT289]]
|
|
// CHECK: lx.atomic.exit289:
|
|
// CHECK-NEXT: [[TMP2962:%.*]] = extractvalue { i64, i1 } [[TMP2959]], 1
|
|
// CHECK-NEXT: [[TMP2963:%.*]] = sext i1 [[TMP2962]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP2963]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP2964:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2965:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2964]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2965]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2966:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2967:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2966]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2967]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2968:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2969:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2968]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2969]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2970:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2971:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2970]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP2971]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2972:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2973:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2974:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2972]], i64 [[TMP2973]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP2975:%.*]] = extractvalue { i64, i1 } [[TMP2974]], 0
|
|
// CHECK-NEXT: store i64 [[TMP2975]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2976:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2977:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2978:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2976]], i64 [[TMP2977]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP2979:%.*]] = extractvalue { i64, i1 } [[TMP2978]], 0
|
|
// CHECK-NEXT: store i64 [[TMP2979]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2980:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2981:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2980]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP2982:%.*]] = icmp sgt i64 [[TMP2981]], [[TMP2980]]
|
|
// CHECK-NEXT: [[TMP2983:%.*]] = select i1 [[TMP2982]], i64 [[TMP2980]], i64 [[TMP2981]]
|
|
// CHECK-NEXT: store i64 [[TMP2983]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2984:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2985:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2984]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP2986:%.*]] = icmp slt i64 [[TMP2985]], [[TMP2984]]
|
|
// CHECK-NEXT: [[TMP2987:%.*]] = select i1 [[TMP2986]], i64 [[TMP2984]], i64 [[TMP2985]]
|
|
// CHECK-NEXT: store i64 [[TMP2987]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2988:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2989:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2988]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP2990:%.*]] = icmp slt i64 [[TMP2989]], [[TMP2988]]
|
|
// CHECK-NEXT: [[TMP2991:%.*]] = select i1 [[TMP2990]], i64 [[TMP2988]], i64 [[TMP2989]]
|
|
// CHECK-NEXT: store i64 [[TMP2991]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2992:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2993:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2992]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP2994:%.*]] = icmp sgt i64 [[TMP2993]], [[TMP2992]]
|
|
// CHECK-NEXT: [[TMP2995:%.*]] = select i1 [[TMP2994]], i64 [[TMP2992]], i64 [[TMP2993]]
|
|
// CHECK-NEXT: store i64 [[TMP2995]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2996:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP2997:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP2998:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2996]], i64 [[TMP2997]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP2999:%.*]] = extractvalue { i64, i1 } [[TMP2998]], 0
|
|
// CHECK-NEXT: [[TMP3000:%.*]] = extractvalue { i64, i1 } [[TMP2998]], 1
|
|
// CHECK-NEXT: [[TMP3001:%.*]] = select i1 [[TMP3000]], i64 [[TMP2996]], i64 [[TMP2999]]
|
|
// CHECK-NEXT: store i64 [[TMP3001]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3002:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3003:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3004:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3002]], i64 [[TMP3003]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3005:%.*]] = extractvalue { i64, i1 } [[TMP3004]], 0
|
|
// CHECK-NEXT: [[TMP3006:%.*]] = extractvalue { i64, i1 } [[TMP3004]], 1
|
|
// CHECK-NEXT: [[TMP3007:%.*]] = select i1 [[TMP3006]], i64 [[TMP3002]], i64 [[TMP3005]]
|
|
// CHECK-NEXT: store i64 [[TMP3007]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3008:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3009:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3010:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3008]], i64 [[TMP3009]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3011:%.*]] = extractvalue { i64, i1 } [[TMP3010]], 0
|
|
// CHECK-NEXT: [[TMP3012:%.*]] = extractvalue { i64, i1 } [[TMP3010]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3012]], label [[LX_ATOMIC_EXIT291:%.*]], label [[LX_ATOMIC_CONT292:%.*]]
|
|
// CHECK: lx.atomic.cont292:
|
|
// CHECK-NEXT: store i64 [[TMP3011]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT291]]
|
|
// CHECK: lx.atomic.exit291:
|
|
// CHECK-NEXT: [[TMP3013:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3014:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3015:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3013]], i64 [[TMP3014]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3016:%.*]] = extractvalue { i64, i1 } [[TMP3015]], 0
|
|
// CHECK-NEXT: [[TMP3017:%.*]] = extractvalue { i64, i1 } [[TMP3015]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3017]], label [[LX_ATOMIC_EXIT293:%.*]], label [[LX_ATOMIC_CONT294:%.*]]
|
|
// CHECK: lx.atomic.cont294:
|
|
// CHECK-NEXT: store i64 [[TMP3016]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT293]]
|
|
// CHECK: lx.atomic.exit293:
|
|
// CHECK-NEXT: [[TMP3018:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3019:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3020:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3018]], i64 [[TMP3019]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3021:%.*]] = extractvalue { i64, i1 } [[TMP3020]], 1
|
|
// CHECK-NEXT: [[TMP3022:%.*]] = sext i1 [[TMP3021]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3022]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP3023:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3024:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3025:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3023]], i64 [[TMP3024]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3026:%.*]] = extractvalue { i64, i1 } [[TMP3025]], 1
|
|
// CHECK-NEXT: [[TMP3027:%.*]] = sext i1 [[TMP3026]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3027]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP3028:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3029:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3030:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3028]], i64 [[TMP3029]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3031:%.*]] = extractvalue { i64, i1 } [[TMP3030]], 0
|
|
// CHECK-NEXT: [[TMP3032:%.*]] = extractvalue { i64, i1 } [[TMP3030]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3032]], label [[LX_ATOMIC_EXIT295:%.*]], label [[LX_ATOMIC_CONT296:%.*]]
|
|
// CHECK: lx.atomic.cont296:
|
|
// CHECK-NEXT: store i64 [[TMP3031]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT295]]
|
|
// CHECK: lx.atomic.exit295:
|
|
// CHECK-NEXT: [[TMP3033:%.*]] = extractvalue { i64, i1 } [[TMP3030]], 1
|
|
// CHECK-NEXT: [[TMP3034:%.*]] = sext i1 [[TMP3033]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3034]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP3035:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3036:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3037:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3035]], i64 [[TMP3036]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3038:%.*]] = extractvalue { i64, i1 } [[TMP3037]], 0
|
|
// CHECK-NEXT: [[TMP3039:%.*]] = extractvalue { i64, i1 } [[TMP3037]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3039]], label [[LX_ATOMIC_EXIT297:%.*]], label [[LX_ATOMIC_CONT298:%.*]]
|
|
// CHECK: lx.atomic.cont298:
|
|
// CHECK-NEXT: store i64 [[TMP3038]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT297]]
|
|
// CHECK: lx.atomic.exit297:
|
|
// CHECK-NEXT: [[TMP3040:%.*]] = extractvalue { i64, i1 } [[TMP3037]], 1
|
|
// CHECK-NEXT: [[TMP3041:%.*]] = sext i1 [[TMP3040]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3041]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP3042:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3043:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3042]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3043]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3044:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3045:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3044]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3045]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3046:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3047:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3046]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3047]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3048:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3049:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3048]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3049]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3050:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3051:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3052:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3050]], i64 [[TMP3051]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3053:%.*]] = extractvalue { i64, i1 } [[TMP3052]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3053]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3054:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3055:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3056:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3054]], i64 [[TMP3055]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3057:%.*]] = extractvalue { i64, i1 } [[TMP3056]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3057]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3058:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3059:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3058]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3060:%.*]] = icmp sgt i64 [[TMP3059]], [[TMP3058]]
|
|
// CHECK-NEXT: [[TMP3061:%.*]] = select i1 [[TMP3060]], i64 [[TMP3058]], i64 [[TMP3059]]
|
|
// CHECK-NEXT: store i64 [[TMP3061]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3062:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3063:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3062]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3064:%.*]] = icmp slt i64 [[TMP3063]], [[TMP3062]]
|
|
// CHECK-NEXT: [[TMP3065:%.*]] = select i1 [[TMP3064]], i64 [[TMP3062]], i64 [[TMP3063]]
|
|
// CHECK-NEXT: store i64 [[TMP3065]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3066:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3067:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3066]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3068:%.*]] = icmp slt i64 [[TMP3067]], [[TMP3066]]
|
|
// CHECK-NEXT: [[TMP3069:%.*]] = select i1 [[TMP3068]], i64 [[TMP3066]], i64 [[TMP3067]]
|
|
// CHECK-NEXT: store i64 [[TMP3069]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3070:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3071:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3070]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3072:%.*]] = icmp sgt i64 [[TMP3071]], [[TMP3070]]
|
|
// CHECK-NEXT: [[TMP3073:%.*]] = select i1 [[TMP3072]], i64 [[TMP3070]], i64 [[TMP3071]]
|
|
// CHECK-NEXT: store i64 [[TMP3073]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3074:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3075:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3076:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3074]], i64 [[TMP3075]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3077:%.*]] = extractvalue { i64, i1 } [[TMP3076]], 0
|
|
// CHECK-NEXT: [[TMP3078:%.*]] = extractvalue { i64, i1 } [[TMP3076]], 1
|
|
// CHECK-NEXT: [[TMP3079:%.*]] = select i1 [[TMP3078]], i64 [[TMP3074]], i64 [[TMP3077]]
|
|
// CHECK-NEXT: store i64 [[TMP3079]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3080:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3081:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3082:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3080]], i64 [[TMP3081]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3083:%.*]] = extractvalue { i64, i1 } [[TMP3082]], 0
|
|
// CHECK-NEXT: [[TMP3084:%.*]] = extractvalue { i64, i1 } [[TMP3082]], 1
|
|
// CHECK-NEXT: [[TMP3085:%.*]] = select i1 [[TMP3084]], i64 [[TMP3080]], i64 [[TMP3083]]
|
|
// CHECK-NEXT: store i64 [[TMP3085]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP3086:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3087:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3088:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3086]], i64 [[TMP3087]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3089:%.*]] = extractvalue { i64, i1 } [[TMP3088]], 0
|
|
// CHECK-NEXT: [[TMP3090:%.*]] = extractvalue { i64, i1 } [[TMP3088]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3090]], label [[LX_ATOMIC_EXIT299:%.*]], label [[LX_ATOMIC_CONT300:%.*]]
|
|
// CHECK: lx.atomic.cont300:
|
|
// CHECK-NEXT: store i64 [[TMP3089]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT299]]
|
|
// CHECK: lx.atomic.exit299:
|
|
// CHECK-NEXT: [[TMP3091:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3092:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3093:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3091]], i64 [[TMP3092]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3094:%.*]] = extractvalue { i64, i1 } [[TMP3093]], 0
|
|
// CHECK-NEXT: [[TMP3095:%.*]] = extractvalue { i64, i1 } [[TMP3093]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3095]], label [[LX_ATOMIC_EXIT301:%.*]], label [[LX_ATOMIC_CONT302:%.*]]
|
|
// CHECK: lx.atomic.cont302:
|
|
// CHECK-NEXT: store i64 [[TMP3094]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT301]]
|
|
// CHECK: lx.atomic.exit301:
|
|
// CHECK-NEXT: [[TMP3096:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3097:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3098:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3096]], i64 [[TMP3097]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3099:%.*]] = extractvalue { i64, i1 } [[TMP3098]], 1
|
|
// CHECK-NEXT: [[TMP3100:%.*]] = sext i1 [[TMP3099]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3100]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP3101:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3102:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3103:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3101]], i64 [[TMP3102]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3104:%.*]] = extractvalue { i64, i1 } [[TMP3103]], 1
|
|
// CHECK-NEXT: [[TMP3105:%.*]] = sext i1 [[TMP3104]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3105]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP3106:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3107:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3108:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3106]], i64 [[TMP3107]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3109:%.*]] = extractvalue { i64, i1 } [[TMP3108]], 0
|
|
// CHECK-NEXT: [[TMP3110:%.*]] = extractvalue { i64, i1 } [[TMP3108]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3110]], label [[LX_ATOMIC_EXIT303:%.*]], label [[LX_ATOMIC_CONT304:%.*]]
|
|
// CHECK: lx.atomic.cont304:
|
|
// CHECK-NEXT: store i64 [[TMP3109]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT303]]
|
|
// CHECK: lx.atomic.exit303:
|
|
// CHECK-NEXT: [[TMP3111:%.*]] = extractvalue { i64, i1 } [[TMP3108]], 1
|
|
// CHECK-NEXT: [[TMP3112:%.*]] = sext i1 [[TMP3111]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3112]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP3113:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3114:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3115:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3113]], i64 [[TMP3114]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3116:%.*]] = extractvalue { i64, i1 } [[TMP3115]], 0
|
|
// CHECK-NEXT: [[TMP3117:%.*]] = extractvalue { i64, i1 } [[TMP3115]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3117]], label [[LX_ATOMIC_EXIT305:%.*]], label [[LX_ATOMIC_CONT306:%.*]]
|
|
// CHECK: lx.atomic.cont306:
|
|
// CHECK-NEXT: store i64 [[TMP3116]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT305]]
|
|
// CHECK: lx.atomic.exit305:
|
|
// CHECK-NEXT: [[TMP3118:%.*]] = extractvalue { i64, i1 } [[TMP3115]], 1
|
|
// CHECK-NEXT: [[TMP3119:%.*]] = sext i1 [[TMP3118]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3119]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: [[TMP3120:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3121:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3120]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3121]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3122:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3123:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3122]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3123]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3124:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3125:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3124]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3125]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3126:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3127:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3126]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3127]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3128:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3129:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3130:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3128]], i64 [[TMP3129]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3131:%.*]] = extractvalue { i64, i1 } [[TMP3130]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3131]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3132:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3133:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3134:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3132]], i64 [[TMP3133]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3135:%.*]] = extractvalue { i64, i1 } [[TMP3134]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3135]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3136:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3137:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3136]] release, align 8
|
|
// CHECK-NEXT: [[TMP3138:%.*]] = icmp sgt i64 [[TMP3137]], [[TMP3136]]
|
|
// CHECK-NEXT: [[TMP3139:%.*]] = select i1 [[TMP3138]], i64 [[TMP3136]], i64 [[TMP3137]]
|
|
// CHECK-NEXT: store i64 [[TMP3139]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3140:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3141:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3140]] release, align 8
|
|
// CHECK-NEXT: [[TMP3142:%.*]] = icmp slt i64 [[TMP3141]], [[TMP3140]]
|
|
// CHECK-NEXT: [[TMP3143:%.*]] = select i1 [[TMP3142]], i64 [[TMP3140]], i64 [[TMP3141]]
|
|
// CHECK-NEXT: store i64 [[TMP3143]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3144:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3145:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3144]] release, align 8
|
|
// CHECK-NEXT: [[TMP3146:%.*]] = icmp slt i64 [[TMP3145]], [[TMP3144]]
|
|
// CHECK-NEXT: [[TMP3147:%.*]] = select i1 [[TMP3146]], i64 [[TMP3144]], i64 [[TMP3145]]
|
|
// CHECK-NEXT: store i64 [[TMP3147]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3148:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3149:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3148]] release, align 8
|
|
// CHECK-NEXT: [[TMP3150:%.*]] = icmp sgt i64 [[TMP3149]], [[TMP3148]]
|
|
// CHECK-NEXT: [[TMP3151:%.*]] = select i1 [[TMP3150]], i64 [[TMP3148]], i64 [[TMP3149]]
|
|
// CHECK-NEXT: store i64 [[TMP3151]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3152:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3153:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3154:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3152]], i64 [[TMP3153]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3155:%.*]] = extractvalue { i64, i1 } [[TMP3154]], 0
|
|
// CHECK-NEXT: [[TMP3156:%.*]] = extractvalue { i64, i1 } [[TMP3154]], 1
|
|
// CHECK-NEXT: [[TMP3157:%.*]] = select i1 [[TMP3156]], i64 [[TMP3152]], i64 [[TMP3155]]
|
|
// CHECK-NEXT: store i64 [[TMP3157]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3158:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3159:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3160:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3158]], i64 [[TMP3159]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3161:%.*]] = extractvalue { i64, i1 } [[TMP3160]], 0
|
|
// CHECK-NEXT: [[TMP3162:%.*]] = extractvalue { i64, i1 } [[TMP3160]], 1
|
|
// CHECK-NEXT: [[TMP3163:%.*]] = select i1 [[TMP3162]], i64 [[TMP3158]], i64 [[TMP3161]]
|
|
// CHECK-NEXT: store i64 [[TMP3163]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3164:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3165:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3166:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3164]], i64 [[TMP3165]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3167:%.*]] = extractvalue { i64, i1 } [[TMP3166]], 0
|
|
// CHECK-NEXT: [[TMP3168:%.*]] = extractvalue { i64, i1 } [[TMP3166]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3168]], label [[LX_ATOMIC_EXIT307:%.*]], label [[LX_ATOMIC_CONT308:%.*]]
|
|
// CHECK: lx.atomic.cont308:
|
|
// CHECK-NEXT: store i64 [[TMP3167]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT307]]
|
|
// CHECK: lx.atomic.exit307:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3169:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3170:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3171:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3169]], i64 [[TMP3170]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3172:%.*]] = extractvalue { i64, i1 } [[TMP3171]], 0
|
|
// CHECK-NEXT: [[TMP3173:%.*]] = extractvalue { i64, i1 } [[TMP3171]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3173]], label [[LX_ATOMIC_EXIT309:%.*]], label [[LX_ATOMIC_CONT310:%.*]]
|
|
// CHECK: lx.atomic.cont310:
|
|
// CHECK-NEXT: store i64 [[TMP3172]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT309]]
|
|
// CHECK: lx.atomic.exit309:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3174:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3175:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3176:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3174]], i64 [[TMP3175]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3177:%.*]] = extractvalue { i64, i1 } [[TMP3176]], 1
|
|
// CHECK-NEXT: [[TMP3178:%.*]] = sext i1 [[TMP3177]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3178]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3179:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3180:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3181:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3179]], i64 [[TMP3180]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3182:%.*]] = extractvalue { i64, i1 } [[TMP3181]], 1
|
|
// CHECK-NEXT: [[TMP3183:%.*]] = sext i1 [[TMP3182]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3183]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3184:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3185:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3186:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3184]], i64 [[TMP3185]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3187:%.*]] = extractvalue { i64, i1 } [[TMP3186]], 0
|
|
// CHECK-NEXT: [[TMP3188:%.*]] = extractvalue { i64, i1 } [[TMP3186]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3188]], label [[LX_ATOMIC_EXIT311:%.*]], label [[LX_ATOMIC_CONT312:%.*]]
|
|
// CHECK: lx.atomic.cont312:
|
|
// CHECK-NEXT: store i64 [[TMP3187]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT311]]
|
|
// CHECK: lx.atomic.exit311:
|
|
// CHECK-NEXT: [[TMP3189:%.*]] = extractvalue { i64, i1 } [[TMP3186]], 1
|
|
// CHECK-NEXT: [[TMP3190:%.*]] = sext i1 [[TMP3189]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3190]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3191:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3192:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3193:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3191]], i64 [[TMP3192]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3194:%.*]] = extractvalue { i64, i1 } [[TMP3193]], 0
|
|
// CHECK-NEXT: [[TMP3195:%.*]] = extractvalue { i64, i1 } [[TMP3193]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3195]], label [[LX_ATOMIC_EXIT313:%.*]], label [[LX_ATOMIC_CONT314:%.*]]
|
|
// CHECK: lx.atomic.cont314:
|
|
// CHECK-NEXT: store i64 [[TMP3194]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT313]]
|
|
// CHECK: lx.atomic.exit313:
|
|
// CHECK-NEXT: [[TMP3196:%.*]] = extractvalue { i64, i1 } [[TMP3193]], 1
|
|
// CHECK-NEXT: [[TMP3197:%.*]] = sext i1 [[TMP3196]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3197]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3198:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3199:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3198]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3199]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3200:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3201:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3200]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3201]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3202:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3203:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3202]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3203]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3204:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3205:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3204]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3205]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3206:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3207:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3208:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3206]], i64 [[TMP3207]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3209:%.*]] = extractvalue { i64, i1 } [[TMP3208]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3209]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3210:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3211:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3212:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3210]], i64 [[TMP3211]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3213:%.*]] = extractvalue { i64, i1 } [[TMP3212]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3213]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3214:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3215:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3214]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3216:%.*]] = icmp sgt i64 [[TMP3215]], [[TMP3214]]
|
|
// CHECK-NEXT: [[TMP3217:%.*]] = select i1 [[TMP3216]], i64 [[TMP3214]], i64 [[TMP3215]]
|
|
// CHECK-NEXT: store i64 [[TMP3217]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3218:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3219:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3218]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3220:%.*]] = icmp slt i64 [[TMP3219]], [[TMP3218]]
|
|
// CHECK-NEXT: [[TMP3221:%.*]] = select i1 [[TMP3220]], i64 [[TMP3218]], i64 [[TMP3219]]
|
|
// CHECK-NEXT: store i64 [[TMP3221]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3222:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3223:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3222]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3224:%.*]] = icmp slt i64 [[TMP3223]], [[TMP3222]]
|
|
// CHECK-NEXT: [[TMP3225:%.*]] = select i1 [[TMP3224]], i64 [[TMP3222]], i64 [[TMP3223]]
|
|
// CHECK-NEXT: store i64 [[TMP3225]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3226:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3227:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3226]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3228:%.*]] = icmp sgt i64 [[TMP3227]], [[TMP3226]]
|
|
// CHECK-NEXT: [[TMP3229:%.*]] = select i1 [[TMP3228]], i64 [[TMP3226]], i64 [[TMP3227]]
|
|
// CHECK-NEXT: store i64 [[TMP3229]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3230:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3231:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3232:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3230]], i64 [[TMP3231]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3233:%.*]] = extractvalue { i64, i1 } [[TMP3232]], 0
|
|
// CHECK-NEXT: [[TMP3234:%.*]] = extractvalue { i64, i1 } [[TMP3232]], 1
|
|
// CHECK-NEXT: [[TMP3235:%.*]] = select i1 [[TMP3234]], i64 [[TMP3230]], i64 [[TMP3233]]
|
|
// CHECK-NEXT: store i64 [[TMP3235]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3236:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3237:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3238:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3236]], i64 [[TMP3237]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3239:%.*]] = extractvalue { i64, i1 } [[TMP3238]], 0
|
|
// CHECK-NEXT: [[TMP3240:%.*]] = extractvalue { i64, i1 } [[TMP3238]], 1
|
|
// CHECK-NEXT: [[TMP3241:%.*]] = select i1 [[TMP3240]], i64 [[TMP3236]], i64 [[TMP3239]]
|
|
// CHECK-NEXT: store i64 [[TMP3241]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3242:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3243:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3244:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3242]], i64 [[TMP3243]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3245:%.*]] = extractvalue { i64, i1 } [[TMP3244]], 0
|
|
// CHECK-NEXT: [[TMP3246:%.*]] = extractvalue { i64, i1 } [[TMP3244]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3246]], label [[LX_ATOMIC_EXIT315:%.*]], label [[LX_ATOMIC_CONT316:%.*]]
|
|
// CHECK: lx.atomic.cont316:
|
|
// CHECK-NEXT: store i64 [[TMP3245]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT315]]
|
|
// CHECK: lx.atomic.exit315:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3247:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3248:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3249:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3247]], i64 [[TMP3248]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3250:%.*]] = extractvalue { i64, i1 } [[TMP3249]], 0
|
|
// CHECK-NEXT: [[TMP3251:%.*]] = extractvalue { i64, i1 } [[TMP3249]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3251]], label [[LX_ATOMIC_EXIT317:%.*]], label [[LX_ATOMIC_CONT318:%.*]]
|
|
// CHECK: lx.atomic.cont318:
|
|
// CHECK-NEXT: store i64 [[TMP3250]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT317]]
|
|
// CHECK: lx.atomic.exit317:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3252:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3253:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3254:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3252]], i64 [[TMP3253]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3255:%.*]] = extractvalue { i64, i1 } [[TMP3254]], 1
|
|
// CHECK-NEXT: [[TMP3256:%.*]] = sext i1 [[TMP3255]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3256]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3257:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3258:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3259:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3257]], i64 [[TMP3258]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3260:%.*]] = extractvalue { i64, i1 } [[TMP3259]], 1
|
|
// CHECK-NEXT: [[TMP3261:%.*]] = sext i1 [[TMP3260]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3261]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3262:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3263:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3264:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3262]], i64 [[TMP3263]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3265:%.*]] = extractvalue { i64, i1 } [[TMP3264]], 0
|
|
// CHECK-NEXT: [[TMP3266:%.*]] = extractvalue { i64, i1 } [[TMP3264]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3266]], label [[LX_ATOMIC_EXIT319:%.*]], label [[LX_ATOMIC_CONT320:%.*]]
|
|
// CHECK: lx.atomic.cont320:
|
|
// CHECK-NEXT: store i64 [[TMP3265]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT319]]
|
|
// CHECK: lx.atomic.exit319:
|
|
// CHECK-NEXT: [[TMP3267:%.*]] = extractvalue { i64, i1 } [[TMP3264]], 1
|
|
// CHECK-NEXT: [[TMP3268:%.*]] = sext i1 [[TMP3267]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3268]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3269:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3270:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP3271:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3269]], i64 [[TMP3270]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3272:%.*]] = extractvalue { i64, i1 } [[TMP3271]], 0
|
|
// CHECK-NEXT: [[TMP3273:%.*]] = extractvalue { i64, i1 } [[TMP3271]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3273]], label [[LX_ATOMIC_EXIT321:%.*]], label [[LX_ATOMIC_CONT322:%.*]]
|
|
// CHECK: lx.atomic.cont322:
|
|
// CHECK-NEXT: store i64 [[TMP3272]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT321]]
|
|
// CHECK: lx.atomic.exit321:
|
|
// CHECK-NEXT: [[TMP3274:%.*]] = extractvalue { i64, i1 } [[TMP3271]], 1
|
|
// CHECK-NEXT: [[TMP3275:%.*]] = sext i1 [[TMP3274]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3275]], ptr [[LR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3276:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3277:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3276]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3277]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3278:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3279:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3278]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3279]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3280:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3281:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3280]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3281]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3282:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3283:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3282]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3283]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3284:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3285:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3286:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3284]], i64 [[TMP3285]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3287:%.*]] = extractvalue { i64, i1 } [[TMP3286]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3287]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3288:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3289:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3290:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3288]], i64 [[TMP3289]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3291:%.*]] = extractvalue { i64, i1 } [[TMP3290]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3291]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3292:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3293:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3292]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3294:%.*]] = icmp ugt i64 [[TMP3293]], [[TMP3292]]
|
|
// CHECK-NEXT: [[TMP3295:%.*]] = select i1 [[TMP3294]], i64 [[TMP3292]], i64 [[TMP3293]]
|
|
// CHECK-NEXT: store i64 [[TMP3295]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3296:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3297:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3296]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3298:%.*]] = icmp ult i64 [[TMP3297]], [[TMP3296]]
|
|
// CHECK-NEXT: [[TMP3299:%.*]] = select i1 [[TMP3298]], i64 [[TMP3296]], i64 [[TMP3297]]
|
|
// CHECK-NEXT: store i64 [[TMP3299]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3300:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3301:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3300]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3302:%.*]] = icmp ult i64 [[TMP3301]], [[TMP3300]]
|
|
// CHECK-NEXT: [[TMP3303:%.*]] = select i1 [[TMP3302]], i64 [[TMP3300]], i64 [[TMP3301]]
|
|
// CHECK-NEXT: store i64 [[TMP3303]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3304:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3305:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3304]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3306:%.*]] = icmp ugt i64 [[TMP3305]], [[TMP3304]]
|
|
// CHECK-NEXT: [[TMP3307:%.*]] = select i1 [[TMP3306]], i64 [[TMP3304]], i64 [[TMP3305]]
|
|
// CHECK-NEXT: store i64 [[TMP3307]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3308:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3309:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3310:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3308]], i64 [[TMP3309]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3311:%.*]] = extractvalue { i64, i1 } [[TMP3310]], 0
|
|
// CHECK-NEXT: [[TMP3312:%.*]] = extractvalue { i64, i1 } [[TMP3310]], 1
|
|
// CHECK-NEXT: [[TMP3313:%.*]] = select i1 [[TMP3312]], i64 [[TMP3308]], i64 [[TMP3311]]
|
|
// CHECK-NEXT: store i64 [[TMP3313]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3314:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3315:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3316:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3314]], i64 [[TMP3315]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3317:%.*]] = extractvalue { i64, i1 } [[TMP3316]], 0
|
|
// CHECK-NEXT: [[TMP3318:%.*]] = extractvalue { i64, i1 } [[TMP3316]], 1
|
|
// CHECK-NEXT: [[TMP3319:%.*]] = select i1 [[TMP3318]], i64 [[TMP3314]], i64 [[TMP3317]]
|
|
// CHECK-NEXT: store i64 [[TMP3319]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3320:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3321:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3322:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3320]], i64 [[TMP3321]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3323:%.*]] = extractvalue { i64, i1 } [[TMP3322]], 0
|
|
// CHECK-NEXT: [[TMP3324:%.*]] = extractvalue { i64, i1 } [[TMP3322]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3324]], label [[ULX_ATOMIC_EXIT:%.*]], label [[ULX_ATOMIC_CONT:%.*]]
|
|
// CHECK: ulx.atomic.cont:
|
|
// CHECK-NEXT: store i64 [[TMP3323]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT]]
|
|
// CHECK: ulx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP3325:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3326:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3327:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3325]], i64 [[TMP3326]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3328:%.*]] = extractvalue { i64, i1 } [[TMP3327]], 0
|
|
// CHECK-NEXT: [[TMP3329:%.*]] = extractvalue { i64, i1 } [[TMP3327]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3329]], label [[ULX_ATOMIC_EXIT323:%.*]], label [[ULX_ATOMIC_CONT324:%.*]]
|
|
// CHECK: ulx.atomic.cont324:
|
|
// CHECK-NEXT: store i64 [[TMP3328]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT323]]
|
|
// CHECK: ulx.atomic.exit323:
|
|
// CHECK-NEXT: [[TMP3330:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3331:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3332:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3330]], i64 [[TMP3331]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3333:%.*]] = extractvalue { i64, i1 } [[TMP3332]], 1
|
|
// CHECK-NEXT: [[TMP3334:%.*]] = zext i1 [[TMP3333]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3334]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3335:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3336:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3337:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3335]], i64 [[TMP3336]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3338:%.*]] = extractvalue { i64, i1 } [[TMP3337]], 1
|
|
// CHECK-NEXT: [[TMP3339:%.*]] = zext i1 [[TMP3338]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3339]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3340:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3341:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3342:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3340]], i64 [[TMP3341]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3343:%.*]] = extractvalue { i64, i1 } [[TMP3342]], 0
|
|
// CHECK-NEXT: [[TMP3344:%.*]] = extractvalue { i64, i1 } [[TMP3342]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3344]], label [[ULX_ATOMIC_EXIT325:%.*]], label [[ULX_ATOMIC_CONT326:%.*]]
|
|
// CHECK: ulx.atomic.cont326:
|
|
// CHECK-NEXT: store i64 [[TMP3343]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT325]]
|
|
// CHECK: ulx.atomic.exit325:
|
|
// CHECK-NEXT: [[TMP3345:%.*]] = extractvalue { i64, i1 } [[TMP3342]], 1
|
|
// CHECK-NEXT: [[TMP3346:%.*]] = zext i1 [[TMP3345]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3346]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3347:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3348:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3349:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3347]], i64 [[TMP3348]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3350:%.*]] = extractvalue { i64, i1 } [[TMP3349]], 0
|
|
// CHECK-NEXT: [[TMP3351:%.*]] = extractvalue { i64, i1 } [[TMP3349]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3351]], label [[ULX_ATOMIC_EXIT327:%.*]], label [[ULX_ATOMIC_CONT328:%.*]]
|
|
// CHECK: ulx.atomic.cont328:
|
|
// CHECK-NEXT: store i64 [[TMP3350]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT327]]
|
|
// CHECK: ulx.atomic.exit327:
|
|
// CHECK-NEXT: [[TMP3352:%.*]] = extractvalue { i64, i1 } [[TMP3349]], 1
|
|
// CHECK-NEXT: [[TMP3353:%.*]] = zext i1 [[TMP3352]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3353]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3354:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3355:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3354]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3355]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3356:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3357:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3356]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3357]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3358:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3359:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3358]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3359]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3360:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3361:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3360]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3361]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3362:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3363:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3364:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3362]], i64 [[TMP3363]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3365:%.*]] = extractvalue { i64, i1 } [[TMP3364]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3365]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3366:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3367:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3368:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3366]], i64 [[TMP3367]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3369:%.*]] = extractvalue { i64, i1 } [[TMP3368]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3369]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3370:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3371:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3370]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP3372:%.*]] = icmp ugt i64 [[TMP3371]], [[TMP3370]]
|
|
// CHECK-NEXT: [[TMP3373:%.*]] = select i1 [[TMP3372]], i64 [[TMP3370]], i64 [[TMP3371]]
|
|
// CHECK-NEXT: store i64 [[TMP3373]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3374:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3375:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3374]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP3376:%.*]] = icmp ult i64 [[TMP3375]], [[TMP3374]]
|
|
// CHECK-NEXT: [[TMP3377:%.*]] = select i1 [[TMP3376]], i64 [[TMP3374]], i64 [[TMP3375]]
|
|
// CHECK-NEXT: store i64 [[TMP3377]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3378:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3379:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3378]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP3380:%.*]] = icmp ult i64 [[TMP3379]], [[TMP3378]]
|
|
// CHECK-NEXT: [[TMP3381:%.*]] = select i1 [[TMP3380]], i64 [[TMP3378]], i64 [[TMP3379]]
|
|
// CHECK-NEXT: store i64 [[TMP3381]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3382:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3383:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3382]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP3384:%.*]] = icmp ugt i64 [[TMP3383]], [[TMP3382]]
|
|
// CHECK-NEXT: [[TMP3385:%.*]] = select i1 [[TMP3384]], i64 [[TMP3382]], i64 [[TMP3383]]
|
|
// CHECK-NEXT: store i64 [[TMP3385]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3386:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3387:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3388:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3386]], i64 [[TMP3387]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3389:%.*]] = extractvalue { i64, i1 } [[TMP3388]], 0
|
|
// CHECK-NEXT: [[TMP3390:%.*]] = extractvalue { i64, i1 } [[TMP3388]], 1
|
|
// CHECK-NEXT: [[TMP3391:%.*]] = select i1 [[TMP3390]], i64 [[TMP3386]], i64 [[TMP3389]]
|
|
// CHECK-NEXT: store i64 [[TMP3391]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3392:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3393:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3394:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3392]], i64 [[TMP3393]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3395:%.*]] = extractvalue { i64, i1 } [[TMP3394]], 0
|
|
// CHECK-NEXT: [[TMP3396:%.*]] = extractvalue { i64, i1 } [[TMP3394]], 1
|
|
// CHECK-NEXT: [[TMP3397:%.*]] = select i1 [[TMP3396]], i64 [[TMP3392]], i64 [[TMP3395]]
|
|
// CHECK-NEXT: store i64 [[TMP3397]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3398:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3399:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3400:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3398]], i64 [[TMP3399]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3401:%.*]] = extractvalue { i64, i1 } [[TMP3400]], 0
|
|
// CHECK-NEXT: [[TMP3402:%.*]] = extractvalue { i64, i1 } [[TMP3400]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3402]], label [[ULX_ATOMIC_EXIT329:%.*]], label [[ULX_ATOMIC_CONT330:%.*]]
|
|
// CHECK: ulx.atomic.cont330:
|
|
// CHECK-NEXT: store i64 [[TMP3401]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT329]]
|
|
// CHECK: ulx.atomic.exit329:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3403:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3404:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3405:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3403]], i64 [[TMP3404]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3406:%.*]] = extractvalue { i64, i1 } [[TMP3405]], 0
|
|
// CHECK-NEXT: [[TMP3407:%.*]] = extractvalue { i64, i1 } [[TMP3405]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3407]], label [[ULX_ATOMIC_EXIT331:%.*]], label [[ULX_ATOMIC_CONT332:%.*]]
|
|
// CHECK: ulx.atomic.cont332:
|
|
// CHECK-NEXT: store i64 [[TMP3406]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT331]]
|
|
// CHECK: ulx.atomic.exit331:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3408:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3409:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3410:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3408]], i64 [[TMP3409]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3411:%.*]] = extractvalue { i64, i1 } [[TMP3410]], 1
|
|
// CHECK-NEXT: [[TMP3412:%.*]] = zext i1 [[TMP3411]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3412]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3413:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3414:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3415:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3413]], i64 [[TMP3414]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3416:%.*]] = extractvalue { i64, i1 } [[TMP3415]], 1
|
|
// CHECK-NEXT: [[TMP3417:%.*]] = zext i1 [[TMP3416]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3417]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3418:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3419:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3420:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3418]], i64 [[TMP3419]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3421:%.*]] = extractvalue { i64, i1 } [[TMP3420]], 0
|
|
// CHECK-NEXT: [[TMP3422:%.*]] = extractvalue { i64, i1 } [[TMP3420]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3422]], label [[ULX_ATOMIC_EXIT333:%.*]], label [[ULX_ATOMIC_CONT334:%.*]]
|
|
// CHECK: ulx.atomic.cont334:
|
|
// CHECK-NEXT: store i64 [[TMP3421]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT333]]
|
|
// CHECK: ulx.atomic.exit333:
|
|
// CHECK-NEXT: [[TMP3423:%.*]] = extractvalue { i64, i1 } [[TMP3420]], 1
|
|
// CHECK-NEXT: [[TMP3424:%.*]] = zext i1 [[TMP3423]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3424]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3425:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3426:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3427:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3425]], i64 [[TMP3426]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3428:%.*]] = extractvalue { i64, i1 } [[TMP3427]], 0
|
|
// CHECK-NEXT: [[TMP3429:%.*]] = extractvalue { i64, i1 } [[TMP3427]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3429]], label [[ULX_ATOMIC_EXIT335:%.*]], label [[ULX_ATOMIC_CONT336:%.*]]
|
|
// CHECK: ulx.atomic.cont336:
|
|
// CHECK-NEXT: store i64 [[TMP3428]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT335]]
|
|
// CHECK: ulx.atomic.exit335:
|
|
// CHECK-NEXT: [[TMP3430:%.*]] = extractvalue { i64, i1 } [[TMP3427]], 1
|
|
// CHECK-NEXT: [[TMP3431:%.*]] = zext i1 [[TMP3430]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3431]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3432:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3433:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3432]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3433]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3434:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3435:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3434]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3435]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3436:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3437:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3436]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3437]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3438:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3439:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3438]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3439]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3440:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3441:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3442:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3440]], i64 [[TMP3441]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3443:%.*]] = extractvalue { i64, i1 } [[TMP3442]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3443]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3444:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3445:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3446:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3444]], i64 [[TMP3445]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3447:%.*]] = extractvalue { i64, i1 } [[TMP3446]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3447]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3448:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3449:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3448]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP3450:%.*]] = icmp ugt i64 [[TMP3449]], [[TMP3448]]
|
|
// CHECK-NEXT: [[TMP3451:%.*]] = select i1 [[TMP3450]], i64 [[TMP3448]], i64 [[TMP3449]]
|
|
// CHECK-NEXT: store i64 [[TMP3451]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3452:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3453:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3452]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP3454:%.*]] = icmp ult i64 [[TMP3453]], [[TMP3452]]
|
|
// CHECK-NEXT: [[TMP3455:%.*]] = select i1 [[TMP3454]], i64 [[TMP3452]], i64 [[TMP3453]]
|
|
// CHECK-NEXT: store i64 [[TMP3455]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3456:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3457:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3456]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP3458:%.*]] = icmp ult i64 [[TMP3457]], [[TMP3456]]
|
|
// CHECK-NEXT: [[TMP3459:%.*]] = select i1 [[TMP3458]], i64 [[TMP3456]], i64 [[TMP3457]]
|
|
// CHECK-NEXT: store i64 [[TMP3459]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3460:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3461:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3460]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP3462:%.*]] = icmp ugt i64 [[TMP3461]], [[TMP3460]]
|
|
// CHECK-NEXT: [[TMP3463:%.*]] = select i1 [[TMP3462]], i64 [[TMP3460]], i64 [[TMP3461]]
|
|
// CHECK-NEXT: store i64 [[TMP3463]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3464:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3465:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3466:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3464]], i64 [[TMP3465]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3467:%.*]] = extractvalue { i64, i1 } [[TMP3466]], 0
|
|
// CHECK-NEXT: [[TMP3468:%.*]] = extractvalue { i64, i1 } [[TMP3466]], 1
|
|
// CHECK-NEXT: [[TMP3469:%.*]] = select i1 [[TMP3468]], i64 [[TMP3464]], i64 [[TMP3467]]
|
|
// CHECK-NEXT: store i64 [[TMP3469]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3470:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3471:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3472:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3470]], i64 [[TMP3471]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3473:%.*]] = extractvalue { i64, i1 } [[TMP3472]], 0
|
|
// CHECK-NEXT: [[TMP3474:%.*]] = extractvalue { i64, i1 } [[TMP3472]], 1
|
|
// CHECK-NEXT: [[TMP3475:%.*]] = select i1 [[TMP3474]], i64 [[TMP3470]], i64 [[TMP3473]]
|
|
// CHECK-NEXT: store i64 [[TMP3475]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3476:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3477:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3478:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3476]], i64 [[TMP3477]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3479:%.*]] = extractvalue { i64, i1 } [[TMP3478]], 0
|
|
// CHECK-NEXT: [[TMP3480:%.*]] = extractvalue { i64, i1 } [[TMP3478]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3480]], label [[ULX_ATOMIC_EXIT337:%.*]], label [[ULX_ATOMIC_CONT338:%.*]]
|
|
// CHECK: ulx.atomic.cont338:
|
|
// CHECK-NEXT: store i64 [[TMP3479]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT337]]
|
|
// CHECK: ulx.atomic.exit337:
|
|
// CHECK-NEXT: [[TMP3481:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3482:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3483:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3481]], i64 [[TMP3482]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3484:%.*]] = extractvalue { i64, i1 } [[TMP3483]], 0
|
|
// CHECK-NEXT: [[TMP3485:%.*]] = extractvalue { i64, i1 } [[TMP3483]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3485]], label [[ULX_ATOMIC_EXIT339:%.*]], label [[ULX_ATOMIC_CONT340:%.*]]
|
|
// CHECK: ulx.atomic.cont340:
|
|
// CHECK-NEXT: store i64 [[TMP3484]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT339]]
|
|
// CHECK: ulx.atomic.exit339:
|
|
// CHECK-NEXT: [[TMP3486:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3487:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3488:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3486]], i64 [[TMP3487]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3489:%.*]] = extractvalue { i64, i1 } [[TMP3488]], 1
|
|
// CHECK-NEXT: [[TMP3490:%.*]] = zext i1 [[TMP3489]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3490]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3491:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3492:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3493:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3491]], i64 [[TMP3492]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3494:%.*]] = extractvalue { i64, i1 } [[TMP3493]], 1
|
|
// CHECK-NEXT: [[TMP3495:%.*]] = zext i1 [[TMP3494]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3495]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3496:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3497:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3498:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3496]], i64 [[TMP3497]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3499:%.*]] = extractvalue { i64, i1 } [[TMP3498]], 0
|
|
// CHECK-NEXT: [[TMP3500:%.*]] = extractvalue { i64, i1 } [[TMP3498]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3500]], label [[ULX_ATOMIC_EXIT341:%.*]], label [[ULX_ATOMIC_CONT342:%.*]]
|
|
// CHECK: ulx.atomic.cont342:
|
|
// CHECK-NEXT: store i64 [[TMP3499]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT341]]
|
|
// CHECK: ulx.atomic.exit341:
|
|
// CHECK-NEXT: [[TMP3501:%.*]] = extractvalue { i64, i1 } [[TMP3498]], 1
|
|
// CHECK-NEXT: [[TMP3502:%.*]] = zext i1 [[TMP3501]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3502]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3503:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3504:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3505:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3503]], i64 [[TMP3504]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3506:%.*]] = extractvalue { i64, i1 } [[TMP3505]], 0
|
|
// CHECK-NEXT: [[TMP3507:%.*]] = extractvalue { i64, i1 } [[TMP3505]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3507]], label [[ULX_ATOMIC_EXIT343:%.*]], label [[ULX_ATOMIC_CONT344:%.*]]
|
|
// CHECK: ulx.atomic.cont344:
|
|
// CHECK-NEXT: store i64 [[TMP3506]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT343]]
|
|
// CHECK: ulx.atomic.exit343:
|
|
// CHECK-NEXT: [[TMP3508:%.*]] = extractvalue { i64, i1 } [[TMP3505]], 1
|
|
// CHECK-NEXT: [[TMP3509:%.*]] = zext i1 [[TMP3508]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3509]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3510:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3511:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3510]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3511]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3512:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3513:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3512]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3513]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3514:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3515:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3514]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3515]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3516:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3517:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3516]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3517]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3518:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3519:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3520:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3518]], i64 [[TMP3519]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3521:%.*]] = extractvalue { i64, i1 } [[TMP3520]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3521]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3522:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3523:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3524:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3522]], i64 [[TMP3523]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3525:%.*]] = extractvalue { i64, i1 } [[TMP3524]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3525]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3526:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3527:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3526]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3528:%.*]] = icmp ugt i64 [[TMP3527]], [[TMP3526]]
|
|
// CHECK-NEXT: [[TMP3529:%.*]] = select i1 [[TMP3528]], i64 [[TMP3526]], i64 [[TMP3527]]
|
|
// CHECK-NEXT: store i64 [[TMP3529]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3530:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3531:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3530]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3532:%.*]] = icmp ult i64 [[TMP3531]], [[TMP3530]]
|
|
// CHECK-NEXT: [[TMP3533:%.*]] = select i1 [[TMP3532]], i64 [[TMP3530]], i64 [[TMP3531]]
|
|
// CHECK-NEXT: store i64 [[TMP3533]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3534:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3535:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3534]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3536:%.*]] = icmp ult i64 [[TMP3535]], [[TMP3534]]
|
|
// CHECK-NEXT: [[TMP3537:%.*]] = select i1 [[TMP3536]], i64 [[TMP3534]], i64 [[TMP3535]]
|
|
// CHECK-NEXT: store i64 [[TMP3537]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3538:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3539:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3538]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3540:%.*]] = icmp ugt i64 [[TMP3539]], [[TMP3538]]
|
|
// CHECK-NEXT: [[TMP3541:%.*]] = select i1 [[TMP3540]], i64 [[TMP3538]], i64 [[TMP3539]]
|
|
// CHECK-NEXT: store i64 [[TMP3541]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3542:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3543:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3544:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3542]], i64 [[TMP3543]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3545:%.*]] = extractvalue { i64, i1 } [[TMP3544]], 0
|
|
// CHECK-NEXT: [[TMP3546:%.*]] = extractvalue { i64, i1 } [[TMP3544]], 1
|
|
// CHECK-NEXT: [[TMP3547:%.*]] = select i1 [[TMP3546]], i64 [[TMP3542]], i64 [[TMP3545]]
|
|
// CHECK-NEXT: store i64 [[TMP3547]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3548:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3549:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3550:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3548]], i64 [[TMP3549]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3551:%.*]] = extractvalue { i64, i1 } [[TMP3550]], 0
|
|
// CHECK-NEXT: [[TMP3552:%.*]] = extractvalue { i64, i1 } [[TMP3550]], 1
|
|
// CHECK-NEXT: [[TMP3553:%.*]] = select i1 [[TMP3552]], i64 [[TMP3548]], i64 [[TMP3551]]
|
|
// CHECK-NEXT: store i64 [[TMP3553]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP3554:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3555:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3556:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3554]], i64 [[TMP3555]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3557:%.*]] = extractvalue { i64, i1 } [[TMP3556]], 0
|
|
// CHECK-NEXT: [[TMP3558:%.*]] = extractvalue { i64, i1 } [[TMP3556]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3558]], label [[ULX_ATOMIC_EXIT345:%.*]], label [[ULX_ATOMIC_CONT346:%.*]]
|
|
// CHECK: ulx.atomic.cont346:
|
|
// CHECK-NEXT: store i64 [[TMP3557]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT345]]
|
|
// CHECK: ulx.atomic.exit345:
|
|
// CHECK-NEXT: [[TMP3559:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3560:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3561:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3559]], i64 [[TMP3560]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3562:%.*]] = extractvalue { i64, i1 } [[TMP3561]], 0
|
|
// CHECK-NEXT: [[TMP3563:%.*]] = extractvalue { i64, i1 } [[TMP3561]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3563]], label [[ULX_ATOMIC_EXIT347:%.*]], label [[ULX_ATOMIC_CONT348:%.*]]
|
|
// CHECK: ulx.atomic.cont348:
|
|
// CHECK-NEXT: store i64 [[TMP3562]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT347]]
|
|
// CHECK: ulx.atomic.exit347:
|
|
// CHECK-NEXT: [[TMP3564:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3565:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3566:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3564]], i64 [[TMP3565]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3567:%.*]] = extractvalue { i64, i1 } [[TMP3566]], 1
|
|
// CHECK-NEXT: [[TMP3568:%.*]] = zext i1 [[TMP3567]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3568]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3569:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3570:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3571:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3569]], i64 [[TMP3570]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3572:%.*]] = extractvalue { i64, i1 } [[TMP3571]], 1
|
|
// CHECK-NEXT: [[TMP3573:%.*]] = zext i1 [[TMP3572]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3573]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3574:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3575:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3576:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3574]], i64 [[TMP3575]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3577:%.*]] = extractvalue { i64, i1 } [[TMP3576]], 0
|
|
// CHECK-NEXT: [[TMP3578:%.*]] = extractvalue { i64, i1 } [[TMP3576]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3578]], label [[ULX_ATOMIC_EXIT349:%.*]], label [[ULX_ATOMIC_CONT350:%.*]]
|
|
// CHECK: ulx.atomic.cont350:
|
|
// CHECK-NEXT: store i64 [[TMP3577]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT349]]
|
|
// CHECK: ulx.atomic.exit349:
|
|
// CHECK-NEXT: [[TMP3579:%.*]] = extractvalue { i64, i1 } [[TMP3576]], 1
|
|
// CHECK-NEXT: [[TMP3580:%.*]] = zext i1 [[TMP3579]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3580]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3581:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3582:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3583:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3581]], i64 [[TMP3582]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3584:%.*]] = extractvalue { i64, i1 } [[TMP3583]], 0
|
|
// CHECK-NEXT: [[TMP3585:%.*]] = extractvalue { i64, i1 } [[TMP3583]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3585]], label [[ULX_ATOMIC_EXIT351:%.*]], label [[ULX_ATOMIC_CONT352:%.*]]
|
|
// CHECK: ulx.atomic.cont352:
|
|
// CHECK-NEXT: store i64 [[TMP3584]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT351]]
|
|
// CHECK: ulx.atomic.exit351:
|
|
// CHECK-NEXT: [[TMP3586:%.*]] = extractvalue { i64, i1 } [[TMP3583]], 1
|
|
// CHECK-NEXT: [[TMP3587:%.*]] = zext i1 [[TMP3586]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3587]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: [[TMP3588:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3589:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3588]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3589]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3590:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3591:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3590]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3591]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3592:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3593:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3592]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3593]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3594:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3595:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3594]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3595]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3596:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3597:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3598:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3596]], i64 [[TMP3597]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3599:%.*]] = extractvalue { i64, i1 } [[TMP3598]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3599]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3600:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3601:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3602:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3600]], i64 [[TMP3601]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3603:%.*]] = extractvalue { i64, i1 } [[TMP3602]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3603]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3604:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3605:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3604]] release, align 8
|
|
// CHECK-NEXT: [[TMP3606:%.*]] = icmp ugt i64 [[TMP3605]], [[TMP3604]]
|
|
// CHECK-NEXT: [[TMP3607:%.*]] = select i1 [[TMP3606]], i64 [[TMP3604]], i64 [[TMP3605]]
|
|
// CHECK-NEXT: store i64 [[TMP3607]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3608:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3609:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3608]] release, align 8
|
|
// CHECK-NEXT: [[TMP3610:%.*]] = icmp ult i64 [[TMP3609]], [[TMP3608]]
|
|
// CHECK-NEXT: [[TMP3611:%.*]] = select i1 [[TMP3610]], i64 [[TMP3608]], i64 [[TMP3609]]
|
|
// CHECK-NEXT: store i64 [[TMP3611]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3612:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3613:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3612]] release, align 8
|
|
// CHECK-NEXT: [[TMP3614:%.*]] = icmp ult i64 [[TMP3613]], [[TMP3612]]
|
|
// CHECK-NEXT: [[TMP3615:%.*]] = select i1 [[TMP3614]], i64 [[TMP3612]], i64 [[TMP3613]]
|
|
// CHECK-NEXT: store i64 [[TMP3615]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3616:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3617:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3616]] release, align 8
|
|
// CHECK-NEXT: [[TMP3618:%.*]] = icmp ugt i64 [[TMP3617]], [[TMP3616]]
|
|
// CHECK-NEXT: [[TMP3619:%.*]] = select i1 [[TMP3618]], i64 [[TMP3616]], i64 [[TMP3617]]
|
|
// CHECK-NEXT: store i64 [[TMP3619]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3620:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3621:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3622:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3620]], i64 [[TMP3621]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3623:%.*]] = extractvalue { i64, i1 } [[TMP3622]], 0
|
|
// CHECK-NEXT: [[TMP3624:%.*]] = extractvalue { i64, i1 } [[TMP3622]], 1
|
|
// CHECK-NEXT: [[TMP3625:%.*]] = select i1 [[TMP3624]], i64 [[TMP3620]], i64 [[TMP3623]]
|
|
// CHECK-NEXT: store i64 [[TMP3625]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3626:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3627:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3628:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3626]], i64 [[TMP3627]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3629:%.*]] = extractvalue { i64, i1 } [[TMP3628]], 0
|
|
// CHECK-NEXT: [[TMP3630:%.*]] = extractvalue { i64, i1 } [[TMP3628]], 1
|
|
// CHECK-NEXT: [[TMP3631:%.*]] = select i1 [[TMP3630]], i64 [[TMP3626]], i64 [[TMP3629]]
|
|
// CHECK-NEXT: store i64 [[TMP3631]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3632:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3633:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3634:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3632]], i64 [[TMP3633]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3635:%.*]] = extractvalue { i64, i1 } [[TMP3634]], 0
|
|
// CHECK-NEXT: [[TMP3636:%.*]] = extractvalue { i64, i1 } [[TMP3634]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3636]], label [[ULX_ATOMIC_EXIT353:%.*]], label [[ULX_ATOMIC_CONT354:%.*]]
|
|
// CHECK: ulx.atomic.cont354:
|
|
// CHECK-NEXT: store i64 [[TMP3635]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT353]]
|
|
// CHECK: ulx.atomic.exit353:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3637:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3638:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3639:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3637]], i64 [[TMP3638]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3640:%.*]] = extractvalue { i64, i1 } [[TMP3639]], 0
|
|
// CHECK-NEXT: [[TMP3641:%.*]] = extractvalue { i64, i1 } [[TMP3639]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3641]], label [[ULX_ATOMIC_EXIT355:%.*]], label [[ULX_ATOMIC_CONT356:%.*]]
|
|
// CHECK: ulx.atomic.cont356:
|
|
// CHECK-NEXT: store i64 [[TMP3640]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT355]]
|
|
// CHECK: ulx.atomic.exit355:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3642:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3643:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3644:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3642]], i64 [[TMP3643]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3645:%.*]] = extractvalue { i64, i1 } [[TMP3644]], 1
|
|
// CHECK-NEXT: [[TMP3646:%.*]] = zext i1 [[TMP3645]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3646]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3647:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3648:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3649:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3647]], i64 [[TMP3648]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3650:%.*]] = extractvalue { i64, i1 } [[TMP3649]], 1
|
|
// CHECK-NEXT: [[TMP3651:%.*]] = zext i1 [[TMP3650]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3651]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3652:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3653:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3654:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3652]], i64 [[TMP3653]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3655:%.*]] = extractvalue { i64, i1 } [[TMP3654]], 0
|
|
// CHECK-NEXT: [[TMP3656:%.*]] = extractvalue { i64, i1 } [[TMP3654]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3656]], label [[ULX_ATOMIC_EXIT357:%.*]], label [[ULX_ATOMIC_CONT358:%.*]]
|
|
// CHECK: ulx.atomic.cont358:
|
|
// CHECK-NEXT: store i64 [[TMP3655]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT357]]
|
|
// CHECK: ulx.atomic.exit357:
|
|
// CHECK-NEXT: [[TMP3657:%.*]] = extractvalue { i64, i1 } [[TMP3654]], 1
|
|
// CHECK-NEXT: [[TMP3658:%.*]] = zext i1 [[TMP3657]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3658]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3659:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3660:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3661:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3659]], i64 [[TMP3660]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3662:%.*]] = extractvalue { i64, i1 } [[TMP3661]], 0
|
|
// CHECK-NEXT: [[TMP3663:%.*]] = extractvalue { i64, i1 } [[TMP3661]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3663]], label [[ULX_ATOMIC_EXIT359:%.*]], label [[ULX_ATOMIC_CONT360:%.*]]
|
|
// CHECK: ulx.atomic.cont360:
|
|
// CHECK-NEXT: store i64 [[TMP3662]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT359]]
|
|
// CHECK: ulx.atomic.exit359:
|
|
// CHECK-NEXT: [[TMP3664:%.*]] = extractvalue { i64, i1 } [[TMP3661]], 1
|
|
// CHECK-NEXT: [[TMP3665:%.*]] = zext i1 [[TMP3664]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3665]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3666:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3667:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3666]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3667]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3668:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3669:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3668]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3669]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3670:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3671:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3670]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3671]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3672:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3673:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3672]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3673]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3674:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3675:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3676:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3674]], i64 [[TMP3675]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3677:%.*]] = extractvalue { i64, i1 } [[TMP3676]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3677]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3678:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3679:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3680:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3678]], i64 [[TMP3679]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3681:%.*]] = extractvalue { i64, i1 } [[TMP3680]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3681]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3682:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3683:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3682]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3684:%.*]] = icmp ugt i64 [[TMP3683]], [[TMP3682]]
|
|
// CHECK-NEXT: [[TMP3685:%.*]] = select i1 [[TMP3684]], i64 [[TMP3682]], i64 [[TMP3683]]
|
|
// CHECK-NEXT: store i64 [[TMP3685]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3686:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3687:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3686]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3688:%.*]] = icmp ult i64 [[TMP3687]], [[TMP3686]]
|
|
// CHECK-NEXT: [[TMP3689:%.*]] = select i1 [[TMP3688]], i64 [[TMP3686]], i64 [[TMP3687]]
|
|
// CHECK-NEXT: store i64 [[TMP3689]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3690:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3691:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3690]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3692:%.*]] = icmp ult i64 [[TMP3691]], [[TMP3690]]
|
|
// CHECK-NEXT: [[TMP3693:%.*]] = select i1 [[TMP3692]], i64 [[TMP3690]], i64 [[TMP3691]]
|
|
// CHECK-NEXT: store i64 [[TMP3693]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3694:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3695:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3694]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3696:%.*]] = icmp ugt i64 [[TMP3695]], [[TMP3694]]
|
|
// CHECK-NEXT: [[TMP3697:%.*]] = select i1 [[TMP3696]], i64 [[TMP3694]], i64 [[TMP3695]]
|
|
// CHECK-NEXT: store i64 [[TMP3697]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3698:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3699:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3700:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3698]], i64 [[TMP3699]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3701:%.*]] = extractvalue { i64, i1 } [[TMP3700]], 0
|
|
// CHECK-NEXT: [[TMP3702:%.*]] = extractvalue { i64, i1 } [[TMP3700]], 1
|
|
// CHECK-NEXT: [[TMP3703:%.*]] = select i1 [[TMP3702]], i64 [[TMP3698]], i64 [[TMP3701]]
|
|
// CHECK-NEXT: store i64 [[TMP3703]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3704:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3705:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3706:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3704]], i64 [[TMP3705]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3707:%.*]] = extractvalue { i64, i1 } [[TMP3706]], 0
|
|
// CHECK-NEXT: [[TMP3708:%.*]] = extractvalue { i64, i1 } [[TMP3706]], 1
|
|
// CHECK-NEXT: [[TMP3709:%.*]] = select i1 [[TMP3708]], i64 [[TMP3704]], i64 [[TMP3707]]
|
|
// CHECK-NEXT: store i64 [[TMP3709]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3710:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3711:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3712:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3710]], i64 [[TMP3711]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3713:%.*]] = extractvalue { i64, i1 } [[TMP3712]], 0
|
|
// CHECK-NEXT: [[TMP3714:%.*]] = extractvalue { i64, i1 } [[TMP3712]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3714]], label [[ULX_ATOMIC_EXIT361:%.*]], label [[ULX_ATOMIC_CONT362:%.*]]
|
|
// CHECK: ulx.atomic.cont362:
|
|
// CHECK-NEXT: store i64 [[TMP3713]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT361]]
|
|
// CHECK: ulx.atomic.exit361:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3715:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3716:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3717:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3715]], i64 [[TMP3716]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3718:%.*]] = extractvalue { i64, i1 } [[TMP3717]], 0
|
|
// CHECK-NEXT: [[TMP3719:%.*]] = extractvalue { i64, i1 } [[TMP3717]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3719]], label [[ULX_ATOMIC_EXIT363:%.*]], label [[ULX_ATOMIC_CONT364:%.*]]
|
|
// CHECK: ulx.atomic.cont364:
|
|
// CHECK-NEXT: store i64 [[TMP3718]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT363]]
|
|
// CHECK: ulx.atomic.exit363:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3720:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3721:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3722:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3720]], i64 [[TMP3721]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3723:%.*]] = extractvalue { i64, i1 } [[TMP3722]], 1
|
|
// CHECK-NEXT: [[TMP3724:%.*]] = zext i1 [[TMP3723]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3724]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3725:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3726:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3727:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3725]], i64 [[TMP3726]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3728:%.*]] = extractvalue { i64, i1 } [[TMP3727]], 1
|
|
// CHECK-NEXT: [[TMP3729:%.*]] = zext i1 [[TMP3728]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3729]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3730:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3731:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3732:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3730]], i64 [[TMP3731]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3733:%.*]] = extractvalue { i64, i1 } [[TMP3732]], 0
|
|
// CHECK-NEXT: [[TMP3734:%.*]] = extractvalue { i64, i1 } [[TMP3732]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3734]], label [[ULX_ATOMIC_EXIT365:%.*]], label [[ULX_ATOMIC_CONT366:%.*]]
|
|
// CHECK: ulx.atomic.cont366:
|
|
// CHECK-NEXT: store i64 [[TMP3733]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT365]]
|
|
// CHECK: ulx.atomic.exit365:
|
|
// CHECK-NEXT: [[TMP3735:%.*]] = extractvalue { i64, i1 } [[TMP3732]], 1
|
|
// CHECK-NEXT: [[TMP3736:%.*]] = zext i1 [[TMP3735]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3736]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3737:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3738:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP3739:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3737]], i64 [[TMP3738]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP3740:%.*]] = extractvalue { i64, i1 } [[TMP3739]], 0
|
|
// CHECK-NEXT: [[TMP3741:%.*]] = extractvalue { i64, i1 } [[TMP3739]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3741]], label [[ULX_ATOMIC_EXIT367:%.*]], label [[ULX_ATOMIC_CONT368:%.*]]
|
|
// CHECK: ulx.atomic.cont368:
|
|
// CHECK-NEXT: store i64 [[TMP3740]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT367]]
|
|
// CHECK: ulx.atomic.exit367:
|
|
// CHECK-NEXT: [[TMP3742:%.*]] = extractvalue { i64, i1 } [[TMP3739]], 1
|
|
// CHECK-NEXT: [[TMP3743:%.*]] = zext i1 [[TMP3742]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3743]], ptr [[ULR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3744:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3745:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3744]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3745]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3746:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3747:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3746]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3747]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3748:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3749:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3748]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3749]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3750:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3751:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3750]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3751]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3752:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3753:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3754:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3752]], i64 [[TMP3753]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3755:%.*]] = extractvalue { i64, i1 } [[TMP3754]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3755]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3756:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3757:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3758:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3756]], i64 [[TMP3757]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3759:%.*]] = extractvalue { i64, i1 } [[TMP3758]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3759]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3760:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3761:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3760]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3762:%.*]] = icmp sgt i64 [[TMP3761]], [[TMP3760]]
|
|
// CHECK-NEXT: [[TMP3763:%.*]] = select i1 [[TMP3762]], i64 [[TMP3760]], i64 [[TMP3761]]
|
|
// CHECK-NEXT: store i64 [[TMP3763]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3764:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3765:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3764]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3766:%.*]] = icmp slt i64 [[TMP3765]], [[TMP3764]]
|
|
// CHECK-NEXT: [[TMP3767:%.*]] = select i1 [[TMP3766]], i64 [[TMP3764]], i64 [[TMP3765]]
|
|
// CHECK-NEXT: store i64 [[TMP3767]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3768:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3769:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3768]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3770:%.*]] = icmp slt i64 [[TMP3769]], [[TMP3768]]
|
|
// CHECK-NEXT: [[TMP3771:%.*]] = select i1 [[TMP3770]], i64 [[TMP3768]], i64 [[TMP3769]]
|
|
// CHECK-NEXT: store i64 [[TMP3771]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3772:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3773:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3772]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3774:%.*]] = icmp sgt i64 [[TMP3773]], [[TMP3772]]
|
|
// CHECK-NEXT: [[TMP3775:%.*]] = select i1 [[TMP3774]], i64 [[TMP3772]], i64 [[TMP3773]]
|
|
// CHECK-NEXT: store i64 [[TMP3775]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3776:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3777:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3778:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3776]], i64 [[TMP3777]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3779:%.*]] = extractvalue { i64, i1 } [[TMP3778]], 0
|
|
// CHECK-NEXT: [[TMP3780:%.*]] = extractvalue { i64, i1 } [[TMP3778]], 1
|
|
// CHECK-NEXT: [[TMP3781:%.*]] = select i1 [[TMP3780]], i64 [[TMP3776]], i64 [[TMP3779]]
|
|
// CHECK-NEXT: store i64 [[TMP3781]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3782:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3783:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3784:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3782]], i64 [[TMP3783]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3785:%.*]] = extractvalue { i64, i1 } [[TMP3784]], 0
|
|
// CHECK-NEXT: [[TMP3786:%.*]] = extractvalue { i64, i1 } [[TMP3784]], 1
|
|
// CHECK-NEXT: [[TMP3787:%.*]] = select i1 [[TMP3786]], i64 [[TMP3782]], i64 [[TMP3785]]
|
|
// CHECK-NEXT: store i64 [[TMP3787]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3788:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3789:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3790:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3788]], i64 [[TMP3789]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3791:%.*]] = extractvalue { i64, i1 } [[TMP3790]], 0
|
|
// CHECK-NEXT: [[TMP3792:%.*]] = extractvalue { i64, i1 } [[TMP3790]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3792]], label [[LLX_ATOMIC_EXIT:%.*]], label [[LLX_ATOMIC_CONT:%.*]]
|
|
// CHECK: llx.atomic.cont:
|
|
// CHECK-NEXT: store i64 [[TMP3791]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT]]
|
|
// CHECK: llx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP3793:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3794:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3795:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3793]], i64 [[TMP3794]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3796:%.*]] = extractvalue { i64, i1 } [[TMP3795]], 0
|
|
// CHECK-NEXT: [[TMP3797:%.*]] = extractvalue { i64, i1 } [[TMP3795]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3797]], label [[LLX_ATOMIC_EXIT369:%.*]], label [[LLX_ATOMIC_CONT370:%.*]]
|
|
// CHECK: llx.atomic.cont370:
|
|
// CHECK-NEXT: store i64 [[TMP3796]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT369]]
|
|
// CHECK: llx.atomic.exit369:
|
|
// CHECK-NEXT: [[TMP3798:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3799:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3800:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3798]], i64 [[TMP3799]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3801:%.*]] = extractvalue { i64, i1 } [[TMP3800]], 1
|
|
// CHECK-NEXT: [[TMP3802:%.*]] = sext i1 [[TMP3801]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3802]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP3803:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3804:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3805:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3803]], i64 [[TMP3804]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3806:%.*]] = extractvalue { i64, i1 } [[TMP3805]], 1
|
|
// CHECK-NEXT: [[TMP3807:%.*]] = sext i1 [[TMP3806]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3807]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP3808:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3809:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3810:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3808]], i64 [[TMP3809]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3811:%.*]] = extractvalue { i64, i1 } [[TMP3810]], 0
|
|
// CHECK-NEXT: [[TMP3812:%.*]] = extractvalue { i64, i1 } [[TMP3810]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3812]], label [[LLX_ATOMIC_EXIT371:%.*]], label [[LLX_ATOMIC_CONT372:%.*]]
|
|
// CHECK: llx.atomic.cont372:
|
|
// CHECK-NEXT: store i64 [[TMP3811]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT371]]
|
|
// CHECK: llx.atomic.exit371:
|
|
// CHECK-NEXT: [[TMP3813:%.*]] = extractvalue { i64, i1 } [[TMP3810]], 1
|
|
// CHECK-NEXT: [[TMP3814:%.*]] = sext i1 [[TMP3813]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3814]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP3815:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3816:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3817:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3815]], i64 [[TMP3816]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3818:%.*]] = extractvalue { i64, i1 } [[TMP3817]], 0
|
|
// CHECK-NEXT: [[TMP3819:%.*]] = extractvalue { i64, i1 } [[TMP3817]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3819]], label [[LLX_ATOMIC_EXIT373:%.*]], label [[LLX_ATOMIC_CONT374:%.*]]
|
|
// CHECK: llx.atomic.cont374:
|
|
// CHECK-NEXT: store i64 [[TMP3818]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT373]]
|
|
// CHECK: llx.atomic.exit373:
|
|
// CHECK-NEXT: [[TMP3820:%.*]] = extractvalue { i64, i1 } [[TMP3817]], 1
|
|
// CHECK-NEXT: [[TMP3821:%.*]] = sext i1 [[TMP3820]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3821]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP3822:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3823:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3822]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3823]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3824:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3825:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3824]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3825]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3826:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3827:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3826]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3827]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3828:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3829:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3828]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3829]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3830:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3831:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3832:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3830]], i64 [[TMP3831]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3833:%.*]] = extractvalue { i64, i1 } [[TMP3832]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3833]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3834:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3835:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3836:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3834]], i64 [[TMP3835]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3837:%.*]] = extractvalue { i64, i1 } [[TMP3836]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3837]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3838:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3839:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3838]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP3840:%.*]] = icmp sgt i64 [[TMP3839]], [[TMP3838]]
|
|
// CHECK-NEXT: [[TMP3841:%.*]] = select i1 [[TMP3840]], i64 [[TMP3838]], i64 [[TMP3839]]
|
|
// CHECK-NEXT: store i64 [[TMP3841]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3842:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3843:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3842]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP3844:%.*]] = icmp slt i64 [[TMP3843]], [[TMP3842]]
|
|
// CHECK-NEXT: [[TMP3845:%.*]] = select i1 [[TMP3844]], i64 [[TMP3842]], i64 [[TMP3843]]
|
|
// CHECK-NEXT: store i64 [[TMP3845]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3846:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3847:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3846]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP3848:%.*]] = icmp slt i64 [[TMP3847]], [[TMP3846]]
|
|
// CHECK-NEXT: [[TMP3849:%.*]] = select i1 [[TMP3848]], i64 [[TMP3846]], i64 [[TMP3847]]
|
|
// CHECK-NEXT: store i64 [[TMP3849]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3850:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3851:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3850]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP3852:%.*]] = icmp sgt i64 [[TMP3851]], [[TMP3850]]
|
|
// CHECK-NEXT: [[TMP3853:%.*]] = select i1 [[TMP3852]], i64 [[TMP3850]], i64 [[TMP3851]]
|
|
// CHECK-NEXT: store i64 [[TMP3853]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3854:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3855:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3856:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3854]], i64 [[TMP3855]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3857:%.*]] = extractvalue { i64, i1 } [[TMP3856]], 0
|
|
// CHECK-NEXT: [[TMP3858:%.*]] = extractvalue { i64, i1 } [[TMP3856]], 1
|
|
// CHECK-NEXT: [[TMP3859:%.*]] = select i1 [[TMP3858]], i64 [[TMP3854]], i64 [[TMP3857]]
|
|
// CHECK-NEXT: store i64 [[TMP3859]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3860:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3861:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3862:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3860]], i64 [[TMP3861]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3863:%.*]] = extractvalue { i64, i1 } [[TMP3862]], 0
|
|
// CHECK-NEXT: [[TMP3864:%.*]] = extractvalue { i64, i1 } [[TMP3862]], 1
|
|
// CHECK-NEXT: [[TMP3865:%.*]] = select i1 [[TMP3864]], i64 [[TMP3860]], i64 [[TMP3863]]
|
|
// CHECK-NEXT: store i64 [[TMP3865]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3866:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3867:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3868:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3866]], i64 [[TMP3867]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3869:%.*]] = extractvalue { i64, i1 } [[TMP3868]], 0
|
|
// CHECK-NEXT: [[TMP3870:%.*]] = extractvalue { i64, i1 } [[TMP3868]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3870]], label [[LLX_ATOMIC_EXIT375:%.*]], label [[LLX_ATOMIC_CONT376:%.*]]
|
|
// CHECK: llx.atomic.cont376:
|
|
// CHECK-NEXT: store i64 [[TMP3869]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT375]]
|
|
// CHECK: llx.atomic.exit375:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3871:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3872:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3873:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3871]], i64 [[TMP3872]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3874:%.*]] = extractvalue { i64, i1 } [[TMP3873]], 0
|
|
// CHECK-NEXT: [[TMP3875:%.*]] = extractvalue { i64, i1 } [[TMP3873]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3875]], label [[LLX_ATOMIC_EXIT377:%.*]], label [[LLX_ATOMIC_CONT378:%.*]]
|
|
// CHECK: llx.atomic.cont378:
|
|
// CHECK-NEXT: store i64 [[TMP3874]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT377]]
|
|
// CHECK: llx.atomic.exit377:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3876:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3877:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3878:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3876]], i64 [[TMP3877]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3879:%.*]] = extractvalue { i64, i1 } [[TMP3878]], 1
|
|
// CHECK-NEXT: [[TMP3880:%.*]] = sext i1 [[TMP3879]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3880]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3881:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3882:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3883:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3881]], i64 [[TMP3882]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3884:%.*]] = extractvalue { i64, i1 } [[TMP3883]], 1
|
|
// CHECK-NEXT: [[TMP3885:%.*]] = sext i1 [[TMP3884]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3885]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3886:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3887:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3888:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3886]], i64 [[TMP3887]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3889:%.*]] = extractvalue { i64, i1 } [[TMP3888]], 0
|
|
// CHECK-NEXT: [[TMP3890:%.*]] = extractvalue { i64, i1 } [[TMP3888]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3890]], label [[LLX_ATOMIC_EXIT379:%.*]], label [[LLX_ATOMIC_CONT380:%.*]]
|
|
// CHECK: llx.atomic.cont380:
|
|
// CHECK-NEXT: store i64 [[TMP3889]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT379]]
|
|
// CHECK: llx.atomic.exit379:
|
|
// CHECK-NEXT: [[TMP3891:%.*]] = extractvalue { i64, i1 } [[TMP3888]], 1
|
|
// CHECK-NEXT: [[TMP3892:%.*]] = sext i1 [[TMP3891]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3892]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3893:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3894:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3895:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3893]], i64 [[TMP3894]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP3896:%.*]] = extractvalue { i64, i1 } [[TMP3895]], 0
|
|
// CHECK-NEXT: [[TMP3897:%.*]] = extractvalue { i64, i1 } [[TMP3895]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3897]], label [[LLX_ATOMIC_EXIT381:%.*]], label [[LLX_ATOMIC_CONT382:%.*]]
|
|
// CHECK: llx.atomic.cont382:
|
|
// CHECK-NEXT: store i64 [[TMP3896]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT381]]
|
|
// CHECK: llx.atomic.exit381:
|
|
// CHECK-NEXT: [[TMP3898:%.*]] = extractvalue { i64, i1 } [[TMP3895]], 1
|
|
// CHECK-NEXT: [[TMP3899:%.*]] = sext i1 [[TMP3898]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3899]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP3900:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3901:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3900]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3901]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3902:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3903:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3902]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3903]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3904:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3905:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3904]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3905]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3906:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3907:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3906]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3907]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3908:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3909:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3910:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3908]], i64 [[TMP3909]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3911:%.*]] = extractvalue { i64, i1 } [[TMP3910]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3911]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3912:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3913:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3914:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3912]], i64 [[TMP3913]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3915:%.*]] = extractvalue { i64, i1 } [[TMP3914]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3915]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3916:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3917:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3916]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP3918:%.*]] = icmp sgt i64 [[TMP3917]], [[TMP3916]]
|
|
// CHECK-NEXT: [[TMP3919:%.*]] = select i1 [[TMP3918]], i64 [[TMP3916]], i64 [[TMP3917]]
|
|
// CHECK-NEXT: store i64 [[TMP3919]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3920:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3921:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3920]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP3922:%.*]] = icmp slt i64 [[TMP3921]], [[TMP3920]]
|
|
// CHECK-NEXT: [[TMP3923:%.*]] = select i1 [[TMP3922]], i64 [[TMP3920]], i64 [[TMP3921]]
|
|
// CHECK-NEXT: store i64 [[TMP3923]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3924:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3925:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3924]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP3926:%.*]] = icmp slt i64 [[TMP3925]], [[TMP3924]]
|
|
// CHECK-NEXT: [[TMP3927:%.*]] = select i1 [[TMP3926]], i64 [[TMP3924]], i64 [[TMP3925]]
|
|
// CHECK-NEXT: store i64 [[TMP3927]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3928:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3929:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3928]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP3930:%.*]] = icmp sgt i64 [[TMP3929]], [[TMP3928]]
|
|
// CHECK-NEXT: [[TMP3931:%.*]] = select i1 [[TMP3930]], i64 [[TMP3928]], i64 [[TMP3929]]
|
|
// CHECK-NEXT: store i64 [[TMP3931]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3932:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3933:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3934:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3932]], i64 [[TMP3933]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3935:%.*]] = extractvalue { i64, i1 } [[TMP3934]], 0
|
|
// CHECK-NEXT: [[TMP3936:%.*]] = extractvalue { i64, i1 } [[TMP3934]], 1
|
|
// CHECK-NEXT: [[TMP3937:%.*]] = select i1 [[TMP3936]], i64 [[TMP3932]], i64 [[TMP3935]]
|
|
// CHECK-NEXT: store i64 [[TMP3937]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3938:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3939:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3940:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3938]], i64 [[TMP3939]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3941:%.*]] = extractvalue { i64, i1 } [[TMP3940]], 0
|
|
// CHECK-NEXT: [[TMP3942:%.*]] = extractvalue { i64, i1 } [[TMP3940]], 1
|
|
// CHECK-NEXT: [[TMP3943:%.*]] = select i1 [[TMP3942]], i64 [[TMP3938]], i64 [[TMP3941]]
|
|
// CHECK-NEXT: store i64 [[TMP3943]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3944:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3945:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3946:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3944]], i64 [[TMP3945]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3947:%.*]] = extractvalue { i64, i1 } [[TMP3946]], 0
|
|
// CHECK-NEXT: [[TMP3948:%.*]] = extractvalue { i64, i1 } [[TMP3946]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3948]], label [[LLX_ATOMIC_EXIT383:%.*]], label [[LLX_ATOMIC_CONT384:%.*]]
|
|
// CHECK: llx.atomic.cont384:
|
|
// CHECK-NEXT: store i64 [[TMP3947]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT383]]
|
|
// CHECK: llx.atomic.exit383:
|
|
// CHECK-NEXT: [[TMP3949:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3950:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3951:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3949]], i64 [[TMP3950]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3952:%.*]] = extractvalue { i64, i1 } [[TMP3951]], 0
|
|
// CHECK-NEXT: [[TMP3953:%.*]] = extractvalue { i64, i1 } [[TMP3951]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3953]], label [[LLX_ATOMIC_EXIT385:%.*]], label [[LLX_ATOMIC_CONT386:%.*]]
|
|
// CHECK: llx.atomic.cont386:
|
|
// CHECK-NEXT: store i64 [[TMP3952]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT385]]
|
|
// CHECK: llx.atomic.exit385:
|
|
// CHECK-NEXT: [[TMP3954:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3955:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3956:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3954]], i64 [[TMP3955]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3957:%.*]] = extractvalue { i64, i1 } [[TMP3956]], 1
|
|
// CHECK-NEXT: [[TMP3958:%.*]] = sext i1 [[TMP3957]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3958]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP3959:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3960:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3961:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3959]], i64 [[TMP3960]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3962:%.*]] = extractvalue { i64, i1 } [[TMP3961]], 1
|
|
// CHECK-NEXT: [[TMP3963:%.*]] = sext i1 [[TMP3962]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3963]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP3964:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3965:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3966:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3964]], i64 [[TMP3965]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3967:%.*]] = extractvalue { i64, i1 } [[TMP3966]], 0
|
|
// CHECK-NEXT: [[TMP3968:%.*]] = extractvalue { i64, i1 } [[TMP3966]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3968]], label [[LLX_ATOMIC_EXIT387:%.*]], label [[LLX_ATOMIC_CONT388:%.*]]
|
|
// CHECK: llx.atomic.cont388:
|
|
// CHECK-NEXT: store i64 [[TMP3967]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT387]]
|
|
// CHECK: llx.atomic.exit387:
|
|
// CHECK-NEXT: [[TMP3969:%.*]] = extractvalue { i64, i1 } [[TMP3966]], 1
|
|
// CHECK-NEXT: [[TMP3970:%.*]] = sext i1 [[TMP3969]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3970]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP3971:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3972:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3973:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3971]], i64 [[TMP3972]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP3974:%.*]] = extractvalue { i64, i1 } [[TMP3973]], 0
|
|
// CHECK-NEXT: [[TMP3975:%.*]] = extractvalue { i64, i1 } [[TMP3973]], 1
|
|
// CHECK-NEXT: br i1 [[TMP3975]], label [[LLX_ATOMIC_EXIT389:%.*]], label [[LLX_ATOMIC_CONT390:%.*]]
|
|
// CHECK: llx.atomic.cont390:
|
|
// CHECK-NEXT: store i64 [[TMP3974]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT389]]
|
|
// CHECK: llx.atomic.exit389:
|
|
// CHECK-NEXT: [[TMP3976:%.*]] = extractvalue { i64, i1 } [[TMP3973]], 1
|
|
// CHECK-NEXT: [[TMP3977:%.*]] = sext i1 [[TMP3976]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP3977]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP3978:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3979:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3978]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3979]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3980:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3981:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3980]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3981]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3982:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3983:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3982]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3983]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3984:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3985:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3984]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3985]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3986:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3987:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3988:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3986]], i64 [[TMP3987]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3989:%.*]] = extractvalue { i64, i1 } [[TMP3988]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3989]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3990:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3991:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP3992:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3990]], i64 [[TMP3991]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3993:%.*]] = extractvalue { i64, i1 } [[TMP3992]], 0
|
|
// CHECK-NEXT: store i64 [[TMP3993]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3994:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3995:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3994]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP3996:%.*]] = icmp sgt i64 [[TMP3995]], [[TMP3994]]
|
|
// CHECK-NEXT: [[TMP3997:%.*]] = select i1 [[TMP3996]], i64 [[TMP3994]], i64 [[TMP3995]]
|
|
// CHECK-NEXT: store i64 [[TMP3997]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP3998:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3999:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3998]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4000:%.*]] = icmp slt i64 [[TMP3999]], [[TMP3998]]
|
|
// CHECK-NEXT: [[TMP4001:%.*]] = select i1 [[TMP4000]], i64 [[TMP3998]], i64 [[TMP3999]]
|
|
// CHECK-NEXT: store i64 [[TMP4001]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP4002:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4003:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4002]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4004:%.*]] = icmp slt i64 [[TMP4003]], [[TMP4002]]
|
|
// CHECK-NEXT: [[TMP4005:%.*]] = select i1 [[TMP4004]], i64 [[TMP4002]], i64 [[TMP4003]]
|
|
// CHECK-NEXT: store i64 [[TMP4005]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP4006:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4007:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4006]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4008:%.*]] = icmp sgt i64 [[TMP4007]], [[TMP4006]]
|
|
// CHECK-NEXT: [[TMP4009:%.*]] = select i1 [[TMP4008]], i64 [[TMP4006]], i64 [[TMP4007]]
|
|
// CHECK-NEXT: store i64 [[TMP4009]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP4010:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4011:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4012:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4010]], i64 [[TMP4011]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4013:%.*]] = extractvalue { i64, i1 } [[TMP4012]], 0
|
|
// CHECK-NEXT: [[TMP4014:%.*]] = extractvalue { i64, i1 } [[TMP4012]], 1
|
|
// CHECK-NEXT: [[TMP4015:%.*]] = select i1 [[TMP4014]], i64 [[TMP4010]], i64 [[TMP4013]]
|
|
// CHECK-NEXT: store i64 [[TMP4015]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP4016:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4017:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4018:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4016]], i64 [[TMP4017]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4019:%.*]] = extractvalue { i64, i1 } [[TMP4018]], 0
|
|
// CHECK-NEXT: [[TMP4020:%.*]] = extractvalue { i64, i1 } [[TMP4018]], 1
|
|
// CHECK-NEXT: [[TMP4021:%.*]] = select i1 [[TMP4020]], i64 [[TMP4016]], i64 [[TMP4019]]
|
|
// CHECK-NEXT: store i64 [[TMP4021]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP4022:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4023:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4024:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4022]], i64 [[TMP4023]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4025:%.*]] = extractvalue { i64, i1 } [[TMP4024]], 0
|
|
// CHECK-NEXT: [[TMP4026:%.*]] = extractvalue { i64, i1 } [[TMP4024]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4026]], label [[LLX_ATOMIC_EXIT391:%.*]], label [[LLX_ATOMIC_CONT392:%.*]]
|
|
// CHECK: llx.atomic.cont392:
|
|
// CHECK-NEXT: store i64 [[TMP4025]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT391]]
|
|
// CHECK: llx.atomic.exit391:
|
|
// CHECK-NEXT: [[TMP4027:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4028:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4029:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4027]], i64 [[TMP4028]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4030:%.*]] = extractvalue { i64, i1 } [[TMP4029]], 0
|
|
// CHECK-NEXT: [[TMP4031:%.*]] = extractvalue { i64, i1 } [[TMP4029]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4031]], label [[LLX_ATOMIC_EXIT393:%.*]], label [[LLX_ATOMIC_CONT394:%.*]]
|
|
// CHECK: llx.atomic.cont394:
|
|
// CHECK-NEXT: store i64 [[TMP4030]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT393]]
|
|
// CHECK: llx.atomic.exit393:
|
|
// CHECK-NEXT: [[TMP4032:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4033:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4034:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4032]], i64 [[TMP4033]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4035:%.*]] = extractvalue { i64, i1 } [[TMP4034]], 1
|
|
// CHECK-NEXT: [[TMP4036:%.*]] = sext i1 [[TMP4035]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4036]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP4037:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4038:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4039:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4037]], i64 [[TMP4038]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4040:%.*]] = extractvalue { i64, i1 } [[TMP4039]], 1
|
|
// CHECK-NEXT: [[TMP4041:%.*]] = sext i1 [[TMP4040]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4041]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP4042:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4043:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4044:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4042]], i64 [[TMP4043]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4045:%.*]] = extractvalue { i64, i1 } [[TMP4044]], 0
|
|
// CHECK-NEXT: [[TMP4046:%.*]] = extractvalue { i64, i1 } [[TMP4044]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4046]], label [[LLX_ATOMIC_EXIT395:%.*]], label [[LLX_ATOMIC_CONT396:%.*]]
|
|
// CHECK: llx.atomic.cont396:
|
|
// CHECK-NEXT: store i64 [[TMP4045]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT395]]
|
|
// CHECK: llx.atomic.exit395:
|
|
// CHECK-NEXT: [[TMP4047:%.*]] = extractvalue { i64, i1 } [[TMP4044]], 1
|
|
// CHECK-NEXT: [[TMP4048:%.*]] = sext i1 [[TMP4047]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4048]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP4049:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4050:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4051:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4049]], i64 [[TMP4050]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4052:%.*]] = extractvalue { i64, i1 } [[TMP4051]], 0
|
|
// CHECK-NEXT: [[TMP4053:%.*]] = extractvalue { i64, i1 } [[TMP4051]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4053]], label [[LLX_ATOMIC_EXIT397:%.*]], label [[LLX_ATOMIC_CONT398:%.*]]
|
|
// CHECK: llx.atomic.cont398:
|
|
// CHECK-NEXT: store i64 [[TMP4052]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT397]]
|
|
// CHECK: llx.atomic.exit397:
|
|
// CHECK-NEXT: [[TMP4054:%.*]] = extractvalue { i64, i1 } [[TMP4051]], 1
|
|
// CHECK-NEXT: [[TMP4055:%.*]] = sext i1 [[TMP4054]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4055]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: [[TMP4056:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4057:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4056]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4057]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4058:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4059:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4058]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4059]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4060:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4061:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4060]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4061]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4062:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4063:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4062]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4063]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4064:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4065:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4066:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4064]], i64 [[TMP4065]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4067:%.*]] = extractvalue { i64, i1 } [[TMP4066]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4067]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4068:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4069:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4070:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4068]], i64 [[TMP4069]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4071:%.*]] = extractvalue { i64, i1 } [[TMP4070]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4071]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4072:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4073:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4072]] release, align 8
|
|
// CHECK-NEXT: [[TMP4074:%.*]] = icmp sgt i64 [[TMP4073]], [[TMP4072]]
|
|
// CHECK-NEXT: [[TMP4075:%.*]] = select i1 [[TMP4074]], i64 [[TMP4072]], i64 [[TMP4073]]
|
|
// CHECK-NEXT: store i64 [[TMP4075]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4076:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4077:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4076]] release, align 8
|
|
// CHECK-NEXT: [[TMP4078:%.*]] = icmp slt i64 [[TMP4077]], [[TMP4076]]
|
|
// CHECK-NEXT: [[TMP4079:%.*]] = select i1 [[TMP4078]], i64 [[TMP4076]], i64 [[TMP4077]]
|
|
// CHECK-NEXT: store i64 [[TMP4079]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4080:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4081:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4080]] release, align 8
|
|
// CHECK-NEXT: [[TMP4082:%.*]] = icmp slt i64 [[TMP4081]], [[TMP4080]]
|
|
// CHECK-NEXT: [[TMP4083:%.*]] = select i1 [[TMP4082]], i64 [[TMP4080]], i64 [[TMP4081]]
|
|
// CHECK-NEXT: store i64 [[TMP4083]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4084:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4085:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4084]] release, align 8
|
|
// CHECK-NEXT: [[TMP4086:%.*]] = icmp sgt i64 [[TMP4085]], [[TMP4084]]
|
|
// CHECK-NEXT: [[TMP4087:%.*]] = select i1 [[TMP4086]], i64 [[TMP4084]], i64 [[TMP4085]]
|
|
// CHECK-NEXT: store i64 [[TMP4087]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4088:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4089:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4090:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4088]], i64 [[TMP4089]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4091:%.*]] = extractvalue { i64, i1 } [[TMP4090]], 0
|
|
// CHECK-NEXT: [[TMP4092:%.*]] = extractvalue { i64, i1 } [[TMP4090]], 1
|
|
// CHECK-NEXT: [[TMP4093:%.*]] = select i1 [[TMP4092]], i64 [[TMP4088]], i64 [[TMP4091]]
|
|
// CHECK-NEXT: store i64 [[TMP4093]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4094:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4095:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4096:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4094]], i64 [[TMP4095]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4097:%.*]] = extractvalue { i64, i1 } [[TMP4096]], 0
|
|
// CHECK-NEXT: [[TMP4098:%.*]] = extractvalue { i64, i1 } [[TMP4096]], 1
|
|
// CHECK-NEXT: [[TMP4099:%.*]] = select i1 [[TMP4098]], i64 [[TMP4094]], i64 [[TMP4097]]
|
|
// CHECK-NEXT: store i64 [[TMP4099]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4100:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4101:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4102:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4100]], i64 [[TMP4101]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4103:%.*]] = extractvalue { i64, i1 } [[TMP4102]], 0
|
|
// CHECK-NEXT: [[TMP4104:%.*]] = extractvalue { i64, i1 } [[TMP4102]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4104]], label [[LLX_ATOMIC_EXIT399:%.*]], label [[LLX_ATOMIC_CONT400:%.*]]
|
|
// CHECK: llx.atomic.cont400:
|
|
// CHECK-NEXT: store i64 [[TMP4103]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT399]]
|
|
// CHECK: llx.atomic.exit399:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4105:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4106:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4107:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4105]], i64 [[TMP4106]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4108:%.*]] = extractvalue { i64, i1 } [[TMP4107]], 0
|
|
// CHECK-NEXT: [[TMP4109:%.*]] = extractvalue { i64, i1 } [[TMP4107]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4109]], label [[LLX_ATOMIC_EXIT401:%.*]], label [[LLX_ATOMIC_CONT402:%.*]]
|
|
// CHECK: llx.atomic.cont402:
|
|
// CHECK-NEXT: store i64 [[TMP4108]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT401]]
|
|
// CHECK: llx.atomic.exit401:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4110:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4111:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4112:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4110]], i64 [[TMP4111]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4113:%.*]] = extractvalue { i64, i1 } [[TMP4112]], 1
|
|
// CHECK-NEXT: [[TMP4114:%.*]] = sext i1 [[TMP4113]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4114]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4115:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4116:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4117:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4115]], i64 [[TMP4116]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4118:%.*]] = extractvalue { i64, i1 } [[TMP4117]], 1
|
|
// CHECK-NEXT: [[TMP4119:%.*]] = sext i1 [[TMP4118]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4119]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4120:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4121:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4122:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4120]], i64 [[TMP4121]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4123:%.*]] = extractvalue { i64, i1 } [[TMP4122]], 0
|
|
// CHECK-NEXT: [[TMP4124:%.*]] = extractvalue { i64, i1 } [[TMP4122]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4124]], label [[LLX_ATOMIC_EXIT403:%.*]], label [[LLX_ATOMIC_CONT404:%.*]]
|
|
// CHECK: llx.atomic.cont404:
|
|
// CHECK-NEXT: store i64 [[TMP4123]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT403]]
|
|
// CHECK: llx.atomic.exit403:
|
|
// CHECK-NEXT: [[TMP4125:%.*]] = extractvalue { i64, i1 } [[TMP4122]], 1
|
|
// CHECK-NEXT: [[TMP4126:%.*]] = sext i1 [[TMP4125]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4126]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4127:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4128:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4129:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4127]], i64 [[TMP4128]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4130:%.*]] = extractvalue { i64, i1 } [[TMP4129]], 0
|
|
// CHECK-NEXT: [[TMP4131:%.*]] = extractvalue { i64, i1 } [[TMP4129]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4131]], label [[LLX_ATOMIC_EXIT405:%.*]], label [[LLX_ATOMIC_CONT406:%.*]]
|
|
// CHECK: llx.atomic.cont406:
|
|
// CHECK-NEXT: store i64 [[TMP4130]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT405]]
|
|
// CHECK: llx.atomic.exit405:
|
|
// CHECK-NEXT: [[TMP4132:%.*]] = extractvalue { i64, i1 } [[TMP4129]], 1
|
|
// CHECK-NEXT: [[TMP4133:%.*]] = sext i1 [[TMP4132]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4133]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4134:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4135:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4134]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4135]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4136:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4137:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4136]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4137]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4138:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4139:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4138]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4139]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4140:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4141:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4140]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4141]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4142:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4143:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4144:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4142]], i64 [[TMP4143]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4145:%.*]] = extractvalue { i64, i1 } [[TMP4144]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4145]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4146:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4147:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4148:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4146]], i64 [[TMP4147]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4149:%.*]] = extractvalue { i64, i1 } [[TMP4148]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4149]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4150:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4151:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4150]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4152:%.*]] = icmp sgt i64 [[TMP4151]], [[TMP4150]]
|
|
// CHECK-NEXT: [[TMP4153:%.*]] = select i1 [[TMP4152]], i64 [[TMP4150]], i64 [[TMP4151]]
|
|
// CHECK-NEXT: store i64 [[TMP4153]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4154:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4155:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4154]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4156:%.*]] = icmp slt i64 [[TMP4155]], [[TMP4154]]
|
|
// CHECK-NEXT: [[TMP4157:%.*]] = select i1 [[TMP4156]], i64 [[TMP4154]], i64 [[TMP4155]]
|
|
// CHECK-NEXT: store i64 [[TMP4157]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4158:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4159:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4158]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4160:%.*]] = icmp slt i64 [[TMP4159]], [[TMP4158]]
|
|
// CHECK-NEXT: [[TMP4161:%.*]] = select i1 [[TMP4160]], i64 [[TMP4158]], i64 [[TMP4159]]
|
|
// CHECK-NEXT: store i64 [[TMP4161]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4162:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4163:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4162]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4164:%.*]] = icmp sgt i64 [[TMP4163]], [[TMP4162]]
|
|
// CHECK-NEXT: [[TMP4165:%.*]] = select i1 [[TMP4164]], i64 [[TMP4162]], i64 [[TMP4163]]
|
|
// CHECK-NEXT: store i64 [[TMP4165]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4166:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4167:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4168:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4166]], i64 [[TMP4167]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4169:%.*]] = extractvalue { i64, i1 } [[TMP4168]], 0
|
|
// CHECK-NEXT: [[TMP4170:%.*]] = extractvalue { i64, i1 } [[TMP4168]], 1
|
|
// CHECK-NEXT: [[TMP4171:%.*]] = select i1 [[TMP4170]], i64 [[TMP4166]], i64 [[TMP4169]]
|
|
// CHECK-NEXT: store i64 [[TMP4171]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4172:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4173:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4174:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4172]], i64 [[TMP4173]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4175:%.*]] = extractvalue { i64, i1 } [[TMP4174]], 0
|
|
// CHECK-NEXT: [[TMP4176:%.*]] = extractvalue { i64, i1 } [[TMP4174]], 1
|
|
// CHECK-NEXT: [[TMP4177:%.*]] = select i1 [[TMP4176]], i64 [[TMP4172]], i64 [[TMP4175]]
|
|
// CHECK-NEXT: store i64 [[TMP4177]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4178:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4179:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4180:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4178]], i64 [[TMP4179]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4181:%.*]] = extractvalue { i64, i1 } [[TMP4180]], 0
|
|
// CHECK-NEXT: [[TMP4182:%.*]] = extractvalue { i64, i1 } [[TMP4180]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4182]], label [[LLX_ATOMIC_EXIT407:%.*]], label [[LLX_ATOMIC_CONT408:%.*]]
|
|
// CHECK: llx.atomic.cont408:
|
|
// CHECK-NEXT: store i64 [[TMP4181]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT407]]
|
|
// CHECK: llx.atomic.exit407:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4183:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4184:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4185:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4183]], i64 [[TMP4184]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4186:%.*]] = extractvalue { i64, i1 } [[TMP4185]], 0
|
|
// CHECK-NEXT: [[TMP4187:%.*]] = extractvalue { i64, i1 } [[TMP4185]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4187]], label [[LLX_ATOMIC_EXIT409:%.*]], label [[LLX_ATOMIC_CONT410:%.*]]
|
|
// CHECK: llx.atomic.cont410:
|
|
// CHECK-NEXT: store i64 [[TMP4186]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT409]]
|
|
// CHECK: llx.atomic.exit409:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4188:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4189:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4190:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4188]], i64 [[TMP4189]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4191:%.*]] = extractvalue { i64, i1 } [[TMP4190]], 1
|
|
// CHECK-NEXT: [[TMP4192:%.*]] = sext i1 [[TMP4191]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4192]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4193:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4194:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4195:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4193]], i64 [[TMP4194]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4196:%.*]] = extractvalue { i64, i1 } [[TMP4195]], 1
|
|
// CHECK-NEXT: [[TMP4197:%.*]] = sext i1 [[TMP4196]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4197]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4198:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4199:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4200:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4198]], i64 [[TMP4199]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4201:%.*]] = extractvalue { i64, i1 } [[TMP4200]], 0
|
|
// CHECK-NEXT: [[TMP4202:%.*]] = extractvalue { i64, i1 } [[TMP4200]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4202]], label [[LLX_ATOMIC_EXIT411:%.*]], label [[LLX_ATOMIC_CONT412:%.*]]
|
|
// CHECK: llx.atomic.cont412:
|
|
// CHECK-NEXT: store i64 [[TMP4201]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT411]]
|
|
// CHECK: llx.atomic.exit411:
|
|
// CHECK-NEXT: [[TMP4203:%.*]] = extractvalue { i64, i1 } [[TMP4200]], 1
|
|
// CHECK-NEXT: [[TMP4204:%.*]] = sext i1 [[TMP4203]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4204]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4205:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP4206:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP4207:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4205]], i64 [[TMP4206]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4208:%.*]] = extractvalue { i64, i1 } [[TMP4207]], 0
|
|
// CHECK-NEXT: [[TMP4209:%.*]] = extractvalue { i64, i1 } [[TMP4207]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4209]], label [[LLX_ATOMIC_EXIT413:%.*]], label [[LLX_ATOMIC_CONT414:%.*]]
|
|
// CHECK: llx.atomic.cont414:
|
|
// CHECK-NEXT: store i64 [[TMP4208]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT413]]
|
|
// CHECK: llx.atomic.exit413:
|
|
// CHECK-NEXT: [[TMP4210:%.*]] = extractvalue { i64, i1 } [[TMP4207]], 1
|
|
// CHECK-NEXT: [[TMP4211:%.*]] = sext i1 [[TMP4210]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4211]], ptr [[LLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4212:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4213:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4212]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4213]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4214:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4215:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4214]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4215]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4216:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4217:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4216]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4217]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4218:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4219:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4218]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4219]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4220:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4221:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4222:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4220]], i64 [[TMP4221]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4223:%.*]] = extractvalue { i64, i1 } [[TMP4222]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4223]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4224:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4225:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4226:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4224]], i64 [[TMP4225]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4227:%.*]] = extractvalue { i64, i1 } [[TMP4226]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4227]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4228:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4229:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4228]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4230:%.*]] = icmp ugt i64 [[TMP4229]], [[TMP4228]]
|
|
// CHECK-NEXT: [[TMP4231:%.*]] = select i1 [[TMP4230]], i64 [[TMP4228]], i64 [[TMP4229]]
|
|
// CHECK-NEXT: store i64 [[TMP4231]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4232:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4233:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4232]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4234:%.*]] = icmp ult i64 [[TMP4233]], [[TMP4232]]
|
|
// CHECK-NEXT: [[TMP4235:%.*]] = select i1 [[TMP4234]], i64 [[TMP4232]], i64 [[TMP4233]]
|
|
// CHECK-NEXT: store i64 [[TMP4235]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4236:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4237:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4236]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4238:%.*]] = icmp ult i64 [[TMP4237]], [[TMP4236]]
|
|
// CHECK-NEXT: [[TMP4239:%.*]] = select i1 [[TMP4238]], i64 [[TMP4236]], i64 [[TMP4237]]
|
|
// CHECK-NEXT: store i64 [[TMP4239]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4240:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4241:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4240]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4242:%.*]] = icmp ugt i64 [[TMP4241]], [[TMP4240]]
|
|
// CHECK-NEXT: [[TMP4243:%.*]] = select i1 [[TMP4242]], i64 [[TMP4240]], i64 [[TMP4241]]
|
|
// CHECK-NEXT: store i64 [[TMP4243]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4244:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4245:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4246:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4244]], i64 [[TMP4245]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4247:%.*]] = extractvalue { i64, i1 } [[TMP4246]], 0
|
|
// CHECK-NEXT: [[TMP4248:%.*]] = extractvalue { i64, i1 } [[TMP4246]], 1
|
|
// CHECK-NEXT: [[TMP4249:%.*]] = select i1 [[TMP4248]], i64 [[TMP4244]], i64 [[TMP4247]]
|
|
// CHECK-NEXT: store i64 [[TMP4249]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4250:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4251:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4252:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4250]], i64 [[TMP4251]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4253:%.*]] = extractvalue { i64, i1 } [[TMP4252]], 0
|
|
// CHECK-NEXT: [[TMP4254:%.*]] = extractvalue { i64, i1 } [[TMP4252]], 1
|
|
// CHECK-NEXT: [[TMP4255:%.*]] = select i1 [[TMP4254]], i64 [[TMP4250]], i64 [[TMP4253]]
|
|
// CHECK-NEXT: store i64 [[TMP4255]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4256:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4257:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4258:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4256]], i64 [[TMP4257]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4259:%.*]] = extractvalue { i64, i1 } [[TMP4258]], 0
|
|
// CHECK-NEXT: [[TMP4260:%.*]] = extractvalue { i64, i1 } [[TMP4258]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4260]], label [[ULLX_ATOMIC_EXIT:%.*]], label [[ULLX_ATOMIC_CONT:%.*]]
|
|
// CHECK: ullx.atomic.cont:
|
|
// CHECK-NEXT: store i64 [[TMP4259]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT]]
|
|
// CHECK: ullx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP4261:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4262:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4263:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4261]], i64 [[TMP4262]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4264:%.*]] = extractvalue { i64, i1 } [[TMP4263]], 0
|
|
// CHECK-NEXT: [[TMP4265:%.*]] = extractvalue { i64, i1 } [[TMP4263]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4265]], label [[ULLX_ATOMIC_EXIT415:%.*]], label [[ULLX_ATOMIC_CONT416:%.*]]
|
|
// CHECK: ullx.atomic.cont416:
|
|
// CHECK-NEXT: store i64 [[TMP4264]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT415]]
|
|
// CHECK: ullx.atomic.exit415:
|
|
// CHECK-NEXT: [[TMP4266:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4267:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4268:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4266]], i64 [[TMP4267]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4269:%.*]] = extractvalue { i64, i1 } [[TMP4268]], 1
|
|
// CHECK-NEXT: [[TMP4270:%.*]] = zext i1 [[TMP4269]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4270]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4271:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4272:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4273:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4271]], i64 [[TMP4272]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4274:%.*]] = extractvalue { i64, i1 } [[TMP4273]], 1
|
|
// CHECK-NEXT: [[TMP4275:%.*]] = zext i1 [[TMP4274]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4275]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4276:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4277:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4278:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4276]], i64 [[TMP4277]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4279:%.*]] = extractvalue { i64, i1 } [[TMP4278]], 0
|
|
// CHECK-NEXT: [[TMP4280:%.*]] = extractvalue { i64, i1 } [[TMP4278]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4280]], label [[ULLX_ATOMIC_EXIT417:%.*]], label [[ULLX_ATOMIC_CONT418:%.*]]
|
|
// CHECK: ullx.atomic.cont418:
|
|
// CHECK-NEXT: store i64 [[TMP4279]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT417]]
|
|
// CHECK: ullx.atomic.exit417:
|
|
// CHECK-NEXT: [[TMP4281:%.*]] = extractvalue { i64, i1 } [[TMP4278]], 1
|
|
// CHECK-NEXT: [[TMP4282:%.*]] = zext i1 [[TMP4281]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4282]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4283:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4284:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4285:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4283]], i64 [[TMP4284]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4286:%.*]] = extractvalue { i64, i1 } [[TMP4285]], 0
|
|
// CHECK-NEXT: [[TMP4287:%.*]] = extractvalue { i64, i1 } [[TMP4285]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4287]], label [[ULLX_ATOMIC_EXIT419:%.*]], label [[ULLX_ATOMIC_CONT420:%.*]]
|
|
// CHECK: ullx.atomic.cont420:
|
|
// CHECK-NEXT: store i64 [[TMP4286]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT419]]
|
|
// CHECK: ullx.atomic.exit419:
|
|
// CHECK-NEXT: [[TMP4288:%.*]] = extractvalue { i64, i1 } [[TMP4285]], 1
|
|
// CHECK-NEXT: [[TMP4289:%.*]] = zext i1 [[TMP4288]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4289]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4290:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4291:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4290]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4291]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4292:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4293:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4292]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4293]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4294:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4295:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4294]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4295]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4296:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4297:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4296]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4297]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4298:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4299:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4300:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4298]], i64 [[TMP4299]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4301:%.*]] = extractvalue { i64, i1 } [[TMP4300]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4301]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4302:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4303:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4304:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4302]], i64 [[TMP4303]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4305:%.*]] = extractvalue { i64, i1 } [[TMP4304]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4305]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4306:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4307:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4306]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP4308:%.*]] = icmp ugt i64 [[TMP4307]], [[TMP4306]]
|
|
// CHECK-NEXT: [[TMP4309:%.*]] = select i1 [[TMP4308]], i64 [[TMP4306]], i64 [[TMP4307]]
|
|
// CHECK-NEXT: store i64 [[TMP4309]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4310:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4311:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4310]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP4312:%.*]] = icmp ult i64 [[TMP4311]], [[TMP4310]]
|
|
// CHECK-NEXT: [[TMP4313:%.*]] = select i1 [[TMP4312]], i64 [[TMP4310]], i64 [[TMP4311]]
|
|
// CHECK-NEXT: store i64 [[TMP4313]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4314:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4315:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4314]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP4316:%.*]] = icmp ult i64 [[TMP4315]], [[TMP4314]]
|
|
// CHECK-NEXT: [[TMP4317:%.*]] = select i1 [[TMP4316]], i64 [[TMP4314]], i64 [[TMP4315]]
|
|
// CHECK-NEXT: store i64 [[TMP4317]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4318:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4319:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4318]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP4320:%.*]] = icmp ugt i64 [[TMP4319]], [[TMP4318]]
|
|
// CHECK-NEXT: [[TMP4321:%.*]] = select i1 [[TMP4320]], i64 [[TMP4318]], i64 [[TMP4319]]
|
|
// CHECK-NEXT: store i64 [[TMP4321]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4322:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4323:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4324:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4322]], i64 [[TMP4323]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4325:%.*]] = extractvalue { i64, i1 } [[TMP4324]], 0
|
|
// CHECK-NEXT: [[TMP4326:%.*]] = extractvalue { i64, i1 } [[TMP4324]], 1
|
|
// CHECK-NEXT: [[TMP4327:%.*]] = select i1 [[TMP4326]], i64 [[TMP4322]], i64 [[TMP4325]]
|
|
// CHECK-NEXT: store i64 [[TMP4327]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4328:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4329:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4330:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4328]], i64 [[TMP4329]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4331:%.*]] = extractvalue { i64, i1 } [[TMP4330]], 0
|
|
// CHECK-NEXT: [[TMP4332:%.*]] = extractvalue { i64, i1 } [[TMP4330]], 1
|
|
// CHECK-NEXT: [[TMP4333:%.*]] = select i1 [[TMP4332]], i64 [[TMP4328]], i64 [[TMP4331]]
|
|
// CHECK-NEXT: store i64 [[TMP4333]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4334:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4335:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4336:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4334]], i64 [[TMP4335]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4337:%.*]] = extractvalue { i64, i1 } [[TMP4336]], 0
|
|
// CHECK-NEXT: [[TMP4338:%.*]] = extractvalue { i64, i1 } [[TMP4336]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4338]], label [[ULLX_ATOMIC_EXIT421:%.*]], label [[ULLX_ATOMIC_CONT422:%.*]]
|
|
// CHECK: ullx.atomic.cont422:
|
|
// CHECK-NEXT: store i64 [[TMP4337]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT421]]
|
|
// CHECK: ullx.atomic.exit421:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4339:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4340:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4341:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4339]], i64 [[TMP4340]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4342:%.*]] = extractvalue { i64, i1 } [[TMP4341]], 0
|
|
// CHECK-NEXT: [[TMP4343:%.*]] = extractvalue { i64, i1 } [[TMP4341]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4343]], label [[ULLX_ATOMIC_EXIT423:%.*]], label [[ULLX_ATOMIC_CONT424:%.*]]
|
|
// CHECK: ullx.atomic.cont424:
|
|
// CHECK-NEXT: store i64 [[TMP4342]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT423]]
|
|
// CHECK: ullx.atomic.exit423:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4344:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4345:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4346:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4344]], i64 [[TMP4345]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4347:%.*]] = extractvalue { i64, i1 } [[TMP4346]], 1
|
|
// CHECK-NEXT: [[TMP4348:%.*]] = zext i1 [[TMP4347]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4348]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4349:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4350:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4351:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4349]], i64 [[TMP4350]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4352:%.*]] = extractvalue { i64, i1 } [[TMP4351]], 1
|
|
// CHECK-NEXT: [[TMP4353:%.*]] = zext i1 [[TMP4352]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4353]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4354:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4355:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4356:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4354]], i64 [[TMP4355]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4357:%.*]] = extractvalue { i64, i1 } [[TMP4356]], 0
|
|
// CHECK-NEXT: [[TMP4358:%.*]] = extractvalue { i64, i1 } [[TMP4356]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4358]], label [[ULLX_ATOMIC_EXIT425:%.*]], label [[ULLX_ATOMIC_CONT426:%.*]]
|
|
// CHECK: ullx.atomic.cont426:
|
|
// CHECK-NEXT: store i64 [[TMP4357]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT425]]
|
|
// CHECK: ullx.atomic.exit425:
|
|
// CHECK-NEXT: [[TMP4359:%.*]] = extractvalue { i64, i1 } [[TMP4356]], 1
|
|
// CHECK-NEXT: [[TMP4360:%.*]] = zext i1 [[TMP4359]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4360]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4361:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4362:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4363:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4361]], i64 [[TMP4362]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP4364:%.*]] = extractvalue { i64, i1 } [[TMP4363]], 0
|
|
// CHECK-NEXT: [[TMP4365:%.*]] = extractvalue { i64, i1 } [[TMP4363]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4365]], label [[ULLX_ATOMIC_EXIT427:%.*]], label [[ULLX_ATOMIC_CONT428:%.*]]
|
|
// CHECK: ullx.atomic.cont428:
|
|
// CHECK-NEXT: store i64 [[TMP4364]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT427]]
|
|
// CHECK: ullx.atomic.exit427:
|
|
// CHECK-NEXT: [[TMP4366:%.*]] = extractvalue { i64, i1 } [[TMP4363]], 1
|
|
// CHECK-NEXT: [[TMP4367:%.*]] = zext i1 [[TMP4366]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4367]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4368:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4369:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4368]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4369]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4370:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4371:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4370]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4371]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4372:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4373:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4372]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4373]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4374:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4375:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4374]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4375]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4376:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4377:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4378:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4376]], i64 [[TMP4377]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4379:%.*]] = extractvalue { i64, i1 } [[TMP4378]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4379]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4380:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4381:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4382:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4380]], i64 [[TMP4381]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4383:%.*]] = extractvalue { i64, i1 } [[TMP4382]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4383]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4384:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4385:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4384]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP4386:%.*]] = icmp ugt i64 [[TMP4385]], [[TMP4384]]
|
|
// CHECK-NEXT: [[TMP4387:%.*]] = select i1 [[TMP4386]], i64 [[TMP4384]], i64 [[TMP4385]]
|
|
// CHECK-NEXT: store i64 [[TMP4387]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4388:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4389:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4388]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP4390:%.*]] = icmp ult i64 [[TMP4389]], [[TMP4388]]
|
|
// CHECK-NEXT: [[TMP4391:%.*]] = select i1 [[TMP4390]], i64 [[TMP4388]], i64 [[TMP4389]]
|
|
// CHECK-NEXT: store i64 [[TMP4391]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4392:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4393:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4392]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP4394:%.*]] = icmp ult i64 [[TMP4393]], [[TMP4392]]
|
|
// CHECK-NEXT: [[TMP4395:%.*]] = select i1 [[TMP4394]], i64 [[TMP4392]], i64 [[TMP4393]]
|
|
// CHECK-NEXT: store i64 [[TMP4395]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4396:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4397:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4396]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP4398:%.*]] = icmp ugt i64 [[TMP4397]], [[TMP4396]]
|
|
// CHECK-NEXT: [[TMP4399:%.*]] = select i1 [[TMP4398]], i64 [[TMP4396]], i64 [[TMP4397]]
|
|
// CHECK-NEXT: store i64 [[TMP4399]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4400:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4401:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4402:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4400]], i64 [[TMP4401]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4403:%.*]] = extractvalue { i64, i1 } [[TMP4402]], 0
|
|
// CHECK-NEXT: [[TMP4404:%.*]] = extractvalue { i64, i1 } [[TMP4402]], 1
|
|
// CHECK-NEXT: [[TMP4405:%.*]] = select i1 [[TMP4404]], i64 [[TMP4400]], i64 [[TMP4403]]
|
|
// CHECK-NEXT: store i64 [[TMP4405]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4406:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4407:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4408:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4406]], i64 [[TMP4407]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4409:%.*]] = extractvalue { i64, i1 } [[TMP4408]], 0
|
|
// CHECK-NEXT: [[TMP4410:%.*]] = extractvalue { i64, i1 } [[TMP4408]], 1
|
|
// CHECK-NEXT: [[TMP4411:%.*]] = select i1 [[TMP4410]], i64 [[TMP4406]], i64 [[TMP4409]]
|
|
// CHECK-NEXT: store i64 [[TMP4411]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4412:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4413:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4414:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4412]], i64 [[TMP4413]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4415:%.*]] = extractvalue { i64, i1 } [[TMP4414]], 0
|
|
// CHECK-NEXT: [[TMP4416:%.*]] = extractvalue { i64, i1 } [[TMP4414]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4416]], label [[ULLX_ATOMIC_EXIT429:%.*]], label [[ULLX_ATOMIC_CONT430:%.*]]
|
|
// CHECK: ullx.atomic.cont430:
|
|
// CHECK-NEXT: store i64 [[TMP4415]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT429]]
|
|
// CHECK: ullx.atomic.exit429:
|
|
// CHECK-NEXT: [[TMP4417:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4418:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4419:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4417]], i64 [[TMP4418]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4420:%.*]] = extractvalue { i64, i1 } [[TMP4419]], 0
|
|
// CHECK-NEXT: [[TMP4421:%.*]] = extractvalue { i64, i1 } [[TMP4419]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4421]], label [[ULLX_ATOMIC_EXIT431:%.*]], label [[ULLX_ATOMIC_CONT432:%.*]]
|
|
// CHECK: ullx.atomic.cont432:
|
|
// CHECK-NEXT: store i64 [[TMP4420]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT431]]
|
|
// CHECK: ullx.atomic.exit431:
|
|
// CHECK-NEXT: [[TMP4422:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4423:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4424:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4422]], i64 [[TMP4423]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4425:%.*]] = extractvalue { i64, i1 } [[TMP4424]], 1
|
|
// CHECK-NEXT: [[TMP4426:%.*]] = zext i1 [[TMP4425]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4426]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4427:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4428:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4429:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4427]], i64 [[TMP4428]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4430:%.*]] = extractvalue { i64, i1 } [[TMP4429]], 1
|
|
// CHECK-NEXT: [[TMP4431:%.*]] = zext i1 [[TMP4430]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4431]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4432:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4433:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4434:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4432]], i64 [[TMP4433]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4435:%.*]] = extractvalue { i64, i1 } [[TMP4434]], 0
|
|
// CHECK-NEXT: [[TMP4436:%.*]] = extractvalue { i64, i1 } [[TMP4434]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4436]], label [[ULLX_ATOMIC_EXIT433:%.*]], label [[ULLX_ATOMIC_CONT434:%.*]]
|
|
// CHECK: ullx.atomic.cont434:
|
|
// CHECK-NEXT: store i64 [[TMP4435]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT433]]
|
|
// CHECK: ullx.atomic.exit433:
|
|
// CHECK-NEXT: [[TMP4437:%.*]] = extractvalue { i64, i1 } [[TMP4434]], 1
|
|
// CHECK-NEXT: [[TMP4438:%.*]] = zext i1 [[TMP4437]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4438]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4439:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4440:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4441:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4439]], i64 [[TMP4440]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP4442:%.*]] = extractvalue { i64, i1 } [[TMP4441]], 0
|
|
// CHECK-NEXT: [[TMP4443:%.*]] = extractvalue { i64, i1 } [[TMP4441]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4443]], label [[ULLX_ATOMIC_EXIT435:%.*]], label [[ULLX_ATOMIC_CONT436:%.*]]
|
|
// CHECK: ullx.atomic.cont436:
|
|
// CHECK-NEXT: store i64 [[TMP4442]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT435]]
|
|
// CHECK: ullx.atomic.exit435:
|
|
// CHECK-NEXT: [[TMP4444:%.*]] = extractvalue { i64, i1 } [[TMP4441]], 1
|
|
// CHECK-NEXT: [[TMP4445:%.*]] = zext i1 [[TMP4444]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4445]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4446:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4447:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4446]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4447]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4448:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4449:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4448]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4449]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4450:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4451:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4450]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4451]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4452:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4453:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4452]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4453]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4454:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4455:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4456:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4454]], i64 [[TMP4455]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4457:%.*]] = extractvalue { i64, i1 } [[TMP4456]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4457]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4458:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4459:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4460:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4458]], i64 [[TMP4459]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4461:%.*]] = extractvalue { i64, i1 } [[TMP4460]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4461]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4462:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4463:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4462]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4464:%.*]] = icmp ugt i64 [[TMP4463]], [[TMP4462]]
|
|
// CHECK-NEXT: [[TMP4465:%.*]] = select i1 [[TMP4464]], i64 [[TMP4462]], i64 [[TMP4463]]
|
|
// CHECK-NEXT: store i64 [[TMP4465]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4466:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4467:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4466]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4468:%.*]] = icmp ult i64 [[TMP4467]], [[TMP4466]]
|
|
// CHECK-NEXT: [[TMP4469:%.*]] = select i1 [[TMP4468]], i64 [[TMP4466]], i64 [[TMP4467]]
|
|
// CHECK-NEXT: store i64 [[TMP4469]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4470:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4471:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4470]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4472:%.*]] = icmp ult i64 [[TMP4471]], [[TMP4470]]
|
|
// CHECK-NEXT: [[TMP4473:%.*]] = select i1 [[TMP4472]], i64 [[TMP4470]], i64 [[TMP4471]]
|
|
// CHECK-NEXT: store i64 [[TMP4473]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4474:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4475:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4474]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4476:%.*]] = icmp ugt i64 [[TMP4475]], [[TMP4474]]
|
|
// CHECK-NEXT: [[TMP4477:%.*]] = select i1 [[TMP4476]], i64 [[TMP4474]], i64 [[TMP4475]]
|
|
// CHECK-NEXT: store i64 [[TMP4477]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4478:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4479:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4480:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4478]], i64 [[TMP4479]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4481:%.*]] = extractvalue { i64, i1 } [[TMP4480]], 0
|
|
// CHECK-NEXT: [[TMP4482:%.*]] = extractvalue { i64, i1 } [[TMP4480]], 1
|
|
// CHECK-NEXT: [[TMP4483:%.*]] = select i1 [[TMP4482]], i64 [[TMP4478]], i64 [[TMP4481]]
|
|
// CHECK-NEXT: store i64 [[TMP4483]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4484:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4485:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4486:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4484]], i64 [[TMP4485]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4487:%.*]] = extractvalue { i64, i1 } [[TMP4486]], 0
|
|
// CHECK-NEXT: [[TMP4488:%.*]] = extractvalue { i64, i1 } [[TMP4486]], 1
|
|
// CHECK-NEXT: [[TMP4489:%.*]] = select i1 [[TMP4488]], i64 [[TMP4484]], i64 [[TMP4487]]
|
|
// CHECK-NEXT: store i64 [[TMP4489]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4490:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4491:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4492:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4490]], i64 [[TMP4491]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4493:%.*]] = extractvalue { i64, i1 } [[TMP4492]], 0
|
|
// CHECK-NEXT: [[TMP4494:%.*]] = extractvalue { i64, i1 } [[TMP4492]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4494]], label [[ULLX_ATOMIC_EXIT437:%.*]], label [[ULLX_ATOMIC_CONT438:%.*]]
|
|
// CHECK: ullx.atomic.cont438:
|
|
// CHECK-NEXT: store i64 [[TMP4493]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT437]]
|
|
// CHECK: ullx.atomic.exit437:
|
|
// CHECK-NEXT: [[TMP4495:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4496:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4497:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4495]], i64 [[TMP4496]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4498:%.*]] = extractvalue { i64, i1 } [[TMP4497]], 0
|
|
// CHECK-NEXT: [[TMP4499:%.*]] = extractvalue { i64, i1 } [[TMP4497]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4499]], label [[ULLX_ATOMIC_EXIT439:%.*]], label [[ULLX_ATOMIC_CONT440:%.*]]
|
|
// CHECK: ullx.atomic.cont440:
|
|
// CHECK-NEXT: store i64 [[TMP4498]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT439]]
|
|
// CHECK: ullx.atomic.exit439:
|
|
// CHECK-NEXT: [[TMP4500:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4501:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4502:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4500]], i64 [[TMP4501]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4503:%.*]] = extractvalue { i64, i1 } [[TMP4502]], 1
|
|
// CHECK-NEXT: [[TMP4504:%.*]] = zext i1 [[TMP4503]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4504]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4505:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4506:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4507:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4505]], i64 [[TMP4506]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4508:%.*]] = extractvalue { i64, i1 } [[TMP4507]], 1
|
|
// CHECK-NEXT: [[TMP4509:%.*]] = zext i1 [[TMP4508]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4509]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4510:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4511:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4512:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4510]], i64 [[TMP4511]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4513:%.*]] = extractvalue { i64, i1 } [[TMP4512]], 0
|
|
// CHECK-NEXT: [[TMP4514:%.*]] = extractvalue { i64, i1 } [[TMP4512]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4514]], label [[ULLX_ATOMIC_EXIT441:%.*]], label [[ULLX_ATOMIC_CONT442:%.*]]
|
|
// CHECK: ullx.atomic.cont442:
|
|
// CHECK-NEXT: store i64 [[TMP4513]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT441]]
|
|
// CHECK: ullx.atomic.exit441:
|
|
// CHECK-NEXT: [[TMP4515:%.*]] = extractvalue { i64, i1 } [[TMP4512]], 1
|
|
// CHECK-NEXT: [[TMP4516:%.*]] = zext i1 [[TMP4515]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4516]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4517:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4518:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4519:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4517]], i64 [[TMP4518]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4520:%.*]] = extractvalue { i64, i1 } [[TMP4519]], 0
|
|
// CHECK-NEXT: [[TMP4521:%.*]] = extractvalue { i64, i1 } [[TMP4519]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4521]], label [[ULLX_ATOMIC_EXIT443:%.*]], label [[ULLX_ATOMIC_CONT444:%.*]]
|
|
// CHECK: ullx.atomic.cont444:
|
|
// CHECK-NEXT: store i64 [[TMP4520]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT443]]
|
|
// CHECK: ullx.atomic.exit443:
|
|
// CHECK-NEXT: [[TMP4522:%.*]] = extractvalue { i64, i1 } [[TMP4519]], 1
|
|
// CHECK-NEXT: [[TMP4523:%.*]] = zext i1 [[TMP4522]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4523]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: [[TMP4524:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4525:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4524]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4525]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4526:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4527:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4526]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4527]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4528:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4529:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4528]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4529]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4530:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4531:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4530]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4531]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4532:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4533:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4534:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4532]], i64 [[TMP4533]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4535:%.*]] = extractvalue { i64, i1 } [[TMP4534]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4535]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4536:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4537:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4538:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4536]], i64 [[TMP4537]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4539:%.*]] = extractvalue { i64, i1 } [[TMP4538]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4539]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4540:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4541:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4540]] release, align 8
|
|
// CHECK-NEXT: [[TMP4542:%.*]] = icmp ugt i64 [[TMP4541]], [[TMP4540]]
|
|
// CHECK-NEXT: [[TMP4543:%.*]] = select i1 [[TMP4542]], i64 [[TMP4540]], i64 [[TMP4541]]
|
|
// CHECK-NEXT: store i64 [[TMP4543]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4544:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4545:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4544]] release, align 8
|
|
// CHECK-NEXT: [[TMP4546:%.*]] = icmp ult i64 [[TMP4545]], [[TMP4544]]
|
|
// CHECK-NEXT: [[TMP4547:%.*]] = select i1 [[TMP4546]], i64 [[TMP4544]], i64 [[TMP4545]]
|
|
// CHECK-NEXT: store i64 [[TMP4547]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4548:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4549:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4548]] release, align 8
|
|
// CHECK-NEXT: [[TMP4550:%.*]] = icmp ult i64 [[TMP4549]], [[TMP4548]]
|
|
// CHECK-NEXT: [[TMP4551:%.*]] = select i1 [[TMP4550]], i64 [[TMP4548]], i64 [[TMP4549]]
|
|
// CHECK-NEXT: store i64 [[TMP4551]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4552:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4553:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4552]] release, align 8
|
|
// CHECK-NEXT: [[TMP4554:%.*]] = icmp ugt i64 [[TMP4553]], [[TMP4552]]
|
|
// CHECK-NEXT: [[TMP4555:%.*]] = select i1 [[TMP4554]], i64 [[TMP4552]], i64 [[TMP4553]]
|
|
// CHECK-NEXT: store i64 [[TMP4555]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4556:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4557:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4558:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4556]], i64 [[TMP4557]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4559:%.*]] = extractvalue { i64, i1 } [[TMP4558]], 0
|
|
// CHECK-NEXT: [[TMP4560:%.*]] = extractvalue { i64, i1 } [[TMP4558]], 1
|
|
// CHECK-NEXT: [[TMP4561:%.*]] = select i1 [[TMP4560]], i64 [[TMP4556]], i64 [[TMP4559]]
|
|
// CHECK-NEXT: store i64 [[TMP4561]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4562:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4563:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4564:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4562]], i64 [[TMP4563]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4565:%.*]] = extractvalue { i64, i1 } [[TMP4564]], 0
|
|
// CHECK-NEXT: [[TMP4566:%.*]] = extractvalue { i64, i1 } [[TMP4564]], 1
|
|
// CHECK-NEXT: [[TMP4567:%.*]] = select i1 [[TMP4566]], i64 [[TMP4562]], i64 [[TMP4565]]
|
|
// CHECK-NEXT: store i64 [[TMP4567]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4568:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4569:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4570:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4568]], i64 [[TMP4569]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4571:%.*]] = extractvalue { i64, i1 } [[TMP4570]], 0
|
|
// CHECK-NEXT: [[TMP4572:%.*]] = extractvalue { i64, i1 } [[TMP4570]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4572]], label [[ULLX_ATOMIC_EXIT445:%.*]], label [[ULLX_ATOMIC_CONT446:%.*]]
|
|
// CHECK: ullx.atomic.cont446:
|
|
// CHECK-NEXT: store i64 [[TMP4571]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT445]]
|
|
// CHECK: ullx.atomic.exit445:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4573:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4574:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4575:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4573]], i64 [[TMP4574]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4576:%.*]] = extractvalue { i64, i1 } [[TMP4575]], 0
|
|
// CHECK-NEXT: [[TMP4577:%.*]] = extractvalue { i64, i1 } [[TMP4575]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4577]], label [[ULLX_ATOMIC_EXIT447:%.*]], label [[ULLX_ATOMIC_CONT448:%.*]]
|
|
// CHECK: ullx.atomic.cont448:
|
|
// CHECK-NEXT: store i64 [[TMP4576]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT447]]
|
|
// CHECK: ullx.atomic.exit447:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4578:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4579:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4580:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4578]], i64 [[TMP4579]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4581:%.*]] = extractvalue { i64, i1 } [[TMP4580]], 1
|
|
// CHECK-NEXT: [[TMP4582:%.*]] = zext i1 [[TMP4581]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4582]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4583:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4584:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4585:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4583]], i64 [[TMP4584]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4586:%.*]] = extractvalue { i64, i1 } [[TMP4585]], 1
|
|
// CHECK-NEXT: [[TMP4587:%.*]] = zext i1 [[TMP4586]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4587]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4588:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4589:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4590:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4588]], i64 [[TMP4589]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4591:%.*]] = extractvalue { i64, i1 } [[TMP4590]], 0
|
|
// CHECK-NEXT: [[TMP4592:%.*]] = extractvalue { i64, i1 } [[TMP4590]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4592]], label [[ULLX_ATOMIC_EXIT449:%.*]], label [[ULLX_ATOMIC_CONT450:%.*]]
|
|
// CHECK: ullx.atomic.cont450:
|
|
// CHECK-NEXT: store i64 [[TMP4591]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT449]]
|
|
// CHECK: ullx.atomic.exit449:
|
|
// CHECK-NEXT: [[TMP4593:%.*]] = extractvalue { i64, i1 } [[TMP4590]], 1
|
|
// CHECK-NEXT: [[TMP4594:%.*]] = zext i1 [[TMP4593]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4594]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4595:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4596:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4597:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4595]], i64 [[TMP4596]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP4598:%.*]] = extractvalue { i64, i1 } [[TMP4597]], 0
|
|
// CHECK-NEXT: [[TMP4599:%.*]] = extractvalue { i64, i1 } [[TMP4597]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4599]], label [[ULLX_ATOMIC_EXIT451:%.*]], label [[ULLX_ATOMIC_CONT452:%.*]]
|
|
// CHECK: ullx.atomic.cont452:
|
|
// CHECK-NEXT: store i64 [[TMP4598]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT451]]
|
|
// CHECK: ullx.atomic.exit451:
|
|
// CHECK-NEXT: [[TMP4600:%.*]] = extractvalue { i64, i1 } [[TMP4597]], 1
|
|
// CHECK-NEXT: [[TMP4601:%.*]] = zext i1 [[TMP4600]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4601]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4602:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4603:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4602]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4603]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4604:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4605:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4604]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4605]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4606:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4607:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4606]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4607]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4608:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4609:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4608]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP4609]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4610:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4611:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4612:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4610]], i64 [[TMP4611]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4613:%.*]] = extractvalue { i64, i1 } [[TMP4612]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4613]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4614:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4615:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4616:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4614]], i64 [[TMP4615]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4617:%.*]] = extractvalue { i64, i1 } [[TMP4616]], 0
|
|
// CHECK-NEXT: store i64 [[TMP4617]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4618:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4619:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4618]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4620:%.*]] = icmp ugt i64 [[TMP4619]], [[TMP4618]]
|
|
// CHECK-NEXT: [[TMP4621:%.*]] = select i1 [[TMP4620]], i64 [[TMP4618]], i64 [[TMP4619]]
|
|
// CHECK-NEXT: store i64 [[TMP4621]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4622:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4623:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4622]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4624:%.*]] = icmp ult i64 [[TMP4623]], [[TMP4622]]
|
|
// CHECK-NEXT: [[TMP4625:%.*]] = select i1 [[TMP4624]], i64 [[TMP4622]], i64 [[TMP4623]]
|
|
// CHECK-NEXT: store i64 [[TMP4625]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4626:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4627:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4626]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4628:%.*]] = icmp ult i64 [[TMP4627]], [[TMP4626]]
|
|
// CHECK-NEXT: [[TMP4629:%.*]] = select i1 [[TMP4628]], i64 [[TMP4626]], i64 [[TMP4627]]
|
|
// CHECK-NEXT: store i64 [[TMP4629]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4630:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4631:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4630]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4632:%.*]] = icmp ugt i64 [[TMP4631]], [[TMP4630]]
|
|
// CHECK-NEXT: [[TMP4633:%.*]] = select i1 [[TMP4632]], i64 [[TMP4630]], i64 [[TMP4631]]
|
|
// CHECK-NEXT: store i64 [[TMP4633]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4634:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4635:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4636:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4634]], i64 [[TMP4635]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4637:%.*]] = extractvalue { i64, i1 } [[TMP4636]], 0
|
|
// CHECK-NEXT: [[TMP4638:%.*]] = extractvalue { i64, i1 } [[TMP4636]], 1
|
|
// CHECK-NEXT: [[TMP4639:%.*]] = select i1 [[TMP4638]], i64 [[TMP4634]], i64 [[TMP4637]]
|
|
// CHECK-NEXT: store i64 [[TMP4639]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4640:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4641:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4642:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4640]], i64 [[TMP4641]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4643:%.*]] = extractvalue { i64, i1 } [[TMP4642]], 0
|
|
// CHECK-NEXT: [[TMP4644:%.*]] = extractvalue { i64, i1 } [[TMP4642]], 1
|
|
// CHECK-NEXT: [[TMP4645:%.*]] = select i1 [[TMP4644]], i64 [[TMP4640]], i64 [[TMP4643]]
|
|
// CHECK-NEXT: store i64 [[TMP4645]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4646:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4647:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4648:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4646]], i64 [[TMP4647]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4649:%.*]] = extractvalue { i64, i1 } [[TMP4648]], 0
|
|
// CHECK-NEXT: [[TMP4650:%.*]] = extractvalue { i64, i1 } [[TMP4648]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4650]], label [[ULLX_ATOMIC_EXIT453:%.*]], label [[ULLX_ATOMIC_CONT454:%.*]]
|
|
// CHECK: ullx.atomic.cont454:
|
|
// CHECK-NEXT: store i64 [[TMP4649]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT453]]
|
|
// CHECK: ullx.atomic.exit453:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4651:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4652:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4653:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4651]], i64 [[TMP4652]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4654:%.*]] = extractvalue { i64, i1 } [[TMP4653]], 0
|
|
// CHECK-NEXT: [[TMP4655:%.*]] = extractvalue { i64, i1 } [[TMP4653]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4655]], label [[ULLX_ATOMIC_EXIT455:%.*]], label [[ULLX_ATOMIC_CONT456:%.*]]
|
|
// CHECK: ullx.atomic.cont456:
|
|
// CHECK-NEXT: store i64 [[TMP4654]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT455]]
|
|
// CHECK: ullx.atomic.exit455:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4656:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4657:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4658:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4656]], i64 [[TMP4657]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4659:%.*]] = extractvalue { i64, i1 } [[TMP4658]], 1
|
|
// CHECK-NEXT: [[TMP4660:%.*]] = zext i1 [[TMP4659]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4660]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4661:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4662:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4663:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4661]], i64 [[TMP4662]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4664:%.*]] = extractvalue { i64, i1 } [[TMP4663]], 1
|
|
// CHECK-NEXT: [[TMP4665:%.*]] = zext i1 [[TMP4664]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4665]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4666:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4667:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4668:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4666]], i64 [[TMP4667]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4669:%.*]] = extractvalue { i64, i1 } [[TMP4668]], 0
|
|
// CHECK-NEXT: [[TMP4670:%.*]] = extractvalue { i64, i1 } [[TMP4668]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4670]], label [[ULLX_ATOMIC_EXIT457:%.*]], label [[ULLX_ATOMIC_CONT458:%.*]]
|
|
// CHECK: ullx.atomic.cont458:
|
|
// CHECK-NEXT: store i64 [[TMP4669]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT457]]
|
|
// CHECK: ullx.atomic.exit457:
|
|
// CHECK-NEXT: [[TMP4671:%.*]] = extractvalue { i64, i1 } [[TMP4668]], 1
|
|
// CHECK-NEXT: [[TMP4672:%.*]] = zext i1 [[TMP4671]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4672]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4673:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP4674:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP4675:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4673]], i64 [[TMP4674]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP4676:%.*]] = extractvalue { i64, i1 } [[TMP4675]], 0
|
|
// CHECK-NEXT: [[TMP4677:%.*]] = extractvalue { i64, i1 } [[TMP4675]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4677]], label [[ULLX_ATOMIC_EXIT459:%.*]], label [[ULLX_ATOMIC_CONT460:%.*]]
|
|
// CHECK: ullx.atomic.cont460:
|
|
// CHECK-NEXT: store i64 [[TMP4676]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT459]]
|
|
// CHECK: ullx.atomic.exit459:
|
|
// CHECK-NEXT: [[TMP4678:%.*]] = extractvalue { i64, i1 } [[TMP4675]], 1
|
|
// CHECK-NEXT: [[TMP4679:%.*]] = zext i1 [[TMP4678]] to i64
|
|
// CHECK-NEXT: store i64 [[TMP4679]], ptr [[ULLR]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4680:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4681:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4680]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP4681]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4682:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4683:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4682]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP4683]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4684:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4685:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4684]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP4685]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4686:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4687:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4686]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP4687]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4688:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4689:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4690:%.*]] = bitcast float [[TMP4688]] to i32
|
|
// CHECK-NEXT: [[TMP4691:%.*]] = bitcast float [[TMP4689]] to i32
|
|
// CHECK-NEXT: [[TMP4692:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4690]], i32 [[TMP4691]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4693:%.*]] = extractvalue { i32, i1 } [[TMP4692]], 0
|
|
// CHECK-NEXT: [[TMP4694:%.*]] = bitcast i32 [[TMP4693]] to float
|
|
// CHECK-NEXT: store float [[TMP4694]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4695:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4696:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4697:%.*]] = bitcast float [[TMP4695]] to i32
|
|
// CHECK-NEXT: [[TMP4698:%.*]] = bitcast float [[TMP4696]] to i32
|
|
// CHECK-NEXT: [[TMP4699:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4697]], i32 [[TMP4698]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4700:%.*]] = extractvalue { i32, i1 } [[TMP4699]], 0
|
|
// CHECK-NEXT: [[TMP4701:%.*]] = bitcast i32 [[TMP4700]] to float
|
|
// CHECK-NEXT: store float [[TMP4701]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4702:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4703:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4702]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4704:%.*]] = fcmp ogt float [[TMP4703]], [[TMP4702]]
|
|
// CHECK-NEXT: [[TMP4705:%.*]] = select i1 [[TMP4704]], float [[TMP4702]], float [[TMP4703]]
|
|
// CHECK-NEXT: store float [[TMP4705]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4706:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4707:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4706]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4708:%.*]] = fcmp olt float [[TMP4707]], [[TMP4706]]
|
|
// CHECK-NEXT: [[TMP4709:%.*]] = select i1 [[TMP4708]], float [[TMP4706]], float [[TMP4707]]
|
|
// CHECK-NEXT: store float [[TMP4709]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4710:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4711:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4710]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4712:%.*]] = fcmp olt float [[TMP4711]], [[TMP4710]]
|
|
// CHECK-NEXT: [[TMP4713:%.*]] = select i1 [[TMP4712]], float [[TMP4710]], float [[TMP4711]]
|
|
// CHECK-NEXT: store float [[TMP4713]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4714:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4715:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4714]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4716:%.*]] = fcmp ogt float [[TMP4715]], [[TMP4714]]
|
|
// CHECK-NEXT: [[TMP4717:%.*]] = select i1 [[TMP4716]], float [[TMP4714]], float [[TMP4715]]
|
|
// CHECK-NEXT: store float [[TMP4717]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4718:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4719:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4720:%.*]] = bitcast float [[TMP4718]] to i32
|
|
// CHECK-NEXT: [[TMP4721:%.*]] = bitcast float [[TMP4719]] to i32
|
|
// CHECK-NEXT: [[TMP4722:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4720]], i32 [[TMP4721]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4723:%.*]] = extractvalue { i32, i1 } [[TMP4722]], 0
|
|
// CHECK-NEXT: [[TMP4724:%.*]] = bitcast i32 [[TMP4723]] to float
|
|
// CHECK-NEXT: [[TMP4725:%.*]] = extractvalue { i32, i1 } [[TMP4722]], 1
|
|
// CHECK-NEXT: [[TMP4726:%.*]] = select i1 [[TMP4725]], float [[TMP4718]], float [[TMP4724]]
|
|
// CHECK-NEXT: store float [[TMP4726]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4727:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4728:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4729:%.*]] = bitcast float [[TMP4727]] to i32
|
|
// CHECK-NEXT: [[TMP4730:%.*]] = bitcast float [[TMP4728]] to i32
|
|
// CHECK-NEXT: [[TMP4731:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4729]], i32 [[TMP4730]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4732:%.*]] = extractvalue { i32, i1 } [[TMP4731]], 0
|
|
// CHECK-NEXT: [[TMP4733:%.*]] = bitcast i32 [[TMP4732]] to float
|
|
// CHECK-NEXT: [[TMP4734:%.*]] = extractvalue { i32, i1 } [[TMP4731]], 1
|
|
// CHECK-NEXT: [[TMP4735:%.*]] = select i1 [[TMP4734]], float [[TMP4727]], float [[TMP4733]]
|
|
// CHECK-NEXT: store float [[TMP4735]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4736:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4737:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4738:%.*]] = bitcast float [[TMP4736]] to i32
|
|
// CHECK-NEXT: [[TMP4739:%.*]] = bitcast float [[TMP4737]] to i32
|
|
// CHECK-NEXT: [[TMP4740:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4738]], i32 [[TMP4739]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4741:%.*]] = extractvalue { i32, i1 } [[TMP4740]], 0
|
|
// CHECK-NEXT: [[TMP4742:%.*]] = bitcast i32 [[TMP4741]] to float
|
|
// CHECK-NEXT: [[TMP4743:%.*]] = extractvalue { i32, i1 } [[TMP4740]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4743]], label [[FX_ATOMIC_EXIT:%.*]], label [[FX_ATOMIC_CONT:%.*]]
|
|
// CHECK: fx.atomic.cont:
|
|
// CHECK-NEXT: store float [[TMP4742]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT]]
|
|
// CHECK: fx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP4744:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4745:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4746:%.*]] = bitcast float [[TMP4744]] to i32
|
|
// CHECK-NEXT: [[TMP4747:%.*]] = bitcast float [[TMP4745]] to i32
|
|
// CHECK-NEXT: [[TMP4748:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4746]], i32 [[TMP4747]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4749:%.*]] = extractvalue { i32, i1 } [[TMP4748]], 0
|
|
// CHECK-NEXT: [[TMP4750:%.*]] = bitcast i32 [[TMP4749]] to float
|
|
// CHECK-NEXT: [[TMP4751:%.*]] = extractvalue { i32, i1 } [[TMP4748]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4751]], label [[FX_ATOMIC_EXIT461:%.*]], label [[FX_ATOMIC_CONT462:%.*]]
|
|
// CHECK: fx.atomic.cont462:
|
|
// CHECK-NEXT: store float [[TMP4750]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT461]]
|
|
// CHECK: fx.atomic.exit461:
|
|
// CHECK-NEXT: [[TMP4752:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4753:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4754:%.*]] = bitcast float [[TMP4752]] to i32
|
|
// CHECK-NEXT: [[TMP4755:%.*]] = bitcast float [[TMP4753]] to i32
|
|
// CHECK-NEXT: [[TMP4756:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4754]], i32 [[TMP4755]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4757:%.*]] = extractvalue { i32, i1 } [[TMP4756]], 1
|
|
// CHECK-NEXT: [[TMP4758:%.*]] = sext i1 [[TMP4757]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4758]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP4759:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4760:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4761:%.*]] = bitcast float [[TMP4759]] to i32
|
|
// CHECK-NEXT: [[TMP4762:%.*]] = bitcast float [[TMP4760]] to i32
|
|
// CHECK-NEXT: [[TMP4763:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4761]], i32 [[TMP4762]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4764:%.*]] = extractvalue { i32, i1 } [[TMP4763]], 1
|
|
// CHECK-NEXT: [[TMP4765:%.*]] = sext i1 [[TMP4764]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4765]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP4766:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4767:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4768:%.*]] = bitcast float [[TMP4766]] to i32
|
|
// CHECK-NEXT: [[TMP4769:%.*]] = bitcast float [[TMP4767]] to i32
|
|
// CHECK-NEXT: [[TMP4770:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4768]], i32 [[TMP4769]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4771:%.*]] = extractvalue { i32, i1 } [[TMP4770]], 0
|
|
// CHECK-NEXT: [[TMP4772:%.*]] = bitcast i32 [[TMP4771]] to float
|
|
// CHECK-NEXT: [[TMP4773:%.*]] = extractvalue { i32, i1 } [[TMP4770]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4773]], label [[FX_ATOMIC_EXIT463:%.*]], label [[FX_ATOMIC_CONT464:%.*]]
|
|
// CHECK: fx.atomic.cont464:
|
|
// CHECK-NEXT: store float [[TMP4772]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT463]]
|
|
// CHECK: fx.atomic.exit463:
|
|
// CHECK-NEXT: [[TMP4774:%.*]] = extractvalue { i32, i1 } [[TMP4770]], 1
|
|
// CHECK-NEXT: [[TMP4775:%.*]] = sext i1 [[TMP4774]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4775]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP4776:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4777:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4778:%.*]] = bitcast float [[TMP4776]] to i32
|
|
// CHECK-NEXT: [[TMP4779:%.*]] = bitcast float [[TMP4777]] to i32
|
|
// CHECK-NEXT: [[TMP4780:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4778]], i32 [[TMP4779]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP4781:%.*]] = extractvalue { i32, i1 } [[TMP4780]], 0
|
|
// CHECK-NEXT: [[TMP4782:%.*]] = bitcast i32 [[TMP4781]] to float
|
|
// CHECK-NEXT: [[TMP4783:%.*]] = extractvalue { i32, i1 } [[TMP4780]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4783]], label [[FX_ATOMIC_EXIT465:%.*]], label [[FX_ATOMIC_CONT466:%.*]]
|
|
// CHECK: fx.atomic.cont466:
|
|
// CHECK-NEXT: store float [[TMP4782]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT465]]
|
|
// CHECK: fx.atomic.exit465:
|
|
// CHECK-NEXT: [[TMP4784:%.*]] = extractvalue { i32, i1 } [[TMP4780]], 1
|
|
// CHECK-NEXT: [[TMP4785:%.*]] = sext i1 [[TMP4784]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4785]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP4786:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4787:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4786]] acq_rel, align 4
|
|
// CHECK-NEXT: store float [[TMP4787]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4788:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4789:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4788]] acq_rel, align 4
|
|
// CHECK-NEXT: store float [[TMP4789]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4790:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4791:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4790]] acq_rel, align 4
|
|
// CHECK-NEXT: store float [[TMP4791]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4792:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4793:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4792]] acq_rel, align 4
|
|
// CHECK-NEXT: store float [[TMP4793]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4794:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4795:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4796:%.*]] = bitcast float [[TMP4794]] to i32
|
|
// CHECK-NEXT: [[TMP4797:%.*]] = bitcast float [[TMP4795]] to i32
|
|
// CHECK-NEXT: [[TMP4798:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4796]], i32 [[TMP4797]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4799:%.*]] = extractvalue { i32, i1 } [[TMP4798]], 0
|
|
// CHECK-NEXT: [[TMP4800:%.*]] = bitcast i32 [[TMP4799]] to float
|
|
// CHECK-NEXT: store float [[TMP4800]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4801:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4802:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4803:%.*]] = bitcast float [[TMP4801]] to i32
|
|
// CHECK-NEXT: [[TMP4804:%.*]] = bitcast float [[TMP4802]] to i32
|
|
// CHECK-NEXT: [[TMP4805:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4803]], i32 [[TMP4804]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4806:%.*]] = extractvalue { i32, i1 } [[TMP4805]], 0
|
|
// CHECK-NEXT: [[TMP4807:%.*]] = bitcast i32 [[TMP4806]] to float
|
|
// CHECK-NEXT: store float [[TMP4807]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4808:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4809:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4808]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP4810:%.*]] = fcmp ogt float [[TMP4809]], [[TMP4808]]
|
|
// CHECK-NEXT: [[TMP4811:%.*]] = select i1 [[TMP4810]], float [[TMP4808]], float [[TMP4809]]
|
|
// CHECK-NEXT: store float [[TMP4811]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4812:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4813:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4812]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP4814:%.*]] = fcmp olt float [[TMP4813]], [[TMP4812]]
|
|
// CHECK-NEXT: [[TMP4815:%.*]] = select i1 [[TMP4814]], float [[TMP4812]], float [[TMP4813]]
|
|
// CHECK-NEXT: store float [[TMP4815]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4816:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4817:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4816]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP4818:%.*]] = fcmp olt float [[TMP4817]], [[TMP4816]]
|
|
// CHECK-NEXT: [[TMP4819:%.*]] = select i1 [[TMP4818]], float [[TMP4816]], float [[TMP4817]]
|
|
// CHECK-NEXT: store float [[TMP4819]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4820:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4821:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4820]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP4822:%.*]] = fcmp ogt float [[TMP4821]], [[TMP4820]]
|
|
// CHECK-NEXT: [[TMP4823:%.*]] = select i1 [[TMP4822]], float [[TMP4820]], float [[TMP4821]]
|
|
// CHECK-NEXT: store float [[TMP4823]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4824:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4825:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4826:%.*]] = bitcast float [[TMP4824]] to i32
|
|
// CHECK-NEXT: [[TMP4827:%.*]] = bitcast float [[TMP4825]] to i32
|
|
// CHECK-NEXT: [[TMP4828:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4826]], i32 [[TMP4827]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4829:%.*]] = extractvalue { i32, i1 } [[TMP4828]], 0
|
|
// CHECK-NEXT: [[TMP4830:%.*]] = bitcast i32 [[TMP4829]] to float
|
|
// CHECK-NEXT: [[TMP4831:%.*]] = extractvalue { i32, i1 } [[TMP4828]], 1
|
|
// CHECK-NEXT: [[TMP4832:%.*]] = select i1 [[TMP4831]], float [[TMP4824]], float [[TMP4830]]
|
|
// CHECK-NEXT: store float [[TMP4832]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4833:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4834:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4835:%.*]] = bitcast float [[TMP4833]] to i32
|
|
// CHECK-NEXT: [[TMP4836:%.*]] = bitcast float [[TMP4834]] to i32
|
|
// CHECK-NEXT: [[TMP4837:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4835]], i32 [[TMP4836]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4838:%.*]] = extractvalue { i32, i1 } [[TMP4837]], 0
|
|
// CHECK-NEXT: [[TMP4839:%.*]] = bitcast i32 [[TMP4838]] to float
|
|
// CHECK-NEXT: [[TMP4840:%.*]] = extractvalue { i32, i1 } [[TMP4837]], 1
|
|
// CHECK-NEXT: [[TMP4841:%.*]] = select i1 [[TMP4840]], float [[TMP4833]], float [[TMP4839]]
|
|
// CHECK-NEXT: store float [[TMP4841]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4842:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4843:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4844:%.*]] = bitcast float [[TMP4842]] to i32
|
|
// CHECK-NEXT: [[TMP4845:%.*]] = bitcast float [[TMP4843]] to i32
|
|
// CHECK-NEXT: [[TMP4846:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4844]], i32 [[TMP4845]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4847:%.*]] = extractvalue { i32, i1 } [[TMP4846]], 0
|
|
// CHECK-NEXT: [[TMP4848:%.*]] = bitcast i32 [[TMP4847]] to float
|
|
// CHECK-NEXT: [[TMP4849:%.*]] = extractvalue { i32, i1 } [[TMP4846]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4849]], label [[FX_ATOMIC_EXIT467:%.*]], label [[FX_ATOMIC_CONT468:%.*]]
|
|
// CHECK: fx.atomic.cont468:
|
|
// CHECK-NEXT: store float [[TMP4848]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT467]]
|
|
// CHECK: fx.atomic.exit467:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4850:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4851:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4852:%.*]] = bitcast float [[TMP4850]] to i32
|
|
// CHECK-NEXT: [[TMP4853:%.*]] = bitcast float [[TMP4851]] to i32
|
|
// CHECK-NEXT: [[TMP4854:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4852]], i32 [[TMP4853]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4855:%.*]] = extractvalue { i32, i1 } [[TMP4854]], 0
|
|
// CHECK-NEXT: [[TMP4856:%.*]] = bitcast i32 [[TMP4855]] to float
|
|
// CHECK-NEXT: [[TMP4857:%.*]] = extractvalue { i32, i1 } [[TMP4854]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4857]], label [[FX_ATOMIC_EXIT469:%.*]], label [[FX_ATOMIC_CONT470:%.*]]
|
|
// CHECK: fx.atomic.cont470:
|
|
// CHECK-NEXT: store float [[TMP4856]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT469]]
|
|
// CHECK: fx.atomic.exit469:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4858:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4859:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4860:%.*]] = bitcast float [[TMP4858]] to i32
|
|
// CHECK-NEXT: [[TMP4861:%.*]] = bitcast float [[TMP4859]] to i32
|
|
// CHECK-NEXT: [[TMP4862:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4860]], i32 [[TMP4861]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4863:%.*]] = extractvalue { i32, i1 } [[TMP4862]], 1
|
|
// CHECK-NEXT: [[TMP4864:%.*]] = sext i1 [[TMP4863]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4864]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4865:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4866:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4867:%.*]] = bitcast float [[TMP4865]] to i32
|
|
// CHECK-NEXT: [[TMP4868:%.*]] = bitcast float [[TMP4866]] to i32
|
|
// CHECK-NEXT: [[TMP4869:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4867]], i32 [[TMP4868]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4870:%.*]] = extractvalue { i32, i1 } [[TMP4869]], 1
|
|
// CHECK-NEXT: [[TMP4871:%.*]] = sext i1 [[TMP4870]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4871]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4872:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4873:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4874:%.*]] = bitcast float [[TMP4872]] to i32
|
|
// CHECK-NEXT: [[TMP4875:%.*]] = bitcast float [[TMP4873]] to i32
|
|
// CHECK-NEXT: [[TMP4876:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4874]], i32 [[TMP4875]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4877:%.*]] = extractvalue { i32, i1 } [[TMP4876]], 0
|
|
// CHECK-NEXT: [[TMP4878:%.*]] = bitcast i32 [[TMP4877]] to float
|
|
// CHECK-NEXT: [[TMP4879:%.*]] = extractvalue { i32, i1 } [[TMP4876]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4879]], label [[FX_ATOMIC_EXIT471:%.*]], label [[FX_ATOMIC_CONT472:%.*]]
|
|
// CHECK: fx.atomic.cont472:
|
|
// CHECK-NEXT: store float [[TMP4878]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT471]]
|
|
// CHECK: fx.atomic.exit471:
|
|
// CHECK-NEXT: [[TMP4880:%.*]] = extractvalue { i32, i1 } [[TMP4876]], 1
|
|
// CHECK-NEXT: [[TMP4881:%.*]] = sext i1 [[TMP4880]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4881]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4882:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4883:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4884:%.*]] = bitcast float [[TMP4882]] to i32
|
|
// CHECK-NEXT: [[TMP4885:%.*]] = bitcast float [[TMP4883]] to i32
|
|
// CHECK-NEXT: [[TMP4886:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4884]], i32 [[TMP4885]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP4887:%.*]] = extractvalue { i32, i1 } [[TMP4886]], 0
|
|
// CHECK-NEXT: [[TMP4888:%.*]] = bitcast i32 [[TMP4887]] to float
|
|
// CHECK-NEXT: [[TMP4889:%.*]] = extractvalue { i32, i1 } [[TMP4886]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4889]], label [[FX_ATOMIC_EXIT473:%.*]], label [[FX_ATOMIC_CONT474:%.*]]
|
|
// CHECK: fx.atomic.cont474:
|
|
// CHECK-NEXT: store float [[TMP4888]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT473]]
|
|
// CHECK: fx.atomic.exit473:
|
|
// CHECK-NEXT: [[TMP4890:%.*]] = extractvalue { i32, i1 } [[TMP4886]], 1
|
|
// CHECK-NEXT: [[TMP4891:%.*]] = sext i1 [[TMP4890]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4891]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP4892:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4893:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4892]] acquire, align 4
|
|
// CHECK-NEXT: store float [[TMP4893]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4894:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4895:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4894]] acquire, align 4
|
|
// CHECK-NEXT: store float [[TMP4895]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4896:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4897:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4896]] acquire, align 4
|
|
// CHECK-NEXT: store float [[TMP4897]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4898:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4899:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4898]] acquire, align 4
|
|
// CHECK-NEXT: store float [[TMP4899]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4900:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4901:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4902:%.*]] = bitcast float [[TMP4900]] to i32
|
|
// CHECK-NEXT: [[TMP4903:%.*]] = bitcast float [[TMP4901]] to i32
|
|
// CHECK-NEXT: [[TMP4904:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4902]], i32 [[TMP4903]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4905:%.*]] = extractvalue { i32, i1 } [[TMP4904]], 0
|
|
// CHECK-NEXT: [[TMP4906:%.*]] = bitcast i32 [[TMP4905]] to float
|
|
// CHECK-NEXT: store float [[TMP4906]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4907:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4908:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4909:%.*]] = bitcast float [[TMP4907]] to i32
|
|
// CHECK-NEXT: [[TMP4910:%.*]] = bitcast float [[TMP4908]] to i32
|
|
// CHECK-NEXT: [[TMP4911:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4909]], i32 [[TMP4910]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4912:%.*]] = extractvalue { i32, i1 } [[TMP4911]], 0
|
|
// CHECK-NEXT: [[TMP4913:%.*]] = bitcast i32 [[TMP4912]] to float
|
|
// CHECK-NEXT: store float [[TMP4913]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4914:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4915:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4914]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP4916:%.*]] = fcmp ogt float [[TMP4915]], [[TMP4914]]
|
|
// CHECK-NEXT: [[TMP4917:%.*]] = select i1 [[TMP4916]], float [[TMP4914]], float [[TMP4915]]
|
|
// CHECK-NEXT: store float [[TMP4917]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4918:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4919:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4918]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP4920:%.*]] = fcmp olt float [[TMP4919]], [[TMP4918]]
|
|
// CHECK-NEXT: [[TMP4921:%.*]] = select i1 [[TMP4920]], float [[TMP4918]], float [[TMP4919]]
|
|
// CHECK-NEXT: store float [[TMP4921]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4922:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4923:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4922]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP4924:%.*]] = fcmp olt float [[TMP4923]], [[TMP4922]]
|
|
// CHECK-NEXT: [[TMP4925:%.*]] = select i1 [[TMP4924]], float [[TMP4922]], float [[TMP4923]]
|
|
// CHECK-NEXT: store float [[TMP4925]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4926:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4927:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4926]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP4928:%.*]] = fcmp ogt float [[TMP4927]], [[TMP4926]]
|
|
// CHECK-NEXT: [[TMP4929:%.*]] = select i1 [[TMP4928]], float [[TMP4926]], float [[TMP4927]]
|
|
// CHECK-NEXT: store float [[TMP4929]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4930:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4931:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4932:%.*]] = bitcast float [[TMP4930]] to i32
|
|
// CHECK-NEXT: [[TMP4933:%.*]] = bitcast float [[TMP4931]] to i32
|
|
// CHECK-NEXT: [[TMP4934:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4932]], i32 [[TMP4933]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4935:%.*]] = extractvalue { i32, i1 } [[TMP4934]], 0
|
|
// CHECK-NEXT: [[TMP4936:%.*]] = bitcast i32 [[TMP4935]] to float
|
|
// CHECK-NEXT: [[TMP4937:%.*]] = extractvalue { i32, i1 } [[TMP4934]], 1
|
|
// CHECK-NEXT: [[TMP4938:%.*]] = select i1 [[TMP4937]], float [[TMP4930]], float [[TMP4936]]
|
|
// CHECK-NEXT: store float [[TMP4938]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4939:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4940:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4941:%.*]] = bitcast float [[TMP4939]] to i32
|
|
// CHECK-NEXT: [[TMP4942:%.*]] = bitcast float [[TMP4940]] to i32
|
|
// CHECK-NEXT: [[TMP4943:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4941]], i32 [[TMP4942]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4944:%.*]] = extractvalue { i32, i1 } [[TMP4943]], 0
|
|
// CHECK-NEXT: [[TMP4945:%.*]] = bitcast i32 [[TMP4944]] to float
|
|
// CHECK-NEXT: [[TMP4946:%.*]] = extractvalue { i32, i1 } [[TMP4943]], 1
|
|
// CHECK-NEXT: [[TMP4947:%.*]] = select i1 [[TMP4946]], float [[TMP4939]], float [[TMP4945]]
|
|
// CHECK-NEXT: store float [[TMP4947]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4948:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4949:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4950:%.*]] = bitcast float [[TMP4948]] to i32
|
|
// CHECK-NEXT: [[TMP4951:%.*]] = bitcast float [[TMP4949]] to i32
|
|
// CHECK-NEXT: [[TMP4952:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4950]], i32 [[TMP4951]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4953:%.*]] = extractvalue { i32, i1 } [[TMP4952]], 0
|
|
// CHECK-NEXT: [[TMP4954:%.*]] = bitcast i32 [[TMP4953]] to float
|
|
// CHECK-NEXT: [[TMP4955:%.*]] = extractvalue { i32, i1 } [[TMP4952]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4955]], label [[FX_ATOMIC_EXIT475:%.*]], label [[FX_ATOMIC_CONT476:%.*]]
|
|
// CHECK: fx.atomic.cont476:
|
|
// CHECK-NEXT: store float [[TMP4954]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT475]]
|
|
// CHECK: fx.atomic.exit475:
|
|
// CHECK-NEXT: [[TMP4956:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4957:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4958:%.*]] = bitcast float [[TMP4956]] to i32
|
|
// CHECK-NEXT: [[TMP4959:%.*]] = bitcast float [[TMP4957]] to i32
|
|
// CHECK-NEXT: [[TMP4960:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4958]], i32 [[TMP4959]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4961:%.*]] = extractvalue { i32, i1 } [[TMP4960]], 0
|
|
// CHECK-NEXT: [[TMP4962:%.*]] = bitcast i32 [[TMP4961]] to float
|
|
// CHECK-NEXT: [[TMP4963:%.*]] = extractvalue { i32, i1 } [[TMP4960]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4963]], label [[FX_ATOMIC_EXIT477:%.*]], label [[FX_ATOMIC_CONT478:%.*]]
|
|
// CHECK: fx.atomic.cont478:
|
|
// CHECK-NEXT: store float [[TMP4962]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT477]]
|
|
// CHECK: fx.atomic.exit477:
|
|
// CHECK-NEXT: [[TMP4964:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4965:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4966:%.*]] = bitcast float [[TMP4964]] to i32
|
|
// CHECK-NEXT: [[TMP4967:%.*]] = bitcast float [[TMP4965]] to i32
|
|
// CHECK-NEXT: [[TMP4968:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4966]], i32 [[TMP4967]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4969:%.*]] = extractvalue { i32, i1 } [[TMP4968]], 1
|
|
// CHECK-NEXT: [[TMP4970:%.*]] = sext i1 [[TMP4969]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4970]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP4971:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4972:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4973:%.*]] = bitcast float [[TMP4971]] to i32
|
|
// CHECK-NEXT: [[TMP4974:%.*]] = bitcast float [[TMP4972]] to i32
|
|
// CHECK-NEXT: [[TMP4975:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4973]], i32 [[TMP4974]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4976:%.*]] = extractvalue { i32, i1 } [[TMP4975]], 1
|
|
// CHECK-NEXT: [[TMP4977:%.*]] = sext i1 [[TMP4976]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4977]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP4978:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4979:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4980:%.*]] = bitcast float [[TMP4978]] to i32
|
|
// CHECK-NEXT: [[TMP4981:%.*]] = bitcast float [[TMP4979]] to i32
|
|
// CHECK-NEXT: [[TMP4982:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4980]], i32 [[TMP4981]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4983:%.*]] = extractvalue { i32, i1 } [[TMP4982]], 0
|
|
// CHECK-NEXT: [[TMP4984:%.*]] = bitcast i32 [[TMP4983]] to float
|
|
// CHECK-NEXT: [[TMP4985:%.*]] = extractvalue { i32, i1 } [[TMP4982]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4985]], label [[FX_ATOMIC_EXIT479:%.*]], label [[FX_ATOMIC_CONT480:%.*]]
|
|
// CHECK: fx.atomic.cont480:
|
|
// CHECK-NEXT: store float [[TMP4984]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT479]]
|
|
// CHECK: fx.atomic.exit479:
|
|
// CHECK-NEXT: [[TMP4986:%.*]] = extractvalue { i32, i1 } [[TMP4982]], 1
|
|
// CHECK-NEXT: [[TMP4987:%.*]] = sext i1 [[TMP4986]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4987]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP4988:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4989:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP4990:%.*]] = bitcast float [[TMP4988]] to i32
|
|
// CHECK-NEXT: [[TMP4991:%.*]] = bitcast float [[TMP4989]] to i32
|
|
// CHECK-NEXT: [[TMP4992:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4990]], i32 [[TMP4991]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP4993:%.*]] = extractvalue { i32, i1 } [[TMP4992]], 0
|
|
// CHECK-NEXT: [[TMP4994:%.*]] = bitcast i32 [[TMP4993]] to float
|
|
// CHECK-NEXT: [[TMP4995:%.*]] = extractvalue { i32, i1 } [[TMP4992]], 1
|
|
// CHECK-NEXT: br i1 [[TMP4995]], label [[FX_ATOMIC_EXIT481:%.*]], label [[FX_ATOMIC_CONT482:%.*]]
|
|
// CHECK: fx.atomic.cont482:
|
|
// CHECK-NEXT: store float [[TMP4994]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT481]]
|
|
// CHECK: fx.atomic.exit481:
|
|
// CHECK-NEXT: [[TMP4996:%.*]] = extractvalue { i32, i1 } [[TMP4992]], 1
|
|
// CHECK-NEXT: [[TMP4997:%.*]] = sext i1 [[TMP4996]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP4997]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP4998:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP4999:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4998]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP4999]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5000:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5001:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5000]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP5001]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5002:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5003:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5002]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP5003]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5004:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5005:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5004]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP5005]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5006:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5007:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5008:%.*]] = bitcast float [[TMP5006]] to i32
|
|
// CHECK-NEXT: [[TMP5009:%.*]] = bitcast float [[TMP5007]] to i32
|
|
// CHECK-NEXT: [[TMP5010:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5008]], i32 [[TMP5009]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5011:%.*]] = extractvalue { i32, i1 } [[TMP5010]], 0
|
|
// CHECK-NEXT: [[TMP5012:%.*]] = bitcast i32 [[TMP5011]] to float
|
|
// CHECK-NEXT: store float [[TMP5012]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5013:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5014:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5015:%.*]] = bitcast float [[TMP5013]] to i32
|
|
// CHECK-NEXT: [[TMP5016:%.*]] = bitcast float [[TMP5014]] to i32
|
|
// CHECK-NEXT: [[TMP5017:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5015]], i32 [[TMP5016]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5018:%.*]] = extractvalue { i32, i1 } [[TMP5017]], 0
|
|
// CHECK-NEXT: [[TMP5019:%.*]] = bitcast i32 [[TMP5018]] to float
|
|
// CHECK-NEXT: store float [[TMP5019]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5020:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5021:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5020]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5022:%.*]] = fcmp ogt float [[TMP5021]], [[TMP5020]]
|
|
// CHECK-NEXT: [[TMP5023:%.*]] = select i1 [[TMP5022]], float [[TMP5020]], float [[TMP5021]]
|
|
// CHECK-NEXT: store float [[TMP5023]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5024:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5025:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5024]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5026:%.*]] = fcmp olt float [[TMP5025]], [[TMP5024]]
|
|
// CHECK-NEXT: [[TMP5027:%.*]] = select i1 [[TMP5026]], float [[TMP5024]], float [[TMP5025]]
|
|
// CHECK-NEXT: store float [[TMP5027]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5028:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5029:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5028]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5030:%.*]] = fcmp olt float [[TMP5029]], [[TMP5028]]
|
|
// CHECK-NEXT: [[TMP5031:%.*]] = select i1 [[TMP5030]], float [[TMP5028]], float [[TMP5029]]
|
|
// CHECK-NEXT: store float [[TMP5031]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5032:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5033:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5032]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5034:%.*]] = fcmp ogt float [[TMP5033]], [[TMP5032]]
|
|
// CHECK-NEXT: [[TMP5035:%.*]] = select i1 [[TMP5034]], float [[TMP5032]], float [[TMP5033]]
|
|
// CHECK-NEXT: store float [[TMP5035]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5036:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5037:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5038:%.*]] = bitcast float [[TMP5036]] to i32
|
|
// CHECK-NEXT: [[TMP5039:%.*]] = bitcast float [[TMP5037]] to i32
|
|
// CHECK-NEXT: [[TMP5040:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5038]], i32 [[TMP5039]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5041:%.*]] = extractvalue { i32, i1 } [[TMP5040]], 0
|
|
// CHECK-NEXT: [[TMP5042:%.*]] = bitcast i32 [[TMP5041]] to float
|
|
// CHECK-NEXT: [[TMP5043:%.*]] = extractvalue { i32, i1 } [[TMP5040]], 1
|
|
// CHECK-NEXT: [[TMP5044:%.*]] = select i1 [[TMP5043]], float [[TMP5036]], float [[TMP5042]]
|
|
// CHECK-NEXT: store float [[TMP5044]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5045:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5046:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5047:%.*]] = bitcast float [[TMP5045]] to i32
|
|
// CHECK-NEXT: [[TMP5048:%.*]] = bitcast float [[TMP5046]] to i32
|
|
// CHECK-NEXT: [[TMP5049:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5047]], i32 [[TMP5048]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5050:%.*]] = extractvalue { i32, i1 } [[TMP5049]], 0
|
|
// CHECK-NEXT: [[TMP5051:%.*]] = bitcast i32 [[TMP5050]] to float
|
|
// CHECK-NEXT: [[TMP5052:%.*]] = extractvalue { i32, i1 } [[TMP5049]], 1
|
|
// CHECK-NEXT: [[TMP5053:%.*]] = select i1 [[TMP5052]], float [[TMP5045]], float [[TMP5051]]
|
|
// CHECK-NEXT: store float [[TMP5053]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP5054:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5055:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5056:%.*]] = bitcast float [[TMP5054]] to i32
|
|
// CHECK-NEXT: [[TMP5057:%.*]] = bitcast float [[TMP5055]] to i32
|
|
// CHECK-NEXT: [[TMP5058:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5056]], i32 [[TMP5057]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5059:%.*]] = extractvalue { i32, i1 } [[TMP5058]], 0
|
|
// CHECK-NEXT: [[TMP5060:%.*]] = bitcast i32 [[TMP5059]] to float
|
|
// CHECK-NEXT: [[TMP5061:%.*]] = extractvalue { i32, i1 } [[TMP5058]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5061]], label [[FX_ATOMIC_EXIT483:%.*]], label [[FX_ATOMIC_CONT484:%.*]]
|
|
// CHECK: fx.atomic.cont484:
|
|
// CHECK-NEXT: store float [[TMP5060]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT483]]
|
|
// CHECK: fx.atomic.exit483:
|
|
// CHECK-NEXT: [[TMP5062:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5063:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5064:%.*]] = bitcast float [[TMP5062]] to i32
|
|
// CHECK-NEXT: [[TMP5065:%.*]] = bitcast float [[TMP5063]] to i32
|
|
// CHECK-NEXT: [[TMP5066:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5064]], i32 [[TMP5065]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5067:%.*]] = extractvalue { i32, i1 } [[TMP5066]], 0
|
|
// CHECK-NEXT: [[TMP5068:%.*]] = bitcast i32 [[TMP5067]] to float
|
|
// CHECK-NEXT: [[TMP5069:%.*]] = extractvalue { i32, i1 } [[TMP5066]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5069]], label [[FX_ATOMIC_EXIT485:%.*]], label [[FX_ATOMIC_CONT486:%.*]]
|
|
// CHECK: fx.atomic.cont486:
|
|
// CHECK-NEXT: store float [[TMP5068]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT485]]
|
|
// CHECK: fx.atomic.exit485:
|
|
// CHECK-NEXT: [[TMP5070:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5071:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5072:%.*]] = bitcast float [[TMP5070]] to i32
|
|
// CHECK-NEXT: [[TMP5073:%.*]] = bitcast float [[TMP5071]] to i32
|
|
// CHECK-NEXT: [[TMP5074:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5072]], i32 [[TMP5073]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5075:%.*]] = extractvalue { i32, i1 } [[TMP5074]], 1
|
|
// CHECK-NEXT: [[TMP5076:%.*]] = sext i1 [[TMP5075]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5076]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5077:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5078:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5079:%.*]] = bitcast float [[TMP5077]] to i32
|
|
// CHECK-NEXT: [[TMP5080:%.*]] = bitcast float [[TMP5078]] to i32
|
|
// CHECK-NEXT: [[TMP5081:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5079]], i32 [[TMP5080]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5082:%.*]] = extractvalue { i32, i1 } [[TMP5081]], 1
|
|
// CHECK-NEXT: [[TMP5083:%.*]] = sext i1 [[TMP5082]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5083]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5084:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5085:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5086:%.*]] = bitcast float [[TMP5084]] to i32
|
|
// CHECK-NEXT: [[TMP5087:%.*]] = bitcast float [[TMP5085]] to i32
|
|
// CHECK-NEXT: [[TMP5088:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5086]], i32 [[TMP5087]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5089:%.*]] = extractvalue { i32, i1 } [[TMP5088]], 0
|
|
// CHECK-NEXT: [[TMP5090:%.*]] = bitcast i32 [[TMP5089]] to float
|
|
// CHECK-NEXT: [[TMP5091:%.*]] = extractvalue { i32, i1 } [[TMP5088]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5091]], label [[FX_ATOMIC_EXIT487:%.*]], label [[FX_ATOMIC_CONT488:%.*]]
|
|
// CHECK: fx.atomic.cont488:
|
|
// CHECK-NEXT: store float [[TMP5090]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT487]]
|
|
// CHECK: fx.atomic.exit487:
|
|
// CHECK-NEXT: [[TMP5092:%.*]] = extractvalue { i32, i1 } [[TMP5088]], 1
|
|
// CHECK-NEXT: [[TMP5093:%.*]] = sext i1 [[TMP5092]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5093]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5094:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5095:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5096:%.*]] = bitcast float [[TMP5094]] to i32
|
|
// CHECK-NEXT: [[TMP5097:%.*]] = bitcast float [[TMP5095]] to i32
|
|
// CHECK-NEXT: [[TMP5098:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5096]], i32 [[TMP5097]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5099:%.*]] = extractvalue { i32, i1 } [[TMP5098]], 0
|
|
// CHECK-NEXT: [[TMP5100:%.*]] = bitcast i32 [[TMP5099]] to float
|
|
// CHECK-NEXT: [[TMP5101:%.*]] = extractvalue { i32, i1 } [[TMP5098]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5101]], label [[FX_ATOMIC_EXIT489:%.*]], label [[FX_ATOMIC_CONT490:%.*]]
|
|
// CHECK: fx.atomic.cont490:
|
|
// CHECK-NEXT: store float [[TMP5100]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT489]]
|
|
// CHECK: fx.atomic.exit489:
|
|
// CHECK-NEXT: [[TMP5102:%.*]] = extractvalue { i32, i1 } [[TMP5098]], 1
|
|
// CHECK-NEXT: [[TMP5103:%.*]] = sext i1 [[TMP5102]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5103]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5104:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5105:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5104]] release, align 4
|
|
// CHECK-NEXT: store float [[TMP5105]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5106:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5107:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5106]] release, align 4
|
|
// CHECK-NEXT: store float [[TMP5107]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5108:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5109:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5108]] release, align 4
|
|
// CHECK-NEXT: store float [[TMP5109]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5110:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5111:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5110]] release, align 4
|
|
// CHECK-NEXT: store float [[TMP5111]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5112:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5113:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5114:%.*]] = bitcast float [[TMP5112]] to i32
|
|
// CHECK-NEXT: [[TMP5115:%.*]] = bitcast float [[TMP5113]] to i32
|
|
// CHECK-NEXT: [[TMP5116:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5114]], i32 [[TMP5115]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5117:%.*]] = extractvalue { i32, i1 } [[TMP5116]], 0
|
|
// CHECK-NEXT: [[TMP5118:%.*]] = bitcast i32 [[TMP5117]] to float
|
|
// CHECK-NEXT: store float [[TMP5118]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5119:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5120:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5121:%.*]] = bitcast float [[TMP5119]] to i32
|
|
// CHECK-NEXT: [[TMP5122:%.*]] = bitcast float [[TMP5120]] to i32
|
|
// CHECK-NEXT: [[TMP5123:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5121]], i32 [[TMP5122]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5124:%.*]] = extractvalue { i32, i1 } [[TMP5123]], 0
|
|
// CHECK-NEXT: [[TMP5125:%.*]] = bitcast i32 [[TMP5124]] to float
|
|
// CHECK-NEXT: store float [[TMP5125]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5126:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5127:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5126]] release, align 4
|
|
// CHECK-NEXT: [[TMP5128:%.*]] = fcmp ogt float [[TMP5127]], [[TMP5126]]
|
|
// CHECK-NEXT: [[TMP5129:%.*]] = select i1 [[TMP5128]], float [[TMP5126]], float [[TMP5127]]
|
|
// CHECK-NEXT: store float [[TMP5129]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5130:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5131:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5130]] release, align 4
|
|
// CHECK-NEXT: [[TMP5132:%.*]] = fcmp olt float [[TMP5131]], [[TMP5130]]
|
|
// CHECK-NEXT: [[TMP5133:%.*]] = select i1 [[TMP5132]], float [[TMP5130]], float [[TMP5131]]
|
|
// CHECK-NEXT: store float [[TMP5133]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5134:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5135:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5134]] release, align 4
|
|
// CHECK-NEXT: [[TMP5136:%.*]] = fcmp olt float [[TMP5135]], [[TMP5134]]
|
|
// CHECK-NEXT: [[TMP5137:%.*]] = select i1 [[TMP5136]], float [[TMP5134]], float [[TMP5135]]
|
|
// CHECK-NEXT: store float [[TMP5137]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5138:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5139:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5138]] release, align 4
|
|
// CHECK-NEXT: [[TMP5140:%.*]] = fcmp ogt float [[TMP5139]], [[TMP5138]]
|
|
// CHECK-NEXT: [[TMP5141:%.*]] = select i1 [[TMP5140]], float [[TMP5138]], float [[TMP5139]]
|
|
// CHECK-NEXT: store float [[TMP5141]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5142:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5143:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5144:%.*]] = bitcast float [[TMP5142]] to i32
|
|
// CHECK-NEXT: [[TMP5145:%.*]] = bitcast float [[TMP5143]] to i32
|
|
// CHECK-NEXT: [[TMP5146:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5144]], i32 [[TMP5145]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5147:%.*]] = extractvalue { i32, i1 } [[TMP5146]], 0
|
|
// CHECK-NEXT: [[TMP5148:%.*]] = bitcast i32 [[TMP5147]] to float
|
|
// CHECK-NEXT: [[TMP5149:%.*]] = extractvalue { i32, i1 } [[TMP5146]], 1
|
|
// CHECK-NEXT: [[TMP5150:%.*]] = select i1 [[TMP5149]], float [[TMP5142]], float [[TMP5148]]
|
|
// CHECK-NEXT: store float [[TMP5150]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5151:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5152:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5153:%.*]] = bitcast float [[TMP5151]] to i32
|
|
// CHECK-NEXT: [[TMP5154:%.*]] = bitcast float [[TMP5152]] to i32
|
|
// CHECK-NEXT: [[TMP5155:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5153]], i32 [[TMP5154]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5156:%.*]] = extractvalue { i32, i1 } [[TMP5155]], 0
|
|
// CHECK-NEXT: [[TMP5157:%.*]] = bitcast i32 [[TMP5156]] to float
|
|
// CHECK-NEXT: [[TMP5158:%.*]] = extractvalue { i32, i1 } [[TMP5155]], 1
|
|
// CHECK-NEXT: [[TMP5159:%.*]] = select i1 [[TMP5158]], float [[TMP5151]], float [[TMP5157]]
|
|
// CHECK-NEXT: store float [[TMP5159]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5160:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5161:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5162:%.*]] = bitcast float [[TMP5160]] to i32
|
|
// CHECK-NEXT: [[TMP5163:%.*]] = bitcast float [[TMP5161]] to i32
|
|
// CHECK-NEXT: [[TMP5164:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5162]], i32 [[TMP5163]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5165:%.*]] = extractvalue { i32, i1 } [[TMP5164]], 0
|
|
// CHECK-NEXT: [[TMP5166:%.*]] = bitcast i32 [[TMP5165]] to float
|
|
// CHECK-NEXT: [[TMP5167:%.*]] = extractvalue { i32, i1 } [[TMP5164]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5167]], label [[FX_ATOMIC_EXIT491:%.*]], label [[FX_ATOMIC_CONT492:%.*]]
|
|
// CHECK: fx.atomic.cont492:
|
|
// CHECK-NEXT: store float [[TMP5166]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT491]]
|
|
// CHECK: fx.atomic.exit491:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5168:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5169:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5170:%.*]] = bitcast float [[TMP5168]] to i32
|
|
// CHECK-NEXT: [[TMP5171:%.*]] = bitcast float [[TMP5169]] to i32
|
|
// CHECK-NEXT: [[TMP5172:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5170]], i32 [[TMP5171]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5173:%.*]] = extractvalue { i32, i1 } [[TMP5172]], 0
|
|
// CHECK-NEXT: [[TMP5174:%.*]] = bitcast i32 [[TMP5173]] to float
|
|
// CHECK-NEXT: [[TMP5175:%.*]] = extractvalue { i32, i1 } [[TMP5172]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5175]], label [[FX_ATOMIC_EXIT493:%.*]], label [[FX_ATOMIC_CONT494:%.*]]
|
|
// CHECK: fx.atomic.cont494:
|
|
// CHECK-NEXT: store float [[TMP5174]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT493]]
|
|
// CHECK: fx.atomic.exit493:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5176:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5177:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5178:%.*]] = bitcast float [[TMP5176]] to i32
|
|
// CHECK-NEXT: [[TMP5179:%.*]] = bitcast float [[TMP5177]] to i32
|
|
// CHECK-NEXT: [[TMP5180:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5178]], i32 [[TMP5179]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5181:%.*]] = extractvalue { i32, i1 } [[TMP5180]], 1
|
|
// CHECK-NEXT: [[TMP5182:%.*]] = sext i1 [[TMP5181]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5182]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5183:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5184:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5185:%.*]] = bitcast float [[TMP5183]] to i32
|
|
// CHECK-NEXT: [[TMP5186:%.*]] = bitcast float [[TMP5184]] to i32
|
|
// CHECK-NEXT: [[TMP5187:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5185]], i32 [[TMP5186]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5188:%.*]] = extractvalue { i32, i1 } [[TMP5187]], 1
|
|
// CHECK-NEXT: [[TMP5189:%.*]] = sext i1 [[TMP5188]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5189]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5190:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5191:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5192:%.*]] = bitcast float [[TMP5190]] to i32
|
|
// CHECK-NEXT: [[TMP5193:%.*]] = bitcast float [[TMP5191]] to i32
|
|
// CHECK-NEXT: [[TMP5194:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5192]], i32 [[TMP5193]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5195:%.*]] = extractvalue { i32, i1 } [[TMP5194]], 0
|
|
// CHECK-NEXT: [[TMP5196:%.*]] = bitcast i32 [[TMP5195]] to float
|
|
// CHECK-NEXT: [[TMP5197:%.*]] = extractvalue { i32, i1 } [[TMP5194]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5197]], label [[FX_ATOMIC_EXIT495:%.*]], label [[FX_ATOMIC_CONT496:%.*]]
|
|
// CHECK: fx.atomic.cont496:
|
|
// CHECK-NEXT: store float [[TMP5196]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT495]]
|
|
// CHECK: fx.atomic.exit495:
|
|
// CHECK-NEXT: [[TMP5198:%.*]] = extractvalue { i32, i1 } [[TMP5194]], 1
|
|
// CHECK-NEXT: [[TMP5199:%.*]] = sext i1 [[TMP5198]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5199]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5200:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5201:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5202:%.*]] = bitcast float [[TMP5200]] to i32
|
|
// CHECK-NEXT: [[TMP5203:%.*]] = bitcast float [[TMP5201]] to i32
|
|
// CHECK-NEXT: [[TMP5204:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5202]], i32 [[TMP5203]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP5205:%.*]] = extractvalue { i32, i1 } [[TMP5204]], 0
|
|
// CHECK-NEXT: [[TMP5206:%.*]] = bitcast i32 [[TMP5205]] to float
|
|
// CHECK-NEXT: [[TMP5207:%.*]] = extractvalue { i32, i1 } [[TMP5204]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5207]], label [[FX_ATOMIC_EXIT497:%.*]], label [[FX_ATOMIC_CONT498:%.*]]
|
|
// CHECK: fx.atomic.cont498:
|
|
// CHECK-NEXT: store float [[TMP5206]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT497]]
|
|
// CHECK: fx.atomic.exit497:
|
|
// CHECK-NEXT: [[TMP5208:%.*]] = extractvalue { i32, i1 } [[TMP5204]], 1
|
|
// CHECK-NEXT: [[TMP5209:%.*]] = sext i1 [[TMP5208]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5209]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5210:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5211:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5210]] seq_cst, align 4
|
|
// CHECK-NEXT: store float [[TMP5211]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5212:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5213:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5212]] seq_cst, align 4
|
|
// CHECK-NEXT: store float [[TMP5213]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5214:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5215:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5214]] seq_cst, align 4
|
|
// CHECK-NEXT: store float [[TMP5215]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5216:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5217:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5216]] seq_cst, align 4
|
|
// CHECK-NEXT: store float [[TMP5217]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5218:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5219:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5220:%.*]] = bitcast float [[TMP5218]] to i32
|
|
// CHECK-NEXT: [[TMP5221:%.*]] = bitcast float [[TMP5219]] to i32
|
|
// CHECK-NEXT: [[TMP5222:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5220]], i32 [[TMP5221]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5223:%.*]] = extractvalue { i32, i1 } [[TMP5222]], 0
|
|
// CHECK-NEXT: [[TMP5224:%.*]] = bitcast i32 [[TMP5223]] to float
|
|
// CHECK-NEXT: store float [[TMP5224]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5225:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5226:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5227:%.*]] = bitcast float [[TMP5225]] to i32
|
|
// CHECK-NEXT: [[TMP5228:%.*]] = bitcast float [[TMP5226]] to i32
|
|
// CHECK-NEXT: [[TMP5229:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5227]], i32 [[TMP5228]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5230:%.*]] = extractvalue { i32, i1 } [[TMP5229]], 0
|
|
// CHECK-NEXT: [[TMP5231:%.*]] = bitcast i32 [[TMP5230]] to float
|
|
// CHECK-NEXT: store float [[TMP5231]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5232:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5233:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5232]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5234:%.*]] = fcmp ogt float [[TMP5233]], [[TMP5232]]
|
|
// CHECK-NEXT: [[TMP5235:%.*]] = select i1 [[TMP5234]], float [[TMP5232]], float [[TMP5233]]
|
|
// CHECK-NEXT: store float [[TMP5235]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5236:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5237:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5236]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5238:%.*]] = fcmp olt float [[TMP5237]], [[TMP5236]]
|
|
// CHECK-NEXT: [[TMP5239:%.*]] = select i1 [[TMP5238]], float [[TMP5236]], float [[TMP5237]]
|
|
// CHECK-NEXT: store float [[TMP5239]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5240:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5241:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5240]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5242:%.*]] = fcmp olt float [[TMP5241]], [[TMP5240]]
|
|
// CHECK-NEXT: [[TMP5243:%.*]] = select i1 [[TMP5242]], float [[TMP5240]], float [[TMP5241]]
|
|
// CHECK-NEXT: store float [[TMP5243]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5244:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5245:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5244]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5246:%.*]] = fcmp ogt float [[TMP5245]], [[TMP5244]]
|
|
// CHECK-NEXT: [[TMP5247:%.*]] = select i1 [[TMP5246]], float [[TMP5244]], float [[TMP5245]]
|
|
// CHECK-NEXT: store float [[TMP5247]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5248:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5249:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5250:%.*]] = bitcast float [[TMP5248]] to i32
|
|
// CHECK-NEXT: [[TMP5251:%.*]] = bitcast float [[TMP5249]] to i32
|
|
// CHECK-NEXT: [[TMP5252:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5250]], i32 [[TMP5251]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5253:%.*]] = extractvalue { i32, i1 } [[TMP5252]], 0
|
|
// CHECK-NEXT: [[TMP5254:%.*]] = bitcast i32 [[TMP5253]] to float
|
|
// CHECK-NEXT: [[TMP5255:%.*]] = extractvalue { i32, i1 } [[TMP5252]], 1
|
|
// CHECK-NEXT: [[TMP5256:%.*]] = select i1 [[TMP5255]], float [[TMP5248]], float [[TMP5254]]
|
|
// CHECK-NEXT: store float [[TMP5256]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5257:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5258:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5259:%.*]] = bitcast float [[TMP5257]] to i32
|
|
// CHECK-NEXT: [[TMP5260:%.*]] = bitcast float [[TMP5258]] to i32
|
|
// CHECK-NEXT: [[TMP5261:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5259]], i32 [[TMP5260]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5262:%.*]] = extractvalue { i32, i1 } [[TMP5261]], 0
|
|
// CHECK-NEXT: [[TMP5263:%.*]] = bitcast i32 [[TMP5262]] to float
|
|
// CHECK-NEXT: [[TMP5264:%.*]] = extractvalue { i32, i1 } [[TMP5261]], 1
|
|
// CHECK-NEXT: [[TMP5265:%.*]] = select i1 [[TMP5264]], float [[TMP5257]], float [[TMP5263]]
|
|
// CHECK-NEXT: store float [[TMP5265]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5266:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5267:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5268:%.*]] = bitcast float [[TMP5266]] to i32
|
|
// CHECK-NEXT: [[TMP5269:%.*]] = bitcast float [[TMP5267]] to i32
|
|
// CHECK-NEXT: [[TMP5270:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5268]], i32 [[TMP5269]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5271:%.*]] = extractvalue { i32, i1 } [[TMP5270]], 0
|
|
// CHECK-NEXT: [[TMP5272:%.*]] = bitcast i32 [[TMP5271]] to float
|
|
// CHECK-NEXT: [[TMP5273:%.*]] = extractvalue { i32, i1 } [[TMP5270]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5273]], label [[FX_ATOMIC_EXIT499:%.*]], label [[FX_ATOMIC_CONT500:%.*]]
|
|
// CHECK: fx.atomic.cont500:
|
|
// CHECK-NEXT: store float [[TMP5272]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT499]]
|
|
// CHECK: fx.atomic.exit499:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5274:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5275:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5276:%.*]] = bitcast float [[TMP5274]] to i32
|
|
// CHECK-NEXT: [[TMP5277:%.*]] = bitcast float [[TMP5275]] to i32
|
|
// CHECK-NEXT: [[TMP5278:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5276]], i32 [[TMP5277]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5279:%.*]] = extractvalue { i32, i1 } [[TMP5278]], 0
|
|
// CHECK-NEXT: [[TMP5280:%.*]] = bitcast i32 [[TMP5279]] to float
|
|
// CHECK-NEXT: [[TMP5281:%.*]] = extractvalue { i32, i1 } [[TMP5278]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5281]], label [[FX_ATOMIC_EXIT501:%.*]], label [[FX_ATOMIC_CONT502:%.*]]
|
|
// CHECK: fx.atomic.cont502:
|
|
// CHECK-NEXT: store float [[TMP5280]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT501]]
|
|
// CHECK: fx.atomic.exit501:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5282:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5283:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5284:%.*]] = bitcast float [[TMP5282]] to i32
|
|
// CHECK-NEXT: [[TMP5285:%.*]] = bitcast float [[TMP5283]] to i32
|
|
// CHECK-NEXT: [[TMP5286:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5284]], i32 [[TMP5285]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5287:%.*]] = extractvalue { i32, i1 } [[TMP5286]], 1
|
|
// CHECK-NEXT: [[TMP5288:%.*]] = sext i1 [[TMP5287]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5288]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5289:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5290:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5291:%.*]] = bitcast float [[TMP5289]] to i32
|
|
// CHECK-NEXT: [[TMP5292:%.*]] = bitcast float [[TMP5290]] to i32
|
|
// CHECK-NEXT: [[TMP5293:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5291]], i32 [[TMP5292]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5294:%.*]] = extractvalue { i32, i1 } [[TMP5293]], 1
|
|
// CHECK-NEXT: [[TMP5295:%.*]] = sext i1 [[TMP5294]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5295]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5296:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5297:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5298:%.*]] = bitcast float [[TMP5296]] to i32
|
|
// CHECK-NEXT: [[TMP5299:%.*]] = bitcast float [[TMP5297]] to i32
|
|
// CHECK-NEXT: [[TMP5300:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5298]], i32 [[TMP5299]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5301:%.*]] = extractvalue { i32, i1 } [[TMP5300]], 0
|
|
// CHECK-NEXT: [[TMP5302:%.*]] = bitcast i32 [[TMP5301]] to float
|
|
// CHECK-NEXT: [[TMP5303:%.*]] = extractvalue { i32, i1 } [[TMP5300]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5303]], label [[FX_ATOMIC_EXIT503:%.*]], label [[FX_ATOMIC_CONT504:%.*]]
|
|
// CHECK: fx.atomic.cont504:
|
|
// CHECK-NEXT: store float [[TMP5302]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT503]]
|
|
// CHECK: fx.atomic.exit503:
|
|
// CHECK-NEXT: [[TMP5304:%.*]] = extractvalue { i32, i1 } [[TMP5300]], 1
|
|
// CHECK-NEXT: [[TMP5305:%.*]] = sext i1 [[TMP5304]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5305]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5306:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5307:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP5308:%.*]] = bitcast float [[TMP5306]] to i32
|
|
// CHECK-NEXT: [[TMP5309:%.*]] = bitcast float [[TMP5307]] to i32
|
|
// CHECK-NEXT: [[TMP5310:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5308]], i32 [[TMP5309]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP5311:%.*]] = extractvalue { i32, i1 } [[TMP5310]], 0
|
|
// CHECK-NEXT: [[TMP5312:%.*]] = bitcast i32 [[TMP5311]] to float
|
|
// CHECK-NEXT: [[TMP5313:%.*]] = extractvalue { i32, i1 } [[TMP5310]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5313]], label [[FX_ATOMIC_EXIT505:%.*]], label [[FX_ATOMIC_CONT506:%.*]]
|
|
// CHECK: fx.atomic.cont506:
|
|
// CHECK-NEXT: store float [[TMP5312]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT505]]
|
|
// CHECK: fx.atomic.exit505:
|
|
// CHECK-NEXT: [[TMP5314:%.*]] = extractvalue { i32, i1 } [[TMP5310]], 1
|
|
// CHECK-NEXT: [[TMP5315:%.*]] = sext i1 [[TMP5314]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5315]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5316:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5317:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5316]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP5317]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5318:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5319:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5318]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP5319]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5320:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5321:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5320]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP5321]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5322:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5323:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5322]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP5323]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5324:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5325:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5326:%.*]] = bitcast double [[TMP5324]] to i64
|
|
// CHECK-NEXT: [[TMP5327:%.*]] = bitcast double [[TMP5325]] to i64
|
|
// CHECK-NEXT: [[TMP5328:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5326]], i64 [[TMP5327]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5329:%.*]] = extractvalue { i64, i1 } [[TMP5328]], 0
|
|
// CHECK-NEXT: [[TMP5330:%.*]] = bitcast i64 [[TMP5329]] to double
|
|
// CHECK-NEXT: store double [[TMP5330]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5331:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5332:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5333:%.*]] = bitcast double [[TMP5331]] to i64
|
|
// CHECK-NEXT: [[TMP5334:%.*]] = bitcast double [[TMP5332]] to i64
|
|
// CHECK-NEXT: [[TMP5335:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5333]], i64 [[TMP5334]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5336:%.*]] = extractvalue { i64, i1 } [[TMP5335]], 0
|
|
// CHECK-NEXT: [[TMP5337:%.*]] = bitcast i64 [[TMP5336]] to double
|
|
// CHECK-NEXT: store double [[TMP5337]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5338:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5339:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5338]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5340:%.*]] = fcmp ogt double [[TMP5339]], [[TMP5338]]
|
|
// CHECK-NEXT: [[TMP5341:%.*]] = select i1 [[TMP5340]], double [[TMP5338]], double [[TMP5339]]
|
|
// CHECK-NEXT: store double [[TMP5341]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5342:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5343:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5342]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5344:%.*]] = fcmp olt double [[TMP5343]], [[TMP5342]]
|
|
// CHECK-NEXT: [[TMP5345:%.*]] = select i1 [[TMP5344]], double [[TMP5342]], double [[TMP5343]]
|
|
// CHECK-NEXT: store double [[TMP5345]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5346:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5347:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5346]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5348:%.*]] = fcmp olt double [[TMP5347]], [[TMP5346]]
|
|
// CHECK-NEXT: [[TMP5349:%.*]] = select i1 [[TMP5348]], double [[TMP5346]], double [[TMP5347]]
|
|
// CHECK-NEXT: store double [[TMP5349]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5350:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5351:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5350]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5352:%.*]] = fcmp ogt double [[TMP5351]], [[TMP5350]]
|
|
// CHECK-NEXT: [[TMP5353:%.*]] = select i1 [[TMP5352]], double [[TMP5350]], double [[TMP5351]]
|
|
// CHECK-NEXT: store double [[TMP5353]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5354:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5355:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5356:%.*]] = bitcast double [[TMP5354]] to i64
|
|
// CHECK-NEXT: [[TMP5357:%.*]] = bitcast double [[TMP5355]] to i64
|
|
// CHECK-NEXT: [[TMP5358:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5356]], i64 [[TMP5357]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5359:%.*]] = extractvalue { i64, i1 } [[TMP5358]], 0
|
|
// CHECK-NEXT: [[TMP5360:%.*]] = bitcast i64 [[TMP5359]] to double
|
|
// CHECK-NEXT: [[TMP5361:%.*]] = extractvalue { i64, i1 } [[TMP5358]], 1
|
|
// CHECK-NEXT: [[TMP5362:%.*]] = select i1 [[TMP5361]], double [[TMP5354]], double [[TMP5360]]
|
|
// CHECK-NEXT: store double [[TMP5362]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5363:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5364:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5365:%.*]] = bitcast double [[TMP5363]] to i64
|
|
// CHECK-NEXT: [[TMP5366:%.*]] = bitcast double [[TMP5364]] to i64
|
|
// CHECK-NEXT: [[TMP5367:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5365]], i64 [[TMP5366]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5368:%.*]] = extractvalue { i64, i1 } [[TMP5367]], 0
|
|
// CHECK-NEXT: [[TMP5369:%.*]] = bitcast i64 [[TMP5368]] to double
|
|
// CHECK-NEXT: [[TMP5370:%.*]] = extractvalue { i64, i1 } [[TMP5367]], 1
|
|
// CHECK-NEXT: [[TMP5371:%.*]] = select i1 [[TMP5370]], double [[TMP5363]], double [[TMP5369]]
|
|
// CHECK-NEXT: store double [[TMP5371]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5372:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5373:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5374:%.*]] = bitcast double [[TMP5372]] to i64
|
|
// CHECK-NEXT: [[TMP5375:%.*]] = bitcast double [[TMP5373]] to i64
|
|
// CHECK-NEXT: [[TMP5376:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5374]], i64 [[TMP5375]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5377:%.*]] = extractvalue { i64, i1 } [[TMP5376]], 0
|
|
// CHECK-NEXT: [[TMP5378:%.*]] = bitcast i64 [[TMP5377]] to double
|
|
// CHECK-NEXT: [[TMP5379:%.*]] = extractvalue { i64, i1 } [[TMP5376]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5379]], label [[DX_ATOMIC_EXIT:%.*]], label [[DX_ATOMIC_CONT:%.*]]
|
|
// CHECK: dx.atomic.cont:
|
|
// CHECK-NEXT: store double [[TMP5378]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT]]
|
|
// CHECK: dx.atomic.exit:
|
|
// CHECK-NEXT: [[TMP5380:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5381:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5382:%.*]] = bitcast double [[TMP5380]] to i64
|
|
// CHECK-NEXT: [[TMP5383:%.*]] = bitcast double [[TMP5381]] to i64
|
|
// CHECK-NEXT: [[TMP5384:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5382]], i64 [[TMP5383]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5385:%.*]] = extractvalue { i64, i1 } [[TMP5384]], 0
|
|
// CHECK-NEXT: [[TMP5386:%.*]] = bitcast i64 [[TMP5385]] to double
|
|
// CHECK-NEXT: [[TMP5387:%.*]] = extractvalue { i64, i1 } [[TMP5384]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5387]], label [[DX_ATOMIC_EXIT507:%.*]], label [[DX_ATOMIC_CONT508:%.*]]
|
|
// CHECK: dx.atomic.cont508:
|
|
// CHECK-NEXT: store double [[TMP5386]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT507]]
|
|
// CHECK: dx.atomic.exit507:
|
|
// CHECK-NEXT: [[TMP5388:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5389:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5390:%.*]] = bitcast double [[TMP5388]] to i64
|
|
// CHECK-NEXT: [[TMP5391:%.*]] = bitcast double [[TMP5389]] to i64
|
|
// CHECK-NEXT: [[TMP5392:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5390]], i64 [[TMP5391]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5393:%.*]] = extractvalue { i64, i1 } [[TMP5392]], 1
|
|
// CHECK-NEXT: [[TMP5394:%.*]] = sext i1 [[TMP5393]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5394]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5395:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5396:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5397:%.*]] = bitcast double [[TMP5395]] to i64
|
|
// CHECK-NEXT: [[TMP5398:%.*]] = bitcast double [[TMP5396]] to i64
|
|
// CHECK-NEXT: [[TMP5399:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5397]], i64 [[TMP5398]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5400:%.*]] = extractvalue { i64, i1 } [[TMP5399]], 1
|
|
// CHECK-NEXT: [[TMP5401:%.*]] = sext i1 [[TMP5400]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5401]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5402:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5403:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5404:%.*]] = bitcast double [[TMP5402]] to i64
|
|
// CHECK-NEXT: [[TMP5405:%.*]] = bitcast double [[TMP5403]] to i64
|
|
// CHECK-NEXT: [[TMP5406:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5404]], i64 [[TMP5405]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5407:%.*]] = extractvalue { i64, i1 } [[TMP5406]], 0
|
|
// CHECK-NEXT: [[TMP5408:%.*]] = bitcast i64 [[TMP5407]] to double
|
|
// CHECK-NEXT: [[TMP5409:%.*]] = extractvalue { i64, i1 } [[TMP5406]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5409]], label [[DX_ATOMIC_EXIT509:%.*]], label [[DX_ATOMIC_CONT510:%.*]]
|
|
// CHECK: dx.atomic.cont510:
|
|
// CHECK-NEXT: store double [[TMP5408]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT509]]
|
|
// CHECK: dx.atomic.exit509:
|
|
// CHECK-NEXT: [[TMP5410:%.*]] = extractvalue { i64, i1 } [[TMP5406]], 1
|
|
// CHECK-NEXT: [[TMP5411:%.*]] = sext i1 [[TMP5410]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5411]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5412:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5413:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5414:%.*]] = bitcast double [[TMP5412]] to i64
|
|
// CHECK-NEXT: [[TMP5415:%.*]] = bitcast double [[TMP5413]] to i64
|
|
// CHECK-NEXT: [[TMP5416:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5414]], i64 [[TMP5415]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5417:%.*]] = extractvalue { i64, i1 } [[TMP5416]], 0
|
|
// CHECK-NEXT: [[TMP5418:%.*]] = bitcast i64 [[TMP5417]] to double
|
|
// CHECK-NEXT: [[TMP5419:%.*]] = extractvalue { i64, i1 } [[TMP5416]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5419]], label [[DX_ATOMIC_EXIT511:%.*]], label [[DX_ATOMIC_CONT512:%.*]]
|
|
// CHECK: dx.atomic.cont512:
|
|
// CHECK-NEXT: store double [[TMP5418]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT511]]
|
|
// CHECK: dx.atomic.exit511:
|
|
// CHECK-NEXT: [[TMP5420:%.*]] = extractvalue { i64, i1 } [[TMP5416]], 1
|
|
// CHECK-NEXT: [[TMP5421:%.*]] = sext i1 [[TMP5420]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5421]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5422:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5423:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5422]] acq_rel, align 8
|
|
// CHECK-NEXT: store double [[TMP5423]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5424:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5425:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5424]] acq_rel, align 8
|
|
// CHECK-NEXT: store double [[TMP5425]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5426:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5427:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5426]] acq_rel, align 8
|
|
// CHECK-NEXT: store double [[TMP5427]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5428:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5429:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5428]] acq_rel, align 8
|
|
// CHECK-NEXT: store double [[TMP5429]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5430:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5431:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5432:%.*]] = bitcast double [[TMP5430]] to i64
|
|
// CHECK-NEXT: [[TMP5433:%.*]] = bitcast double [[TMP5431]] to i64
|
|
// CHECK-NEXT: [[TMP5434:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5432]], i64 [[TMP5433]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5435:%.*]] = extractvalue { i64, i1 } [[TMP5434]], 0
|
|
// CHECK-NEXT: [[TMP5436:%.*]] = bitcast i64 [[TMP5435]] to double
|
|
// CHECK-NEXT: store double [[TMP5436]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5437:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5438:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5439:%.*]] = bitcast double [[TMP5437]] to i64
|
|
// CHECK-NEXT: [[TMP5440:%.*]] = bitcast double [[TMP5438]] to i64
|
|
// CHECK-NEXT: [[TMP5441:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5439]], i64 [[TMP5440]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5442:%.*]] = extractvalue { i64, i1 } [[TMP5441]], 0
|
|
// CHECK-NEXT: [[TMP5443:%.*]] = bitcast i64 [[TMP5442]] to double
|
|
// CHECK-NEXT: store double [[TMP5443]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5444:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5445:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5444]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP5446:%.*]] = fcmp ogt double [[TMP5445]], [[TMP5444]]
|
|
// CHECK-NEXT: [[TMP5447:%.*]] = select i1 [[TMP5446]], double [[TMP5444]], double [[TMP5445]]
|
|
// CHECK-NEXT: store double [[TMP5447]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5448:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5449:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5448]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP5450:%.*]] = fcmp olt double [[TMP5449]], [[TMP5448]]
|
|
// CHECK-NEXT: [[TMP5451:%.*]] = select i1 [[TMP5450]], double [[TMP5448]], double [[TMP5449]]
|
|
// CHECK-NEXT: store double [[TMP5451]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5452:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5453:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5452]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP5454:%.*]] = fcmp olt double [[TMP5453]], [[TMP5452]]
|
|
// CHECK-NEXT: [[TMP5455:%.*]] = select i1 [[TMP5454]], double [[TMP5452]], double [[TMP5453]]
|
|
// CHECK-NEXT: store double [[TMP5455]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5456:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5457:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5456]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP5458:%.*]] = fcmp ogt double [[TMP5457]], [[TMP5456]]
|
|
// CHECK-NEXT: [[TMP5459:%.*]] = select i1 [[TMP5458]], double [[TMP5456]], double [[TMP5457]]
|
|
// CHECK-NEXT: store double [[TMP5459]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5460:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5461:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5462:%.*]] = bitcast double [[TMP5460]] to i64
|
|
// CHECK-NEXT: [[TMP5463:%.*]] = bitcast double [[TMP5461]] to i64
|
|
// CHECK-NEXT: [[TMP5464:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5462]], i64 [[TMP5463]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5465:%.*]] = extractvalue { i64, i1 } [[TMP5464]], 0
|
|
// CHECK-NEXT: [[TMP5466:%.*]] = bitcast i64 [[TMP5465]] to double
|
|
// CHECK-NEXT: [[TMP5467:%.*]] = extractvalue { i64, i1 } [[TMP5464]], 1
|
|
// CHECK-NEXT: [[TMP5468:%.*]] = select i1 [[TMP5467]], double [[TMP5460]], double [[TMP5466]]
|
|
// CHECK-NEXT: store double [[TMP5468]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5469:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5470:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5471:%.*]] = bitcast double [[TMP5469]] to i64
|
|
// CHECK-NEXT: [[TMP5472:%.*]] = bitcast double [[TMP5470]] to i64
|
|
// CHECK-NEXT: [[TMP5473:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5471]], i64 [[TMP5472]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5474:%.*]] = extractvalue { i64, i1 } [[TMP5473]], 0
|
|
// CHECK-NEXT: [[TMP5475:%.*]] = bitcast i64 [[TMP5474]] to double
|
|
// CHECK-NEXT: [[TMP5476:%.*]] = extractvalue { i64, i1 } [[TMP5473]], 1
|
|
// CHECK-NEXT: [[TMP5477:%.*]] = select i1 [[TMP5476]], double [[TMP5469]], double [[TMP5475]]
|
|
// CHECK-NEXT: store double [[TMP5477]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5478:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5479:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5480:%.*]] = bitcast double [[TMP5478]] to i64
|
|
// CHECK-NEXT: [[TMP5481:%.*]] = bitcast double [[TMP5479]] to i64
|
|
// CHECK-NEXT: [[TMP5482:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5480]], i64 [[TMP5481]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5483:%.*]] = extractvalue { i64, i1 } [[TMP5482]], 0
|
|
// CHECK-NEXT: [[TMP5484:%.*]] = bitcast i64 [[TMP5483]] to double
|
|
// CHECK-NEXT: [[TMP5485:%.*]] = extractvalue { i64, i1 } [[TMP5482]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5485]], label [[DX_ATOMIC_EXIT513:%.*]], label [[DX_ATOMIC_CONT514:%.*]]
|
|
// CHECK: dx.atomic.cont514:
|
|
// CHECK-NEXT: store double [[TMP5484]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT513]]
|
|
// CHECK: dx.atomic.exit513:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5486:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5487:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5488:%.*]] = bitcast double [[TMP5486]] to i64
|
|
// CHECK-NEXT: [[TMP5489:%.*]] = bitcast double [[TMP5487]] to i64
|
|
// CHECK-NEXT: [[TMP5490:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5488]], i64 [[TMP5489]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5491:%.*]] = extractvalue { i64, i1 } [[TMP5490]], 0
|
|
// CHECK-NEXT: [[TMP5492:%.*]] = bitcast i64 [[TMP5491]] to double
|
|
// CHECK-NEXT: [[TMP5493:%.*]] = extractvalue { i64, i1 } [[TMP5490]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5493]], label [[DX_ATOMIC_EXIT515:%.*]], label [[DX_ATOMIC_CONT516:%.*]]
|
|
// CHECK: dx.atomic.cont516:
|
|
// CHECK-NEXT: store double [[TMP5492]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT515]]
|
|
// CHECK: dx.atomic.exit515:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5494:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5495:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5496:%.*]] = bitcast double [[TMP5494]] to i64
|
|
// CHECK-NEXT: [[TMP5497:%.*]] = bitcast double [[TMP5495]] to i64
|
|
// CHECK-NEXT: [[TMP5498:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5496]], i64 [[TMP5497]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5499:%.*]] = extractvalue { i64, i1 } [[TMP5498]], 1
|
|
// CHECK-NEXT: [[TMP5500:%.*]] = sext i1 [[TMP5499]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5500]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5501:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5502:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5503:%.*]] = bitcast double [[TMP5501]] to i64
|
|
// CHECK-NEXT: [[TMP5504:%.*]] = bitcast double [[TMP5502]] to i64
|
|
// CHECK-NEXT: [[TMP5505:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5503]], i64 [[TMP5504]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5506:%.*]] = extractvalue { i64, i1 } [[TMP5505]], 1
|
|
// CHECK-NEXT: [[TMP5507:%.*]] = sext i1 [[TMP5506]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5507]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5508:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5509:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5510:%.*]] = bitcast double [[TMP5508]] to i64
|
|
// CHECK-NEXT: [[TMP5511:%.*]] = bitcast double [[TMP5509]] to i64
|
|
// CHECK-NEXT: [[TMP5512:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5510]], i64 [[TMP5511]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5513:%.*]] = extractvalue { i64, i1 } [[TMP5512]], 0
|
|
// CHECK-NEXT: [[TMP5514:%.*]] = bitcast i64 [[TMP5513]] to double
|
|
// CHECK-NEXT: [[TMP5515:%.*]] = extractvalue { i64, i1 } [[TMP5512]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5515]], label [[DX_ATOMIC_EXIT517:%.*]], label [[DX_ATOMIC_CONT518:%.*]]
|
|
// CHECK: dx.atomic.cont518:
|
|
// CHECK-NEXT: store double [[TMP5514]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT517]]
|
|
// CHECK: dx.atomic.exit517:
|
|
// CHECK-NEXT: [[TMP5516:%.*]] = extractvalue { i64, i1 } [[TMP5512]], 1
|
|
// CHECK-NEXT: [[TMP5517:%.*]] = sext i1 [[TMP5516]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5517]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5518:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5519:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5520:%.*]] = bitcast double [[TMP5518]] to i64
|
|
// CHECK-NEXT: [[TMP5521:%.*]] = bitcast double [[TMP5519]] to i64
|
|
// CHECK-NEXT: [[TMP5522:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5520]], i64 [[TMP5521]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP5523:%.*]] = extractvalue { i64, i1 } [[TMP5522]], 0
|
|
// CHECK-NEXT: [[TMP5524:%.*]] = bitcast i64 [[TMP5523]] to double
|
|
// CHECK-NEXT: [[TMP5525:%.*]] = extractvalue { i64, i1 } [[TMP5522]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5525]], label [[DX_ATOMIC_EXIT519:%.*]], label [[DX_ATOMIC_CONT520:%.*]]
|
|
// CHECK: dx.atomic.cont520:
|
|
// CHECK-NEXT: store double [[TMP5524]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT519]]
|
|
// CHECK: dx.atomic.exit519:
|
|
// CHECK-NEXT: [[TMP5526:%.*]] = extractvalue { i64, i1 } [[TMP5522]], 1
|
|
// CHECK-NEXT: [[TMP5527:%.*]] = sext i1 [[TMP5526]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5527]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5528:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5529:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5528]] acquire, align 8
|
|
// CHECK-NEXT: store double [[TMP5529]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5530:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5531:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5530]] acquire, align 8
|
|
// CHECK-NEXT: store double [[TMP5531]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5532:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5533:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5532]] acquire, align 8
|
|
// CHECK-NEXT: store double [[TMP5533]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5534:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5535:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5534]] acquire, align 8
|
|
// CHECK-NEXT: store double [[TMP5535]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5536:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5537:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5538:%.*]] = bitcast double [[TMP5536]] to i64
|
|
// CHECK-NEXT: [[TMP5539:%.*]] = bitcast double [[TMP5537]] to i64
|
|
// CHECK-NEXT: [[TMP5540:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5538]], i64 [[TMP5539]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5541:%.*]] = extractvalue { i64, i1 } [[TMP5540]], 0
|
|
// CHECK-NEXT: [[TMP5542:%.*]] = bitcast i64 [[TMP5541]] to double
|
|
// CHECK-NEXT: store double [[TMP5542]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5543:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5544:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5545:%.*]] = bitcast double [[TMP5543]] to i64
|
|
// CHECK-NEXT: [[TMP5546:%.*]] = bitcast double [[TMP5544]] to i64
|
|
// CHECK-NEXT: [[TMP5547:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5545]], i64 [[TMP5546]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5548:%.*]] = extractvalue { i64, i1 } [[TMP5547]], 0
|
|
// CHECK-NEXT: [[TMP5549:%.*]] = bitcast i64 [[TMP5548]] to double
|
|
// CHECK-NEXT: store double [[TMP5549]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5550:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5551:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5550]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP5552:%.*]] = fcmp ogt double [[TMP5551]], [[TMP5550]]
|
|
// CHECK-NEXT: [[TMP5553:%.*]] = select i1 [[TMP5552]], double [[TMP5550]], double [[TMP5551]]
|
|
// CHECK-NEXT: store double [[TMP5553]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5554:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5555:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5554]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP5556:%.*]] = fcmp olt double [[TMP5555]], [[TMP5554]]
|
|
// CHECK-NEXT: [[TMP5557:%.*]] = select i1 [[TMP5556]], double [[TMP5554]], double [[TMP5555]]
|
|
// CHECK-NEXT: store double [[TMP5557]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5558:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5559:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5558]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP5560:%.*]] = fcmp olt double [[TMP5559]], [[TMP5558]]
|
|
// CHECK-NEXT: [[TMP5561:%.*]] = select i1 [[TMP5560]], double [[TMP5558]], double [[TMP5559]]
|
|
// CHECK-NEXT: store double [[TMP5561]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5562:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5563:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5562]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP5564:%.*]] = fcmp ogt double [[TMP5563]], [[TMP5562]]
|
|
// CHECK-NEXT: [[TMP5565:%.*]] = select i1 [[TMP5564]], double [[TMP5562]], double [[TMP5563]]
|
|
// CHECK-NEXT: store double [[TMP5565]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5566:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5567:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5568:%.*]] = bitcast double [[TMP5566]] to i64
|
|
// CHECK-NEXT: [[TMP5569:%.*]] = bitcast double [[TMP5567]] to i64
|
|
// CHECK-NEXT: [[TMP5570:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5568]], i64 [[TMP5569]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5571:%.*]] = extractvalue { i64, i1 } [[TMP5570]], 0
|
|
// CHECK-NEXT: [[TMP5572:%.*]] = bitcast i64 [[TMP5571]] to double
|
|
// CHECK-NEXT: [[TMP5573:%.*]] = extractvalue { i64, i1 } [[TMP5570]], 1
|
|
// CHECK-NEXT: [[TMP5574:%.*]] = select i1 [[TMP5573]], double [[TMP5566]], double [[TMP5572]]
|
|
// CHECK-NEXT: store double [[TMP5574]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5575:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5576:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5577:%.*]] = bitcast double [[TMP5575]] to i64
|
|
// CHECK-NEXT: [[TMP5578:%.*]] = bitcast double [[TMP5576]] to i64
|
|
// CHECK-NEXT: [[TMP5579:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5577]], i64 [[TMP5578]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5580:%.*]] = extractvalue { i64, i1 } [[TMP5579]], 0
|
|
// CHECK-NEXT: [[TMP5581:%.*]] = bitcast i64 [[TMP5580]] to double
|
|
// CHECK-NEXT: [[TMP5582:%.*]] = extractvalue { i64, i1 } [[TMP5579]], 1
|
|
// CHECK-NEXT: [[TMP5583:%.*]] = select i1 [[TMP5582]], double [[TMP5575]], double [[TMP5581]]
|
|
// CHECK-NEXT: store double [[TMP5583]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5584:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5585:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5586:%.*]] = bitcast double [[TMP5584]] to i64
|
|
// CHECK-NEXT: [[TMP5587:%.*]] = bitcast double [[TMP5585]] to i64
|
|
// CHECK-NEXT: [[TMP5588:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5586]], i64 [[TMP5587]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5589:%.*]] = extractvalue { i64, i1 } [[TMP5588]], 0
|
|
// CHECK-NEXT: [[TMP5590:%.*]] = bitcast i64 [[TMP5589]] to double
|
|
// CHECK-NEXT: [[TMP5591:%.*]] = extractvalue { i64, i1 } [[TMP5588]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5591]], label [[DX_ATOMIC_EXIT521:%.*]], label [[DX_ATOMIC_CONT522:%.*]]
|
|
// CHECK: dx.atomic.cont522:
|
|
// CHECK-NEXT: store double [[TMP5590]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT521]]
|
|
// CHECK: dx.atomic.exit521:
|
|
// CHECK-NEXT: [[TMP5592:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5593:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5594:%.*]] = bitcast double [[TMP5592]] to i64
|
|
// CHECK-NEXT: [[TMP5595:%.*]] = bitcast double [[TMP5593]] to i64
|
|
// CHECK-NEXT: [[TMP5596:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5594]], i64 [[TMP5595]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5597:%.*]] = extractvalue { i64, i1 } [[TMP5596]], 0
|
|
// CHECK-NEXT: [[TMP5598:%.*]] = bitcast i64 [[TMP5597]] to double
|
|
// CHECK-NEXT: [[TMP5599:%.*]] = extractvalue { i64, i1 } [[TMP5596]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5599]], label [[DX_ATOMIC_EXIT523:%.*]], label [[DX_ATOMIC_CONT524:%.*]]
|
|
// CHECK: dx.atomic.cont524:
|
|
// CHECK-NEXT: store double [[TMP5598]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT523]]
|
|
// CHECK: dx.atomic.exit523:
|
|
// CHECK-NEXT: [[TMP5600:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5601:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5602:%.*]] = bitcast double [[TMP5600]] to i64
|
|
// CHECK-NEXT: [[TMP5603:%.*]] = bitcast double [[TMP5601]] to i64
|
|
// CHECK-NEXT: [[TMP5604:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5602]], i64 [[TMP5603]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5605:%.*]] = extractvalue { i64, i1 } [[TMP5604]], 1
|
|
// CHECK-NEXT: [[TMP5606:%.*]] = sext i1 [[TMP5605]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5606]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5607:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5608:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5609:%.*]] = bitcast double [[TMP5607]] to i64
|
|
// CHECK-NEXT: [[TMP5610:%.*]] = bitcast double [[TMP5608]] to i64
|
|
// CHECK-NEXT: [[TMP5611:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5609]], i64 [[TMP5610]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5612:%.*]] = extractvalue { i64, i1 } [[TMP5611]], 1
|
|
// CHECK-NEXT: [[TMP5613:%.*]] = sext i1 [[TMP5612]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5613]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5614:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5615:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5616:%.*]] = bitcast double [[TMP5614]] to i64
|
|
// CHECK-NEXT: [[TMP5617:%.*]] = bitcast double [[TMP5615]] to i64
|
|
// CHECK-NEXT: [[TMP5618:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5616]], i64 [[TMP5617]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5619:%.*]] = extractvalue { i64, i1 } [[TMP5618]], 0
|
|
// CHECK-NEXT: [[TMP5620:%.*]] = bitcast i64 [[TMP5619]] to double
|
|
// CHECK-NEXT: [[TMP5621:%.*]] = extractvalue { i64, i1 } [[TMP5618]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5621]], label [[DX_ATOMIC_EXIT525:%.*]], label [[DX_ATOMIC_CONT526:%.*]]
|
|
// CHECK: dx.atomic.cont526:
|
|
// CHECK-NEXT: store double [[TMP5620]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT525]]
|
|
// CHECK: dx.atomic.exit525:
|
|
// CHECK-NEXT: [[TMP5622:%.*]] = extractvalue { i64, i1 } [[TMP5618]], 1
|
|
// CHECK-NEXT: [[TMP5623:%.*]] = sext i1 [[TMP5622]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5623]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5624:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5625:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5626:%.*]] = bitcast double [[TMP5624]] to i64
|
|
// CHECK-NEXT: [[TMP5627:%.*]] = bitcast double [[TMP5625]] to i64
|
|
// CHECK-NEXT: [[TMP5628:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5626]], i64 [[TMP5627]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP5629:%.*]] = extractvalue { i64, i1 } [[TMP5628]], 0
|
|
// CHECK-NEXT: [[TMP5630:%.*]] = bitcast i64 [[TMP5629]] to double
|
|
// CHECK-NEXT: [[TMP5631:%.*]] = extractvalue { i64, i1 } [[TMP5628]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5631]], label [[DX_ATOMIC_EXIT527:%.*]], label [[DX_ATOMIC_CONT528:%.*]]
|
|
// CHECK: dx.atomic.cont528:
|
|
// CHECK-NEXT: store double [[TMP5630]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT527]]
|
|
// CHECK: dx.atomic.exit527:
|
|
// CHECK-NEXT: [[TMP5632:%.*]] = extractvalue { i64, i1 } [[TMP5628]], 1
|
|
// CHECK-NEXT: [[TMP5633:%.*]] = sext i1 [[TMP5632]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5633]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5634:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5635:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5634]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP5635]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5636:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5637:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5636]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP5637]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5638:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5639:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5638]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP5639]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5640:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5641:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5640]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP5641]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5642:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5643:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5644:%.*]] = bitcast double [[TMP5642]] to i64
|
|
// CHECK-NEXT: [[TMP5645:%.*]] = bitcast double [[TMP5643]] to i64
|
|
// CHECK-NEXT: [[TMP5646:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5644]], i64 [[TMP5645]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5647:%.*]] = extractvalue { i64, i1 } [[TMP5646]], 0
|
|
// CHECK-NEXT: [[TMP5648:%.*]] = bitcast i64 [[TMP5647]] to double
|
|
// CHECK-NEXT: store double [[TMP5648]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5649:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5650:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5651:%.*]] = bitcast double [[TMP5649]] to i64
|
|
// CHECK-NEXT: [[TMP5652:%.*]] = bitcast double [[TMP5650]] to i64
|
|
// CHECK-NEXT: [[TMP5653:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5651]], i64 [[TMP5652]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5654:%.*]] = extractvalue { i64, i1 } [[TMP5653]], 0
|
|
// CHECK-NEXT: [[TMP5655:%.*]] = bitcast i64 [[TMP5654]] to double
|
|
// CHECK-NEXT: store double [[TMP5655]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5656:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5657:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5656]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5658:%.*]] = fcmp ogt double [[TMP5657]], [[TMP5656]]
|
|
// CHECK-NEXT: [[TMP5659:%.*]] = select i1 [[TMP5658]], double [[TMP5656]], double [[TMP5657]]
|
|
// CHECK-NEXT: store double [[TMP5659]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5660:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5661:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5660]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5662:%.*]] = fcmp olt double [[TMP5661]], [[TMP5660]]
|
|
// CHECK-NEXT: [[TMP5663:%.*]] = select i1 [[TMP5662]], double [[TMP5660]], double [[TMP5661]]
|
|
// CHECK-NEXT: store double [[TMP5663]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5664:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5665:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5664]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5666:%.*]] = fcmp olt double [[TMP5665]], [[TMP5664]]
|
|
// CHECK-NEXT: [[TMP5667:%.*]] = select i1 [[TMP5666]], double [[TMP5664]], double [[TMP5665]]
|
|
// CHECK-NEXT: store double [[TMP5667]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5668:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5669:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5668]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5670:%.*]] = fcmp ogt double [[TMP5669]], [[TMP5668]]
|
|
// CHECK-NEXT: [[TMP5671:%.*]] = select i1 [[TMP5670]], double [[TMP5668]], double [[TMP5669]]
|
|
// CHECK-NEXT: store double [[TMP5671]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5672:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5673:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5674:%.*]] = bitcast double [[TMP5672]] to i64
|
|
// CHECK-NEXT: [[TMP5675:%.*]] = bitcast double [[TMP5673]] to i64
|
|
// CHECK-NEXT: [[TMP5676:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5674]], i64 [[TMP5675]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5677:%.*]] = extractvalue { i64, i1 } [[TMP5676]], 0
|
|
// CHECK-NEXT: [[TMP5678:%.*]] = bitcast i64 [[TMP5677]] to double
|
|
// CHECK-NEXT: [[TMP5679:%.*]] = extractvalue { i64, i1 } [[TMP5676]], 1
|
|
// CHECK-NEXT: [[TMP5680:%.*]] = select i1 [[TMP5679]], double [[TMP5672]], double [[TMP5678]]
|
|
// CHECK-NEXT: store double [[TMP5680]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5681:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5682:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5683:%.*]] = bitcast double [[TMP5681]] to i64
|
|
// CHECK-NEXT: [[TMP5684:%.*]] = bitcast double [[TMP5682]] to i64
|
|
// CHECK-NEXT: [[TMP5685:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5683]], i64 [[TMP5684]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5686:%.*]] = extractvalue { i64, i1 } [[TMP5685]], 0
|
|
// CHECK-NEXT: [[TMP5687:%.*]] = bitcast i64 [[TMP5686]] to double
|
|
// CHECK-NEXT: [[TMP5688:%.*]] = extractvalue { i64, i1 } [[TMP5685]], 1
|
|
// CHECK-NEXT: [[TMP5689:%.*]] = select i1 [[TMP5688]], double [[TMP5681]], double [[TMP5687]]
|
|
// CHECK-NEXT: store double [[TMP5689]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP5690:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5691:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5692:%.*]] = bitcast double [[TMP5690]] to i64
|
|
// CHECK-NEXT: [[TMP5693:%.*]] = bitcast double [[TMP5691]] to i64
|
|
// CHECK-NEXT: [[TMP5694:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5692]], i64 [[TMP5693]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5695:%.*]] = extractvalue { i64, i1 } [[TMP5694]], 0
|
|
// CHECK-NEXT: [[TMP5696:%.*]] = bitcast i64 [[TMP5695]] to double
|
|
// CHECK-NEXT: [[TMP5697:%.*]] = extractvalue { i64, i1 } [[TMP5694]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5697]], label [[DX_ATOMIC_EXIT529:%.*]], label [[DX_ATOMIC_CONT530:%.*]]
|
|
// CHECK: dx.atomic.cont530:
|
|
// CHECK-NEXT: store double [[TMP5696]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT529]]
|
|
// CHECK: dx.atomic.exit529:
|
|
// CHECK-NEXT: [[TMP5698:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5699:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5700:%.*]] = bitcast double [[TMP5698]] to i64
|
|
// CHECK-NEXT: [[TMP5701:%.*]] = bitcast double [[TMP5699]] to i64
|
|
// CHECK-NEXT: [[TMP5702:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5700]], i64 [[TMP5701]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5703:%.*]] = extractvalue { i64, i1 } [[TMP5702]], 0
|
|
// CHECK-NEXT: [[TMP5704:%.*]] = bitcast i64 [[TMP5703]] to double
|
|
// CHECK-NEXT: [[TMP5705:%.*]] = extractvalue { i64, i1 } [[TMP5702]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5705]], label [[DX_ATOMIC_EXIT531:%.*]], label [[DX_ATOMIC_CONT532:%.*]]
|
|
// CHECK: dx.atomic.cont532:
|
|
// CHECK-NEXT: store double [[TMP5704]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT531]]
|
|
// CHECK: dx.atomic.exit531:
|
|
// CHECK-NEXT: [[TMP5706:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5707:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5708:%.*]] = bitcast double [[TMP5706]] to i64
|
|
// CHECK-NEXT: [[TMP5709:%.*]] = bitcast double [[TMP5707]] to i64
|
|
// CHECK-NEXT: [[TMP5710:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5708]], i64 [[TMP5709]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5711:%.*]] = extractvalue { i64, i1 } [[TMP5710]], 1
|
|
// CHECK-NEXT: [[TMP5712:%.*]] = sext i1 [[TMP5711]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5712]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5713:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5714:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5715:%.*]] = bitcast double [[TMP5713]] to i64
|
|
// CHECK-NEXT: [[TMP5716:%.*]] = bitcast double [[TMP5714]] to i64
|
|
// CHECK-NEXT: [[TMP5717:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5715]], i64 [[TMP5716]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5718:%.*]] = extractvalue { i64, i1 } [[TMP5717]], 1
|
|
// CHECK-NEXT: [[TMP5719:%.*]] = sext i1 [[TMP5718]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5719]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5720:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5721:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5722:%.*]] = bitcast double [[TMP5720]] to i64
|
|
// CHECK-NEXT: [[TMP5723:%.*]] = bitcast double [[TMP5721]] to i64
|
|
// CHECK-NEXT: [[TMP5724:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5722]], i64 [[TMP5723]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5725:%.*]] = extractvalue { i64, i1 } [[TMP5724]], 0
|
|
// CHECK-NEXT: [[TMP5726:%.*]] = bitcast i64 [[TMP5725]] to double
|
|
// CHECK-NEXT: [[TMP5727:%.*]] = extractvalue { i64, i1 } [[TMP5724]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5727]], label [[DX_ATOMIC_EXIT533:%.*]], label [[DX_ATOMIC_CONT534:%.*]]
|
|
// CHECK: dx.atomic.cont534:
|
|
// CHECK-NEXT: store double [[TMP5726]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT533]]
|
|
// CHECK: dx.atomic.exit533:
|
|
// CHECK-NEXT: [[TMP5728:%.*]] = extractvalue { i64, i1 } [[TMP5724]], 1
|
|
// CHECK-NEXT: [[TMP5729:%.*]] = sext i1 [[TMP5728]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5729]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5730:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5731:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5732:%.*]] = bitcast double [[TMP5730]] to i64
|
|
// CHECK-NEXT: [[TMP5733:%.*]] = bitcast double [[TMP5731]] to i64
|
|
// CHECK-NEXT: [[TMP5734:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5732]], i64 [[TMP5733]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5735:%.*]] = extractvalue { i64, i1 } [[TMP5734]], 0
|
|
// CHECK-NEXT: [[TMP5736:%.*]] = bitcast i64 [[TMP5735]] to double
|
|
// CHECK-NEXT: [[TMP5737:%.*]] = extractvalue { i64, i1 } [[TMP5734]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5737]], label [[DX_ATOMIC_EXIT535:%.*]], label [[DX_ATOMIC_CONT536:%.*]]
|
|
// CHECK: dx.atomic.cont536:
|
|
// CHECK-NEXT: store double [[TMP5736]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT535]]
|
|
// CHECK: dx.atomic.exit535:
|
|
// CHECK-NEXT: [[TMP5738:%.*]] = extractvalue { i64, i1 } [[TMP5734]], 1
|
|
// CHECK-NEXT: [[TMP5739:%.*]] = sext i1 [[TMP5738]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5739]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: [[TMP5740:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5741:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5740]] release, align 8
|
|
// CHECK-NEXT: store double [[TMP5741]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5742:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5743:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5742]] release, align 8
|
|
// CHECK-NEXT: store double [[TMP5743]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5744:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5745:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5744]] release, align 8
|
|
// CHECK-NEXT: store double [[TMP5745]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5746:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5747:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5746]] release, align 8
|
|
// CHECK-NEXT: store double [[TMP5747]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5748:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5749:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5750:%.*]] = bitcast double [[TMP5748]] to i64
|
|
// CHECK-NEXT: [[TMP5751:%.*]] = bitcast double [[TMP5749]] to i64
|
|
// CHECK-NEXT: [[TMP5752:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5750]], i64 [[TMP5751]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5753:%.*]] = extractvalue { i64, i1 } [[TMP5752]], 0
|
|
// CHECK-NEXT: [[TMP5754:%.*]] = bitcast i64 [[TMP5753]] to double
|
|
// CHECK-NEXT: store double [[TMP5754]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5755:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5756:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5757:%.*]] = bitcast double [[TMP5755]] to i64
|
|
// CHECK-NEXT: [[TMP5758:%.*]] = bitcast double [[TMP5756]] to i64
|
|
// CHECK-NEXT: [[TMP5759:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5757]], i64 [[TMP5758]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5760:%.*]] = extractvalue { i64, i1 } [[TMP5759]], 0
|
|
// CHECK-NEXT: [[TMP5761:%.*]] = bitcast i64 [[TMP5760]] to double
|
|
// CHECK-NEXT: store double [[TMP5761]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5762:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5763:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5762]] release, align 8
|
|
// CHECK-NEXT: [[TMP5764:%.*]] = fcmp ogt double [[TMP5763]], [[TMP5762]]
|
|
// CHECK-NEXT: [[TMP5765:%.*]] = select i1 [[TMP5764]], double [[TMP5762]], double [[TMP5763]]
|
|
// CHECK-NEXT: store double [[TMP5765]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5766:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5767:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5766]] release, align 8
|
|
// CHECK-NEXT: [[TMP5768:%.*]] = fcmp olt double [[TMP5767]], [[TMP5766]]
|
|
// CHECK-NEXT: [[TMP5769:%.*]] = select i1 [[TMP5768]], double [[TMP5766]], double [[TMP5767]]
|
|
// CHECK-NEXT: store double [[TMP5769]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5770:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5771:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5770]] release, align 8
|
|
// CHECK-NEXT: [[TMP5772:%.*]] = fcmp olt double [[TMP5771]], [[TMP5770]]
|
|
// CHECK-NEXT: [[TMP5773:%.*]] = select i1 [[TMP5772]], double [[TMP5770]], double [[TMP5771]]
|
|
// CHECK-NEXT: store double [[TMP5773]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5774:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5775:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5774]] release, align 8
|
|
// CHECK-NEXT: [[TMP5776:%.*]] = fcmp ogt double [[TMP5775]], [[TMP5774]]
|
|
// CHECK-NEXT: [[TMP5777:%.*]] = select i1 [[TMP5776]], double [[TMP5774]], double [[TMP5775]]
|
|
// CHECK-NEXT: store double [[TMP5777]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5778:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5779:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5780:%.*]] = bitcast double [[TMP5778]] to i64
|
|
// CHECK-NEXT: [[TMP5781:%.*]] = bitcast double [[TMP5779]] to i64
|
|
// CHECK-NEXT: [[TMP5782:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5780]], i64 [[TMP5781]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5783:%.*]] = extractvalue { i64, i1 } [[TMP5782]], 0
|
|
// CHECK-NEXT: [[TMP5784:%.*]] = bitcast i64 [[TMP5783]] to double
|
|
// CHECK-NEXT: [[TMP5785:%.*]] = extractvalue { i64, i1 } [[TMP5782]], 1
|
|
// CHECK-NEXT: [[TMP5786:%.*]] = select i1 [[TMP5785]], double [[TMP5778]], double [[TMP5784]]
|
|
// CHECK-NEXT: store double [[TMP5786]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5787:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5788:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5789:%.*]] = bitcast double [[TMP5787]] to i64
|
|
// CHECK-NEXT: [[TMP5790:%.*]] = bitcast double [[TMP5788]] to i64
|
|
// CHECK-NEXT: [[TMP5791:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5789]], i64 [[TMP5790]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5792:%.*]] = extractvalue { i64, i1 } [[TMP5791]], 0
|
|
// CHECK-NEXT: [[TMP5793:%.*]] = bitcast i64 [[TMP5792]] to double
|
|
// CHECK-NEXT: [[TMP5794:%.*]] = extractvalue { i64, i1 } [[TMP5791]], 1
|
|
// CHECK-NEXT: [[TMP5795:%.*]] = select i1 [[TMP5794]], double [[TMP5787]], double [[TMP5793]]
|
|
// CHECK-NEXT: store double [[TMP5795]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5796:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5797:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5798:%.*]] = bitcast double [[TMP5796]] to i64
|
|
// CHECK-NEXT: [[TMP5799:%.*]] = bitcast double [[TMP5797]] to i64
|
|
// CHECK-NEXT: [[TMP5800:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5798]], i64 [[TMP5799]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5801:%.*]] = extractvalue { i64, i1 } [[TMP5800]], 0
|
|
// CHECK-NEXT: [[TMP5802:%.*]] = bitcast i64 [[TMP5801]] to double
|
|
// CHECK-NEXT: [[TMP5803:%.*]] = extractvalue { i64, i1 } [[TMP5800]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5803]], label [[DX_ATOMIC_EXIT537:%.*]], label [[DX_ATOMIC_CONT538:%.*]]
|
|
// CHECK: dx.atomic.cont538:
|
|
// CHECK-NEXT: store double [[TMP5802]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT537]]
|
|
// CHECK: dx.atomic.exit537:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5804:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5805:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5806:%.*]] = bitcast double [[TMP5804]] to i64
|
|
// CHECK-NEXT: [[TMP5807:%.*]] = bitcast double [[TMP5805]] to i64
|
|
// CHECK-NEXT: [[TMP5808:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5806]], i64 [[TMP5807]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5809:%.*]] = extractvalue { i64, i1 } [[TMP5808]], 0
|
|
// CHECK-NEXT: [[TMP5810:%.*]] = bitcast i64 [[TMP5809]] to double
|
|
// CHECK-NEXT: [[TMP5811:%.*]] = extractvalue { i64, i1 } [[TMP5808]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5811]], label [[DX_ATOMIC_EXIT539:%.*]], label [[DX_ATOMIC_CONT540:%.*]]
|
|
// CHECK: dx.atomic.cont540:
|
|
// CHECK-NEXT: store double [[TMP5810]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT539]]
|
|
// CHECK: dx.atomic.exit539:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5812:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5813:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5814:%.*]] = bitcast double [[TMP5812]] to i64
|
|
// CHECK-NEXT: [[TMP5815:%.*]] = bitcast double [[TMP5813]] to i64
|
|
// CHECK-NEXT: [[TMP5816:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5814]], i64 [[TMP5815]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5817:%.*]] = extractvalue { i64, i1 } [[TMP5816]], 1
|
|
// CHECK-NEXT: [[TMP5818:%.*]] = sext i1 [[TMP5817]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5818]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5819:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5820:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5821:%.*]] = bitcast double [[TMP5819]] to i64
|
|
// CHECK-NEXT: [[TMP5822:%.*]] = bitcast double [[TMP5820]] to i64
|
|
// CHECK-NEXT: [[TMP5823:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5821]], i64 [[TMP5822]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5824:%.*]] = extractvalue { i64, i1 } [[TMP5823]], 1
|
|
// CHECK-NEXT: [[TMP5825:%.*]] = sext i1 [[TMP5824]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5825]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5826:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5827:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5828:%.*]] = bitcast double [[TMP5826]] to i64
|
|
// CHECK-NEXT: [[TMP5829:%.*]] = bitcast double [[TMP5827]] to i64
|
|
// CHECK-NEXT: [[TMP5830:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5828]], i64 [[TMP5829]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5831:%.*]] = extractvalue { i64, i1 } [[TMP5830]], 0
|
|
// CHECK-NEXT: [[TMP5832:%.*]] = bitcast i64 [[TMP5831]] to double
|
|
// CHECK-NEXT: [[TMP5833:%.*]] = extractvalue { i64, i1 } [[TMP5830]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5833]], label [[DX_ATOMIC_EXIT541:%.*]], label [[DX_ATOMIC_CONT542:%.*]]
|
|
// CHECK: dx.atomic.cont542:
|
|
// CHECK-NEXT: store double [[TMP5832]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT541]]
|
|
// CHECK: dx.atomic.exit541:
|
|
// CHECK-NEXT: [[TMP5834:%.*]] = extractvalue { i64, i1 } [[TMP5830]], 1
|
|
// CHECK-NEXT: [[TMP5835:%.*]] = sext i1 [[TMP5834]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5835]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5836:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5837:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5838:%.*]] = bitcast double [[TMP5836]] to i64
|
|
// CHECK-NEXT: [[TMP5839:%.*]] = bitcast double [[TMP5837]] to i64
|
|
// CHECK-NEXT: [[TMP5840:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5838]], i64 [[TMP5839]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP5841:%.*]] = extractvalue { i64, i1 } [[TMP5840]], 0
|
|
// CHECK-NEXT: [[TMP5842:%.*]] = bitcast i64 [[TMP5841]] to double
|
|
// CHECK-NEXT: [[TMP5843:%.*]] = extractvalue { i64, i1 } [[TMP5840]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5843]], label [[DX_ATOMIC_EXIT543:%.*]], label [[DX_ATOMIC_CONT544:%.*]]
|
|
// CHECK: dx.atomic.cont544:
|
|
// CHECK-NEXT: store double [[TMP5842]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT543]]
|
|
// CHECK: dx.atomic.exit543:
|
|
// CHECK-NEXT: [[TMP5844:%.*]] = extractvalue { i64, i1 } [[TMP5840]], 1
|
|
// CHECK-NEXT: [[TMP5845:%.*]] = sext i1 [[TMP5844]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5845]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5846:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5847:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5846]] seq_cst, align 8
|
|
// CHECK-NEXT: store double [[TMP5847]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5848:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5849:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5848]] seq_cst, align 8
|
|
// CHECK-NEXT: store double [[TMP5849]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5850:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5851:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5850]] seq_cst, align 8
|
|
// CHECK-NEXT: store double [[TMP5851]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5852:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5853:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5852]] seq_cst, align 8
|
|
// CHECK-NEXT: store double [[TMP5853]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5854:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5855:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5856:%.*]] = bitcast double [[TMP5854]] to i64
|
|
// CHECK-NEXT: [[TMP5857:%.*]] = bitcast double [[TMP5855]] to i64
|
|
// CHECK-NEXT: [[TMP5858:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5856]], i64 [[TMP5857]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5859:%.*]] = extractvalue { i64, i1 } [[TMP5858]], 0
|
|
// CHECK-NEXT: [[TMP5860:%.*]] = bitcast i64 [[TMP5859]] to double
|
|
// CHECK-NEXT: store double [[TMP5860]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5861:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5862:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5863:%.*]] = bitcast double [[TMP5861]] to i64
|
|
// CHECK-NEXT: [[TMP5864:%.*]] = bitcast double [[TMP5862]] to i64
|
|
// CHECK-NEXT: [[TMP5865:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5863]], i64 [[TMP5864]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5866:%.*]] = extractvalue { i64, i1 } [[TMP5865]], 0
|
|
// CHECK-NEXT: [[TMP5867:%.*]] = bitcast i64 [[TMP5866]] to double
|
|
// CHECK-NEXT: store double [[TMP5867]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5868:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5869:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5868]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5870:%.*]] = fcmp ogt double [[TMP5869]], [[TMP5868]]
|
|
// CHECK-NEXT: [[TMP5871:%.*]] = select i1 [[TMP5870]], double [[TMP5868]], double [[TMP5869]]
|
|
// CHECK-NEXT: store double [[TMP5871]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5872:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5873:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5872]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5874:%.*]] = fcmp olt double [[TMP5873]], [[TMP5872]]
|
|
// CHECK-NEXT: [[TMP5875:%.*]] = select i1 [[TMP5874]], double [[TMP5872]], double [[TMP5873]]
|
|
// CHECK-NEXT: store double [[TMP5875]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5876:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5877:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5876]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5878:%.*]] = fcmp olt double [[TMP5877]], [[TMP5876]]
|
|
// CHECK-NEXT: [[TMP5879:%.*]] = select i1 [[TMP5878]], double [[TMP5876]], double [[TMP5877]]
|
|
// CHECK-NEXT: store double [[TMP5879]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5880:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5881:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5880]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5882:%.*]] = fcmp ogt double [[TMP5881]], [[TMP5880]]
|
|
// CHECK-NEXT: [[TMP5883:%.*]] = select i1 [[TMP5882]], double [[TMP5880]], double [[TMP5881]]
|
|
// CHECK-NEXT: store double [[TMP5883]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5884:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5885:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5886:%.*]] = bitcast double [[TMP5884]] to i64
|
|
// CHECK-NEXT: [[TMP5887:%.*]] = bitcast double [[TMP5885]] to i64
|
|
// CHECK-NEXT: [[TMP5888:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5886]], i64 [[TMP5887]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5889:%.*]] = extractvalue { i64, i1 } [[TMP5888]], 0
|
|
// CHECK-NEXT: [[TMP5890:%.*]] = bitcast i64 [[TMP5889]] to double
|
|
// CHECK-NEXT: [[TMP5891:%.*]] = extractvalue { i64, i1 } [[TMP5888]], 1
|
|
// CHECK-NEXT: [[TMP5892:%.*]] = select i1 [[TMP5891]], double [[TMP5884]], double [[TMP5890]]
|
|
// CHECK-NEXT: store double [[TMP5892]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5893:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5894:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5895:%.*]] = bitcast double [[TMP5893]] to i64
|
|
// CHECK-NEXT: [[TMP5896:%.*]] = bitcast double [[TMP5894]] to i64
|
|
// CHECK-NEXT: [[TMP5897:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5895]], i64 [[TMP5896]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5898:%.*]] = extractvalue { i64, i1 } [[TMP5897]], 0
|
|
// CHECK-NEXT: [[TMP5899:%.*]] = bitcast i64 [[TMP5898]] to double
|
|
// CHECK-NEXT: [[TMP5900:%.*]] = extractvalue { i64, i1 } [[TMP5897]], 1
|
|
// CHECK-NEXT: [[TMP5901:%.*]] = select i1 [[TMP5900]], double [[TMP5893]], double [[TMP5899]]
|
|
// CHECK-NEXT: store double [[TMP5901]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5902:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5903:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5904:%.*]] = bitcast double [[TMP5902]] to i64
|
|
// CHECK-NEXT: [[TMP5905:%.*]] = bitcast double [[TMP5903]] to i64
|
|
// CHECK-NEXT: [[TMP5906:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5904]], i64 [[TMP5905]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5907:%.*]] = extractvalue { i64, i1 } [[TMP5906]], 0
|
|
// CHECK-NEXT: [[TMP5908:%.*]] = bitcast i64 [[TMP5907]] to double
|
|
// CHECK-NEXT: [[TMP5909:%.*]] = extractvalue { i64, i1 } [[TMP5906]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5909]], label [[DX_ATOMIC_EXIT545:%.*]], label [[DX_ATOMIC_CONT546:%.*]]
|
|
// CHECK: dx.atomic.cont546:
|
|
// CHECK-NEXT: store double [[TMP5908]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT545]]
|
|
// CHECK: dx.atomic.exit545:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5910:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5911:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5912:%.*]] = bitcast double [[TMP5910]] to i64
|
|
// CHECK-NEXT: [[TMP5913:%.*]] = bitcast double [[TMP5911]] to i64
|
|
// CHECK-NEXT: [[TMP5914:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5912]], i64 [[TMP5913]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5915:%.*]] = extractvalue { i64, i1 } [[TMP5914]], 0
|
|
// CHECK-NEXT: [[TMP5916:%.*]] = bitcast i64 [[TMP5915]] to double
|
|
// CHECK-NEXT: [[TMP5917:%.*]] = extractvalue { i64, i1 } [[TMP5914]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5917]], label [[DX_ATOMIC_EXIT547:%.*]], label [[DX_ATOMIC_CONT548:%.*]]
|
|
// CHECK: dx.atomic.cont548:
|
|
// CHECK-NEXT: store double [[TMP5916]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT547]]
|
|
// CHECK: dx.atomic.exit547:
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5918:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5919:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5920:%.*]] = bitcast double [[TMP5918]] to i64
|
|
// CHECK-NEXT: [[TMP5921:%.*]] = bitcast double [[TMP5919]] to i64
|
|
// CHECK-NEXT: [[TMP5922:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5920]], i64 [[TMP5921]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5923:%.*]] = extractvalue { i64, i1 } [[TMP5922]], 1
|
|
// CHECK-NEXT: [[TMP5924:%.*]] = sext i1 [[TMP5923]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5924]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5925:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5926:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5927:%.*]] = bitcast double [[TMP5925]] to i64
|
|
// CHECK-NEXT: [[TMP5928:%.*]] = bitcast double [[TMP5926]] to i64
|
|
// CHECK-NEXT: [[TMP5929:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5927]], i64 [[TMP5928]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5930:%.*]] = extractvalue { i64, i1 } [[TMP5929]], 1
|
|
// CHECK-NEXT: [[TMP5931:%.*]] = sext i1 [[TMP5930]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5931]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5932:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5933:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5934:%.*]] = bitcast double [[TMP5932]] to i64
|
|
// CHECK-NEXT: [[TMP5935:%.*]] = bitcast double [[TMP5933]] to i64
|
|
// CHECK-NEXT: [[TMP5936:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5934]], i64 [[TMP5935]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5937:%.*]] = extractvalue { i64, i1 } [[TMP5936]], 0
|
|
// CHECK-NEXT: [[TMP5938:%.*]] = bitcast i64 [[TMP5937]] to double
|
|
// CHECK-NEXT: [[TMP5939:%.*]] = extractvalue { i64, i1 } [[TMP5936]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5939]], label [[DX_ATOMIC_EXIT549:%.*]], label [[DX_ATOMIC_CONT550:%.*]]
|
|
// CHECK: dx.atomic.cont550:
|
|
// CHECK-NEXT: store double [[TMP5938]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT549]]
|
|
// CHECK: dx.atomic.exit549:
|
|
// CHECK-NEXT: [[TMP5940:%.*]] = extractvalue { i64, i1 } [[TMP5936]], 1
|
|
// CHECK-NEXT: [[TMP5941:%.*]] = sext i1 [[TMP5940]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5941]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP5942:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5943:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP5944:%.*]] = bitcast double [[TMP5942]] to i64
|
|
// CHECK-NEXT: [[TMP5945:%.*]] = bitcast double [[TMP5943]] to i64
|
|
// CHECK-NEXT: [[TMP5946:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5944]], i64 [[TMP5945]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP5947:%.*]] = extractvalue { i64, i1 } [[TMP5946]], 0
|
|
// CHECK-NEXT: [[TMP5948:%.*]] = bitcast i64 [[TMP5947]] to double
|
|
// CHECK-NEXT: [[TMP5949:%.*]] = extractvalue { i64, i1 } [[TMP5946]], 1
|
|
// CHECK-NEXT: br i1 [[TMP5949]], label [[DX_ATOMIC_EXIT551:%.*]], label [[DX_ATOMIC_CONT552:%.*]]
|
|
// CHECK: dx.atomic.cont552:
|
|
// CHECK-NEXT: store double [[TMP5948]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT551]]
|
|
// CHECK: dx.atomic.exit551:
|
|
// CHECK-NEXT: [[TMP5950:%.*]] = extractvalue { i64, i1 } [[TMP5946]], 1
|
|
// CHECK-NEXT: [[TMP5951:%.*]] = sext i1 [[TMP5950]] to i32
|
|
// CHECK-NEXT: store i32 [[TMP5951]], ptr [[IR]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK-LABEL: @cxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[CX:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[CV:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[CE:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[CD:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP0]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP1]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP2]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP3]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP4]], i8 [[TMP5]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i8, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i8 [[TMP7]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP8]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i8 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i8 [[TMP8]], i8 [[TMP9]]
|
|
// CHECK-NEXT: store i8 [[TMP11]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP12]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i8 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i8 [[TMP12]], i8 [[TMP13]]
|
|
// CHECK-NEXT: store i8 [[TMP15]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i8, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i8 [[TMP16]], i8 [[TMP19]]
|
|
// CHECK-NEXT: store i8 [[TMP21]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP22]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP23]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP24]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP25]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP26]], i8 [[TMP27]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i8, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i8 [[TMP29]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP30]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i8 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i8 [[TMP30]], i8 [[TMP31]]
|
|
// CHECK-NEXT: store i8 [[TMP33]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP34]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i8 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP34]], i8 [[TMP35]]
|
|
// CHECK-NEXT: store i8 [[TMP37]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP38]], i8 [[TMP39]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
|
|
// CHECK-NEXT: store i8 [[TMP43]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP44]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP45]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP46]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP47]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP48]], i8 [[TMP49]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i8, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i8 [[TMP51]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP52]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i8 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i8 [[TMP52]], i8 [[TMP53]]
|
|
// CHECK-NEXT: store i8 [[TMP55]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP56]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i8 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i8 [[TMP56]], i8 [[TMP57]]
|
|
// CHECK-NEXT: store i8 [[TMP59]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP60]], i8 [[TMP61]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i8, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i8, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i8 [[TMP60]], i8 [[TMP63]]
|
|
// CHECK-NEXT: store i8 [[TMP65]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP66]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP67]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP68]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP69]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP70]], i8 [[TMP71]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i8, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i8 [[TMP73]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP74]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i8 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i8 [[TMP74]], i8 [[TMP75]]
|
|
// CHECK-NEXT: store i8 [[TMP77]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP78]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i8 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i8 [[TMP78]], i8 [[TMP79]]
|
|
// CHECK-NEXT: store i8 [[TMP81]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP82]], i8 [[TMP83]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i8, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i8, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i8 [[TMP82]], i8 [[TMP85]]
|
|
// CHECK-NEXT: store i8 [[TMP87]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP88]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP89]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP90]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP91]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP92]], i8 [[TMP93]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i8, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i8 [[TMP95]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP96]] release, align 1
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i8 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i8 [[TMP96]], i8 [[TMP97]]
|
|
// CHECK-NEXT: store i8 [[TMP99]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP100]] release, align 1
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i8 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i8 [[TMP100]], i8 [[TMP101]]
|
|
// CHECK-NEXT: store i8 [[TMP103]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP104]], i8 [[TMP105]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i8, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i8, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP104]], i8 [[TMP107]]
|
|
// CHECK-NEXT: store i8 [[TMP109]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP110]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP111]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP112]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP113]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP114]], i8 [[TMP115]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i8, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i8 [[TMP117]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP118]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i8 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP118]], i8 [[TMP119]]
|
|
// CHECK-NEXT: store i8 [[TMP121]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP122]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i8 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i8 [[TMP122]], i8 [[TMP123]]
|
|
// CHECK-NEXT: store i8 [[TMP125]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i8, ptr [[CE]], align 1
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i8, ptr [[CD]], align 1
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP126]], i8 [[TMP127]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i8, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i8 [[TMP126]], i8 [[TMP129]]
|
|
// CHECK-NEXT: store i8 [[TMP131]], ptr [[CV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i8, ptr [[CV]], align 1
|
|
// CHECK-NEXT: ret i8 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @ucxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[UCX:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCV:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCE:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[UCD:%.*]] = alloca i8, align 1
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP0]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP1]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP2]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP3]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP4]], i8 [[TMP5]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i8, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i8 [[TMP7]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP8]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i8 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i8 [[TMP8]], i8 [[TMP9]]
|
|
// CHECK-NEXT: store i8 [[TMP11]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP12]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i8 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i8 [[TMP12]], i8 [[TMP13]]
|
|
// CHECK-NEXT: store i8 [[TMP15]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i8, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i8 [[TMP16]], i8 [[TMP19]]
|
|
// CHECK-NEXT: store i8 [[TMP21]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP22]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP23]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP24]] acq_rel, align 1
|
|
// CHECK-NEXT: store i8 [[TMP25]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP26]], i8 [[TMP27]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i8, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i8 [[TMP29]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP30]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i8 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i8 [[TMP30]], i8 [[TMP31]]
|
|
// CHECK-NEXT: store i8 [[TMP33]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP34]] acq_rel, align 1
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i8 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP34]], i8 [[TMP35]]
|
|
// CHECK-NEXT: store i8 [[TMP37]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP38]], i8 [[TMP39]] acq_rel acquire, align 1
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
|
|
// CHECK-NEXT: store i8 [[TMP43]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP44]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP45]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP46]] acquire, align 1
|
|
// CHECK-NEXT: store i8 [[TMP47]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP48]], i8 [[TMP49]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i8, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i8 [[TMP51]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP52]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i8 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i8 [[TMP52]], i8 [[TMP53]]
|
|
// CHECK-NEXT: store i8 [[TMP55]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP56]] acquire, align 1
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i8 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i8 [[TMP56]], i8 [[TMP57]]
|
|
// CHECK-NEXT: store i8 [[TMP59]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP60]], i8 [[TMP61]] acquire acquire, align 1
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i8, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i8, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i8 [[TMP60]], i8 [[TMP63]]
|
|
// CHECK-NEXT: store i8 [[TMP65]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP66]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP67]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP68]] monotonic, align 1
|
|
// CHECK-NEXT: store i8 [[TMP69]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP70]], i8 [[TMP71]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i8, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i8 [[TMP73]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP74]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i8 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i8 [[TMP74]], i8 [[TMP75]]
|
|
// CHECK-NEXT: store i8 [[TMP77]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP78]] monotonic, align 1
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i8 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i8 [[TMP78]], i8 [[TMP79]]
|
|
// CHECK-NEXT: store i8 [[TMP81]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP82]], i8 [[TMP83]] monotonic monotonic, align 1
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i8, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i8, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i8 [[TMP82]], i8 [[TMP85]]
|
|
// CHECK-NEXT: store i8 [[TMP87]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP88]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP89]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP90]] release, align 1
|
|
// CHECK-NEXT: store i8 [[TMP91]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP92]], i8 [[TMP93]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i8, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i8 [[TMP95]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP96]] release, align 1
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i8 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i8 [[TMP96]], i8 [[TMP97]]
|
|
// CHECK-NEXT: store i8 [[TMP99]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP100]] release, align 1
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i8 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i8 [[TMP100]], i8 [[TMP101]]
|
|
// CHECK-NEXT: store i8 [[TMP103]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP104]], i8 [[TMP105]] release monotonic, align 1
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i8, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i8, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP104]], i8 [[TMP107]]
|
|
// CHECK-NEXT: store i8 [[TMP109]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP110]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP111]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP112]] seq_cst, align 1
|
|
// CHECK-NEXT: store i8 [[TMP113]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP114]], i8 [[TMP115]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i8, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i8 [[TMP117]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP118]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i8 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP118]], i8 [[TMP119]]
|
|
// CHECK-NEXT: store i8 [[TMP121]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP122]] seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i8 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i8 [[TMP122]], i8 [[TMP123]]
|
|
// CHECK-NEXT: store i8 [[TMP125]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP126]], i8 [[TMP127]] seq_cst seq_cst, align 1
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i8, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i8 [[TMP126]], i8 [[TMP129]]
|
|
// CHECK-NEXT: store i8 [[TMP131]], ptr [[UCV]], align 1
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i8, ptr [[UCV]], align 1
|
|
// CHECK-NEXT: ret i8 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @sxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[SX:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[SV:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[SE:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[SD:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP0]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP2]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP3]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP4]], i16 [[TMP5]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i16, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i16 [[TMP7]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP8]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i16 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i16 [[TMP8]], i16 [[TMP9]]
|
|
// CHECK-NEXT: store i16 [[TMP11]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP12]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i16 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i16 [[TMP12]], i16 [[TMP13]]
|
|
// CHECK-NEXT: store i16 [[TMP15]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP16]], i16 [[TMP17]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i16, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP16]], i16 [[TMP19]]
|
|
// CHECK-NEXT: store i16 [[TMP21]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP22]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP23]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP24]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP25]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP26]], i16 [[TMP27]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i16, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i16 [[TMP29]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP30]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i16 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i16 [[TMP30]], i16 [[TMP31]]
|
|
// CHECK-NEXT: store i16 [[TMP33]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP34]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i16 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i16 [[TMP34]], i16 [[TMP35]]
|
|
// CHECK-NEXT: store i16 [[TMP37]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP38]], i16 [[TMP39]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i16, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i16, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i16 [[TMP38]], i16 [[TMP41]]
|
|
// CHECK-NEXT: store i16 [[TMP43]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP44]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP45]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP46]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP47]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP48]], i16 [[TMP49]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i16, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i16 [[TMP51]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP52]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i16 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i16 [[TMP52]], i16 [[TMP53]]
|
|
// CHECK-NEXT: store i16 [[TMP55]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP56]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i16 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i16 [[TMP56]], i16 [[TMP57]]
|
|
// CHECK-NEXT: store i16 [[TMP59]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP60]], i16 [[TMP61]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i16, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i16, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i16 [[TMP60]], i16 [[TMP63]]
|
|
// CHECK-NEXT: store i16 [[TMP65]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP66]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP67]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP68]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP69]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP70]], i16 [[TMP71]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i16, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i16 [[TMP73]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP74]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i16 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i16 [[TMP74]], i16 [[TMP75]]
|
|
// CHECK-NEXT: store i16 [[TMP77]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP78]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i16 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i16 [[TMP78]], i16 [[TMP79]]
|
|
// CHECK-NEXT: store i16 [[TMP81]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP82]], i16 [[TMP83]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i16, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i16, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i16 [[TMP82]], i16 [[TMP85]]
|
|
// CHECK-NEXT: store i16 [[TMP87]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP88]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP89]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP90]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP91]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP92]], i16 [[TMP93]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i16, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i16 [[TMP95]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP96]] release, align 2
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i16 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i16 [[TMP96]], i16 [[TMP97]]
|
|
// CHECK-NEXT: store i16 [[TMP99]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP100]] release, align 2
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i16 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i16 [[TMP100]], i16 [[TMP101]]
|
|
// CHECK-NEXT: store i16 [[TMP103]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP104]], i16 [[TMP105]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i16, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i16, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i16 [[TMP104]], i16 [[TMP107]]
|
|
// CHECK-NEXT: store i16 [[TMP109]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP110]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP111]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP112]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP113]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP114]], i16 [[TMP115]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i16, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i16 [[TMP117]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP118]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i16 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i16 [[TMP118]], i16 [[TMP119]]
|
|
// CHECK-NEXT: store i16 [[TMP121]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP122]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i16 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i16 [[TMP122]], i16 [[TMP123]]
|
|
// CHECK-NEXT: store i16 [[TMP125]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i16, ptr [[SE]], align 2
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i16, ptr [[SD]], align 2
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP126]], i16 [[TMP127]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i16, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i16, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i16 [[TMP126]], i16 [[TMP129]]
|
|
// CHECK-NEXT: store i16 [[TMP131]], ptr [[SV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i16, ptr [[SV]], align 2
|
|
// CHECK-NEXT: ret i16 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @usxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[USX:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USV:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USE:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[USD:%.*]] = alloca i16, align 2
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP0]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP1]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP2]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP3]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP4]], i16 [[TMP5]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i16, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i16 [[TMP7]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP8]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i16 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i16 [[TMP8]], i16 [[TMP9]]
|
|
// CHECK-NEXT: store i16 [[TMP11]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP12]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i16 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i16 [[TMP12]], i16 [[TMP13]]
|
|
// CHECK-NEXT: store i16 [[TMP15]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP16]], i16 [[TMP17]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i16, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP16]], i16 [[TMP19]]
|
|
// CHECK-NEXT: store i16 [[TMP21]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP22]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP23]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP24]] acq_rel, align 2
|
|
// CHECK-NEXT: store i16 [[TMP25]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP26]], i16 [[TMP27]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i16, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i16 [[TMP29]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP30]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i16 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i16 [[TMP30]], i16 [[TMP31]]
|
|
// CHECK-NEXT: store i16 [[TMP33]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP34]] acq_rel, align 2
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i16 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i16 [[TMP34]], i16 [[TMP35]]
|
|
// CHECK-NEXT: store i16 [[TMP37]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP38]], i16 [[TMP39]] acq_rel acquire, align 2
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i16, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i16, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i16 [[TMP38]], i16 [[TMP41]]
|
|
// CHECK-NEXT: store i16 [[TMP43]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP44]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP45]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP46]] acquire, align 2
|
|
// CHECK-NEXT: store i16 [[TMP47]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP48]], i16 [[TMP49]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i16, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i16 [[TMP51]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP52]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i16 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i16 [[TMP52]], i16 [[TMP53]]
|
|
// CHECK-NEXT: store i16 [[TMP55]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP56]] acquire, align 2
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i16 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i16 [[TMP56]], i16 [[TMP57]]
|
|
// CHECK-NEXT: store i16 [[TMP59]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP60]], i16 [[TMP61]] acquire acquire, align 2
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i16, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i16, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i16 [[TMP60]], i16 [[TMP63]]
|
|
// CHECK-NEXT: store i16 [[TMP65]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP66]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP67]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP68]] monotonic, align 2
|
|
// CHECK-NEXT: store i16 [[TMP69]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP70]], i16 [[TMP71]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i16, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i16 [[TMP73]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP74]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i16 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i16 [[TMP74]], i16 [[TMP75]]
|
|
// CHECK-NEXT: store i16 [[TMP77]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP78]] monotonic, align 2
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i16 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i16 [[TMP78]], i16 [[TMP79]]
|
|
// CHECK-NEXT: store i16 [[TMP81]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP82]], i16 [[TMP83]] monotonic monotonic, align 2
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i16, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i16, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i16 [[TMP82]], i16 [[TMP85]]
|
|
// CHECK-NEXT: store i16 [[TMP87]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP88]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP89]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP90]] release, align 2
|
|
// CHECK-NEXT: store i16 [[TMP91]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP92]], i16 [[TMP93]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i16, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i16 [[TMP95]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP96]] release, align 2
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i16 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i16 [[TMP96]], i16 [[TMP97]]
|
|
// CHECK-NEXT: store i16 [[TMP99]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP100]] release, align 2
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i16 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i16 [[TMP100]], i16 [[TMP101]]
|
|
// CHECK-NEXT: store i16 [[TMP103]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP104]], i16 [[TMP105]] release monotonic, align 2
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i16, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i16, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i16 [[TMP104]], i16 [[TMP107]]
|
|
// CHECK-NEXT: store i16 [[TMP109]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP110]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP111]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP112]] seq_cst, align 2
|
|
// CHECK-NEXT: store i16 [[TMP113]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP114]], i16 [[TMP115]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i16, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i16 [[TMP117]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP118]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i16 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i16 [[TMP118]], i16 [[TMP119]]
|
|
// CHECK-NEXT: store i16 [[TMP121]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP122]] seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i16 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i16 [[TMP122]], i16 [[TMP123]]
|
|
// CHECK-NEXT: store i16 [[TMP125]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i16, ptr [[USE]], align 2
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i16, ptr [[USD]], align 2
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP126]], i16 [[TMP127]] seq_cst seq_cst, align 2
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i16, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i16, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i16 [[TMP126]], i16 [[TMP129]]
|
|
// CHECK-NEXT: store i16 [[TMP131]], ptr [[USV]], align 2
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i16, ptr [[USV]], align 2
|
|
// CHECK-NEXT: ret i16 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @ixevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[IX:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[IV:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[IE:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[ID:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP0]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP3]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP4]], i32 [[TMP5]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i32 [[TMP7]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP8]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i32 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
|
|
// CHECK-NEXT: store i32 [[TMP11]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP12]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i32 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP12]], i32 [[TMP13]]
|
|
// CHECK-NEXT: store i32 [[TMP15]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP16]], i32 [[TMP17]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i32, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP16]], i32 [[TMP19]]
|
|
// CHECK-NEXT: store i32 [[TMP21]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP22]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP23]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP24]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP25]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP26]], i32 [[TMP27]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i32, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i32 [[TMP29]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP30]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i32 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i32 [[TMP30]], i32 [[TMP31]]
|
|
// CHECK-NEXT: store i32 [[TMP33]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP34]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i32 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 [[TMP34]], i32 [[TMP35]]
|
|
// CHECK-NEXT: store i32 [[TMP37]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP38]], i32 [[TMP39]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i32, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i32, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP38]], i32 [[TMP41]]
|
|
// CHECK-NEXT: store i32 [[TMP43]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP44]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP45]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP46]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP47]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP48]], i32 [[TMP49]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i32, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i32 [[TMP51]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP52]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i32 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP52]], i32 [[TMP53]]
|
|
// CHECK-NEXT: store i32 [[TMP55]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP56]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i32 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i32 [[TMP56]], i32 [[TMP57]]
|
|
// CHECK-NEXT: store i32 [[TMP59]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP60]], i32 [[TMP61]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i32, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i32, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i32 [[TMP60]], i32 [[TMP63]]
|
|
// CHECK-NEXT: store i32 [[TMP65]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP66]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP67]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP68]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP69]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP70]], i32 [[TMP71]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i32, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i32 [[TMP73]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP74]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i32 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 [[TMP74]], i32 [[TMP75]]
|
|
// CHECK-NEXT: store i32 [[TMP77]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP78]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i32 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i32 [[TMP78]], i32 [[TMP79]]
|
|
// CHECK-NEXT: store i32 [[TMP81]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP82]], i32 [[TMP83]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i32, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i32, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i32 [[TMP82]], i32 [[TMP85]]
|
|
// CHECK-NEXT: store i32 [[TMP87]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP88]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP89]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP90]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP91]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP92]], i32 [[TMP93]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i32, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i32 [[TMP95]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP96]] release, align 4
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i32 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i32 [[TMP96]], i32 [[TMP97]]
|
|
// CHECK-NEXT: store i32 [[TMP99]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP100]] release, align 4
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i32 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i32 [[TMP100]], i32 [[TMP101]]
|
|
// CHECK-NEXT: store i32 [[TMP103]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP104]], i32 [[TMP105]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i32, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i32 [[TMP104]], i32 [[TMP107]]
|
|
// CHECK-NEXT: store i32 [[TMP109]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP110]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP111]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP112]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP113]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP114]], i32 [[TMP115]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i32, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i32 [[TMP117]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP118]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i32 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i32 [[TMP118]], i32 [[TMP119]]
|
|
// CHECK-NEXT: store i32 [[TMP121]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP122]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i32 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i32 [[TMP122]], i32 [[TMP123]]
|
|
// CHECK-NEXT: store i32 [[TMP125]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[IE]], align 4
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i32, ptr [[ID]], align 4
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP126]], i32 [[TMP127]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i32, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i32, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i32 [[TMP126]], i32 [[TMP129]]
|
|
// CHECK-NEXT: store i32 [[TMP131]], ptr [[IV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i32, ptr [[IV]], align 4
|
|
// CHECK-NEXT: ret i32 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @uixevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[UIX:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UIV:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UIE:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[UID:%.*]] = alloca i32, align 4
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP0]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP1]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP3]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP4]], i32 [[TMP5]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i32 [[TMP7]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP8]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i32 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
|
|
// CHECK-NEXT: store i32 [[TMP11]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP12]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i32 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP12]], i32 [[TMP13]]
|
|
// CHECK-NEXT: store i32 [[TMP15]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP16]], i32 [[TMP17]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i32, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP16]], i32 [[TMP19]]
|
|
// CHECK-NEXT: store i32 [[TMP21]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP22]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP23]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP24]] acq_rel, align 4
|
|
// CHECK-NEXT: store i32 [[TMP25]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP26]], i32 [[TMP27]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i32, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i32 [[TMP29]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP30]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i32 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i32 [[TMP30]], i32 [[TMP31]]
|
|
// CHECK-NEXT: store i32 [[TMP33]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP34]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i32 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 [[TMP34]], i32 [[TMP35]]
|
|
// CHECK-NEXT: store i32 [[TMP37]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP38]], i32 [[TMP39]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i32, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i32, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP38]], i32 [[TMP41]]
|
|
// CHECK-NEXT: store i32 [[TMP43]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP44]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP45]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP46]] acquire, align 4
|
|
// CHECK-NEXT: store i32 [[TMP47]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP48]], i32 [[TMP49]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i32, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i32 [[TMP51]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP52]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i32 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP52]], i32 [[TMP53]]
|
|
// CHECK-NEXT: store i32 [[TMP55]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP56]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i32 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i32 [[TMP56]], i32 [[TMP57]]
|
|
// CHECK-NEXT: store i32 [[TMP59]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP60]], i32 [[TMP61]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i32, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i32, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i32 [[TMP60]], i32 [[TMP63]]
|
|
// CHECK-NEXT: store i32 [[TMP65]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP66]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP67]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP68]] monotonic, align 4
|
|
// CHECK-NEXT: store i32 [[TMP69]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP70]], i32 [[TMP71]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i32, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i32 [[TMP73]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP74]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i32 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 [[TMP74]], i32 [[TMP75]]
|
|
// CHECK-NEXT: store i32 [[TMP77]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP78]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i32 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i32 [[TMP78]], i32 [[TMP79]]
|
|
// CHECK-NEXT: store i32 [[TMP81]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP82]], i32 [[TMP83]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i32, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i32, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i32 [[TMP82]], i32 [[TMP85]]
|
|
// CHECK-NEXT: store i32 [[TMP87]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP88]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP89]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP90]] release, align 4
|
|
// CHECK-NEXT: store i32 [[TMP91]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP92]], i32 [[TMP93]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i32, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i32 [[TMP95]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP96]] release, align 4
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i32 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i32 [[TMP96]], i32 [[TMP97]]
|
|
// CHECK-NEXT: store i32 [[TMP99]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP100]] release, align 4
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i32 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i32 [[TMP100]], i32 [[TMP101]]
|
|
// CHECK-NEXT: store i32 [[TMP103]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP104]], i32 [[TMP105]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i32, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i32 [[TMP104]], i32 [[TMP107]]
|
|
// CHECK-NEXT: store i32 [[TMP109]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP110]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP111]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP112]] seq_cst, align 4
|
|
// CHECK-NEXT: store i32 [[TMP113]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP114]], i32 [[TMP115]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i32, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i32 [[TMP117]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP118]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i32 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i32 [[TMP118]], i32 [[TMP119]]
|
|
// CHECK-NEXT: store i32 [[TMP121]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP122]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i32 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i32 [[TMP122]], i32 [[TMP123]]
|
|
// CHECK-NEXT: store i32 [[TMP125]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i32, ptr [[UID]], align 4
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP126]], i32 [[TMP127]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i32, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i32, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i32 [[TMP126]], i32 [[TMP129]]
|
|
// CHECK-NEXT: store i32 [[TMP131]], ptr [[UIV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i32, ptr [[UIV]], align 4
|
|
// CHECK-NEXT: ret i32 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @lxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[LX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LV:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP0]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP1]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i64 [[TMP7]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP8]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
|
|
// CHECK-NEXT: store i64 [[TMP11]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP12]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
|
|
// CHECK-NEXT: store i64 [[TMP15]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
|
|
// CHECK-NEXT: store i64 [[TMP21]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP22]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP23]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP24]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP25]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i64 [[TMP29]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP30]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i64 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
|
|
// CHECK-NEXT: store i64 [[TMP33]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP34]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i64 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
|
|
// CHECK-NEXT: store i64 [[TMP37]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
|
|
// CHECK-NEXT: store i64 [[TMP43]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP44]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP45]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP46]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP47]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i64 [[TMP51]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP52]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i64 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
|
|
// CHECK-NEXT: store i64 [[TMP55]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP56]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i64 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
|
|
// CHECK-NEXT: store i64 [[TMP59]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
|
|
// CHECK-NEXT: store i64 [[TMP65]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP66]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP67]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP68]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP69]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i64 [[TMP73]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP74]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i64 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
|
|
// CHECK-NEXT: store i64 [[TMP77]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP78]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i64 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
|
|
// CHECK-NEXT: store i64 [[TMP81]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
|
|
// CHECK-NEXT: store i64 [[TMP87]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP88]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP89]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP90]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP91]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i64 [[TMP95]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP96]] release, align 8
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i64 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
|
|
// CHECK-NEXT: store i64 [[TMP99]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP100]] release, align 8
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i64 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
|
|
// CHECK-NEXT: store i64 [[TMP103]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
|
|
// CHECK-NEXT: store i64 [[TMP109]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP110]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP111]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP112]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP113]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i64 [[TMP117]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP118]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i64 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
|
|
// CHECK-NEXT: store i64 [[TMP121]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP122]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i64 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
|
|
// CHECK-NEXT: store i64 [[TMP125]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i64, ptr [[LE]], align 8
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i64, ptr [[LD]], align 8
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
|
|
// CHECK-NEXT: store i64 [[TMP131]], ptr [[LV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr [[LV]], align 8
|
|
// CHECK-NEXT: ret i64 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @ulxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[ULX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULV:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP0]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP1]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i64 [[TMP7]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP8]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
|
|
// CHECK-NEXT: store i64 [[TMP11]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP12]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
|
|
// CHECK-NEXT: store i64 [[TMP15]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
|
|
// CHECK-NEXT: store i64 [[TMP21]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP22]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP23]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP24]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP25]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i64 [[TMP29]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP30]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i64 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
|
|
// CHECK-NEXT: store i64 [[TMP33]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP34]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i64 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
|
|
// CHECK-NEXT: store i64 [[TMP37]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
|
|
// CHECK-NEXT: store i64 [[TMP43]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP44]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP45]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP46]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP47]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i64 [[TMP51]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP52]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i64 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
|
|
// CHECK-NEXT: store i64 [[TMP55]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP56]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i64 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
|
|
// CHECK-NEXT: store i64 [[TMP59]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
|
|
// CHECK-NEXT: store i64 [[TMP65]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP66]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP67]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP68]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP69]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i64 [[TMP73]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP74]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i64 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
|
|
// CHECK-NEXT: store i64 [[TMP77]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP78]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i64 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
|
|
// CHECK-NEXT: store i64 [[TMP81]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
|
|
// CHECK-NEXT: store i64 [[TMP87]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP88]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP89]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP90]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP91]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i64 [[TMP95]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP96]] release, align 8
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i64 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
|
|
// CHECK-NEXT: store i64 [[TMP99]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP100]] release, align 8
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i64 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
|
|
// CHECK-NEXT: store i64 [[TMP103]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
|
|
// CHECK-NEXT: store i64 [[TMP109]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP110]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP111]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP112]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP113]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i64 [[TMP117]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP118]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i64 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
|
|
// CHECK-NEXT: store i64 [[TMP121]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP122]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i64 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
|
|
// CHECK-NEXT: store i64 [[TMP125]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
|
|
// CHECK-NEXT: store i64 [[TMP131]], ptr [[ULV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr [[ULV]], align 8
|
|
// CHECK-NEXT: ret i64 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @llxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[LLX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLV:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[LLD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP0]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP1]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i64 [[TMP7]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP8]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
|
|
// CHECK-NEXT: store i64 [[TMP11]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP12]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
|
|
// CHECK-NEXT: store i64 [[TMP15]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
|
|
// CHECK-NEXT: store i64 [[TMP21]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP22]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP23]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP24]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP25]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i64 [[TMP29]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP30]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i64 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
|
|
// CHECK-NEXT: store i64 [[TMP33]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP34]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i64 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
|
|
// CHECK-NEXT: store i64 [[TMP37]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
|
|
// CHECK-NEXT: store i64 [[TMP43]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP44]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP45]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP46]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP47]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i64 [[TMP51]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP52]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i64 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
|
|
// CHECK-NEXT: store i64 [[TMP55]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP56]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i64 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
|
|
// CHECK-NEXT: store i64 [[TMP59]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
|
|
// CHECK-NEXT: store i64 [[TMP65]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP66]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP67]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP68]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP69]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i64 [[TMP73]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP74]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i64 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
|
|
// CHECK-NEXT: store i64 [[TMP77]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP78]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i64 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
|
|
// CHECK-NEXT: store i64 [[TMP81]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
|
|
// CHECK-NEXT: store i64 [[TMP87]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP88]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP89]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP90]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP91]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i64 [[TMP95]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP96]] release, align 8
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i64 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
|
|
// CHECK-NEXT: store i64 [[TMP99]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP100]] release, align 8
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i64 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
|
|
// CHECK-NEXT: store i64 [[TMP103]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
|
|
// CHECK-NEXT: store i64 [[TMP109]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP110]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP111]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP112]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP113]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i64 [[TMP117]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP118]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i64 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
|
|
// CHECK-NEXT: store i64 [[TMP121]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP122]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i64 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
|
|
// CHECK-NEXT: store i64 [[TMP125]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
|
|
// CHECK-NEXT: store i64 [[TMP131]], ptr [[LLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr [[LLV]], align 8
|
|
// CHECK-NEXT: ret i64 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @ullxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[ULLX:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLV:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLE:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[ULLD:%.*]] = alloca i64, align 8
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP0]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP1]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP3]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
|
|
// CHECK-NEXT: store i64 [[TMP7]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP8]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[TMP8]]
|
|
// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
|
|
// CHECK-NEXT: store i64 [[TMP11]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP12]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP13]], [[TMP12]]
|
|
// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
|
|
// CHECK-NEXT: store i64 [[TMP15]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
|
|
// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
|
|
// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
|
|
// CHECK-NEXT: store i64 [[TMP21]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP22]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP23]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP24]] acq_rel, align 8
|
|
// CHECK-NEXT: store i64 [[TMP25]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
|
|
// CHECK-NEXT: store i64 [[TMP29]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP30]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i64 [[TMP31]], [[TMP30]]
|
|
// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
|
|
// CHECK-NEXT: store i64 [[TMP33]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP34:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP34]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i64 [[TMP35]], [[TMP34]]
|
|
// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
|
|
// CHECK-NEXT: store i64 [[TMP37]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP38:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
|
|
// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
|
|
// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
|
|
// CHECK-NEXT: store i64 [[TMP43]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP44]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP45]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP46]] acquire, align 8
|
|
// CHECK-NEXT: store i64 [[TMP47]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
|
|
// CHECK-NEXT: store i64 [[TMP51]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP52]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i64 [[TMP53]], [[TMP52]]
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
|
|
// CHECK-NEXT: store i64 [[TMP55]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP56]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i64 [[TMP57]], [[TMP56]]
|
|
// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
|
|
// CHECK-NEXT: store i64 [[TMP59]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
|
|
// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
|
|
// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
|
|
// CHECK-NEXT: store i64 [[TMP65]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP66:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP66]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP67]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP68]] monotonic, align 8
|
|
// CHECK-NEXT: store i64 [[TMP69]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP70:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
|
|
// CHECK-NEXT: store i64 [[TMP73]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP74:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP74]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i64 [[TMP75]], [[TMP74]]
|
|
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
|
|
// CHECK-NEXT: store i64 [[TMP77]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP78]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i64 [[TMP79]], [[TMP78]]
|
|
// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
|
|
// CHECK-NEXT: store i64 [[TMP81]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP82:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP83:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
|
|
// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
|
|
// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
|
|
// CHECK-NEXT: store i64 [[TMP87]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP88]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP89]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP90]] release, align 8
|
|
// CHECK-NEXT: store i64 [[TMP91]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP93:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
|
|
// CHECK-NEXT: store i64 [[TMP95]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP96]] release, align 8
|
|
// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i64 [[TMP97]], [[TMP96]]
|
|
// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
|
|
// CHECK-NEXT: store i64 [[TMP99]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP100]] release, align 8
|
|
// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i64 [[TMP101]], [[TMP100]]
|
|
// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
|
|
// CHECK-NEXT: store i64 [[TMP103]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP105:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
|
|
// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
|
|
// CHECK-NEXT: store i64 [[TMP109]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP110:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP110]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP111]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP112]] seq_cst, align 8
|
|
// CHECK-NEXT: store i64 [[TMP113]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP115:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
|
|
// CHECK-NEXT: store i64 [[TMP117]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP118:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP118]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i64 [[TMP119]], [[TMP118]]
|
|
// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
|
|
// CHECK-NEXT: store i64 [[TMP121]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP122:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP122]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i64 [[TMP123]], [[TMP122]]
|
|
// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
|
|
// CHECK-NEXT: store i64 [[TMP125]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP126:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
|
|
// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
|
|
// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
|
|
// CHECK-NEXT: store i64 [[TMP131]], ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr [[ULLV]], align 8
|
|
// CHECK-NEXT: ret i64 [[TMP132]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @fxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[FX:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[FV:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[FE:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[FD:%.*]] = alloca float, align 4
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP0]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP1]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP3]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP6:%.*]] = bitcast float [[TMP4]] to i32
|
|
// CHECK-NEXT: [[TMP7:%.*]] = bitcast float [[TMP5]] to i32
|
|
// CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP6]], i32 [[TMP7]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i1 } [[TMP8]], 0
|
|
// CHECK-NEXT: [[TMP10:%.*]] = bitcast i32 [[TMP9]] to float
|
|
// CHECK-NEXT: store float [[TMP10]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP12:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP11]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP13:%.*]] = fcmp olt float [[TMP12]], [[TMP11]]
|
|
// CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], float [[TMP11]], float [[TMP12]]
|
|
// CHECK-NEXT: store float [[TMP14]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP16:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP15]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP17:%.*]] = fcmp ogt float [[TMP16]], [[TMP15]]
|
|
// CHECK-NEXT: [[TMP18:%.*]] = select i1 [[TMP17]], float [[TMP15]], float [[TMP16]]
|
|
// CHECK-NEXT: store float [[TMP18]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP21:%.*]] = bitcast float [[TMP19]] to i32
|
|
// CHECK-NEXT: [[TMP22:%.*]] = bitcast float [[TMP20]] to i32
|
|
// CHECK-NEXT: [[TMP23:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP21]], i32 [[TMP22]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP24:%.*]] = extractvalue { i32, i1 } [[TMP23]], 0
|
|
// CHECK-NEXT: [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
|
|
// CHECK-NEXT: [[TMP26:%.*]] = extractvalue { i32, i1 } [[TMP23]], 1
|
|
// CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP26]], float [[TMP19]], float [[TMP25]]
|
|
// CHECK-NEXT: store float [[TMP27]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP28:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP29:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP28]] acq_rel, align 4
|
|
// CHECK-NEXT: store float [[TMP29]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP30]] acq_rel, align 4
|
|
// CHECK-NEXT: store float [[TMP31]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP32:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP33:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP34:%.*]] = bitcast float [[TMP32]] to i32
|
|
// CHECK-NEXT: [[TMP35:%.*]] = bitcast float [[TMP33]] to i32
|
|
// CHECK-NEXT: [[TMP36:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP34]], i32 [[TMP35]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP37:%.*]] = extractvalue { i32, i1 } [[TMP36]], 0
|
|
// CHECK-NEXT: [[TMP38:%.*]] = bitcast i32 [[TMP37]] to float
|
|
// CHECK-NEXT: store float [[TMP38]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP40:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP39]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP41:%.*]] = fcmp olt float [[TMP40]], [[TMP39]]
|
|
// CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], float [[TMP39]], float [[TMP40]]
|
|
// CHECK-NEXT: store float [[TMP42]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP43:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP44:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP43]] acq_rel, align 4
|
|
// CHECK-NEXT: [[TMP45:%.*]] = fcmp ogt float [[TMP44]], [[TMP43]]
|
|
// CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP45]], float [[TMP43]], float [[TMP44]]
|
|
// CHECK-NEXT: store float [[TMP46]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP47:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP49:%.*]] = bitcast float [[TMP47]] to i32
|
|
// CHECK-NEXT: [[TMP50:%.*]] = bitcast float [[TMP48]] to i32
|
|
// CHECK-NEXT: [[TMP51:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP49]], i32 [[TMP50]] acq_rel acquire, align 4
|
|
// CHECK-NEXT: [[TMP52:%.*]] = extractvalue { i32, i1 } [[TMP51]], 0
|
|
// CHECK-NEXT: [[TMP53:%.*]] = bitcast i32 [[TMP52]] to float
|
|
// CHECK-NEXT: [[TMP54:%.*]] = extractvalue { i32, i1 } [[TMP51]], 1
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], float [[TMP47]], float [[TMP53]]
|
|
// CHECK-NEXT: store float [[TMP55]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP56]] acquire, align 4
|
|
// CHECK-NEXT: store float [[TMP57]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP58:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP58]] acquire, align 4
|
|
// CHECK-NEXT: store float [[TMP59]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP62:%.*]] = bitcast float [[TMP60]] to i32
|
|
// CHECK-NEXT: [[TMP63:%.*]] = bitcast float [[TMP61]] to i32
|
|
// CHECK-NEXT: [[TMP64:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP62]], i32 [[TMP63]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP65:%.*]] = extractvalue { i32, i1 } [[TMP64]], 0
|
|
// CHECK-NEXT: [[TMP66:%.*]] = bitcast i32 [[TMP65]] to float
|
|
// CHECK-NEXT: store float [[TMP66]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP67:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP68:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP67]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP69:%.*]] = fcmp olt float [[TMP68]], [[TMP67]]
|
|
// CHECK-NEXT: [[TMP70:%.*]] = select i1 [[TMP69]], float [[TMP67]], float [[TMP68]]
|
|
// CHECK-NEXT: store float [[TMP70]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP72:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP71]] acquire, align 4
|
|
// CHECK-NEXT: [[TMP73:%.*]] = fcmp ogt float [[TMP72]], [[TMP71]]
|
|
// CHECK-NEXT: [[TMP74:%.*]] = select i1 [[TMP73]], float [[TMP71]], float [[TMP72]]
|
|
// CHECK-NEXT: store float [[TMP74]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP75:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP76:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP77:%.*]] = bitcast float [[TMP75]] to i32
|
|
// CHECK-NEXT: [[TMP78:%.*]] = bitcast float [[TMP76]] to i32
|
|
// CHECK-NEXT: [[TMP79:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP77]], i32 [[TMP78]] acquire acquire, align 4
|
|
// CHECK-NEXT: [[TMP80:%.*]] = extractvalue { i32, i1 } [[TMP79]], 0
|
|
// CHECK-NEXT: [[TMP81:%.*]] = bitcast i32 [[TMP80]] to float
|
|
// CHECK-NEXT: [[TMP82:%.*]] = extractvalue { i32, i1 } [[TMP79]], 1
|
|
// CHECK-NEXT: [[TMP83:%.*]] = select i1 [[TMP82]], float [[TMP75]], float [[TMP81]]
|
|
// CHECK-NEXT: store float [[TMP83]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP84:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP85:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP84]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP85]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP86:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP86]] monotonic, align 4
|
|
// CHECK-NEXT: store float [[TMP87]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP89:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP90:%.*]] = bitcast float [[TMP88]] to i32
|
|
// CHECK-NEXT: [[TMP91:%.*]] = bitcast float [[TMP89]] to i32
|
|
// CHECK-NEXT: [[TMP92:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP90]], i32 [[TMP91]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP93:%.*]] = extractvalue { i32, i1 } [[TMP92]], 0
|
|
// CHECK-NEXT: [[TMP94:%.*]] = bitcast i32 [[TMP93]] to float
|
|
// CHECK-NEXT: store float [[TMP94]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP95:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP96:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP95]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP97:%.*]] = fcmp olt float [[TMP96]], [[TMP95]]
|
|
// CHECK-NEXT: [[TMP98:%.*]] = select i1 [[TMP97]], float [[TMP95]], float [[TMP96]]
|
|
// CHECK-NEXT: store float [[TMP98]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP99:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP100:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP99]] monotonic, align 4
|
|
// CHECK-NEXT: [[TMP101:%.*]] = fcmp ogt float [[TMP100]], [[TMP99]]
|
|
// CHECK-NEXT: [[TMP102:%.*]] = select i1 [[TMP101]], float [[TMP99]], float [[TMP100]]
|
|
// CHECK-NEXT: store float [[TMP102]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP103:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP105:%.*]] = bitcast float [[TMP103]] to i32
|
|
// CHECK-NEXT: [[TMP106:%.*]] = bitcast float [[TMP104]] to i32
|
|
// CHECK-NEXT: [[TMP107:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP105]], i32 [[TMP106]] monotonic monotonic, align 4
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP107]], 0
|
|
// CHECK-NEXT: [[TMP109:%.*]] = bitcast i32 [[TMP108]] to float
|
|
// CHECK-NEXT: [[TMP110:%.*]] = extractvalue { i32, i1 } [[TMP107]], 1
|
|
// CHECK-NEXT: [[TMP111:%.*]] = select i1 [[TMP110]], float [[TMP103]], float [[TMP109]]
|
|
// CHECK-NEXT: store float [[TMP111]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP112]] release, align 4
|
|
// CHECK-NEXT: store float [[TMP113]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP115:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP114]] release, align 4
|
|
// CHECK-NEXT: store float [[TMP115]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP116:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP117:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP118:%.*]] = bitcast float [[TMP116]] to i32
|
|
// CHECK-NEXT: [[TMP119:%.*]] = bitcast float [[TMP117]] to i32
|
|
// CHECK-NEXT: [[TMP120:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP118]], i32 [[TMP119]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP121:%.*]] = extractvalue { i32, i1 } [[TMP120]], 0
|
|
// CHECK-NEXT: [[TMP122:%.*]] = bitcast i32 [[TMP121]] to float
|
|
// CHECK-NEXT: store float [[TMP122]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP123:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP124:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP123]] release, align 4
|
|
// CHECK-NEXT: [[TMP125:%.*]] = fcmp olt float [[TMP124]], [[TMP123]]
|
|
// CHECK-NEXT: [[TMP126:%.*]] = select i1 [[TMP125]], float [[TMP123]], float [[TMP124]]
|
|
// CHECK-NEXT: store float [[TMP126]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP128:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP127]] release, align 4
|
|
// CHECK-NEXT: [[TMP129:%.*]] = fcmp ogt float [[TMP128]], [[TMP127]]
|
|
// CHECK-NEXT: [[TMP130:%.*]] = select i1 [[TMP129]], float [[TMP127]], float [[TMP128]]
|
|
// CHECK-NEXT: store float [[TMP130]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP131:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP133:%.*]] = bitcast float [[TMP131]] to i32
|
|
// CHECK-NEXT: [[TMP134:%.*]] = bitcast float [[TMP132]] to i32
|
|
// CHECK-NEXT: [[TMP135:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP133]], i32 [[TMP134]] release monotonic, align 4
|
|
// CHECK-NEXT: [[TMP136:%.*]] = extractvalue { i32, i1 } [[TMP135]], 0
|
|
// CHECK-NEXT: [[TMP137:%.*]] = bitcast i32 [[TMP136]] to float
|
|
// CHECK-NEXT: [[TMP138:%.*]] = extractvalue { i32, i1 } [[TMP135]], 1
|
|
// CHECK-NEXT: [[TMP139:%.*]] = select i1 [[TMP138]], float [[TMP131]], float [[TMP137]]
|
|
// CHECK-NEXT: store float [[TMP139]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP140:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP141:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP140]] seq_cst, align 4
|
|
// CHECK-NEXT: store float [[TMP141]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP142:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP143:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP142]] seq_cst, align 4
|
|
// CHECK-NEXT: store float [[TMP143]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP144:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP145:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP146:%.*]] = bitcast float [[TMP144]] to i32
|
|
// CHECK-NEXT: [[TMP147:%.*]] = bitcast float [[TMP145]] to i32
|
|
// CHECK-NEXT: [[TMP148:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP146]], i32 [[TMP147]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP149:%.*]] = extractvalue { i32, i1 } [[TMP148]], 0
|
|
// CHECK-NEXT: [[TMP150:%.*]] = bitcast i32 [[TMP149]] to float
|
|
// CHECK-NEXT: store float [[TMP150]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP151:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP152:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP151]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP153:%.*]] = fcmp olt float [[TMP152]], [[TMP151]]
|
|
// CHECK-NEXT: [[TMP154:%.*]] = select i1 [[TMP153]], float [[TMP151]], float [[TMP152]]
|
|
// CHECK-NEXT: store float [[TMP154]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP155:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP156:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP155]] seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP157:%.*]] = fcmp ogt float [[TMP156]], [[TMP155]]
|
|
// CHECK-NEXT: [[TMP158:%.*]] = select i1 [[TMP157]], float [[TMP155]], float [[TMP156]]
|
|
// CHECK-NEXT: store float [[TMP158]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP159:%.*]] = load float, ptr [[FE]], align 4
|
|
// CHECK-NEXT: [[TMP160:%.*]] = load float, ptr [[FD]], align 4
|
|
// CHECK-NEXT: [[TMP161:%.*]] = bitcast float [[TMP159]] to i32
|
|
// CHECK-NEXT: [[TMP162:%.*]] = bitcast float [[TMP160]] to i32
|
|
// CHECK-NEXT: [[TMP163:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP161]], i32 [[TMP162]] seq_cst seq_cst, align 4
|
|
// CHECK-NEXT: [[TMP164:%.*]] = extractvalue { i32, i1 } [[TMP163]], 0
|
|
// CHECK-NEXT: [[TMP165:%.*]] = bitcast i32 [[TMP164]] to float
|
|
// CHECK-NEXT: [[TMP166:%.*]] = extractvalue { i32, i1 } [[TMP163]], 1
|
|
// CHECK-NEXT: [[TMP167:%.*]] = select i1 [[TMP166]], float [[TMP159]], float [[TMP165]]
|
|
// CHECK-NEXT: store float [[TMP167]], ptr [[FV]], align 4
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP168:%.*]] = load float, ptr [[FV]], align 4
|
|
// CHECK-NEXT: ret float [[TMP168]]
|
|
//
|
|
//
|
|
// CHECK-LABEL: @dxevd(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[DX:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[DV:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[DE:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[DD:%.*]] = alloca double, align 8
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP0]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP1]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP3:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP2]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP3]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP5:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP6:%.*]] = bitcast double [[TMP4]] to i64
|
|
// CHECK-NEXT: [[TMP7:%.*]] = bitcast double [[TMP5]] to i64
|
|
// CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP6]], i64 [[TMP7]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i64, i1 } [[TMP8]], 0
|
|
// CHECK-NEXT: [[TMP10:%.*]] = bitcast i64 [[TMP9]] to double
|
|
// CHECK-NEXT: store double [[TMP10]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP11:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP12:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP11]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP13:%.*]] = fcmp olt double [[TMP12]], [[TMP11]]
|
|
// CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], double [[TMP11]], double [[TMP12]]
|
|
// CHECK-NEXT: store double [[TMP14]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP15:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP16:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP15]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP17:%.*]] = fcmp ogt double [[TMP16]], [[TMP15]]
|
|
// CHECK-NEXT: [[TMP18:%.*]] = select i1 [[TMP17]], double [[TMP15]], double [[TMP16]]
|
|
// CHECK-NEXT: store double [[TMP18]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP19:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP20:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP21:%.*]] = bitcast double [[TMP19]] to i64
|
|
// CHECK-NEXT: [[TMP22:%.*]] = bitcast double [[TMP20]] to i64
|
|
// CHECK-NEXT: [[TMP23:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP21]], i64 [[TMP22]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP24:%.*]] = extractvalue { i64, i1 } [[TMP23]], 0
|
|
// CHECK-NEXT: [[TMP25:%.*]] = bitcast i64 [[TMP24]] to double
|
|
// CHECK-NEXT: [[TMP26:%.*]] = extractvalue { i64, i1 } [[TMP23]], 1
|
|
// CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP26]], double [[TMP19]], double [[TMP25]]
|
|
// CHECK-NEXT: store double [[TMP27]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP28:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP29:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP28]] acq_rel, align 8
|
|
// CHECK-NEXT: store double [[TMP29]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP30:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP30]] acq_rel, align 8
|
|
// CHECK-NEXT: store double [[TMP31]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP32:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP33:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP34:%.*]] = bitcast double [[TMP32]] to i64
|
|
// CHECK-NEXT: [[TMP35:%.*]] = bitcast double [[TMP33]] to i64
|
|
// CHECK-NEXT: [[TMP36:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP34]], i64 [[TMP35]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP37:%.*]] = extractvalue { i64, i1 } [[TMP36]], 0
|
|
// CHECK-NEXT: [[TMP38:%.*]] = bitcast i64 [[TMP37]] to double
|
|
// CHECK-NEXT: store double [[TMP38]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP39:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP40:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP39]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP41:%.*]] = fcmp olt double [[TMP40]], [[TMP39]]
|
|
// CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], double [[TMP39]], double [[TMP40]]
|
|
// CHECK-NEXT: store double [[TMP42]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP43:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP44:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP43]] acq_rel, align 8
|
|
// CHECK-NEXT: [[TMP45:%.*]] = fcmp ogt double [[TMP44]], [[TMP43]]
|
|
// CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP45]], double [[TMP43]], double [[TMP44]]
|
|
// CHECK-NEXT: store double [[TMP46]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP47:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP48:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP49:%.*]] = bitcast double [[TMP47]] to i64
|
|
// CHECK-NEXT: [[TMP50:%.*]] = bitcast double [[TMP48]] to i64
|
|
// CHECK-NEXT: [[TMP51:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP49]], i64 [[TMP50]] acq_rel acquire, align 8
|
|
// CHECK-NEXT: [[TMP52:%.*]] = extractvalue { i64, i1 } [[TMP51]], 0
|
|
// CHECK-NEXT: [[TMP53:%.*]] = bitcast i64 [[TMP52]] to double
|
|
// CHECK-NEXT: [[TMP54:%.*]] = extractvalue { i64, i1 } [[TMP51]], 1
|
|
// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], double [[TMP47]], double [[TMP53]]
|
|
// CHECK-NEXT: store double [[TMP55]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP56:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP56]] acquire, align 8
|
|
// CHECK-NEXT: store double [[TMP57]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP58:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP58]] acquire, align 8
|
|
// CHECK-NEXT: store double [[TMP59]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP60:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP61:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP62:%.*]] = bitcast double [[TMP60]] to i64
|
|
// CHECK-NEXT: [[TMP63:%.*]] = bitcast double [[TMP61]] to i64
|
|
// CHECK-NEXT: [[TMP64:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP62]], i64 [[TMP63]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP65:%.*]] = extractvalue { i64, i1 } [[TMP64]], 0
|
|
// CHECK-NEXT: [[TMP66:%.*]] = bitcast i64 [[TMP65]] to double
|
|
// CHECK-NEXT: store double [[TMP66]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP67:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP68:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP67]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP69:%.*]] = fcmp olt double [[TMP68]], [[TMP67]]
|
|
// CHECK-NEXT: [[TMP70:%.*]] = select i1 [[TMP69]], double [[TMP67]], double [[TMP68]]
|
|
// CHECK-NEXT: store double [[TMP70]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP71:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP72:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP71]] acquire, align 8
|
|
// CHECK-NEXT: [[TMP73:%.*]] = fcmp ogt double [[TMP72]], [[TMP71]]
|
|
// CHECK-NEXT: [[TMP74:%.*]] = select i1 [[TMP73]], double [[TMP71]], double [[TMP72]]
|
|
// CHECK-NEXT: store double [[TMP74]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP75:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP76:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP77:%.*]] = bitcast double [[TMP75]] to i64
|
|
// CHECK-NEXT: [[TMP78:%.*]] = bitcast double [[TMP76]] to i64
|
|
// CHECK-NEXT: [[TMP79:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP77]], i64 [[TMP78]] acquire acquire, align 8
|
|
// CHECK-NEXT: [[TMP80:%.*]] = extractvalue { i64, i1 } [[TMP79]], 0
|
|
// CHECK-NEXT: [[TMP81:%.*]] = bitcast i64 [[TMP80]] to double
|
|
// CHECK-NEXT: [[TMP82:%.*]] = extractvalue { i64, i1 } [[TMP79]], 1
|
|
// CHECK-NEXT: [[TMP83:%.*]] = select i1 [[TMP82]], double [[TMP75]], double [[TMP81]]
|
|
// CHECK-NEXT: store double [[TMP83]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP84:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP85:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP84]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP85]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP86:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP86]] monotonic, align 8
|
|
// CHECK-NEXT: store double [[TMP87]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP88:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP89:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP90:%.*]] = bitcast double [[TMP88]] to i64
|
|
// CHECK-NEXT: [[TMP91:%.*]] = bitcast double [[TMP89]] to i64
|
|
// CHECK-NEXT: [[TMP92:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP90]], i64 [[TMP91]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP93:%.*]] = extractvalue { i64, i1 } [[TMP92]], 0
|
|
// CHECK-NEXT: [[TMP94:%.*]] = bitcast i64 [[TMP93]] to double
|
|
// CHECK-NEXT: store double [[TMP94]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP95:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP96:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP95]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP97:%.*]] = fcmp olt double [[TMP96]], [[TMP95]]
|
|
// CHECK-NEXT: [[TMP98:%.*]] = select i1 [[TMP97]], double [[TMP95]], double [[TMP96]]
|
|
// CHECK-NEXT: store double [[TMP98]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP99:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP100:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP99]] monotonic, align 8
|
|
// CHECK-NEXT: [[TMP101:%.*]] = fcmp ogt double [[TMP100]], [[TMP99]]
|
|
// CHECK-NEXT: [[TMP102:%.*]] = select i1 [[TMP101]], double [[TMP99]], double [[TMP100]]
|
|
// CHECK-NEXT: store double [[TMP102]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP103:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP104:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP105:%.*]] = bitcast double [[TMP103]] to i64
|
|
// CHECK-NEXT: [[TMP106:%.*]] = bitcast double [[TMP104]] to i64
|
|
// CHECK-NEXT: [[TMP107:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP105]], i64 [[TMP106]] monotonic monotonic, align 8
|
|
// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP107]], 0
|
|
// CHECK-NEXT: [[TMP109:%.*]] = bitcast i64 [[TMP108]] to double
|
|
// CHECK-NEXT: [[TMP110:%.*]] = extractvalue { i64, i1 } [[TMP107]], 1
|
|
// CHECK-NEXT: [[TMP111:%.*]] = select i1 [[TMP110]], double [[TMP103]], double [[TMP109]]
|
|
// CHECK-NEXT: store double [[TMP111]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: [[TMP112:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP112]] release, align 8
|
|
// CHECK-NEXT: store double [[TMP113]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP114:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP115:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP114]] release, align 8
|
|
// CHECK-NEXT: store double [[TMP115]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP116:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP117:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP118:%.*]] = bitcast double [[TMP116]] to i64
|
|
// CHECK-NEXT: [[TMP119:%.*]] = bitcast double [[TMP117]] to i64
|
|
// CHECK-NEXT: [[TMP120:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP118]], i64 [[TMP119]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP121:%.*]] = extractvalue { i64, i1 } [[TMP120]], 0
|
|
// CHECK-NEXT: [[TMP122:%.*]] = bitcast i64 [[TMP121]] to double
|
|
// CHECK-NEXT: store double [[TMP122]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP123:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP124:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP123]] release, align 8
|
|
// CHECK-NEXT: [[TMP125:%.*]] = fcmp olt double [[TMP124]], [[TMP123]]
|
|
// CHECK-NEXT: [[TMP126:%.*]] = select i1 [[TMP125]], double [[TMP123]], double [[TMP124]]
|
|
// CHECK-NEXT: store double [[TMP126]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP127:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP128:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP127]] release, align 8
|
|
// CHECK-NEXT: [[TMP129:%.*]] = fcmp ogt double [[TMP128]], [[TMP127]]
|
|
// CHECK-NEXT: [[TMP130:%.*]] = select i1 [[TMP129]], double [[TMP127]], double [[TMP128]]
|
|
// CHECK-NEXT: store double [[TMP130]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP131:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP132:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP133:%.*]] = bitcast double [[TMP131]] to i64
|
|
// CHECK-NEXT: [[TMP134:%.*]] = bitcast double [[TMP132]] to i64
|
|
// CHECK-NEXT: [[TMP135:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP133]], i64 [[TMP134]] release monotonic, align 8
|
|
// CHECK-NEXT: [[TMP136:%.*]] = extractvalue { i64, i1 } [[TMP135]], 0
|
|
// CHECK-NEXT: [[TMP137:%.*]] = bitcast i64 [[TMP136]] to double
|
|
// CHECK-NEXT: [[TMP138:%.*]] = extractvalue { i64, i1 } [[TMP135]], 1
|
|
// CHECK-NEXT: [[TMP139:%.*]] = select i1 [[TMP138]], double [[TMP131]], double [[TMP137]]
|
|
// CHECK-NEXT: store double [[TMP139]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP140:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP141:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP140]] seq_cst, align 8
|
|
// CHECK-NEXT: store double [[TMP141]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP142:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP143:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP142]] seq_cst, align 8
|
|
// CHECK-NEXT: store double [[TMP143]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP144:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP145:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP146:%.*]] = bitcast double [[TMP144]] to i64
|
|
// CHECK-NEXT: [[TMP147:%.*]] = bitcast double [[TMP145]] to i64
|
|
// CHECK-NEXT: [[TMP148:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP146]], i64 [[TMP147]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP149:%.*]] = extractvalue { i64, i1 } [[TMP148]], 0
|
|
// CHECK-NEXT: [[TMP150:%.*]] = bitcast i64 [[TMP149]] to double
|
|
// CHECK-NEXT: store double [[TMP150]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP151:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP152:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP151]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP153:%.*]] = fcmp olt double [[TMP152]], [[TMP151]]
|
|
// CHECK-NEXT: [[TMP154:%.*]] = select i1 [[TMP153]], double [[TMP151]], double [[TMP152]]
|
|
// CHECK-NEXT: store double [[TMP154]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP155:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP156:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP155]] seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP157:%.*]] = fcmp ogt double [[TMP156]], [[TMP155]]
|
|
// CHECK-NEXT: [[TMP158:%.*]] = select i1 [[TMP157]], double [[TMP155]], double [[TMP156]]
|
|
// CHECK-NEXT: store double [[TMP158]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP159:%.*]] = load double, ptr [[DE]], align 8
|
|
// CHECK-NEXT: [[TMP160:%.*]] = load double, ptr [[DD]], align 8
|
|
// CHECK-NEXT: [[TMP161:%.*]] = bitcast double [[TMP159]] to i64
|
|
// CHECK-NEXT: [[TMP162:%.*]] = bitcast double [[TMP160]] to i64
|
|
// CHECK-NEXT: [[TMP163:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP161]], i64 [[TMP162]] seq_cst seq_cst, align 8
|
|
// CHECK-NEXT: [[TMP164:%.*]] = extractvalue { i64, i1 } [[TMP163]], 0
|
|
// CHECK-NEXT: [[TMP165:%.*]] = bitcast i64 [[TMP164]] to double
|
|
// CHECK-NEXT: [[TMP166:%.*]] = extractvalue { i64, i1 } [[TMP163]], 1
|
|
// CHECK-NEXT: [[TMP167:%.*]] = select i1 [[TMP166]], double [[TMP159]], double [[TMP165]]
|
|
// CHECK-NEXT: store double [[TMP167]], ptr [[DV]], align 8
|
|
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
|
|
// CHECK-NEXT: [[TMP168:%.*]] = load double, ptr [[DV]], align 8
|
|
// CHECK-NEXT: ret double [[TMP168]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @foo(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[CX:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[CE:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[CD:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCX:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCE:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCD:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[SX:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[SE:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[SD:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USX:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USE:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USD:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[IX:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[IE:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[ID:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UIX:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UIE:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UID:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[LX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[FX:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[FE:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[FD:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[DX:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[DE:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[DD:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV4:%.*]] = sext i8 [[TMP3]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV5:%.*]] = trunc i32 [[COND]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV5]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV7:%.*]] = sext i8 [[TMP5]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
|
|
// SIMD-ONLY0: cond.true10:
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV11:%.*]] = sext i8 [[TMP6]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false12:
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV13:%.*]] = sext i8 [[TMP7]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV16:%.*]] = trunc i32 [[COND15]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV16]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV17:%.*]] = sext i8 [[TMP8]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV18:%.*]] = sext i8 [[TMP9]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[CONV17]], [[CONV18]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true21:
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV22:%.*]] = sext i8 [[TMP10]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV24:%.*]] = sext i8 [[TMP11]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25]]
|
|
// SIMD-ONLY0: cond.end25:
|
|
// SIMD-ONLY0-NEXT: [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV27:%.*]] = trunc i32 [[COND26]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV27]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV28:%.*]] = sext i8 [[TMP12]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV29:%.*]] = sext i8 [[TMP13]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP30:%.*]] = icmp slt i32 [[CONV28]], [[CONV29]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV33:%.*]] = sext i8 [[TMP14]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36:%.*]]
|
|
// SIMD-ONLY0: cond.false34:
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV35:%.*]] = sext i8 [[TMP15]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36]]
|
|
// SIMD-ONLY0: cond.end36:
|
|
// SIMD-ONLY0-NEXT: [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV38:%.*]] = trunc i32 [[COND37]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV38]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV39:%.*]] = sext i8 [[TMP16]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV40:%.*]] = sext i8 [[TMP17]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp sgt i32 [[CONV39]], [[CONV40]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
// SIMD-ONLY0: if.then:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP18]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END]]
|
|
// SIMD-ONLY0: if.end:
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV43:%.*]] = sext i8 [[TMP19]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV44:%.*]] = sext i8 [[TMP20]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP45:%.*]] = icmp slt i32 [[CONV43]], [[CONV44]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP45]], label [[IF_THEN47:%.*]], label [[IF_END48:%.*]]
|
|
// SIMD-ONLY0: if.then47:
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP21]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END48]]
|
|
// SIMD-ONLY0: if.end48:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV49:%.*]] = sext i8 [[TMP22]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV50:%.*]] = sext i8 [[TMP23]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP51:%.*]] = icmp sgt i32 [[CONV49]], [[CONV50]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP51]], label [[IF_THEN53:%.*]], label [[IF_END54:%.*]]
|
|
// SIMD-ONLY0: if.then53:
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP24]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END54]]
|
|
// SIMD-ONLY0: if.end54:
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV55:%.*]] = sext i8 [[TMP25]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV56:%.*]] = sext i8 [[TMP26]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP57:%.*]] = icmp slt i32 [[CONV55]], [[CONV56]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP57]], label [[IF_THEN59:%.*]], label [[IF_END60:%.*]]
|
|
// SIMD-ONLY0: if.then59:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP27]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END60]]
|
|
// SIMD-ONLY0: if.end60:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV61:%.*]] = sext i8 [[TMP28]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV62:%.*]] = sext i8 [[TMP29]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP63:%.*]] = icmp eq i32 [[CONV61]], [[CONV62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
|
|
// SIMD-ONLY0: cond.true65:
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV66:%.*]] = sext i8 [[TMP30]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false67:
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV68:%.*]] = sext i8 [[TMP31]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV71:%.*]] = trunc i32 [[COND70]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV71]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV72:%.*]] = sext i8 [[TMP32]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV73:%.*]] = sext i8 [[TMP33]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP74:%.*]] = icmp eq i32 [[CONV72]], [[CONV73]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true76:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV77:%.*]] = sext i8 [[TMP34]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV79:%.*]] = sext i8 [[TMP35]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80]]
|
|
// SIMD-ONLY0: cond.end80:
|
|
// SIMD-ONLY0-NEXT: [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV82:%.*]] = trunc i32 [[COND81]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV82]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV83:%.*]] = sext i8 [[TMP36]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV84:%.*]] = sext i8 [[TMP37]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP85]], label [[IF_THEN87:%.*]], label [[IF_END88:%.*]]
|
|
// SIMD-ONLY0: if.then87:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP38]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END88]]
|
|
// SIMD-ONLY0: if.end88:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV89:%.*]] = sext i8 [[TMP39]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV90:%.*]] = sext i8 [[TMP40]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = icmp eq i32 [[CONV89]], [[CONV90]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP91]], label [[IF_THEN93:%.*]], label [[IF_END94:%.*]]
|
|
// SIMD-ONLY0: if.then93:
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP41]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END94]]
|
|
// SIMD-ONLY0: if.end94:
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV95:%.*]] = zext i8 [[TMP42]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV96:%.*]] = zext i8 [[TMP43]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP97:%.*]] = icmp sgt i32 [[CONV95]], [[CONV96]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP97]], label [[COND_TRUE99:%.*]], label [[COND_FALSE101:%.*]]
|
|
// SIMD-ONLY0: cond.true99:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV100:%.*]] = zext i8 [[TMP44]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END103:%.*]]
|
|
// SIMD-ONLY0: cond.false101:
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV102:%.*]] = zext i8 [[TMP45]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END103]]
|
|
// SIMD-ONLY0: cond.end103:
|
|
// SIMD-ONLY0-NEXT: [[COND104:%.*]] = phi i32 [ [[CONV100]], [[COND_TRUE99]] ], [ [[CONV102]], [[COND_FALSE101]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV105:%.*]] = trunc i32 [[COND104]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV105]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV106:%.*]] = zext i8 [[TMP46]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV107:%.*]] = zext i8 [[TMP47]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP108:%.*]] = icmp slt i32 [[CONV106]], [[CONV107]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP108]], label [[COND_TRUE110:%.*]], label [[COND_FALSE112:%.*]]
|
|
// SIMD-ONLY0: cond.true110:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV111:%.*]] = zext i8 [[TMP48]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114:%.*]]
|
|
// SIMD-ONLY0: cond.false112:
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV113:%.*]] = zext i8 [[TMP49]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114]]
|
|
// SIMD-ONLY0: cond.end114:
|
|
// SIMD-ONLY0-NEXT: [[COND115:%.*]] = phi i32 [ [[CONV111]], [[COND_TRUE110]] ], [ [[CONV113]], [[COND_FALSE112]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV116:%.*]] = trunc i32 [[COND115]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV116]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV117:%.*]] = zext i8 [[TMP50]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV118:%.*]] = zext i8 [[TMP51]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP119:%.*]] = icmp sgt i32 [[CONV117]], [[CONV118]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP119]], label [[COND_TRUE121:%.*]], label [[COND_FALSE123:%.*]]
|
|
// SIMD-ONLY0: cond.true121:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV122:%.*]] = zext i8 [[TMP52]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END125:%.*]]
|
|
// SIMD-ONLY0: cond.false123:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV124:%.*]] = zext i8 [[TMP53]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END125]]
|
|
// SIMD-ONLY0: cond.end125:
|
|
// SIMD-ONLY0-NEXT: [[COND126:%.*]] = phi i32 [ [[CONV122]], [[COND_TRUE121]] ], [ [[CONV124]], [[COND_FALSE123]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV127:%.*]] = trunc i32 [[COND126]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV127]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV128:%.*]] = zext i8 [[TMP54]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV129:%.*]] = zext i8 [[TMP55]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP130:%.*]] = icmp slt i32 [[CONV128]], [[CONV129]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP130]], label [[COND_TRUE132:%.*]], label [[COND_FALSE134:%.*]]
|
|
// SIMD-ONLY0: cond.true132:
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV133:%.*]] = zext i8 [[TMP56]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END136:%.*]]
|
|
// SIMD-ONLY0: cond.false134:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV135:%.*]] = zext i8 [[TMP57]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END136]]
|
|
// SIMD-ONLY0: cond.end136:
|
|
// SIMD-ONLY0-NEXT: [[COND137:%.*]] = phi i32 [ [[CONV133]], [[COND_TRUE132]] ], [ [[CONV135]], [[COND_FALSE134]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV138:%.*]] = trunc i32 [[COND137]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV138]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV139:%.*]] = zext i8 [[TMP58]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV140:%.*]] = zext i8 [[TMP59]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = icmp sgt i32 [[CONV139]], [[CONV140]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[IF_THEN143:%.*]], label [[IF_END144:%.*]]
|
|
// SIMD-ONLY0: if.then143:
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP60]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END144]]
|
|
// SIMD-ONLY0: if.end144:
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV145:%.*]] = zext i8 [[TMP61]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV146:%.*]] = zext i8 [[TMP62]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP147:%.*]] = icmp slt i32 [[CONV145]], [[CONV146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP147]], label [[IF_THEN149:%.*]], label [[IF_END150:%.*]]
|
|
// SIMD-ONLY0: if.then149:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP63]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END150]]
|
|
// SIMD-ONLY0: if.end150:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV151:%.*]] = zext i8 [[TMP64]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV152:%.*]] = zext i8 [[TMP65]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP153:%.*]] = icmp sgt i32 [[CONV151]], [[CONV152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP153]], label [[IF_THEN155:%.*]], label [[IF_END156:%.*]]
|
|
// SIMD-ONLY0: if.then155:
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP66]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END156]]
|
|
// SIMD-ONLY0: if.end156:
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV157:%.*]] = zext i8 [[TMP67]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV158:%.*]] = zext i8 [[TMP68]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP159:%.*]] = icmp slt i32 [[CONV157]], [[CONV158]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP159]], label [[IF_THEN161:%.*]], label [[IF_END162:%.*]]
|
|
// SIMD-ONLY0: if.then161:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP69]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END162]]
|
|
// SIMD-ONLY0: if.end162:
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV163:%.*]] = zext i8 [[TMP70]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV164:%.*]] = zext i8 [[TMP71]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP165:%.*]] = icmp eq i32 [[CONV163]], [[CONV164]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP165]], label [[COND_TRUE167:%.*]], label [[COND_FALSE169:%.*]]
|
|
// SIMD-ONLY0: cond.true167:
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV168:%.*]] = zext i8 [[TMP72]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END171:%.*]]
|
|
// SIMD-ONLY0: cond.false169:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV170:%.*]] = zext i8 [[TMP73]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END171]]
|
|
// SIMD-ONLY0: cond.end171:
|
|
// SIMD-ONLY0-NEXT: [[COND172:%.*]] = phi i32 [ [[CONV168]], [[COND_TRUE167]] ], [ [[CONV170]], [[COND_FALSE169]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV173:%.*]] = trunc i32 [[COND172]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV173]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV174:%.*]] = zext i8 [[TMP74]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV175:%.*]] = zext i8 [[TMP75]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP176:%.*]] = icmp eq i32 [[CONV174]], [[CONV175]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP176]], label [[COND_TRUE178:%.*]], label [[COND_FALSE180:%.*]]
|
|
// SIMD-ONLY0: cond.true178:
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV179:%.*]] = zext i8 [[TMP76]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END182:%.*]]
|
|
// SIMD-ONLY0: cond.false180:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV181:%.*]] = zext i8 [[TMP77]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END182]]
|
|
// SIMD-ONLY0: cond.end182:
|
|
// SIMD-ONLY0-NEXT: [[COND183:%.*]] = phi i32 [ [[CONV179]], [[COND_TRUE178]] ], [ [[CONV181]], [[COND_FALSE180]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV184:%.*]] = trunc i32 [[COND183]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV184]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV185:%.*]] = zext i8 [[TMP78]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV186:%.*]] = zext i8 [[TMP79]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP187:%.*]] = icmp eq i32 [[CONV185]], [[CONV186]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP187]], label [[IF_THEN189:%.*]], label [[IF_END190:%.*]]
|
|
// SIMD-ONLY0: if.then189:
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP80]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END190]]
|
|
// SIMD-ONLY0: if.end190:
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV191:%.*]] = zext i8 [[TMP81]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV192:%.*]] = zext i8 [[TMP82]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP193:%.*]] = icmp eq i32 [[CONV191]], [[CONV192]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP193]], label [[IF_THEN195:%.*]], label [[IF_END196:%.*]]
|
|
// SIMD-ONLY0: if.then195:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP83]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END196]]
|
|
// SIMD-ONLY0: if.end196:
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV197:%.*]] = sext i8 [[TMP84]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV198:%.*]] = sext i8 [[TMP85]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP199:%.*]] = icmp sgt i32 [[CONV197]], [[CONV198]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP199]], label [[COND_TRUE201:%.*]], label [[COND_FALSE203:%.*]]
|
|
// SIMD-ONLY0: cond.true201:
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV202:%.*]] = sext i8 [[TMP86]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END205:%.*]]
|
|
// SIMD-ONLY0: cond.false203:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV204:%.*]] = sext i8 [[TMP87]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END205]]
|
|
// SIMD-ONLY0: cond.end205:
|
|
// SIMD-ONLY0-NEXT: [[COND206:%.*]] = phi i32 [ [[CONV202]], [[COND_TRUE201]] ], [ [[CONV204]], [[COND_FALSE203]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV207:%.*]] = trunc i32 [[COND206]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV207]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV208:%.*]] = sext i8 [[TMP88]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV209:%.*]] = sext i8 [[TMP89]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP210:%.*]] = icmp slt i32 [[CONV208]], [[CONV209]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP210]], label [[COND_TRUE212:%.*]], label [[COND_FALSE214:%.*]]
|
|
// SIMD-ONLY0: cond.true212:
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV213:%.*]] = sext i8 [[TMP90]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END216:%.*]]
|
|
// SIMD-ONLY0: cond.false214:
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV215:%.*]] = sext i8 [[TMP91]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END216]]
|
|
// SIMD-ONLY0: cond.end216:
|
|
// SIMD-ONLY0-NEXT: [[COND217:%.*]] = phi i32 [ [[CONV213]], [[COND_TRUE212]] ], [ [[CONV215]], [[COND_FALSE214]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV218:%.*]] = trunc i32 [[COND217]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV218]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV219:%.*]] = sext i8 [[TMP92]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV220:%.*]] = sext i8 [[TMP93]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP221:%.*]] = icmp sgt i32 [[CONV219]], [[CONV220]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP221]], label [[COND_TRUE223:%.*]], label [[COND_FALSE225:%.*]]
|
|
// SIMD-ONLY0: cond.true223:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV224:%.*]] = sext i8 [[TMP94]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END227:%.*]]
|
|
// SIMD-ONLY0: cond.false225:
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV226:%.*]] = sext i8 [[TMP95]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END227]]
|
|
// SIMD-ONLY0: cond.end227:
|
|
// SIMD-ONLY0-NEXT: [[COND228:%.*]] = phi i32 [ [[CONV224]], [[COND_TRUE223]] ], [ [[CONV226]], [[COND_FALSE225]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV229:%.*]] = trunc i32 [[COND228]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV229]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV230:%.*]] = sext i8 [[TMP96]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV231:%.*]] = sext i8 [[TMP97]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP232:%.*]] = icmp slt i32 [[CONV230]], [[CONV231]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP232]], label [[COND_TRUE234:%.*]], label [[COND_FALSE236:%.*]]
|
|
// SIMD-ONLY0: cond.true234:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV235:%.*]] = sext i8 [[TMP98]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END238:%.*]]
|
|
// SIMD-ONLY0: cond.false236:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV237:%.*]] = sext i8 [[TMP99]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END238]]
|
|
// SIMD-ONLY0: cond.end238:
|
|
// SIMD-ONLY0-NEXT: [[COND239:%.*]] = phi i32 [ [[CONV235]], [[COND_TRUE234]] ], [ [[CONV237]], [[COND_FALSE236]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV240:%.*]] = trunc i32 [[COND239]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV240]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV241:%.*]] = sext i8 [[TMP100]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV242:%.*]] = sext i8 [[TMP101]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP243:%.*]] = icmp sgt i32 [[CONV241]], [[CONV242]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP243]], label [[IF_THEN245:%.*]], label [[IF_END246:%.*]]
|
|
// SIMD-ONLY0: if.then245:
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP102]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END246]]
|
|
// SIMD-ONLY0: if.end246:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV247:%.*]] = sext i8 [[TMP103]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV248:%.*]] = sext i8 [[TMP104]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP249:%.*]] = icmp slt i32 [[CONV247]], [[CONV248]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP249]], label [[IF_THEN251:%.*]], label [[IF_END252:%.*]]
|
|
// SIMD-ONLY0: if.then251:
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP105]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END252]]
|
|
// SIMD-ONLY0: if.end252:
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV253:%.*]] = sext i8 [[TMP106]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV254:%.*]] = sext i8 [[TMP107]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP255:%.*]] = icmp sgt i32 [[CONV253]], [[CONV254]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP255]], label [[IF_THEN257:%.*]], label [[IF_END258:%.*]]
|
|
// SIMD-ONLY0: if.then257:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP108]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END258]]
|
|
// SIMD-ONLY0: if.end258:
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV259:%.*]] = sext i8 [[TMP109]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV260:%.*]] = sext i8 [[TMP110]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP261:%.*]] = icmp slt i32 [[CONV259]], [[CONV260]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP261]], label [[IF_THEN263:%.*]], label [[IF_END264:%.*]]
|
|
// SIMD-ONLY0: if.then263:
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP111]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END264]]
|
|
// SIMD-ONLY0: if.end264:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV265:%.*]] = sext i8 [[TMP112]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV266:%.*]] = sext i8 [[TMP113]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP267:%.*]] = icmp eq i32 [[CONV265]], [[CONV266]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP267]], label [[COND_TRUE269:%.*]], label [[COND_FALSE271:%.*]]
|
|
// SIMD-ONLY0: cond.true269:
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV270:%.*]] = sext i8 [[TMP114]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END273:%.*]]
|
|
// SIMD-ONLY0: cond.false271:
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV272:%.*]] = sext i8 [[TMP115]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END273]]
|
|
// SIMD-ONLY0: cond.end273:
|
|
// SIMD-ONLY0-NEXT: [[COND274:%.*]] = phi i32 [ [[CONV270]], [[COND_TRUE269]] ], [ [[CONV272]], [[COND_FALSE271]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV275:%.*]] = trunc i32 [[COND274]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV275]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV276:%.*]] = sext i8 [[TMP116]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV277:%.*]] = sext i8 [[TMP117]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP278:%.*]] = icmp eq i32 [[CONV276]], [[CONV277]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP278]], label [[COND_TRUE280:%.*]], label [[COND_FALSE282:%.*]]
|
|
// SIMD-ONLY0: cond.true280:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV281:%.*]] = sext i8 [[TMP118]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END284:%.*]]
|
|
// SIMD-ONLY0: cond.false282:
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV283:%.*]] = sext i8 [[TMP119]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END284]]
|
|
// SIMD-ONLY0: cond.end284:
|
|
// SIMD-ONLY0-NEXT: [[COND285:%.*]] = phi i32 [ [[CONV281]], [[COND_TRUE280]] ], [ [[CONV283]], [[COND_FALSE282]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV286:%.*]] = trunc i32 [[COND285]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV286]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV287:%.*]] = sext i8 [[TMP120]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV288:%.*]] = sext i8 [[TMP121]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP289:%.*]] = icmp eq i32 [[CONV287]], [[CONV288]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP289]], label [[IF_THEN291:%.*]], label [[IF_END292:%.*]]
|
|
// SIMD-ONLY0: if.then291:
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP122]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END292]]
|
|
// SIMD-ONLY0: if.end292:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV293:%.*]] = sext i8 [[TMP123]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV294:%.*]] = sext i8 [[TMP124]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP295:%.*]] = icmp eq i32 [[CONV293]], [[CONV294]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP295]], label [[IF_THEN297:%.*]], label [[IF_END298:%.*]]
|
|
// SIMD-ONLY0: if.then297:
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP125]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END298]]
|
|
// SIMD-ONLY0: if.end298:
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV299:%.*]] = zext i8 [[TMP126]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV300:%.*]] = zext i8 [[TMP127]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP301:%.*]] = icmp sgt i32 [[CONV299]], [[CONV300]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP301]], label [[COND_TRUE303:%.*]], label [[COND_FALSE305:%.*]]
|
|
// SIMD-ONLY0: cond.true303:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV304:%.*]] = zext i8 [[TMP128]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END307:%.*]]
|
|
// SIMD-ONLY0: cond.false305:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV306:%.*]] = zext i8 [[TMP129]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END307]]
|
|
// SIMD-ONLY0: cond.end307:
|
|
// SIMD-ONLY0-NEXT: [[COND308:%.*]] = phi i32 [ [[CONV304]], [[COND_TRUE303]] ], [ [[CONV306]], [[COND_FALSE305]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV309:%.*]] = trunc i32 [[COND308]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV309]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV310:%.*]] = zext i8 [[TMP130]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV311:%.*]] = zext i8 [[TMP131]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP312:%.*]] = icmp slt i32 [[CONV310]], [[CONV311]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP312]], label [[COND_TRUE314:%.*]], label [[COND_FALSE316:%.*]]
|
|
// SIMD-ONLY0: cond.true314:
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV315:%.*]] = zext i8 [[TMP132]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END318:%.*]]
|
|
// SIMD-ONLY0: cond.false316:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV317:%.*]] = zext i8 [[TMP133]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END318]]
|
|
// SIMD-ONLY0: cond.end318:
|
|
// SIMD-ONLY0-NEXT: [[COND319:%.*]] = phi i32 [ [[CONV315]], [[COND_TRUE314]] ], [ [[CONV317]], [[COND_FALSE316]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV320:%.*]] = trunc i32 [[COND319]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV320]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV321:%.*]] = zext i8 [[TMP134]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV322:%.*]] = zext i8 [[TMP135]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP323:%.*]] = icmp sgt i32 [[CONV321]], [[CONV322]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP323]], label [[COND_TRUE325:%.*]], label [[COND_FALSE327:%.*]]
|
|
// SIMD-ONLY0: cond.true325:
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV326:%.*]] = zext i8 [[TMP136]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END329:%.*]]
|
|
// SIMD-ONLY0: cond.false327:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV328:%.*]] = zext i8 [[TMP137]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END329]]
|
|
// SIMD-ONLY0: cond.end329:
|
|
// SIMD-ONLY0-NEXT: [[COND330:%.*]] = phi i32 [ [[CONV326]], [[COND_TRUE325]] ], [ [[CONV328]], [[COND_FALSE327]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV331:%.*]] = trunc i32 [[COND330]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV331]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV332:%.*]] = zext i8 [[TMP138]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV333:%.*]] = zext i8 [[TMP139]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP334:%.*]] = icmp slt i32 [[CONV332]], [[CONV333]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP334]], label [[COND_TRUE336:%.*]], label [[COND_FALSE338:%.*]]
|
|
// SIMD-ONLY0: cond.true336:
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV337:%.*]] = zext i8 [[TMP140]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END340:%.*]]
|
|
// SIMD-ONLY0: cond.false338:
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV339:%.*]] = zext i8 [[TMP141]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END340]]
|
|
// SIMD-ONLY0: cond.end340:
|
|
// SIMD-ONLY0-NEXT: [[COND341:%.*]] = phi i32 [ [[CONV337]], [[COND_TRUE336]] ], [ [[CONV339]], [[COND_FALSE338]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV342:%.*]] = trunc i32 [[COND341]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV342]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV343:%.*]] = zext i8 [[TMP142]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV344:%.*]] = zext i8 [[TMP143]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP345:%.*]] = icmp sgt i32 [[CONV343]], [[CONV344]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP345]], label [[IF_THEN347:%.*]], label [[IF_END348:%.*]]
|
|
// SIMD-ONLY0: if.then347:
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP144]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END348]]
|
|
// SIMD-ONLY0: if.end348:
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV349:%.*]] = zext i8 [[TMP145]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV350:%.*]] = zext i8 [[TMP146]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP351:%.*]] = icmp slt i32 [[CONV349]], [[CONV350]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP351]], label [[IF_THEN353:%.*]], label [[IF_END354:%.*]]
|
|
// SIMD-ONLY0: if.then353:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP147]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END354]]
|
|
// SIMD-ONLY0: if.end354:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV355:%.*]] = zext i8 [[TMP148]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV356:%.*]] = zext i8 [[TMP149]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP357:%.*]] = icmp sgt i32 [[CONV355]], [[CONV356]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP357]], label [[IF_THEN359:%.*]], label [[IF_END360:%.*]]
|
|
// SIMD-ONLY0: if.then359:
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP150]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END360]]
|
|
// SIMD-ONLY0: if.end360:
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV361:%.*]] = zext i8 [[TMP151]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV362:%.*]] = zext i8 [[TMP152]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP363:%.*]] = icmp slt i32 [[CONV361]], [[CONV362]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP363]], label [[IF_THEN365:%.*]], label [[IF_END366:%.*]]
|
|
// SIMD-ONLY0: if.then365:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP153]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END366]]
|
|
// SIMD-ONLY0: if.end366:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV367:%.*]] = zext i8 [[TMP154]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV368:%.*]] = zext i8 [[TMP155]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP369:%.*]] = icmp eq i32 [[CONV367]], [[CONV368]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP369]], label [[COND_TRUE371:%.*]], label [[COND_FALSE373:%.*]]
|
|
// SIMD-ONLY0: cond.true371:
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV372:%.*]] = zext i8 [[TMP156]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END375:%.*]]
|
|
// SIMD-ONLY0: cond.false373:
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV374:%.*]] = zext i8 [[TMP157]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END375]]
|
|
// SIMD-ONLY0: cond.end375:
|
|
// SIMD-ONLY0-NEXT: [[COND376:%.*]] = phi i32 [ [[CONV372]], [[COND_TRUE371]] ], [ [[CONV374]], [[COND_FALSE373]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV377:%.*]] = trunc i32 [[COND376]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV377]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV378:%.*]] = zext i8 [[TMP158]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV379:%.*]] = zext i8 [[TMP159]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP380:%.*]] = icmp eq i32 [[CONV378]], [[CONV379]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP380]], label [[COND_TRUE382:%.*]], label [[COND_FALSE384:%.*]]
|
|
// SIMD-ONLY0: cond.true382:
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV383:%.*]] = zext i8 [[TMP160]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END386:%.*]]
|
|
// SIMD-ONLY0: cond.false384:
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV385:%.*]] = zext i8 [[TMP161]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END386]]
|
|
// SIMD-ONLY0: cond.end386:
|
|
// SIMD-ONLY0-NEXT: [[COND387:%.*]] = phi i32 [ [[CONV383]], [[COND_TRUE382]] ], [ [[CONV385]], [[COND_FALSE384]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV388:%.*]] = trunc i32 [[COND387]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV388]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV389:%.*]] = zext i8 [[TMP162]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV390:%.*]] = zext i8 [[TMP163]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP391:%.*]] = icmp eq i32 [[CONV389]], [[CONV390]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP391]], label [[IF_THEN393:%.*]], label [[IF_END394:%.*]]
|
|
// SIMD-ONLY0: if.then393:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP164]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END394]]
|
|
// SIMD-ONLY0: if.end394:
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV395:%.*]] = zext i8 [[TMP165]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV396:%.*]] = zext i8 [[TMP166]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP397:%.*]] = icmp eq i32 [[CONV395]], [[CONV396]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP397]], label [[IF_THEN399:%.*]], label [[IF_END400:%.*]]
|
|
// SIMD-ONLY0: if.then399:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP167]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END400]]
|
|
// SIMD-ONLY0: if.end400:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV401:%.*]] = sext i8 [[TMP168]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV402:%.*]] = sext i8 [[TMP169]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP403:%.*]] = icmp sgt i32 [[CONV401]], [[CONV402]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP403]], label [[COND_TRUE405:%.*]], label [[COND_FALSE407:%.*]]
|
|
// SIMD-ONLY0: cond.true405:
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV406:%.*]] = sext i8 [[TMP170]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END409:%.*]]
|
|
// SIMD-ONLY0: cond.false407:
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV408:%.*]] = sext i8 [[TMP171]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END409]]
|
|
// SIMD-ONLY0: cond.end409:
|
|
// SIMD-ONLY0-NEXT: [[COND410:%.*]] = phi i32 [ [[CONV406]], [[COND_TRUE405]] ], [ [[CONV408]], [[COND_FALSE407]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV411:%.*]] = trunc i32 [[COND410]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV411]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV412:%.*]] = sext i8 [[TMP172]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV413:%.*]] = sext i8 [[TMP173]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP414:%.*]] = icmp slt i32 [[CONV412]], [[CONV413]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP414]], label [[COND_TRUE416:%.*]], label [[COND_FALSE418:%.*]]
|
|
// SIMD-ONLY0: cond.true416:
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV417:%.*]] = sext i8 [[TMP174]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END420:%.*]]
|
|
// SIMD-ONLY0: cond.false418:
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV419:%.*]] = sext i8 [[TMP175]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END420]]
|
|
// SIMD-ONLY0: cond.end420:
|
|
// SIMD-ONLY0-NEXT: [[COND421:%.*]] = phi i32 [ [[CONV417]], [[COND_TRUE416]] ], [ [[CONV419]], [[COND_FALSE418]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV422:%.*]] = trunc i32 [[COND421]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV422]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV423:%.*]] = sext i8 [[TMP176]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV424:%.*]] = sext i8 [[TMP177]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP425:%.*]] = icmp sgt i32 [[CONV423]], [[CONV424]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP425]], label [[COND_TRUE427:%.*]], label [[COND_FALSE429:%.*]]
|
|
// SIMD-ONLY0: cond.true427:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV428:%.*]] = sext i8 [[TMP178]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END431:%.*]]
|
|
// SIMD-ONLY0: cond.false429:
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV430:%.*]] = sext i8 [[TMP179]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END431]]
|
|
// SIMD-ONLY0: cond.end431:
|
|
// SIMD-ONLY0-NEXT: [[COND432:%.*]] = phi i32 [ [[CONV428]], [[COND_TRUE427]] ], [ [[CONV430]], [[COND_FALSE429]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV433:%.*]] = trunc i32 [[COND432]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV433]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV434:%.*]] = sext i8 [[TMP180]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP181:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV435:%.*]] = sext i8 [[TMP181]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP436:%.*]] = icmp slt i32 [[CONV434]], [[CONV435]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP436]], label [[COND_TRUE438:%.*]], label [[COND_FALSE440:%.*]]
|
|
// SIMD-ONLY0: cond.true438:
|
|
// SIMD-ONLY0-NEXT: [[TMP182:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV439:%.*]] = sext i8 [[TMP182]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END442:%.*]]
|
|
// SIMD-ONLY0: cond.false440:
|
|
// SIMD-ONLY0-NEXT: [[TMP183:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV441:%.*]] = sext i8 [[TMP183]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END442]]
|
|
// SIMD-ONLY0: cond.end442:
|
|
// SIMD-ONLY0-NEXT: [[COND443:%.*]] = phi i32 [ [[CONV439]], [[COND_TRUE438]] ], [ [[CONV441]], [[COND_FALSE440]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV444:%.*]] = trunc i32 [[COND443]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV444]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP184:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV445:%.*]] = sext i8 [[TMP184]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP185:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV446:%.*]] = sext i8 [[TMP185]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP447:%.*]] = icmp sgt i32 [[CONV445]], [[CONV446]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP447]], label [[IF_THEN449:%.*]], label [[IF_END450:%.*]]
|
|
// SIMD-ONLY0: if.then449:
|
|
// SIMD-ONLY0-NEXT: [[TMP186:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP186]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END450]]
|
|
// SIMD-ONLY0: if.end450:
|
|
// SIMD-ONLY0-NEXT: [[TMP187:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV451:%.*]] = sext i8 [[TMP187]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP188:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV452:%.*]] = sext i8 [[TMP188]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP453:%.*]] = icmp slt i32 [[CONV451]], [[CONV452]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP453]], label [[IF_THEN455:%.*]], label [[IF_END456:%.*]]
|
|
// SIMD-ONLY0: if.then455:
|
|
// SIMD-ONLY0-NEXT: [[TMP189:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP189]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END456]]
|
|
// SIMD-ONLY0: if.end456:
|
|
// SIMD-ONLY0-NEXT: [[TMP190:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV457:%.*]] = sext i8 [[TMP190]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP191:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV458:%.*]] = sext i8 [[TMP191]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP459:%.*]] = icmp sgt i32 [[CONV457]], [[CONV458]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP459]], label [[IF_THEN461:%.*]], label [[IF_END462:%.*]]
|
|
// SIMD-ONLY0: if.then461:
|
|
// SIMD-ONLY0-NEXT: [[TMP192:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP192]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END462]]
|
|
// SIMD-ONLY0: if.end462:
|
|
// SIMD-ONLY0-NEXT: [[TMP193:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV463:%.*]] = sext i8 [[TMP193]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP194:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV464:%.*]] = sext i8 [[TMP194]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP465:%.*]] = icmp slt i32 [[CONV463]], [[CONV464]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP465]], label [[IF_THEN467:%.*]], label [[IF_END468:%.*]]
|
|
// SIMD-ONLY0: if.then467:
|
|
// SIMD-ONLY0-NEXT: [[TMP195:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP195]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END468]]
|
|
// SIMD-ONLY0: if.end468:
|
|
// SIMD-ONLY0-NEXT: [[TMP196:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV469:%.*]] = sext i8 [[TMP196]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP197:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV470:%.*]] = sext i8 [[TMP197]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP471:%.*]] = icmp eq i32 [[CONV469]], [[CONV470]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP471]], label [[COND_TRUE473:%.*]], label [[COND_FALSE475:%.*]]
|
|
// SIMD-ONLY0: cond.true473:
|
|
// SIMD-ONLY0-NEXT: [[TMP198:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV474:%.*]] = sext i8 [[TMP198]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END477:%.*]]
|
|
// SIMD-ONLY0: cond.false475:
|
|
// SIMD-ONLY0-NEXT: [[TMP199:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV476:%.*]] = sext i8 [[TMP199]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END477]]
|
|
// SIMD-ONLY0: cond.end477:
|
|
// SIMD-ONLY0-NEXT: [[COND478:%.*]] = phi i32 [ [[CONV474]], [[COND_TRUE473]] ], [ [[CONV476]], [[COND_FALSE475]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV479:%.*]] = trunc i32 [[COND478]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV479]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP200:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV480:%.*]] = sext i8 [[TMP200]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP201:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV481:%.*]] = sext i8 [[TMP201]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP482:%.*]] = icmp eq i32 [[CONV480]], [[CONV481]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP482]], label [[COND_TRUE484:%.*]], label [[COND_FALSE486:%.*]]
|
|
// SIMD-ONLY0: cond.true484:
|
|
// SIMD-ONLY0-NEXT: [[TMP202:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV485:%.*]] = sext i8 [[TMP202]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END488:%.*]]
|
|
// SIMD-ONLY0: cond.false486:
|
|
// SIMD-ONLY0-NEXT: [[TMP203:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV487:%.*]] = sext i8 [[TMP203]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END488]]
|
|
// SIMD-ONLY0: cond.end488:
|
|
// SIMD-ONLY0-NEXT: [[COND489:%.*]] = phi i32 [ [[CONV485]], [[COND_TRUE484]] ], [ [[CONV487]], [[COND_FALSE486]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV490:%.*]] = trunc i32 [[COND489]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV490]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP204:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV491:%.*]] = sext i8 [[TMP204]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP205:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV492:%.*]] = sext i8 [[TMP205]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP493:%.*]] = icmp eq i32 [[CONV491]], [[CONV492]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP493]], label [[IF_THEN495:%.*]], label [[IF_END496:%.*]]
|
|
// SIMD-ONLY0: if.then495:
|
|
// SIMD-ONLY0-NEXT: [[TMP206:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP206]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END496]]
|
|
// SIMD-ONLY0: if.end496:
|
|
// SIMD-ONLY0-NEXT: [[TMP207:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV497:%.*]] = sext i8 [[TMP207]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP208:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV498:%.*]] = sext i8 [[TMP208]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP499:%.*]] = icmp eq i32 [[CONV497]], [[CONV498]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP499]], label [[IF_THEN501:%.*]], label [[IF_END502:%.*]]
|
|
// SIMD-ONLY0: if.then501:
|
|
// SIMD-ONLY0-NEXT: [[TMP209:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP209]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END502]]
|
|
// SIMD-ONLY0: if.end502:
|
|
// SIMD-ONLY0-NEXT: [[TMP210:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV503:%.*]] = zext i8 [[TMP210]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP211:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV504:%.*]] = zext i8 [[TMP211]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP505:%.*]] = icmp sgt i32 [[CONV503]], [[CONV504]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP505]], label [[COND_TRUE507:%.*]], label [[COND_FALSE509:%.*]]
|
|
// SIMD-ONLY0: cond.true507:
|
|
// SIMD-ONLY0-NEXT: [[TMP212:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV508:%.*]] = zext i8 [[TMP212]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END511:%.*]]
|
|
// SIMD-ONLY0: cond.false509:
|
|
// SIMD-ONLY0-NEXT: [[TMP213:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV510:%.*]] = zext i8 [[TMP213]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END511]]
|
|
// SIMD-ONLY0: cond.end511:
|
|
// SIMD-ONLY0-NEXT: [[COND512:%.*]] = phi i32 [ [[CONV508]], [[COND_TRUE507]] ], [ [[CONV510]], [[COND_FALSE509]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV513:%.*]] = trunc i32 [[COND512]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV513]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP214:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV514:%.*]] = zext i8 [[TMP214]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP215:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV515:%.*]] = zext i8 [[TMP215]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP516:%.*]] = icmp slt i32 [[CONV514]], [[CONV515]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP516]], label [[COND_TRUE518:%.*]], label [[COND_FALSE520:%.*]]
|
|
// SIMD-ONLY0: cond.true518:
|
|
// SIMD-ONLY0-NEXT: [[TMP216:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV519:%.*]] = zext i8 [[TMP216]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END522:%.*]]
|
|
// SIMD-ONLY0: cond.false520:
|
|
// SIMD-ONLY0-NEXT: [[TMP217:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV521:%.*]] = zext i8 [[TMP217]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END522]]
|
|
// SIMD-ONLY0: cond.end522:
|
|
// SIMD-ONLY0-NEXT: [[COND523:%.*]] = phi i32 [ [[CONV519]], [[COND_TRUE518]] ], [ [[CONV521]], [[COND_FALSE520]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV524:%.*]] = trunc i32 [[COND523]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV524]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP218:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV525:%.*]] = zext i8 [[TMP218]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP219:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV526:%.*]] = zext i8 [[TMP219]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP527:%.*]] = icmp sgt i32 [[CONV525]], [[CONV526]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP527]], label [[COND_TRUE529:%.*]], label [[COND_FALSE531:%.*]]
|
|
// SIMD-ONLY0: cond.true529:
|
|
// SIMD-ONLY0-NEXT: [[TMP220:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV530:%.*]] = zext i8 [[TMP220]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END533:%.*]]
|
|
// SIMD-ONLY0: cond.false531:
|
|
// SIMD-ONLY0-NEXT: [[TMP221:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV532:%.*]] = zext i8 [[TMP221]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END533]]
|
|
// SIMD-ONLY0: cond.end533:
|
|
// SIMD-ONLY0-NEXT: [[COND534:%.*]] = phi i32 [ [[CONV530]], [[COND_TRUE529]] ], [ [[CONV532]], [[COND_FALSE531]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV535:%.*]] = trunc i32 [[COND534]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV535]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP222:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV536:%.*]] = zext i8 [[TMP222]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP223:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV537:%.*]] = zext i8 [[TMP223]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP538:%.*]] = icmp slt i32 [[CONV536]], [[CONV537]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP538]], label [[COND_TRUE540:%.*]], label [[COND_FALSE542:%.*]]
|
|
// SIMD-ONLY0: cond.true540:
|
|
// SIMD-ONLY0-NEXT: [[TMP224:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV541:%.*]] = zext i8 [[TMP224]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END544:%.*]]
|
|
// SIMD-ONLY0: cond.false542:
|
|
// SIMD-ONLY0-NEXT: [[TMP225:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV543:%.*]] = zext i8 [[TMP225]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END544]]
|
|
// SIMD-ONLY0: cond.end544:
|
|
// SIMD-ONLY0-NEXT: [[COND545:%.*]] = phi i32 [ [[CONV541]], [[COND_TRUE540]] ], [ [[CONV543]], [[COND_FALSE542]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV546:%.*]] = trunc i32 [[COND545]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV546]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP226:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV547:%.*]] = zext i8 [[TMP226]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP227:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV548:%.*]] = zext i8 [[TMP227]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP549:%.*]] = icmp sgt i32 [[CONV547]], [[CONV548]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP549]], label [[IF_THEN551:%.*]], label [[IF_END552:%.*]]
|
|
// SIMD-ONLY0: if.then551:
|
|
// SIMD-ONLY0-NEXT: [[TMP228:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP228]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END552]]
|
|
// SIMD-ONLY0: if.end552:
|
|
// SIMD-ONLY0-NEXT: [[TMP229:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV553:%.*]] = zext i8 [[TMP229]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP230:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV554:%.*]] = zext i8 [[TMP230]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP555:%.*]] = icmp slt i32 [[CONV553]], [[CONV554]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP555]], label [[IF_THEN557:%.*]], label [[IF_END558:%.*]]
|
|
// SIMD-ONLY0: if.then557:
|
|
// SIMD-ONLY0-NEXT: [[TMP231:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP231]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END558]]
|
|
// SIMD-ONLY0: if.end558:
|
|
// SIMD-ONLY0-NEXT: [[TMP232:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV559:%.*]] = zext i8 [[TMP232]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP233:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV560:%.*]] = zext i8 [[TMP233]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP561:%.*]] = icmp sgt i32 [[CONV559]], [[CONV560]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP561]], label [[IF_THEN563:%.*]], label [[IF_END564:%.*]]
|
|
// SIMD-ONLY0: if.then563:
|
|
// SIMD-ONLY0-NEXT: [[TMP234:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP234]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END564]]
|
|
// SIMD-ONLY0: if.end564:
|
|
// SIMD-ONLY0-NEXT: [[TMP235:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV565:%.*]] = zext i8 [[TMP235]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP236:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV566:%.*]] = zext i8 [[TMP236]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP567:%.*]] = icmp slt i32 [[CONV565]], [[CONV566]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP567]], label [[IF_THEN569:%.*]], label [[IF_END570:%.*]]
|
|
// SIMD-ONLY0: if.then569:
|
|
// SIMD-ONLY0-NEXT: [[TMP237:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP237]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END570]]
|
|
// SIMD-ONLY0: if.end570:
|
|
// SIMD-ONLY0-NEXT: [[TMP238:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV571:%.*]] = zext i8 [[TMP238]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP239:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV572:%.*]] = zext i8 [[TMP239]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP573:%.*]] = icmp eq i32 [[CONV571]], [[CONV572]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP573]], label [[COND_TRUE575:%.*]], label [[COND_FALSE577:%.*]]
|
|
// SIMD-ONLY0: cond.true575:
|
|
// SIMD-ONLY0-NEXT: [[TMP240:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV576:%.*]] = zext i8 [[TMP240]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END579:%.*]]
|
|
// SIMD-ONLY0: cond.false577:
|
|
// SIMD-ONLY0-NEXT: [[TMP241:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV578:%.*]] = zext i8 [[TMP241]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END579]]
|
|
// SIMD-ONLY0: cond.end579:
|
|
// SIMD-ONLY0-NEXT: [[COND580:%.*]] = phi i32 [ [[CONV576]], [[COND_TRUE575]] ], [ [[CONV578]], [[COND_FALSE577]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV581:%.*]] = trunc i32 [[COND580]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV581]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP242:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV582:%.*]] = zext i8 [[TMP242]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP243:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV583:%.*]] = zext i8 [[TMP243]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP584:%.*]] = icmp eq i32 [[CONV582]], [[CONV583]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP584]], label [[COND_TRUE586:%.*]], label [[COND_FALSE588:%.*]]
|
|
// SIMD-ONLY0: cond.true586:
|
|
// SIMD-ONLY0-NEXT: [[TMP244:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV587:%.*]] = zext i8 [[TMP244]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END590:%.*]]
|
|
// SIMD-ONLY0: cond.false588:
|
|
// SIMD-ONLY0-NEXT: [[TMP245:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV589:%.*]] = zext i8 [[TMP245]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END590]]
|
|
// SIMD-ONLY0: cond.end590:
|
|
// SIMD-ONLY0-NEXT: [[COND591:%.*]] = phi i32 [ [[CONV587]], [[COND_TRUE586]] ], [ [[CONV589]], [[COND_FALSE588]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV592:%.*]] = trunc i32 [[COND591]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV592]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP246:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV593:%.*]] = zext i8 [[TMP246]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP247:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV594:%.*]] = zext i8 [[TMP247]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP595:%.*]] = icmp eq i32 [[CONV593]], [[CONV594]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP595]], label [[IF_THEN597:%.*]], label [[IF_END598:%.*]]
|
|
// SIMD-ONLY0: if.then597:
|
|
// SIMD-ONLY0-NEXT: [[TMP248:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP248]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END598]]
|
|
// SIMD-ONLY0: if.end598:
|
|
// SIMD-ONLY0-NEXT: [[TMP249:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV599:%.*]] = zext i8 [[TMP249]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP250:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV600:%.*]] = zext i8 [[TMP250]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP601:%.*]] = icmp eq i32 [[CONV599]], [[CONV600]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP601]], label [[IF_THEN603:%.*]], label [[IF_END604:%.*]]
|
|
// SIMD-ONLY0: if.then603:
|
|
// SIMD-ONLY0-NEXT: [[TMP251:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP251]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END604]]
|
|
// SIMD-ONLY0: if.end604:
|
|
// SIMD-ONLY0-NEXT: [[TMP252:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV605:%.*]] = sext i8 [[TMP252]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP253:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV606:%.*]] = sext i8 [[TMP253]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP607:%.*]] = icmp sgt i32 [[CONV605]], [[CONV606]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP607]], label [[COND_TRUE609:%.*]], label [[COND_FALSE611:%.*]]
|
|
// SIMD-ONLY0: cond.true609:
|
|
// SIMD-ONLY0-NEXT: [[TMP254:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV610:%.*]] = sext i8 [[TMP254]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END613:%.*]]
|
|
// SIMD-ONLY0: cond.false611:
|
|
// SIMD-ONLY0-NEXT: [[TMP255:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV612:%.*]] = sext i8 [[TMP255]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END613]]
|
|
// SIMD-ONLY0: cond.end613:
|
|
// SIMD-ONLY0-NEXT: [[COND614:%.*]] = phi i32 [ [[CONV610]], [[COND_TRUE609]] ], [ [[CONV612]], [[COND_FALSE611]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV615:%.*]] = trunc i32 [[COND614]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV615]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP256:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV616:%.*]] = sext i8 [[TMP256]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP257:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV617:%.*]] = sext i8 [[TMP257]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP618:%.*]] = icmp slt i32 [[CONV616]], [[CONV617]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP618]], label [[COND_TRUE620:%.*]], label [[COND_FALSE622:%.*]]
|
|
// SIMD-ONLY0: cond.true620:
|
|
// SIMD-ONLY0-NEXT: [[TMP258:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV621:%.*]] = sext i8 [[TMP258]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END624:%.*]]
|
|
// SIMD-ONLY0: cond.false622:
|
|
// SIMD-ONLY0-NEXT: [[TMP259:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV623:%.*]] = sext i8 [[TMP259]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END624]]
|
|
// SIMD-ONLY0: cond.end624:
|
|
// SIMD-ONLY0-NEXT: [[COND625:%.*]] = phi i32 [ [[CONV621]], [[COND_TRUE620]] ], [ [[CONV623]], [[COND_FALSE622]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV626:%.*]] = trunc i32 [[COND625]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV626]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP260:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV627:%.*]] = sext i8 [[TMP260]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP261:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV628:%.*]] = sext i8 [[TMP261]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP629:%.*]] = icmp sgt i32 [[CONV627]], [[CONV628]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP629]], label [[COND_TRUE631:%.*]], label [[COND_FALSE633:%.*]]
|
|
// SIMD-ONLY0: cond.true631:
|
|
// SIMD-ONLY0-NEXT: [[TMP262:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV632:%.*]] = sext i8 [[TMP262]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END635:%.*]]
|
|
// SIMD-ONLY0: cond.false633:
|
|
// SIMD-ONLY0-NEXT: [[TMP263:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV634:%.*]] = sext i8 [[TMP263]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END635]]
|
|
// SIMD-ONLY0: cond.end635:
|
|
// SIMD-ONLY0-NEXT: [[COND636:%.*]] = phi i32 [ [[CONV632]], [[COND_TRUE631]] ], [ [[CONV634]], [[COND_FALSE633]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV637:%.*]] = trunc i32 [[COND636]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV637]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP264:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV638:%.*]] = sext i8 [[TMP264]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP265:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV639:%.*]] = sext i8 [[TMP265]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP640:%.*]] = icmp slt i32 [[CONV638]], [[CONV639]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP640]], label [[COND_TRUE642:%.*]], label [[COND_FALSE644:%.*]]
|
|
// SIMD-ONLY0: cond.true642:
|
|
// SIMD-ONLY0-NEXT: [[TMP266:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV643:%.*]] = sext i8 [[TMP266]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END646:%.*]]
|
|
// SIMD-ONLY0: cond.false644:
|
|
// SIMD-ONLY0-NEXT: [[TMP267:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV645:%.*]] = sext i8 [[TMP267]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END646]]
|
|
// SIMD-ONLY0: cond.end646:
|
|
// SIMD-ONLY0-NEXT: [[COND647:%.*]] = phi i32 [ [[CONV643]], [[COND_TRUE642]] ], [ [[CONV645]], [[COND_FALSE644]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV648:%.*]] = trunc i32 [[COND647]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV648]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP268:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV649:%.*]] = sext i8 [[TMP268]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP269:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV650:%.*]] = sext i8 [[TMP269]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP651:%.*]] = icmp sgt i32 [[CONV649]], [[CONV650]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP651]], label [[IF_THEN653:%.*]], label [[IF_END654:%.*]]
|
|
// SIMD-ONLY0: if.then653:
|
|
// SIMD-ONLY0-NEXT: [[TMP270:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP270]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END654]]
|
|
// SIMD-ONLY0: if.end654:
|
|
// SIMD-ONLY0-NEXT: [[TMP271:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV655:%.*]] = sext i8 [[TMP271]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP272:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV656:%.*]] = sext i8 [[TMP272]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP657:%.*]] = icmp slt i32 [[CONV655]], [[CONV656]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP657]], label [[IF_THEN659:%.*]], label [[IF_END660:%.*]]
|
|
// SIMD-ONLY0: if.then659:
|
|
// SIMD-ONLY0-NEXT: [[TMP273:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP273]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END660]]
|
|
// SIMD-ONLY0: if.end660:
|
|
// SIMD-ONLY0-NEXT: [[TMP274:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV661:%.*]] = sext i8 [[TMP274]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP275:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV662:%.*]] = sext i8 [[TMP275]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP663:%.*]] = icmp sgt i32 [[CONV661]], [[CONV662]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP663]], label [[IF_THEN665:%.*]], label [[IF_END666:%.*]]
|
|
// SIMD-ONLY0: if.then665:
|
|
// SIMD-ONLY0-NEXT: [[TMP276:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP276]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END666]]
|
|
// SIMD-ONLY0: if.end666:
|
|
// SIMD-ONLY0-NEXT: [[TMP277:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV667:%.*]] = sext i8 [[TMP277]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP278:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV668:%.*]] = sext i8 [[TMP278]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP669:%.*]] = icmp slt i32 [[CONV667]], [[CONV668]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP669]], label [[IF_THEN671:%.*]], label [[IF_END672:%.*]]
|
|
// SIMD-ONLY0: if.then671:
|
|
// SIMD-ONLY0-NEXT: [[TMP279:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP279]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END672]]
|
|
// SIMD-ONLY0: if.end672:
|
|
// SIMD-ONLY0-NEXT: [[TMP280:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV673:%.*]] = sext i8 [[TMP280]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP281:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV674:%.*]] = sext i8 [[TMP281]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP675:%.*]] = icmp eq i32 [[CONV673]], [[CONV674]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP675]], label [[COND_TRUE677:%.*]], label [[COND_FALSE679:%.*]]
|
|
// SIMD-ONLY0: cond.true677:
|
|
// SIMD-ONLY0-NEXT: [[TMP282:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV678:%.*]] = sext i8 [[TMP282]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END681:%.*]]
|
|
// SIMD-ONLY0: cond.false679:
|
|
// SIMD-ONLY0-NEXT: [[TMP283:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV680:%.*]] = sext i8 [[TMP283]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END681]]
|
|
// SIMD-ONLY0: cond.end681:
|
|
// SIMD-ONLY0-NEXT: [[COND682:%.*]] = phi i32 [ [[CONV678]], [[COND_TRUE677]] ], [ [[CONV680]], [[COND_FALSE679]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV683:%.*]] = trunc i32 [[COND682]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV683]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP284:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV684:%.*]] = sext i8 [[TMP284]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP285:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV685:%.*]] = sext i8 [[TMP285]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP686:%.*]] = icmp eq i32 [[CONV684]], [[CONV685]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP686]], label [[COND_TRUE688:%.*]], label [[COND_FALSE690:%.*]]
|
|
// SIMD-ONLY0: cond.true688:
|
|
// SIMD-ONLY0-NEXT: [[TMP286:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV689:%.*]] = sext i8 [[TMP286]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END692:%.*]]
|
|
// SIMD-ONLY0: cond.false690:
|
|
// SIMD-ONLY0-NEXT: [[TMP287:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV691:%.*]] = sext i8 [[TMP287]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END692]]
|
|
// SIMD-ONLY0: cond.end692:
|
|
// SIMD-ONLY0-NEXT: [[COND693:%.*]] = phi i32 [ [[CONV689]], [[COND_TRUE688]] ], [ [[CONV691]], [[COND_FALSE690]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV694:%.*]] = trunc i32 [[COND693]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV694]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP288:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV695:%.*]] = sext i8 [[TMP288]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP289:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV696:%.*]] = sext i8 [[TMP289]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP697:%.*]] = icmp eq i32 [[CONV695]], [[CONV696]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP697]], label [[IF_THEN699:%.*]], label [[IF_END700:%.*]]
|
|
// SIMD-ONLY0: if.then699:
|
|
// SIMD-ONLY0-NEXT: [[TMP290:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP290]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END700]]
|
|
// SIMD-ONLY0: if.end700:
|
|
// SIMD-ONLY0-NEXT: [[TMP291:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV701:%.*]] = sext i8 [[TMP291]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP292:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV702:%.*]] = sext i8 [[TMP292]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP703:%.*]] = icmp eq i32 [[CONV701]], [[CONV702]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP703]], label [[IF_THEN705:%.*]], label [[IF_END706:%.*]]
|
|
// SIMD-ONLY0: if.then705:
|
|
// SIMD-ONLY0-NEXT: [[TMP293:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP293]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END706]]
|
|
// SIMD-ONLY0: if.end706:
|
|
// SIMD-ONLY0-NEXT: [[TMP294:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV707:%.*]] = zext i8 [[TMP294]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP295:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV708:%.*]] = zext i8 [[TMP295]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP709:%.*]] = icmp sgt i32 [[CONV707]], [[CONV708]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP709]], label [[COND_TRUE711:%.*]], label [[COND_FALSE713:%.*]]
|
|
// SIMD-ONLY0: cond.true711:
|
|
// SIMD-ONLY0-NEXT: [[TMP296:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV712:%.*]] = zext i8 [[TMP296]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END715:%.*]]
|
|
// SIMD-ONLY0: cond.false713:
|
|
// SIMD-ONLY0-NEXT: [[TMP297:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV714:%.*]] = zext i8 [[TMP297]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END715]]
|
|
// SIMD-ONLY0: cond.end715:
|
|
// SIMD-ONLY0-NEXT: [[COND716:%.*]] = phi i32 [ [[CONV712]], [[COND_TRUE711]] ], [ [[CONV714]], [[COND_FALSE713]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV717:%.*]] = trunc i32 [[COND716]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV717]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP298:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV718:%.*]] = zext i8 [[TMP298]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP299:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV719:%.*]] = zext i8 [[TMP299]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP720:%.*]] = icmp slt i32 [[CONV718]], [[CONV719]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP720]], label [[COND_TRUE722:%.*]], label [[COND_FALSE724:%.*]]
|
|
// SIMD-ONLY0: cond.true722:
|
|
// SIMD-ONLY0-NEXT: [[TMP300:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV723:%.*]] = zext i8 [[TMP300]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END726:%.*]]
|
|
// SIMD-ONLY0: cond.false724:
|
|
// SIMD-ONLY0-NEXT: [[TMP301:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV725:%.*]] = zext i8 [[TMP301]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END726]]
|
|
// SIMD-ONLY0: cond.end726:
|
|
// SIMD-ONLY0-NEXT: [[COND727:%.*]] = phi i32 [ [[CONV723]], [[COND_TRUE722]] ], [ [[CONV725]], [[COND_FALSE724]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV728:%.*]] = trunc i32 [[COND727]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV728]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP302:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV729:%.*]] = zext i8 [[TMP302]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP303:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV730:%.*]] = zext i8 [[TMP303]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP731:%.*]] = icmp sgt i32 [[CONV729]], [[CONV730]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP731]], label [[COND_TRUE733:%.*]], label [[COND_FALSE735:%.*]]
|
|
// SIMD-ONLY0: cond.true733:
|
|
// SIMD-ONLY0-NEXT: [[TMP304:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV734:%.*]] = zext i8 [[TMP304]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END737:%.*]]
|
|
// SIMD-ONLY0: cond.false735:
|
|
// SIMD-ONLY0-NEXT: [[TMP305:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV736:%.*]] = zext i8 [[TMP305]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END737]]
|
|
// SIMD-ONLY0: cond.end737:
|
|
// SIMD-ONLY0-NEXT: [[COND738:%.*]] = phi i32 [ [[CONV734]], [[COND_TRUE733]] ], [ [[CONV736]], [[COND_FALSE735]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV739:%.*]] = trunc i32 [[COND738]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV739]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP306:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV740:%.*]] = zext i8 [[TMP306]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP307:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV741:%.*]] = zext i8 [[TMP307]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP742:%.*]] = icmp slt i32 [[CONV740]], [[CONV741]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP742]], label [[COND_TRUE744:%.*]], label [[COND_FALSE746:%.*]]
|
|
// SIMD-ONLY0: cond.true744:
|
|
// SIMD-ONLY0-NEXT: [[TMP308:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV745:%.*]] = zext i8 [[TMP308]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END748:%.*]]
|
|
// SIMD-ONLY0: cond.false746:
|
|
// SIMD-ONLY0-NEXT: [[TMP309:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV747:%.*]] = zext i8 [[TMP309]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END748]]
|
|
// SIMD-ONLY0: cond.end748:
|
|
// SIMD-ONLY0-NEXT: [[COND749:%.*]] = phi i32 [ [[CONV745]], [[COND_TRUE744]] ], [ [[CONV747]], [[COND_FALSE746]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV750:%.*]] = trunc i32 [[COND749]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV750]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP310:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV751:%.*]] = zext i8 [[TMP310]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP311:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV752:%.*]] = zext i8 [[TMP311]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP753:%.*]] = icmp sgt i32 [[CONV751]], [[CONV752]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP753]], label [[IF_THEN755:%.*]], label [[IF_END756:%.*]]
|
|
// SIMD-ONLY0: if.then755:
|
|
// SIMD-ONLY0-NEXT: [[TMP312:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP312]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END756]]
|
|
// SIMD-ONLY0: if.end756:
|
|
// SIMD-ONLY0-NEXT: [[TMP313:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV757:%.*]] = zext i8 [[TMP313]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP314:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV758:%.*]] = zext i8 [[TMP314]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP759:%.*]] = icmp slt i32 [[CONV757]], [[CONV758]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP759]], label [[IF_THEN761:%.*]], label [[IF_END762:%.*]]
|
|
// SIMD-ONLY0: if.then761:
|
|
// SIMD-ONLY0-NEXT: [[TMP315:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP315]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END762]]
|
|
// SIMD-ONLY0: if.end762:
|
|
// SIMD-ONLY0-NEXT: [[TMP316:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV763:%.*]] = zext i8 [[TMP316]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP317:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV764:%.*]] = zext i8 [[TMP317]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP765:%.*]] = icmp sgt i32 [[CONV763]], [[CONV764]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP765]], label [[IF_THEN767:%.*]], label [[IF_END768:%.*]]
|
|
// SIMD-ONLY0: if.then767:
|
|
// SIMD-ONLY0-NEXT: [[TMP318:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP318]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END768]]
|
|
// SIMD-ONLY0: if.end768:
|
|
// SIMD-ONLY0-NEXT: [[TMP319:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV769:%.*]] = zext i8 [[TMP319]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP320:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV770:%.*]] = zext i8 [[TMP320]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP771:%.*]] = icmp slt i32 [[CONV769]], [[CONV770]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP771]], label [[IF_THEN773:%.*]], label [[IF_END774:%.*]]
|
|
// SIMD-ONLY0: if.then773:
|
|
// SIMD-ONLY0-NEXT: [[TMP321:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP321]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END774]]
|
|
// SIMD-ONLY0: if.end774:
|
|
// SIMD-ONLY0-NEXT: [[TMP322:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV775:%.*]] = zext i8 [[TMP322]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP323:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV776:%.*]] = zext i8 [[TMP323]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP777:%.*]] = icmp eq i32 [[CONV775]], [[CONV776]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP777]], label [[COND_TRUE779:%.*]], label [[COND_FALSE781:%.*]]
|
|
// SIMD-ONLY0: cond.true779:
|
|
// SIMD-ONLY0-NEXT: [[TMP324:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV780:%.*]] = zext i8 [[TMP324]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END783:%.*]]
|
|
// SIMD-ONLY0: cond.false781:
|
|
// SIMD-ONLY0-NEXT: [[TMP325:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV782:%.*]] = zext i8 [[TMP325]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END783]]
|
|
// SIMD-ONLY0: cond.end783:
|
|
// SIMD-ONLY0-NEXT: [[COND784:%.*]] = phi i32 [ [[CONV780]], [[COND_TRUE779]] ], [ [[CONV782]], [[COND_FALSE781]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV785:%.*]] = trunc i32 [[COND784]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV785]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP326:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV786:%.*]] = zext i8 [[TMP326]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP327:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV787:%.*]] = zext i8 [[TMP327]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP788:%.*]] = icmp eq i32 [[CONV786]], [[CONV787]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP788]], label [[COND_TRUE790:%.*]], label [[COND_FALSE792:%.*]]
|
|
// SIMD-ONLY0: cond.true790:
|
|
// SIMD-ONLY0-NEXT: [[TMP328:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV791:%.*]] = zext i8 [[TMP328]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END794:%.*]]
|
|
// SIMD-ONLY0: cond.false792:
|
|
// SIMD-ONLY0-NEXT: [[TMP329:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV793:%.*]] = zext i8 [[TMP329]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END794]]
|
|
// SIMD-ONLY0: cond.end794:
|
|
// SIMD-ONLY0-NEXT: [[COND795:%.*]] = phi i32 [ [[CONV791]], [[COND_TRUE790]] ], [ [[CONV793]], [[COND_FALSE792]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV796:%.*]] = trunc i32 [[COND795]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV796]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP330:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV797:%.*]] = zext i8 [[TMP330]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP331:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV798:%.*]] = zext i8 [[TMP331]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP799:%.*]] = icmp eq i32 [[CONV797]], [[CONV798]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP799]], label [[IF_THEN801:%.*]], label [[IF_END802:%.*]]
|
|
// SIMD-ONLY0: if.then801:
|
|
// SIMD-ONLY0-NEXT: [[TMP332:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP332]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END802]]
|
|
// SIMD-ONLY0: if.end802:
|
|
// SIMD-ONLY0-NEXT: [[TMP333:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV803:%.*]] = zext i8 [[TMP333]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP334:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV804:%.*]] = zext i8 [[TMP334]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP805:%.*]] = icmp eq i32 [[CONV803]], [[CONV804]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP805]], label [[IF_THEN807:%.*]], label [[IF_END808:%.*]]
|
|
// SIMD-ONLY0: if.then807:
|
|
// SIMD-ONLY0-NEXT: [[TMP335:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP335]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END808]]
|
|
// SIMD-ONLY0: if.end808:
|
|
// SIMD-ONLY0-NEXT: [[TMP336:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV809:%.*]] = sext i8 [[TMP336]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP337:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV810:%.*]] = sext i8 [[TMP337]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP811:%.*]] = icmp sgt i32 [[CONV809]], [[CONV810]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP811]], label [[COND_TRUE813:%.*]], label [[COND_FALSE815:%.*]]
|
|
// SIMD-ONLY0: cond.true813:
|
|
// SIMD-ONLY0-NEXT: [[TMP338:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV814:%.*]] = sext i8 [[TMP338]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END817:%.*]]
|
|
// SIMD-ONLY0: cond.false815:
|
|
// SIMD-ONLY0-NEXT: [[TMP339:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV816:%.*]] = sext i8 [[TMP339]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END817]]
|
|
// SIMD-ONLY0: cond.end817:
|
|
// SIMD-ONLY0-NEXT: [[COND818:%.*]] = phi i32 [ [[CONV814]], [[COND_TRUE813]] ], [ [[CONV816]], [[COND_FALSE815]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV819:%.*]] = trunc i32 [[COND818]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV819]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP340:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV820:%.*]] = sext i8 [[TMP340]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP341:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV821:%.*]] = sext i8 [[TMP341]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP822:%.*]] = icmp slt i32 [[CONV820]], [[CONV821]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP822]], label [[COND_TRUE824:%.*]], label [[COND_FALSE826:%.*]]
|
|
// SIMD-ONLY0: cond.true824:
|
|
// SIMD-ONLY0-NEXT: [[TMP342:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV825:%.*]] = sext i8 [[TMP342]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END828:%.*]]
|
|
// SIMD-ONLY0: cond.false826:
|
|
// SIMD-ONLY0-NEXT: [[TMP343:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV827:%.*]] = sext i8 [[TMP343]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END828]]
|
|
// SIMD-ONLY0: cond.end828:
|
|
// SIMD-ONLY0-NEXT: [[COND829:%.*]] = phi i32 [ [[CONV825]], [[COND_TRUE824]] ], [ [[CONV827]], [[COND_FALSE826]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV830:%.*]] = trunc i32 [[COND829]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV830]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP344:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV831:%.*]] = sext i8 [[TMP344]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP345:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV832:%.*]] = sext i8 [[TMP345]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP833:%.*]] = icmp sgt i32 [[CONV831]], [[CONV832]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP833]], label [[COND_TRUE835:%.*]], label [[COND_FALSE837:%.*]]
|
|
// SIMD-ONLY0: cond.true835:
|
|
// SIMD-ONLY0-NEXT: [[TMP346:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV836:%.*]] = sext i8 [[TMP346]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END839:%.*]]
|
|
// SIMD-ONLY0: cond.false837:
|
|
// SIMD-ONLY0-NEXT: [[TMP347:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV838:%.*]] = sext i8 [[TMP347]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END839]]
|
|
// SIMD-ONLY0: cond.end839:
|
|
// SIMD-ONLY0-NEXT: [[COND840:%.*]] = phi i32 [ [[CONV836]], [[COND_TRUE835]] ], [ [[CONV838]], [[COND_FALSE837]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV841:%.*]] = trunc i32 [[COND840]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV841]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP348:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV842:%.*]] = sext i8 [[TMP348]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP349:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV843:%.*]] = sext i8 [[TMP349]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP844:%.*]] = icmp slt i32 [[CONV842]], [[CONV843]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP844]], label [[COND_TRUE846:%.*]], label [[COND_FALSE848:%.*]]
|
|
// SIMD-ONLY0: cond.true846:
|
|
// SIMD-ONLY0-NEXT: [[TMP350:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV847:%.*]] = sext i8 [[TMP350]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END850:%.*]]
|
|
// SIMD-ONLY0: cond.false848:
|
|
// SIMD-ONLY0-NEXT: [[TMP351:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV849:%.*]] = sext i8 [[TMP351]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END850]]
|
|
// SIMD-ONLY0: cond.end850:
|
|
// SIMD-ONLY0-NEXT: [[COND851:%.*]] = phi i32 [ [[CONV847]], [[COND_TRUE846]] ], [ [[CONV849]], [[COND_FALSE848]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV852:%.*]] = trunc i32 [[COND851]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV852]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP352:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV853:%.*]] = sext i8 [[TMP352]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP353:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV854:%.*]] = sext i8 [[TMP353]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP855:%.*]] = icmp sgt i32 [[CONV853]], [[CONV854]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP855]], label [[IF_THEN857:%.*]], label [[IF_END858:%.*]]
|
|
// SIMD-ONLY0: if.then857:
|
|
// SIMD-ONLY0-NEXT: [[TMP354:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP354]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END858]]
|
|
// SIMD-ONLY0: if.end858:
|
|
// SIMD-ONLY0-NEXT: [[TMP355:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV859:%.*]] = sext i8 [[TMP355]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP356:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV860:%.*]] = sext i8 [[TMP356]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP861:%.*]] = icmp slt i32 [[CONV859]], [[CONV860]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP861]], label [[IF_THEN863:%.*]], label [[IF_END864:%.*]]
|
|
// SIMD-ONLY0: if.then863:
|
|
// SIMD-ONLY0-NEXT: [[TMP357:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP357]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END864]]
|
|
// SIMD-ONLY0: if.end864:
|
|
// SIMD-ONLY0-NEXT: [[TMP358:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV865:%.*]] = sext i8 [[TMP358]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP359:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV866:%.*]] = sext i8 [[TMP359]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP867:%.*]] = icmp sgt i32 [[CONV865]], [[CONV866]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP867]], label [[IF_THEN869:%.*]], label [[IF_END870:%.*]]
|
|
// SIMD-ONLY0: if.then869:
|
|
// SIMD-ONLY0-NEXT: [[TMP360:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP360]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END870]]
|
|
// SIMD-ONLY0: if.end870:
|
|
// SIMD-ONLY0-NEXT: [[TMP361:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV871:%.*]] = sext i8 [[TMP361]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP362:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV872:%.*]] = sext i8 [[TMP362]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP873:%.*]] = icmp slt i32 [[CONV871]], [[CONV872]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP873]], label [[IF_THEN875:%.*]], label [[IF_END876:%.*]]
|
|
// SIMD-ONLY0: if.then875:
|
|
// SIMD-ONLY0-NEXT: [[TMP363:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP363]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END876]]
|
|
// SIMD-ONLY0: if.end876:
|
|
// SIMD-ONLY0-NEXT: [[TMP364:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV877:%.*]] = sext i8 [[TMP364]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP365:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV878:%.*]] = sext i8 [[TMP365]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP879:%.*]] = icmp eq i32 [[CONV877]], [[CONV878]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP879]], label [[COND_TRUE881:%.*]], label [[COND_FALSE883:%.*]]
|
|
// SIMD-ONLY0: cond.true881:
|
|
// SIMD-ONLY0-NEXT: [[TMP366:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV882:%.*]] = sext i8 [[TMP366]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END885:%.*]]
|
|
// SIMD-ONLY0: cond.false883:
|
|
// SIMD-ONLY0-NEXT: [[TMP367:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV884:%.*]] = sext i8 [[TMP367]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END885]]
|
|
// SIMD-ONLY0: cond.end885:
|
|
// SIMD-ONLY0-NEXT: [[COND886:%.*]] = phi i32 [ [[CONV882]], [[COND_TRUE881]] ], [ [[CONV884]], [[COND_FALSE883]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV887:%.*]] = trunc i32 [[COND886]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV887]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP368:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV888:%.*]] = sext i8 [[TMP368]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP369:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV889:%.*]] = sext i8 [[TMP369]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP890:%.*]] = icmp eq i32 [[CONV888]], [[CONV889]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP890]], label [[COND_TRUE892:%.*]], label [[COND_FALSE894:%.*]]
|
|
// SIMD-ONLY0: cond.true892:
|
|
// SIMD-ONLY0-NEXT: [[TMP370:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV893:%.*]] = sext i8 [[TMP370]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END896:%.*]]
|
|
// SIMD-ONLY0: cond.false894:
|
|
// SIMD-ONLY0-NEXT: [[TMP371:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV895:%.*]] = sext i8 [[TMP371]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END896]]
|
|
// SIMD-ONLY0: cond.end896:
|
|
// SIMD-ONLY0-NEXT: [[COND897:%.*]] = phi i32 [ [[CONV893]], [[COND_TRUE892]] ], [ [[CONV895]], [[COND_FALSE894]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV898:%.*]] = trunc i32 [[COND897]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV898]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP372:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV899:%.*]] = sext i8 [[TMP372]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP373:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV900:%.*]] = sext i8 [[TMP373]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP901:%.*]] = icmp eq i32 [[CONV899]], [[CONV900]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP901]], label [[IF_THEN903:%.*]], label [[IF_END904:%.*]]
|
|
// SIMD-ONLY0: if.then903:
|
|
// SIMD-ONLY0-NEXT: [[TMP374:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP374]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END904]]
|
|
// SIMD-ONLY0: if.end904:
|
|
// SIMD-ONLY0-NEXT: [[TMP375:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV905:%.*]] = sext i8 [[TMP375]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP376:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV906:%.*]] = sext i8 [[TMP376]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP907:%.*]] = icmp eq i32 [[CONV905]], [[CONV906]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP907]], label [[IF_THEN909:%.*]], label [[IF_END910:%.*]]
|
|
// SIMD-ONLY0: if.then909:
|
|
// SIMD-ONLY0-NEXT: [[TMP377:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP377]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END910]]
|
|
// SIMD-ONLY0: if.end910:
|
|
// SIMD-ONLY0-NEXT: [[TMP378:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV911:%.*]] = zext i8 [[TMP378]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP379:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV912:%.*]] = zext i8 [[TMP379]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP913:%.*]] = icmp sgt i32 [[CONV911]], [[CONV912]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP913]], label [[COND_TRUE915:%.*]], label [[COND_FALSE917:%.*]]
|
|
// SIMD-ONLY0: cond.true915:
|
|
// SIMD-ONLY0-NEXT: [[TMP380:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV916:%.*]] = zext i8 [[TMP380]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END919:%.*]]
|
|
// SIMD-ONLY0: cond.false917:
|
|
// SIMD-ONLY0-NEXT: [[TMP381:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV918:%.*]] = zext i8 [[TMP381]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END919]]
|
|
// SIMD-ONLY0: cond.end919:
|
|
// SIMD-ONLY0-NEXT: [[COND920:%.*]] = phi i32 [ [[CONV916]], [[COND_TRUE915]] ], [ [[CONV918]], [[COND_FALSE917]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV921:%.*]] = trunc i32 [[COND920]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV921]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP382:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV922:%.*]] = zext i8 [[TMP382]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP383:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV923:%.*]] = zext i8 [[TMP383]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP924:%.*]] = icmp slt i32 [[CONV922]], [[CONV923]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP924]], label [[COND_TRUE926:%.*]], label [[COND_FALSE928:%.*]]
|
|
// SIMD-ONLY0: cond.true926:
|
|
// SIMD-ONLY0-NEXT: [[TMP384:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV927:%.*]] = zext i8 [[TMP384]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END930:%.*]]
|
|
// SIMD-ONLY0: cond.false928:
|
|
// SIMD-ONLY0-NEXT: [[TMP385:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV929:%.*]] = zext i8 [[TMP385]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END930]]
|
|
// SIMD-ONLY0: cond.end930:
|
|
// SIMD-ONLY0-NEXT: [[COND931:%.*]] = phi i32 [ [[CONV927]], [[COND_TRUE926]] ], [ [[CONV929]], [[COND_FALSE928]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV932:%.*]] = trunc i32 [[COND931]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV932]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP386:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV933:%.*]] = zext i8 [[TMP386]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP387:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV934:%.*]] = zext i8 [[TMP387]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP935:%.*]] = icmp sgt i32 [[CONV933]], [[CONV934]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP935]], label [[COND_TRUE937:%.*]], label [[COND_FALSE939:%.*]]
|
|
// SIMD-ONLY0: cond.true937:
|
|
// SIMD-ONLY0-NEXT: [[TMP388:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV938:%.*]] = zext i8 [[TMP388]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END941:%.*]]
|
|
// SIMD-ONLY0: cond.false939:
|
|
// SIMD-ONLY0-NEXT: [[TMP389:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV940:%.*]] = zext i8 [[TMP389]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END941]]
|
|
// SIMD-ONLY0: cond.end941:
|
|
// SIMD-ONLY0-NEXT: [[COND942:%.*]] = phi i32 [ [[CONV938]], [[COND_TRUE937]] ], [ [[CONV940]], [[COND_FALSE939]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV943:%.*]] = trunc i32 [[COND942]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV943]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP390:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV944:%.*]] = zext i8 [[TMP390]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP391:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV945:%.*]] = zext i8 [[TMP391]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP946:%.*]] = icmp slt i32 [[CONV944]], [[CONV945]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP946]], label [[COND_TRUE948:%.*]], label [[COND_FALSE950:%.*]]
|
|
// SIMD-ONLY0: cond.true948:
|
|
// SIMD-ONLY0-NEXT: [[TMP392:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV949:%.*]] = zext i8 [[TMP392]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END952:%.*]]
|
|
// SIMD-ONLY0: cond.false950:
|
|
// SIMD-ONLY0-NEXT: [[TMP393:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV951:%.*]] = zext i8 [[TMP393]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END952]]
|
|
// SIMD-ONLY0: cond.end952:
|
|
// SIMD-ONLY0-NEXT: [[COND953:%.*]] = phi i32 [ [[CONV949]], [[COND_TRUE948]] ], [ [[CONV951]], [[COND_FALSE950]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV954:%.*]] = trunc i32 [[COND953]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV954]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP394:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV955:%.*]] = zext i8 [[TMP394]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP395:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV956:%.*]] = zext i8 [[TMP395]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP957:%.*]] = icmp sgt i32 [[CONV955]], [[CONV956]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP957]], label [[IF_THEN959:%.*]], label [[IF_END960:%.*]]
|
|
// SIMD-ONLY0: if.then959:
|
|
// SIMD-ONLY0-NEXT: [[TMP396:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP396]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END960]]
|
|
// SIMD-ONLY0: if.end960:
|
|
// SIMD-ONLY0-NEXT: [[TMP397:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV961:%.*]] = zext i8 [[TMP397]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP398:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV962:%.*]] = zext i8 [[TMP398]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP963:%.*]] = icmp slt i32 [[CONV961]], [[CONV962]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP963]], label [[IF_THEN965:%.*]], label [[IF_END966:%.*]]
|
|
// SIMD-ONLY0: if.then965:
|
|
// SIMD-ONLY0-NEXT: [[TMP399:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP399]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END966]]
|
|
// SIMD-ONLY0: if.end966:
|
|
// SIMD-ONLY0-NEXT: [[TMP400:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV967:%.*]] = zext i8 [[TMP400]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP401:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV968:%.*]] = zext i8 [[TMP401]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP969:%.*]] = icmp sgt i32 [[CONV967]], [[CONV968]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP969]], label [[IF_THEN971:%.*]], label [[IF_END972:%.*]]
|
|
// SIMD-ONLY0: if.then971:
|
|
// SIMD-ONLY0-NEXT: [[TMP402:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP402]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END972]]
|
|
// SIMD-ONLY0: if.end972:
|
|
// SIMD-ONLY0-NEXT: [[TMP403:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV973:%.*]] = zext i8 [[TMP403]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP404:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV974:%.*]] = zext i8 [[TMP404]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP975:%.*]] = icmp slt i32 [[CONV973]], [[CONV974]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP975]], label [[IF_THEN977:%.*]], label [[IF_END978:%.*]]
|
|
// SIMD-ONLY0: if.then977:
|
|
// SIMD-ONLY0-NEXT: [[TMP405:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP405]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END978]]
|
|
// SIMD-ONLY0: if.end978:
|
|
// SIMD-ONLY0-NEXT: [[TMP406:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV979:%.*]] = zext i8 [[TMP406]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP407:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV980:%.*]] = zext i8 [[TMP407]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP981:%.*]] = icmp eq i32 [[CONV979]], [[CONV980]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP981]], label [[COND_TRUE983:%.*]], label [[COND_FALSE985:%.*]]
|
|
// SIMD-ONLY0: cond.true983:
|
|
// SIMD-ONLY0-NEXT: [[TMP408:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV984:%.*]] = zext i8 [[TMP408]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END987:%.*]]
|
|
// SIMD-ONLY0: cond.false985:
|
|
// SIMD-ONLY0-NEXT: [[TMP409:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV986:%.*]] = zext i8 [[TMP409]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END987]]
|
|
// SIMD-ONLY0: cond.end987:
|
|
// SIMD-ONLY0-NEXT: [[COND988:%.*]] = phi i32 [ [[CONV984]], [[COND_TRUE983]] ], [ [[CONV986]], [[COND_FALSE985]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV989:%.*]] = trunc i32 [[COND988]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV989]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP410:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV990:%.*]] = zext i8 [[TMP410]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP411:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV991:%.*]] = zext i8 [[TMP411]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP992:%.*]] = icmp eq i32 [[CONV990]], [[CONV991]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP992]], label [[COND_TRUE994:%.*]], label [[COND_FALSE996:%.*]]
|
|
// SIMD-ONLY0: cond.true994:
|
|
// SIMD-ONLY0-NEXT: [[TMP412:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV995:%.*]] = zext i8 [[TMP412]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END998:%.*]]
|
|
// SIMD-ONLY0: cond.false996:
|
|
// SIMD-ONLY0-NEXT: [[TMP413:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV997:%.*]] = zext i8 [[TMP413]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END998]]
|
|
// SIMD-ONLY0: cond.end998:
|
|
// SIMD-ONLY0-NEXT: [[COND999:%.*]] = phi i32 [ [[CONV995]], [[COND_TRUE994]] ], [ [[CONV997]], [[COND_FALSE996]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1000:%.*]] = trunc i32 [[COND999]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1000]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP414:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1001:%.*]] = zext i8 [[TMP414]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP415:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1002:%.*]] = zext i8 [[TMP415]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1003:%.*]] = icmp eq i32 [[CONV1001]], [[CONV1002]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1003]], label [[IF_THEN1005:%.*]], label [[IF_END1006:%.*]]
|
|
// SIMD-ONLY0: if.then1005:
|
|
// SIMD-ONLY0-NEXT: [[TMP416:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP416]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1006]]
|
|
// SIMD-ONLY0: if.end1006:
|
|
// SIMD-ONLY0-NEXT: [[TMP417:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1007:%.*]] = zext i8 [[TMP417]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP418:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1008:%.*]] = zext i8 [[TMP418]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1009:%.*]] = icmp eq i32 [[CONV1007]], [[CONV1008]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1009]], label [[IF_THEN1011:%.*]], label [[IF_END1012:%.*]]
|
|
// SIMD-ONLY0: if.then1011:
|
|
// SIMD-ONLY0-NEXT: [[TMP419:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP419]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1012]]
|
|
// SIMD-ONLY0: if.end1012:
|
|
// SIMD-ONLY0-NEXT: [[TMP420:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1013:%.*]] = sext i8 [[TMP420]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP421:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1014:%.*]] = sext i8 [[TMP421]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1015:%.*]] = icmp sgt i32 [[CONV1013]], [[CONV1014]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1015]], label [[COND_TRUE1017:%.*]], label [[COND_FALSE1019:%.*]]
|
|
// SIMD-ONLY0: cond.true1017:
|
|
// SIMD-ONLY0-NEXT: [[TMP422:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1018:%.*]] = sext i8 [[TMP422]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1021:%.*]]
|
|
// SIMD-ONLY0: cond.false1019:
|
|
// SIMD-ONLY0-NEXT: [[TMP423:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1020:%.*]] = sext i8 [[TMP423]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1021]]
|
|
// SIMD-ONLY0: cond.end1021:
|
|
// SIMD-ONLY0-NEXT: [[COND1022:%.*]] = phi i32 [ [[CONV1018]], [[COND_TRUE1017]] ], [ [[CONV1020]], [[COND_FALSE1019]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1023:%.*]] = trunc i32 [[COND1022]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1023]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP424:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1024:%.*]] = sext i8 [[TMP424]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP425:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1025:%.*]] = sext i8 [[TMP425]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1026:%.*]] = icmp slt i32 [[CONV1024]], [[CONV1025]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1026]], label [[COND_TRUE1028:%.*]], label [[COND_FALSE1030:%.*]]
|
|
// SIMD-ONLY0: cond.true1028:
|
|
// SIMD-ONLY0-NEXT: [[TMP426:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1029:%.*]] = sext i8 [[TMP426]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1032:%.*]]
|
|
// SIMD-ONLY0: cond.false1030:
|
|
// SIMD-ONLY0-NEXT: [[TMP427:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1031:%.*]] = sext i8 [[TMP427]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1032]]
|
|
// SIMD-ONLY0: cond.end1032:
|
|
// SIMD-ONLY0-NEXT: [[COND1033:%.*]] = phi i32 [ [[CONV1029]], [[COND_TRUE1028]] ], [ [[CONV1031]], [[COND_FALSE1030]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1034:%.*]] = trunc i32 [[COND1033]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1034]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP428:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1035:%.*]] = sext i8 [[TMP428]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP429:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1036:%.*]] = sext i8 [[TMP429]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1037:%.*]] = icmp sgt i32 [[CONV1035]], [[CONV1036]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1037]], label [[COND_TRUE1039:%.*]], label [[COND_FALSE1041:%.*]]
|
|
// SIMD-ONLY0: cond.true1039:
|
|
// SIMD-ONLY0-NEXT: [[TMP430:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1040:%.*]] = sext i8 [[TMP430]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1043:%.*]]
|
|
// SIMD-ONLY0: cond.false1041:
|
|
// SIMD-ONLY0-NEXT: [[TMP431:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1042:%.*]] = sext i8 [[TMP431]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1043]]
|
|
// SIMD-ONLY0: cond.end1043:
|
|
// SIMD-ONLY0-NEXT: [[COND1044:%.*]] = phi i32 [ [[CONV1040]], [[COND_TRUE1039]] ], [ [[CONV1042]], [[COND_FALSE1041]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1045:%.*]] = trunc i32 [[COND1044]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1045]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP432:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1046:%.*]] = sext i8 [[TMP432]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP433:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1047:%.*]] = sext i8 [[TMP433]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1048:%.*]] = icmp slt i32 [[CONV1046]], [[CONV1047]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1048]], label [[COND_TRUE1050:%.*]], label [[COND_FALSE1052:%.*]]
|
|
// SIMD-ONLY0: cond.true1050:
|
|
// SIMD-ONLY0-NEXT: [[TMP434:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1051:%.*]] = sext i8 [[TMP434]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1054:%.*]]
|
|
// SIMD-ONLY0: cond.false1052:
|
|
// SIMD-ONLY0-NEXT: [[TMP435:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1053:%.*]] = sext i8 [[TMP435]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1054]]
|
|
// SIMD-ONLY0: cond.end1054:
|
|
// SIMD-ONLY0-NEXT: [[COND1055:%.*]] = phi i32 [ [[CONV1051]], [[COND_TRUE1050]] ], [ [[CONV1053]], [[COND_FALSE1052]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1056:%.*]] = trunc i32 [[COND1055]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1056]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP436:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1057:%.*]] = sext i8 [[TMP436]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP437:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1058:%.*]] = sext i8 [[TMP437]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1059:%.*]] = icmp sgt i32 [[CONV1057]], [[CONV1058]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1059]], label [[IF_THEN1061:%.*]], label [[IF_END1062:%.*]]
|
|
// SIMD-ONLY0: if.then1061:
|
|
// SIMD-ONLY0-NEXT: [[TMP438:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP438]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1062]]
|
|
// SIMD-ONLY0: if.end1062:
|
|
// SIMD-ONLY0-NEXT: [[TMP439:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1063:%.*]] = sext i8 [[TMP439]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP440:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1064:%.*]] = sext i8 [[TMP440]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1065:%.*]] = icmp slt i32 [[CONV1063]], [[CONV1064]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1065]], label [[IF_THEN1067:%.*]], label [[IF_END1068:%.*]]
|
|
// SIMD-ONLY0: if.then1067:
|
|
// SIMD-ONLY0-NEXT: [[TMP441:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP441]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1068]]
|
|
// SIMD-ONLY0: if.end1068:
|
|
// SIMD-ONLY0-NEXT: [[TMP442:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1069:%.*]] = sext i8 [[TMP442]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP443:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1070:%.*]] = sext i8 [[TMP443]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1071:%.*]] = icmp sgt i32 [[CONV1069]], [[CONV1070]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1071]], label [[IF_THEN1073:%.*]], label [[IF_END1074:%.*]]
|
|
// SIMD-ONLY0: if.then1073:
|
|
// SIMD-ONLY0-NEXT: [[TMP444:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP444]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1074]]
|
|
// SIMD-ONLY0: if.end1074:
|
|
// SIMD-ONLY0-NEXT: [[TMP445:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1075:%.*]] = sext i8 [[TMP445]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP446:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1076:%.*]] = sext i8 [[TMP446]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1077:%.*]] = icmp slt i32 [[CONV1075]], [[CONV1076]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1077]], label [[IF_THEN1079:%.*]], label [[IF_END1080:%.*]]
|
|
// SIMD-ONLY0: if.then1079:
|
|
// SIMD-ONLY0-NEXT: [[TMP447:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP447]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1080]]
|
|
// SIMD-ONLY0: if.end1080:
|
|
// SIMD-ONLY0-NEXT: [[TMP448:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1081:%.*]] = sext i8 [[TMP448]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP449:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1082:%.*]] = sext i8 [[TMP449]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1083:%.*]] = icmp eq i32 [[CONV1081]], [[CONV1082]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1083]], label [[COND_TRUE1085:%.*]], label [[COND_FALSE1087:%.*]]
|
|
// SIMD-ONLY0: cond.true1085:
|
|
// SIMD-ONLY0-NEXT: [[TMP450:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1086:%.*]] = sext i8 [[TMP450]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1089:%.*]]
|
|
// SIMD-ONLY0: cond.false1087:
|
|
// SIMD-ONLY0-NEXT: [[TMP451:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1088:%.*]] = sext i8 [[TMP451]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1089]]
|
|
// SIMD-ONLY0: cond.end1089:
|
|
// SIMD-ONLY0-NEXT: [[COND1090:%.*]] = phi i32 [ [[CONV1086]], [[COND_TRUE1085]] ], [ [[CONV1088]], [[COND_FALSE1087]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1091:%.*]] = trunc i32 [[COND1090]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1091]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP452:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1092:%.*]] = sext i8 [[TMP452]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP453:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1093:%.*]] = sext i8 [[TMP453]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1094:%.*]] = icmp eq i32 [[CONV1092]], [[CONV1093]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1094]], label [[COND_TRUE1096:%.*]], label [[COND_FALSE1098:%.*]]
|
|
// SIMD-ONLY0: cond.true1096:
|
|
// SIMD-ONLY0-NEXT: [[TMP454:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1097:%.*]] = sext i8 [[TMP454]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1100:%.*]]
|
|
// SIMD-ONLY0: cond.false1098:
|
|
// SIMD-ONLY0-NEXT: [[TMP455:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1099:%.*]] = sext i8 [[TMP455]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1100]]
|
|
// SIMD-ONLY0: cond.end1100:
|
|
// SIMD-ONLY0-NEXT: [[COND1101:%.*]] = phi i32 [ [[CONV1097]], [[COND_TRUE1096]] ], [ [[CONV1099]], [[COND_FALSE1098]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1102:%.*]] = trunc i32 [[COND1101]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1102]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP456:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1103:%.*]] = sext i8 [[TMP456]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP457:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1104:%.*]] = sext i8 [[TMP457]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1105:%.*]] = icmp eq i32 [[CONV1103]], [[CONV1104]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1105]], label [[IF_THEN1107:%.*]], label [[IF_END1108:%.*]]
|
|
// SIMD-ONLY0: if.then1107:
|
|
// SIMD-ONLY0-NEXT: [[TMP458:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP458]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1108]]
|
|
// SIMD-ONLY0: if.end1108:
|
|
// SIMD-ONLY0-NEXT: [[TMP459:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1109:%.*]] = sext i8 [[TMP459]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP460:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1110:%.*]] = sext i8 [[TMP460]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1111:%.*]] = icmp eq i32 [[CONV1109]], [[CONV1110]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1111]], label [[IF_THEN1113:%.*]], label [[IF_END1114:%.*]]
|
|
// SIMD-ONLY0: if.then1113:
|
|
// SIMD-ONLY0-NEXT: [[TMP461:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP461]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1114]]
|
|
// SIMD-ONLY0: if.end1114:
|
|
// SIMD-ONLY0-NEXT: [[TMP462:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1115:%.*]] = zext i8 [[TMP462]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP463:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1116:%.*]] = zext i8 [[TMP463]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1117:%.*]] = icmp sgt i32 [[CONV1115]], [[CONV1116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1117]], label [[COND_TRUE1119:%.*]], label [[COND_FALSE1121:%.*]]
|
|
// SIMD-ONLY0: cond.true1119:
|
|
// SIMD-ONLY0-NEXT: [[TMP464:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1120:%.*]] = zext i8 [[TMP464]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1123:%.*]]
|
|
// SIMD-ONLY0: cond.false1121:
|
|
// SIMD-ONLY0-NEXT: [[TMP465:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1122:%.*]] = zext i8 [[TMP465]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1123]]
|
|
// SIMD-ONLY0: cond.end1123:
|
|
// SIMD-ONLY0-NEXT: [[COND1124:%.*]] = phi i32 [ [[CONV1120]], [[COND_TRUE1119]] ], [ [[CONV1122]], [[COND_FALSE1121]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1125:%.*]] = trunc i32 [[COND1124]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1125]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP466:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1126:%.*]] = zext i8 [[TMP466]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP467:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1127:%.*]] = zext i8 [[TMP467]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1128:%.*]] = icmp slt i32 [[CONV1126]], [[CONV1127]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1128]], label [[COND_TRUE1130:%.*]], label [[COND_FALSE1132:%.*]]
|
|
// SIMD-ONLY0: cond.true1130:
|
|
// SIMD-ONLY0-NEXT: [[TMP468:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1131:%.*]] = zext i8 [[TMP468]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1134:%.*]]
|
|
// SIMD-ONLY0: cond.false1132:
|
|
// SIMD-ONLY0-NEXT: [[TMP469:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1133:%.*]] = zext i8 [[TMP469]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1134]]
|
|
// SIMD-ONLY0: cond.end1134:
|
|
// SIMD-ONLY0-NEXT: [[COND1135:%.*]] = phi i32 [ [[CONV1131]], [[COND_TRUE1130]] ], [ [[CONV1133]], [[COND_FALSE1132]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1136:%.*]] = trunc i32 [[COND1135]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1136]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP470:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1137:%.*]] = zext i8 [[TMP470]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP471:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1138:%.*]] = zext i8 [[TMP471]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1139:%.*]] = icmp sgt i32 [[CONV1137]], [[CONV1138]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1139]], label [[COND_TRUE1141:%.*]], label [[COND_FALSE1143:%.*]]
|
|
// SIMD-ONLY0: cond.true1141:
|
|
// SIMD-ONLY0-NEXT: [[TMP472:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1142:%.*]] = zext i8 [[TMP472]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1145:%.*]]
|
|
// SIMD-ONLY0: cond.false1143:
|
|
// SIMD-ONLY0-NEXT: [[TMP473:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1144:%.*]] = zext i8 [[TMP473]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1145]]
|
|
// SIMD-ONLY0: cond.end1145:
|
|
// SIMD-ONLY0-NEXT: [[COND1146:%.*]] = phi i32 [ [[CONV1142]], [[COND_TRUE1141]] ], [ [[CONV1144]], [[COND_FALSE1143]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1147:%.*]] = trunc i32 [[COND1146]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1147]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP474:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1148:%.*]] = zext i8 [[TMP474]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP475:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1149:%.*]] = zext i8 [[TMP475]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1150:%.*]] = icmp slt i32 [[CONV1148]], [[CONV1149]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1150]], label [[COND_TRUE1152:%.*]], label [[COND_FALSE1154:%.*]]
|
|
// SIMD-ONLY0: cond.true1152:
|
|
// SIMD-ONLY0-NEXT: [[TMP476:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1153:%.*]] = zext i8 [[TMP476]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1156:%.*]]
|
|
// SIMD-ONLY0: cond.false1154:
|
|
// SIMD-ONLY0-NEXT: [[TMP477:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1155:%.*]] = zext i8 [[TMP477]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1156]]
|
|
// SIMD-ONLY0: cond.end1156:
|
|
// SIMD-ONLY0-NEXT: [[COND1157:%.*]] = phi i32 [ [[CONV1153]], [[COND_TRUE1152]] ], [ [[CONV1155]], [[COND_FALSE1154]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1158:%.*]] = trunc i32 [[COND1157]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1158]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP478:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1159:%.*]] = zext i8 [[TMP478]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP479:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1160:%.*]] = zext i8 [[TMP479]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1161:%.*]] = icmp sgt i32 [[CONV1159]], [[CONV1160]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1161]], label [[IF_THEN1163:%.*]], label [[IF_END1164:%.*]]
|
|
// SIMD-ONLY0: if.then1163:
|
|
// SIMD-ONLY0-NEXT: [[TMP480:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP480]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1164]]
|
|
// SIMD-ONLY0: if.end1164:
|
|
// SIMD-ONLY0-NEXT: [[TMP481:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1165:%.*]] = zext i8 [[TMP481]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP482:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1166:%.*]] = zext i8 [[TMP482]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1167:%.*]] = icmp slt i32 [[CONV1165]], [[CONV1166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1167]], label [[IF_THEN1169:%.*]], label [[IF_END1170:%.*]]
|
|
// SIMD-ONLY0: if.then1169:
|
|
// SIMD-ONLY0-NEXT: [[TMP483:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP483]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1170]]
|
|
// SIMD-ONLY0: if.end1170:
|
|
// SIMD-ONLY0-NEXT: [[TMP484:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1171:%.*]] = zext i8 [[TMP484]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP485:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1172:%.*]] = zext i8 [[TMP485]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1173:%.*]] = icmp sgt i32 [[CONV1171]], [[CONV1172]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1173]], label [[IF_THEN1175:%.*]], label [[IF_END1176:%.*]]
|
|
// SIMD-ONLY0: if.then1175:
|
|
// SIMD-ONLY0-NEXT: [[TMP486:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP486]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1176]]
|
|
// SIMD-ONLY0: if.end1176:
|
|
// SIMD-ONLY0-NEXT: [[TMP487:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1177:%.*]] = zext i8 [[TMP487]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP488:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1178:%.*]] = zext i8 [[TMP488]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1179:%.*]] = icmp slt i32 [[CONV1177]], [[CONV1178]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1179]], label [[IF_THEN1181:%.*]], label [[IF_END1182:%.*]]
|
|
// SIMD-ONLY0: if.then1181:
|
|
// SIMD-ONLY0-NEXT: [[TMP489:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP489]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1182]]
|
|
// SIMD-ONLY0: if.end1182:
|
|
// SIMD-ONLY0-NEXT: [[TMP490:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1183:%.*]] = zext i8 [[TMP490]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP491:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1184:%.*]] = zext i8 [[TMP491]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1185:%.*]] = icmp eq i32 [[CONV1183]], [[CONV1184]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1185]], label [[COND_TRUE1187:%.*]], label [[COND_FALSE1189:%.*]]
|
|
// SIMD-ONLY0: cond.true1187:
|
|
// SIMD-ONLY0-NEXT: [[TMP492:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1188:%.*]] = zext i8 [[TMP492]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1191:%.*]]
|
|
// SIMD-ONLY0: cond.false1189:
|
|
// SIMD-ONLY0-NEXT: [[TMP493:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1190:%.*]] = zext i8 [[TMP493]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1191]]
|
|
// SIMD-ONLY0: cond.end1191:
|
|
// SIMD-ONLY0-NEXT: [[COND1192:%.*]] = phi i32 [ [[CONV1188]], [[COND_TRUE1187]] ], [ [[CONV1190]], [[COND_FALSE1189]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1193:%.*]] = trunc i32 [[COND1192]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1193]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP494:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1194:%.*]] = zext i8 [[TMP494]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP495:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1195:%.*]] = zext i8 [[TMP495]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1196:%.*]] = icmp eq i32 [[CONV1194]], [[CONV1195]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1196]], label [[COND_TRUE1198:%.*]], label [[COND_FALSE1200:%.*]]
|
|
// SIMD-ONLY0: cond.true1198:
|
|
// SIMD-ONLY0-NEXT: [[TMP496:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1199:%.*]] = zext i8 [[TMP496]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1202:%.*]]
|
|
// SIMD-ONLY0: cond.false1200:
|
|
// SIMD-ONLY0-NEXT: [[TMP497:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1201:%.*]] = zext i8 [[TMP497]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1202]]
|
|
// SIMD-ONLY0: cond.end1202:
|
|
// SIMD-ONLY0-NEXT: [[COND1203:%.*]] = phi i32 [ [[CONV1199]], [[COND_TRUE1198]] ], [ [[CONV1201]], [[COND_FALSE1200]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1204:%.*]] = trunc i32 [[COND1203]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1204]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP498:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1205:%.*]] = zext i8 [[TMP498]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP499:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1206:%.*]] = zext i8 [[TMP499]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1207:%.*]] = icmp eq i32 [[CONV1205]], [[CONV1206]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1207]], label [[IF_THEN1209:%.*]], label [[IF_END1210:%.*]]
|
|
// SIMD-ONLY0: if.then1209:
|
|
// SIMD-ONLY0-NEXT: [[TMP500:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP500]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1210]]
|
|
// SIMD-ONLY0: if.end1210:
|
|
// SIMD-ONLY0-NEXT: [[TMP501:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1211:%.*]] = zext i8 [[TMP501]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP502:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1212:%.*]] = zext i8 [[TMP502]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1213:%.*]] = icmp eq i32 [[CONV1211]], [[CONV1212]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1213]], label [[IF_THEN1215:%.*]], label [[IF_END1216:%.*]]
|
|
// SIMD-ONLY0: if.then1215:
|
|
// SIMD-ONLY0-NEXT: [[TMP503:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP503]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1216]]
|
|
// SIMD-ONLY0: if.end1216:
|
|
// SIMD-ONLY0-NEXT: [[TMP504:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1217:%.*]] = sext i16 [[TMP504]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP505:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1218:%.*]] = sext i16 [[TMP505]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1219:%.*]] = icmp sgt i32 [[CONV1217]], [[CONV1218]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1219]], label [[COND_TRUE1221:%.*]], label [[COND_FALSE1223:%.*]]
|
|
// SIMD-ONLY0: cond.true1221:
|
|
// SIMD-ONLY0-NEXT: [[TMP506:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1222:%.*]] = sext i16 [[TMP506]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1225:%.*]]
|
|
// SIMD-ONLY0: cond.false1223:
|
|
// SIMD-ONLY0-NEXT: [[TMP507:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1224:%.*]] = sext i16 [[TMP507]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1225]]
|
|
// SIMD-ONLY0: cond.end1225:
|
|
// SIMD-ONLY0-NEXT: [[COND1226:%.*]] = phi i32 [ [[CONV1222]], [[COND_TRUE1221]] ], [ [[CONV1224]], [[COND_FALSE1223]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1227:%.*]] = trunc i32 [[COND1226]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1227]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP508:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1228:%.*]] = sext i16 [[TMP508]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP509:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1229:%.*]] = sext i16 [[TMP509]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1230:%.*]] = icmp slt i32 [[CONV1228]], [[CONV1229]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1230]], label [[COND_TRUE1232:%.*]], label [[COND_FALSE1234:%.*]]
|
|
// SIMD-ONLY0: cond.true1232:
|
|
// SIMD-ONLY0-NEXT: [[TMP510:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1233:%.*]] = sext i16 [[TMP510]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1236:%.*]]
|
|
// SIMD-ONLY0: cond.false1234:
|
|
// SIMD-ONLY0-NEXT: [[TMP511:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1235:%.*]] = sext i16 [[TMP511]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1236]]
|
|
// SIMD-ONLY0: cond.end1236:
|
|
// SIMD-ONLY0-NEXT: [[COND1237:%.*]] = phi i32 [ [[CONV1233]], [[COND_TRUE1232]] ], [ [[CONV1235]], [[COND_FALSE1234]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1238:%.*]] = trunc i32 [[COND1237]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1238]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP512:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1239:%.*]] = sext i16 [[TMP512]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP513:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1240:%.*]] = sext i16 [[TMP513]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1241:%.*]] = icmp sgt i32 [[CONV1239]], [[CONV1240]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1241]], label [[COND_TRUE1243:%.*]], label [[COND_FALSE1245:%.*]]
|
|
// SIMD-ONLY0: cond.true1243:
|
|
// SIMD-ONLY0-NEXT: [[TMP514:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1244:%.*]] = sext i16 [[TMP514]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1247:%.*]]
|
|
// SIMD-ONLY0: cond.false1245:
|
|
// SIMD-ONLY0-NEXT: [[TMP515:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1246:%.*]] = sext i16 [[TMP515]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1247]]
|
|
// SIMD-ONLY0: cond.end1247:
|
|
// SIMD-ONLY0-NEXT: [[COND1248:%.*]] = phi i32 [ [[CONV1244]], [[COND_TRUE1243]] ], [ [[CONV1246]], [[COND_FALSE1245]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1249:%.*]] = trunc i32 [[COND1248]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1249]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP516:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1250:%.*]] = sext i16 [[TMP516]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP517:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1251:%.*]] = sext i16 [[TMP517]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1252:%.*]] = icmp slt i32 [[CONV1250]], [[CONV1251]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1252]], label [[COND_TRUE1254:%.*]], label [[COND_FALSE1256:%.*]]
|
|
// SIMD-ONLY0: cond.true1254:
|
|
// SIMD-ONLY0-NEXT: [[TMP518:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1255:%.*]] = sext i16 [[TMP518]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1258:%.*]]
|
|
// SIMD-ONLY0: cond.false1256:
|
|
// SIMD-ONLY0-NEXT: [[TMP519:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1257:%.*]] = sext i16 [[TMP519]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1258]]
|
|
// SIMD-ONLY0: cond.end1258:
|
|
// SIMD-ONLY0-NEXT: [[COND1259:%.*]] = phi i32 [ [[CONV1255]], [[COND_TRUE1254]] ], [ [[CONV1257]], [[COND_FALSE1256]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1260:%.*]] = trunc i32 [[COND1259]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1260]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP520:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1261:%.*]] = sext i16 [[TMP520]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP521:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1262:%.*]] = sext i16 [[TMP521]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1263:%.*]] = icmp sgt i32 [[CONV1261]], [[CONV1262]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1263]], label [[IF_THEN1265:%.*]], label [[IF_END1266:%.*]]
|
|
// SIMD-ONLY0: if.then1265:
|
|
// SIMD-ONLY0-NEXT: [[TMP522:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP522]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1266]]
|
|
// SIMD-ONLY0: if.end1266:
|
|
// SIMD-ONLY0-NEXT: [[TMP523:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1267:%.*]] = sext i16 [[TMP523]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP524:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1268:%.*]] = sext i16 [[TMP524]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1269:%.*]] = icmp slt i32 [[CONV1267]], [[CONV1268]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1269]], label [[IF_THEN1271:%.*]], label [[IF_END1272:%.*]]
|
|
// SIMD-ONLY0: if.then1271:
|
|
// SIMD-ONLY0-NEXT: [[TMP525:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP525]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1272]]
|
|
// SIMD-ONLY0: if.end1272:
|
|
// SIMD-ONLY0-NEXT: [[TMP526:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1273:%.*]] = sext i16 [[TMP526]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP527:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1274:%.*]] = sext i16 [[TMP527]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1275:%.*]] = icmp sgt i32 [[CONV1273]], [[CONV1274]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1275]], label [[IF_THEN1277:%.*]], label [[IF_END1278:%.*]]
|
|
// SIMD-ONLY0: if.then1277:
|
|
// SIMD-ONLY0-NEXT: [[TMP528:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP528]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1278]]
|
|
// SIMD-ONLY0: if.end1278:
|
|
// SIMD-ONLY0-NEXT: [[TMP529:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1279:%.*]] = sext i16 [[TMP529]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP530:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1280:%.*]] = sext i16 [[TMP530]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1281:%.*]] = icmp slt i32 [[CONV1279]], [[CONV1280]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1281]], label [[IF_THEN1283:%.*]], label [[IF_END1284:%.*]]
|
|
// SIMD-ONLY0: if.then1283:
|
|
// SIMD-ONLY0-NEXT: [[TMP531:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP531]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1284]]
|
|
// SIMD-ONLY0: if.end1284:
|
|
// SIMD-ONLY0-NEXT: [[TMP532:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1285:%.*]] = sext i16 [[TMP532]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP533:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1286:%.*]] = sext i16 [[TMP533]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1287:%.*]] = icmp eq i32 [[CONV1285]], [[CONV1286]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1287]], label [[COND_TRUE1289:%.*]], label [[COND_FALSE1291:%.*]]
|
|
// SIMD-ONLY0: cond.true1289:
|
|
// SIMD-ONLY0-NEXT: [[TMP534:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1290:%.*]] = sext i16 [[TMP534]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1293:%.*]]
|
|
// SIMD-ONLY0: cond.false1291:
|
|
// SIMD-ONLY0-NEXT: [[TMP535:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1292:%.*]] = sext i16 [[TMP535]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1293]]
|
|
// SIMD-ONLY0: cond.end1293:
|
|
// SIMD-ONLY0-NEXT: [[COND1294:%.*]] = phi i32 [ [[CONV1290]], [[COND_TRUE1289]] ], [ [[CONV1292]], [[COND_FALSE1291]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1295:%.*]] = trunc i32 [[COND1294]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1295]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP536:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1296:%.*]] = sext i16 [[TMP536]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP537:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1297:%.*]] = sext i16 [[TMP537]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1298:%.*]] = icmp eq i32 [[CONV1296]], [[CONV1297]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1298]], label [[COND_TRUE1300:%.*]], label [[COND_FALSE1302:%.*]]
|
|
// SIMD-ONLY0: cond.true1300:
|
|
// SIMD-ONLY0-NEXT: [[TMP538:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1301:%.*]] = sext i16 [[TMP538]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1304:%.*]]
|
|
// SIMD-ONLY0: cond.false1302:
|
|
// SIMD-ONLY0-NEXT: [[TMP539:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1303:%.*]] = sext i16 [[TMP539]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1304]]
|
|
// SIMD-ONLY0: cond.end1304:
|
|
// SIMD-ONLY0-NEXT: [[COND1305:%.*]] = phi i32 [ [[CONV1301]], [[COND_TRUE1300]] ], [ [[CONV1303]], [[COND_FALSE1302]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1306:%.*]] = trunc i32 [[COND1305]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1306]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP540:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1307:%.*]] = sext i16 [[TMP540]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP541:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1308:%.*]] = sext i16 [[TMP541]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1309:%.*]] = icmp eq i32 [[CONV1307]], [[CONV1308]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1309]], label [[IF_THEN1311:%.*]], label [[IF_END1312:%.*]]
|
|
// SIMD-ONLY0: if.then1311:
|
|
// SIMD-ONLY0-NEXT: [[TMP542:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP542]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1312]]
|
|
// SIMD-ONLY0: if.end1312:
|
|
// SIMD-ONLY0-NEXT: [[TMP543:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1313:%.*]] = sext i16 [[TMP543]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP544:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1314:%.*]] = sext i16 [[TMP544]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1315:%.*]] = icmp eq i32 [[CONV1313]], [[CONV1314]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1315]], label [[IF_THEN1317:%.*]], label [[IF_END1318:%.*]]
|
|
// SIMD-ONLY0: if.then1317:
|
|
// SIMD-ONLY0-NEXT: [[TMP545:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP545]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1318]]
|
|
// SIMD-ONLY0: if.end1318:
|
|
// SIMD-ONLY0-NEXT: [[TMP546:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1319:%.*]] = zext i16 [[TMP546]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP547:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1320:%.*]] = zext i16 [[TMP547]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1321:%.*]] = icmp sgt i32 [[CONV1319]], [[CONV1320]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1321]], label [[COND_TRUE1323:%.*]], label [[COND_FALSE1325:%.*]]
|
|
// SIMD-ONLY0: cond.true1323:
|
|
// SIMD-ONLY0-NEXT: [[TMP548:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1324:%.*]] = zext i16 [[TMP548]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1327:%.*]]
|
|
// SIMD-ONLY0: cond.false1325:
|
|
// SIMD-ONLY0-NEXT: [[TMP549:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1326:%.*]] = zext i16 [[TMP549]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1327]]
|
|
// SIMD-ONLY0: cond.end1327:
|
|
// SIMD-ONLY0-NEXT: [[COND1328:%.*]] = phi i32 [ [[CONV1324]], [[COND_TRUE1323]] ], [ [[CONV1326]], [[COND_FALSE1325]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1329:%.*]] = trunc i32 [[COND1328]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1329]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP550:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1330:%.*]] = zext i16 [[TMP550]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP551:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1331:%.*]] = zext i16 [[TMP551]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1332:%.*]] = icmp slt i32 [[CONV1330]], [[CONV1331]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1332]], label [[COND_TRUE1334:%.*]], label [[COND_FALSE1336:%.*]]
|
|
// SIMD-ONLY0: cond.true1334:
|
|
// SIMD-ONLY0-NEXT: [[TMP552:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1335:%.*]] = zext i16 [[TMP552]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1338:%.*]]
|
|
// SIMD-ONLY0: cond.false1336:
|
|
// SIMD-ONLY0-NEXT: [[TMP553:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1337:%.*]] = zext i16 [[TMP553]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1338]]
|
|
// SIMD-ONLY0: cond.end1338:
|
|
// SIMD-ONLY0-NEXT: [[COND1339:%.*]] = phi i32 [ [[CONV1335]], [[COND_TRUE1334]] ], [ [[CONV1337]], [[COND_FALSE1336]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1340:%.*]] = trunc i32 [[COND1339]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1340]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP554:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1341:%.*]] = zext i16 [[TMP554]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP555:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1342:%.*]] = zext i16 [[TMP555]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1343:%.*]] = icmp sgt i32 [[CONV1341]], [[CONV1342]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1343]], label [[COND_TRUE1345:%.*]], label [[COND_FALSE1347:%.*]]
|
|
// SIMD-ONLY0: cond.true1345:
|
|
// SIMD-ONLY0-NEXT: [[TMP556:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1346:%.*]] = zext i16 [[TMP556]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1349:%.*]]
|
|
// SIMD-ONLY0: cond.false1347:
|
|
// SIMD-ONLY0-NEXT: [[TMP557:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1348:%.*]] = zext i16 [[TMP557]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1349]]
|
|
// SIMD-ONLY0: cond.end1349:
|
|
// SIMD-ONLY0-NEXT: [[COND1350:%.*]] = phi i32 [ [[CONV1346]], [[COND_TRUE1345]] ], [ [[CONV1348]], [[COND_FALSE1347]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1351:%.*]] = trunc i32 [[COND1350]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1351]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP558:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1352:%.*]] = zext i16 [[TMP558]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP559:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1353:%.*]] = zext i16 [[TMP559]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1354:%.*]] = icmp slt i32 [[CONV1352]], [[CONV1353]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1354]], label [[COND_TRUE1356:%.*]], label [[COND_FALSE1358:%.*]]
|
|
// SIMD-ONLY0: cond.true1356:
|
|
// SIMD-ONLY0-NEXT: [[TMP560:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1357:%.*]] = zext i16 [[TMP560]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1360:%.*]]
|
|
// SIMD-ONLY0: cond.false1358:
|
|
// SIMD-ONLY0-NEXT: [[TMP561:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1359:%.*]] = zext i16 [[TMP561]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1360]]
|
|
// SIMD-ONLY0: cond.end1360:
|
|
// SIMD-ONLY0-NEXT: [[COND1361:%.*]] = phi i32 [ [[CONV1357]], [[COND_TRUE1356]] ], [ [[CONV1359]], [[COND_FALSE1358]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1362:%.*]] = trunc i32 [[COND1361]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1362]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP562:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1363:%.*]] = zext i16 [[TMP562]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP563:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1364:%.*]] = zext i16 [[TMP563]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1365:%.*]] = icmp sgt i32 [[CONV1363]], [[CONV1364]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1365]], label [[IF_THEN1367:%.*]], label [[IF_END1368:%.*]]
|
|
// SIMD-ONLY0: if.then1367:
|
|
// SIMD-ONLY0-NEXT: [[TMP564:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP564]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1368]]
|
|
// SIMD-ONLY0: if.end1368:
|
|
// SIMD-ONLY0-NEXT: [[TMP565:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1369:%.*]] = zext i16 [[TMP565]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP566:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1370:%.*]] = zext i16 [[TMP566]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1371:%.*]] = icmp slt i32 [[CONV1369]], [[CONV1370]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1371]], label [[IF_THEN1373:%.*]], label [[IF_END1374:%.*]]
|
|
// SIMD-ONLY0: if.then1373:
|
|
// SIMD-ONLY0-NEXT: [[TMP567:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP567]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1374]]
|
|
// SIMD-ONLY0: if.end1374:
|
|
// SIMD-ONLY0-NEXT: [[TMP568:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1375:%.*]] = zext i16 [[TMP568]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP569:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1376:%.*]] = zext i16 [[TMP569]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1377:%.*]] = icmp sgt i32 [[CONV1375]], [[CONV1376]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1377]], label [[IF_THEN1379:%.*]], label [[IF_END1380:%.*]]
|
|
// SIMD-ONLY0: if.then1379:
|
|
// SIMD-ONLY0-NEXT: [[TMP570:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP570]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1380]]
|
|
// SIMD-ONLY0: if.end1380:
|
|
// SIMD-ONLY0-NEXT: [[TMP571:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1381:%.*]] = zext i16 [[TMP571]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP572:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1382:%.*]] = zext i16 [[TMP572]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1383:%.*]] = icmp slt i32 [[CONV1381]], [[CONV1382]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1383]], label [[IF_THEN1385:%.*]], label [[IF_END1386:%.*]]
|
|
// SIMD-ONLY0: if.then1385:
|
|
// SIMD-ONLY0-NEXT: [[TMP573:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP573]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1386]]
|
|
// SIMD-ONLY0: if.end1386:
|
|
// SIMD-ONLY0-NEXT: [[TMP574:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1387:%.*]] = zext i16 [[TMP574]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP575:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1388:%.*]] = zext i16 [[TMP575]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1389:%.*]] = icmp eq i32 [[CONV1387]], [[CONV1388]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1389]], label [[COND_TRUE1391:%.*]], label [[COND_FALSE1393:%.*]]
|
|
// SIMD-ONLY0: cond.true1391:
|
|
// SIMD-ONLY0-NEXT: [[TMP576:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1392:%.*]] = zext i16 [[TMP576]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1395:%.*]]
|
|
// SIMD-ONLY0: cond.false1393:
|
|
// SIMD-ONLY0-NEXT: [[TMP577:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1394:%.*]] = zext i16 [[TMP577]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1395]]
|
|
// SIMD-ONLY0: cond.end1395:
|
|
// SIMD-ONLY0-NEXT: [[COND1396:%.*]] = phi i32 [ [[CONV1392]], [[COND_TRUE1391]] ], [ [[CONV1394]], [[COND_FALSE1393]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1397:%.*]] = trunc i32 [[COND1396]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1397]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP578:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1398:%.*]] = zext i16 [[TMP578]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP579:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1399:%.*]] = zext i16 [[TMP579]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1400:%.*]] = icmp eq i32 [[CONV1398]], [[CONV1399]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1400]], label [[COND_TRUE1402:%.*]], label [[COND_FALSE1404:%.*]]
|
|
// SIMD-ONLY0: cond.true1402:
|
|
// SIMD-ONLY0-NEXT: [[TMP580:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1403:%.*]] = zext i16 [[TMP580]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1406:%.*]]
|
|
// SIMD-ONLY0: cond.false1404:
|
|
// SIMD-ONLY0-NEXT: [[TMP581:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1405:%.*]] = zext i16 [[TMP581]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1406]]
|
|
// SIMD-ONLY0: cond.end1406:
|
|
// SIMD-ONLY0-NEXT: [[COND1407:%.*]] = phi i32 [ [[CONV1403]], [[COND_TRUE1402]] ], [ [[CONV1405]], [[COND_FALSE1404]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1408:%.*]] = trunc i32 [[COND1407]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1408]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP582:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1409:%.*]] = zext i16 [[TMP582]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP583:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1410:%.*]] = zext i16 [[TMP583]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1411:%.*]] = icmp eq i32 [[CONV1409]], [[CONV1410]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1411]], label [[IF_THEN1413:%.*]], label [[IF_END1414:%.*]]
|
|
// SIMD-ONLY0: if.then1413:
|
|
// SIMD-ONLY0-NEXT: [[TMP584:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP584]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1414]]
|
|
// SIMD-ONLY0: if.end1414:
|
|
// SIMD-ONLY0-NEXT: [[TMP585:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1415:%.*]] = zext i16 [[TMP585]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP586:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1416:%.*]] = zext i16 [[TMP586]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1417:%.*]] = icmp eq i32 [[CONV1415]], [[CONV1416]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1417]], label [[IF_THEN1419:%.*]], label [[IF_END1420:%.*]]
|
|
// SIMD-ONLY0: if.then1419:
|
|
// SIMD-ONLY0-NEXT: [[TMP587:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP587]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1420]]
|
|
// SIMD-ONLY0: if.end1420:
|
|
// SIMD-ONLY0-NEXT: [[TMP588:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1421:%.*]] = sext i16 [[TMP588]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP589:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1422:%.*]] = sext i16 [[TMP589]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1423:%.*]] = icmp sgt i32 [[CONV1421]], [[CONV1422]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1423]], label [[COND_TRUE1425:%.*]], label [[COND_FALSE1427:%.*]]
|
|
// SIMD-ONLY0: cond.true1425:
|
|
// SIMD-ONLY0-NEXT: [[TMP590:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1426:%.*]] = sext i16 [[TMP590]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1429:%.*]]
|
|
// SIMD-ONLY0: cond.false1427:
|
|
// SIMD-ONLY0-NEXT: [[TMP591:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1428:%.*]] = sext i16 [[TMP591]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1429]]
|
|
// SIMD-ONLY0: cond.end1429:
|
|
// SIMD-ONLY0-NEXT: [[COND1430:%.*]] = phi i32 [ [[CONV1426]], [[COND_TRUE1425]] ], [ [[CONV1428]], [[COND_FALSE1427]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1431:%.*]] = trunc i32 [[COND1430]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1431]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP592:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1432:%.*]] = sext i16 [[TMP592]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP593:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1433:%.*]] = sext i16 [[TMP593]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1434:%.*]] = icmp slt i32 [[CONV1432]], [[CONV1433]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1434]], label [[COND_TRUE1436:%.*]], label [[COND_FALSE1438:%.*]]
|
|
// SIMD-ONLY0: cond.true1436:
|
|
// SIMD-ONLY0-NEXT: [[TMP594:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1437:%.*]] = sext i16 [[TMP594]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1440:%.*]]
|
|
// SIMD-ONLY0: cond.false1438:
|
|
// SIMD-ONLY0-NEXT: [[TMP595:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1439:%.*]] = sext i16 [[TMP595]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1440]]
|
|
// SIMD-ONLY0: cond.end1440:
|
|
// SIMD-ONLY0-NEXT: [[COND1441:%.*]] = phi i32 [ [[CONV1437]], [[COND_TRUE1436]] ], [ [[CONV1439]], [[COND_FALSE1438]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1442:%.*]] = trunc i32 [[COND1441]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1442]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP596:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1443:%.*]] = sext i16 [[TMP596]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP597:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1444:%.*]] = sext i16 [[TMP597]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1445:%.*]] = icmp sgt i32 [[CONV1443]], [[CONV1444]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1445]], label [[COND_TRUE1447:%.*]], label [[COND_FALSE1449:%.*]]
|
|
// SIMD-ONLY0: cond.true1447:
|
|
// SIMD-ONLY0-NEXT: [[TMP598:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1448:%.*]] = sext i16 [[TMP598]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1451:%.*]]
|
|
// SIMD-ONLY0: cond.false1449:
|
|
// SIMD-ONLY0-NEXT: [[TMP599:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1450:%.*]] = sext i16 [[TMP599]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1451]]
|
|
// SIMD-ONLY0: cond.end1451:
|
|
// SIMD-ONLY0-NEXT: [[COND1452:%.*]] = phi i32 [ [[CONV1448]], [[COND_TRUE1447]] ], [ [[CONV1450]], [[COND_FALSE1449]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1453:%.*]] = trunc i32 [[COND1452]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1453]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP600:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1454:%.*]] = sext i16 [[TMP600]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP601:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1455:%.*]] = sext i16 [[TMP601]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1456:%.*]] = icmp slt i32 [[CONV1454]], [[CONV1455]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1456]], label [[COND_TRUE1458:%.*]], label [[COND_FALSE1460:%.*]]
|
|
// SIMD-ONLY0: cond.true1458:
|
|
// SIMD-ONLY0-NEXT: [[TMP602:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1459:%.*]] = sext i16 [[TMP602]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1462:%.*]]
|
|
// SIMD-ONLY0: cond.false1460:
|
|
// SIMD-ONLY0-NEXT: [[TMP603:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1461:%.*]] = sext i16 [[TMP603]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1462]]
|
|
// SIMD-ONLY0: cond.end1462:
|
|
// SIMD-ONLY0-NEXT: [[COND1463:%.*]] = phi i32 [ [[CONV1459]], [[COND_TRUE1458]] ], [ [[CONV1461]], [[COND_FALSE1460]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1464:%.*]] = trunc i32 [[COND1463]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1464]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP604:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1465:%.*]] = sext i16 [[TMP604]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP605:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1466:%.*]] = sext i16 [[TMP605]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1467:%.*]] = icmp sgt i32 [[CONV1465]], [[CONV1466]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1467]], label [[IF_THEN1469:%.*]], label [[IF_END1470:%.*]]
|
|
// SIMD-ONLY0: if.then1469:
|
|
// SIMD-ONLY0-NEXT: [[TMP606:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP606]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1470]]
|
|
// SIMD-ONLY0: if.end1470:
|
|
// SIMD-ONLY0-NEXT: [[TMP607:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1471:%.*]] = sext i16 [[TMP607]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP608:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1472:%.*]] = sext i16 [[TMP608]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1473:%.*]] = icmp slt i32 [[CONV1471]], [[CONV1472]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1473]], label [[IF_THEN1475:%.*]], label [[IF_END1476:%.*]]
|
|
// SIMD-ONLY0: if.then1475:
|
|
// SIMD-ONLY0-NEXT: [[TMP609:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP609]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1476]]
|
|
// SIMD-ONLY0: if.end1476:
|
|
// SIMD-ONLY0-NEXT: [[TMP610:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1477:%.*]] = sext i16 [[TMP610]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP611:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1478:%.*]] = sext i16 [[TMP611]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1479:%.*]] = icmp sgt i32 [[CONV1477]], [[CONV1478]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1479]], label [[IF_THEN1481:%.*]], label [[IF_END1482:%.*]]
|
|
// SIMD-ONLY0: if.then1481:
|
|
// SIMD-ONLY0-NEXT: [[TMP612:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP612]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1482]]
|
|
// SIMD-ONLY0: if.end1482:
|
|
// SIMD-ONLY0-NEXT: [[TMP613:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1483:%.*]] = sext i16 [[TMP613]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP614:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1484:%.*]] = sext i16 [[TMP614]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1485:%.*]] = icmp slt i32 [[CONV1483]], [[CONV1484]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1485]], label [[IF_THEN1487:%.*]], label [[IF_END1488:%.*]]
|
|
// SIMD-ONLY0: if.then1487:
|
|
// SIMD-ONLY0-NEXT: [[TMP615:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP615]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1488]]
|
|
// SIMD-ONLY0: if.end1488:
|
|
// SIMD-ONLY0-NEXT: [[TMP616:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1489:%.*]] = sext i16 [[TMP616]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP617:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1490:%.*]] = sext i16 [[TMP617]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1491:%.*]] = icmp eq i32 [[CONV1489]], [[CONV1490]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1491]], label [[COND_TRUE1493:%.*]], label [[COND_FALSE1495:%.*]]
|
|
// SIMD-ONLY0: cond.true1493:
|
|
// SIMD-ONLY0-NEXT: [[TMP618:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1494:%.*]] = sext i16 [[TMP618]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1497:%.*]]
|
|
// SIMD-ONLY0: cond.false1495:
|
|
// SIMD-ONLY0-NEXT: [[TMP619:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1496:%.*]] = sext i16 [[TMP619]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1497]]
|
|
// SIMD-ONLY0: cond.end1497:
|
|
// SIMD-ONLY0-NEXT: [[COND1498:%.*]] = phi i32 [ [[CONV1494]], [[COND_TRUE1493]] ], [ [[CONV1496]], [[COND_FALSE1495]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1499:%.*]] = trunc i32 [[COND1498]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1499]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP620:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1500:%.*]] = sext i16 [[TMP620]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP621:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1501:%.*]] = sext i16 [[TMP621]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1502:%.*]] = icmp eq i32 [[CONV1500]], [[CONV1501]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1502]], label [[COND_TRUE1504:%.*]], label [[COND_FALSE1506:%.*]]
|
|
// SIMD-ONLY0: cond.true1504:
|
|
// SIMD-ONLY0-NEXT: [[TMP622:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1505:%.*]] = sext i16 [[TMP622]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1508:%.*]]
|
|
// SIMD-ONLY0: cond.false1506:
|
|
// SIMD-ONLY0-NEXT: [[TMP623:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1507:%.*]] = sext i16 [[TMP623]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1508]]
|
|
// SIMD-ONLY0: cond.end1508:
|
|
// SIMD-ONLY0-NEXT: [[COND1509:%.*]] = phi i32 [ [[CONV1505]], [[COND_TRUE1504]] ], [ [[CONV1507]], [[COND_FALSE1506]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1510:%.*]] = trunc i32 [[COND1509]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1510]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP624:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1511:%.*]] = sext i16 [[TMP624]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP625:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1512:%.*]] = sext i16 [[TMP625]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1513:%.*]] = icmp eq i32 [[CONV1511]], [[CONV1512]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1513]], label [[IF_THEN1515:%.*]], label [[IF_END1516:%.*]]
|
|
// SIMD-ONLY0: if.then1515:
|
|
// SIMD-ONLY0-NEXT: [[TMP626:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP626]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1516]]
|
|
// SIMD-ONLY0: if.end1516:
|
|
// SIMD-ONLY0-NEXT: [[TMP627:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1517:%.*]] = sext i16 [[TMP627]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP628:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1518:%.*]] = sext i16 [[TMP628]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1519:%.*]] = icmp eq i32 [[CONV1517]], [[CONV1518]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1519]], label [[IF_THEN1521:%.*]], label [[IF_END1522:%.*]]
|
|
// SIMD-ONLY0: if.then1521:
|
|
// SIMD-ONLY0-NEXT: [[TMP629:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP629]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1522]]
|
|
// SIMD-ONLY0: if.end1522:
|
|
// SIMD-ONLY0-NEXT: [[TMP630:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1523:%.*]] = zext i16 [[TMP630]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP631:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1524:%.*]] = zext i16 [[TMP631]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1525:%.*]] = icmp sgt i32 [[CONV1523]], [[CONV1524]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1525]], label [[COND_TRUE1527:%.*]], label [[COND_FALSE1529:%.*]]
|
|
// SIMD-ONLY0: cond.true1527:
|
|
// SIMD-ONLY0-NEXT: [[TMP632:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1528:%.*]] = zext i16 [[TMP632]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1531:%.*]]
|
|
// SIMD-ONLY0: cond.false1529:
|
|
// SIMD-ONLY0-NEXT: [[TMP633:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1530:%.*]] = zext i16 [[TMP633]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1531]]
|
|
// SIMD-ONLY0: cond.end1531:
|
|
// SIMD-ONLY0-NEXT: [[COND1532:%.*]] = phi i32 [ [[CONV1528]], [[COND_TRUE1527]] ], [ [[CONV1530]], [[COND_FALSE1529]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1533:%.*]] = trunc i32 [[COND1532]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1533]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP634:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1534:%.*]] = zext i16 [[TMP634]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP635:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1535:%.*]] = zext i16 [[TMP635]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1536:%.*]] = icmp slt i32 [[CONV1534]], [[CONV1535]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1536]], label [[COND_TRUE1538:%.*]], label [[COND_FALSE1540:%.*]]
|
|
// SIMD-ONLY0: cond.true1538:
|
|
// SIMD-ONLY0-NEXT: [[TMP636:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1539:%.*]] = zext i16 [[TMP636]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1542:%.*]]
|
|
// SIMD-ONLY0: cond.false1540:
|
|
// SIMD-ONLY0-NEXT: [[TMP637:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1541:%.*]] = zext i16 [[TMP637]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1542]]
|
|
// SIMD-ONLY0: cond.end1542:
|
|
// SIMD-ONLY0-NEXT: [[COND1543:%.*]] = phi i32 [ [[CONV1539]], [[COND_TRUE1538]] ], [ [[CONV1541]], [[COND_FALSE1540]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1544:%.*]] = trunc i32 [[COND1543]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1544]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP638:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1545:%.*]] = zext i16 [[TMP638]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP639:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1546:%.*]] = zext i16 [[TMP639]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1547:%.*]] = icmp sgt i32 [[CONV1545]], [[CONV1546]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1547]], label [[COND_TRUE1549:%.*]], label [[COND_FALSE1551:%.*]]
|
|
// SIMD-ONLY0: cond.true1549:
|
|
// SIMD-ONLY0-NEXT: [[TMP640:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1550:%.*]] = zext i16 [[TMP640]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1553:%.*]]
|
|
// SIMD-ONLY0: cond.false1551:
|
|
// SIMD-ONLY0-NEXT: [[TMP641:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1552:%.*]] = zext i16 [[TMP641]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1553]]
|
|
// SIMD-ONLY0: cond.end1553:
|
|
// SIMD-ONLY0-NEXT: [[COND1554:%.*]] = phi i32 [ [[CONV1550]], [[COND_TRUE1549]] ], [ [[CONV1552]], [[COND_FALSE1551]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1555:%.*]] = trunc i32 [[COND1554]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1555]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP642:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1556:%.*]] = zext i16 [[TMP642]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP643:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1557:%.*]] = zext i16 [[TMP643]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1558:%.*]] = icmp slt i32 [[CONV1556]], [[CONV1557]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1558]], label [[COND_TRUE1560:%.*]], label [[COND_FALSE1562:%.*]]
|
|
// SIMD-ONLY0: cond.true1560:
|
|
// SIMD-ONLY0-NEXT: [[TMP644:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1561:%.*]] = zext i16 [[TMP644]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1564:%.*]]
|
|
// SIMD-ONLY0: cond.false1562:
|
|
// SIMD-ONLY0-NEXT: [[TMP645:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1563:%.*]] = zext i16 [[TMP645]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1564]]
|
|
// SIMD-ONLY0: cond.end1564:
|
|
// SIMD-ONLY0-NEXT: [[COND1565:%.*]] = phi i32 [ [[CONV1561]], [[COND_TRUE1560]] ], [ [[CONV1563]], [[COND_FALSE1562]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1566:%.*]] = trunc i32 [[COND1565]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1566]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP646:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1567:%.*]] = zext i16 [[TMP646]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP647:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1568:%.*]] = zext i16 [[TMP647]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1569:%.*]] = icmp sgt i32 [[CONV1567]], [[CONV1568]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1569]], label [[IF_THEN1571:%.*]], label [[IF_END1572:%.*]]
|
|
// SIMD-ONLY0: if.then1571:
|
|
// SIMD-ONLY0-NEXT: [[TMP648:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP648]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1572]]
|
|
// SIMD-ONLY0: if.end1572:
|
|
// SIMD-ONLY0-NEXT: [[TMP649:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1573:%.*]] = zext i16 [[TMP649]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP650:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1574:%.*]] = zext i16 [[TMP650]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1575:%.*]] = icmp slt i32 [[CONV1573]], [[CONV1574]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1575]], label [[IF_THEN1577:%.*]], label [[IF_END1578:%.*]]
|
|
// SIMD-ONLY0: if.then1577:
|
|
// SIMD-ONLY0-NEXT: [[TMP651:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP651]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1578]]
|
|
// SIMD-ONLY0: if.end1578:
|
|
// SIMD-ONLY0-NEXT: [[TMP652:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1579:%.*]] = zext i16 [[TMP652]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP653:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1580:%.*]] = zext i16 [[TMP653]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1581:%.*]] = icmp sgt i32 [[CONV1579]], [[CONV1580]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1581]], label [[IF_THEN1583:%.*]], label [[IF_END1584:%.*]]
|
|
// SIMD-ONLY0: if.then1583:
|
|
// SIMD-ONLY0-NEXT: [[TMP654:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP654]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1584]]
|
|
// SIMD-ONLY0: if.end1584:
|
|
// SIMD-ONLY0-NEXT: [[TMP655:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1585:%.*]] = zext i16 [[TMP655]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP656:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1586:%.*]] = zext i16 [[TMP656]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1587:%.*]] = icmp slt i32 [[CONV1585]], [[CONV1586]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1587]], label [[IF_THEN1589:%.*]], label [[IF_END1590:%.*]]
|
|
// SIMD-ONLY0: if.then1589:
|
|
// SIMD-ONLY0-NEXT: [[TMP657:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP657]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1590]]
|
|
// SIMD-ONLY0: if.end1590:
|
|
// SIMD-ONLY0-NEXT: [[TMP658:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1591:%.*]] = zext i16 [[TMP658]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP659:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1592:%.*]] = zext i16 [[TMP659]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1593:%.*]] = icmp eq i32 [[CONV1591]], [[CONV1592]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1593]], label [[COND_TRUE1595:%.*]], label [[COND_FALSE1597:%.*]]
|
|
// SIMD-ONLY0: cond.true1595:
|
|
// SIMD-ONLY0-NEXT: [[TMP660:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1596:%.*]] = zext i16 [[TMP660]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1599:%.*]]
|
|
// SIMD-ONLY0: cond.false1597:
|
|
// SIMD-ONLY0-NEXT: [[TMP661:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1598:%.*]] = zext i16 [[TMP661]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1599]]
|
|
// SIMD-ONLY0: cond.end1599:
|
|
// SIMD-ONLY0-NEXT: [[COND1600:%.*]] = phi i32 [ [[CONV1596]], [[COND_TRUE1595]] ], [ [[CONV1598]], [[COND_FALSE1597]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1601:%.*]] = trunc i32 [[COND1600]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1601]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP662:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1602:%.*]] = zext i16 [[TMP662]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP663:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1603:%.*]] = zext i16 [[TMP663]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1604:%.*]] = icmp eq i32 [[CONV1602]], [[CONV1603]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1604]], label [[COND_TRUE1606:%.*]], label [[COND_FALSE1608:%.*]]
|
|
// SIMD-ONLY0: cond.true1606:
|
|
// SIMD-ONLY0-NEXT: [[TMP664:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1607:%.*]] = zext i16 [[TMP664]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1610:%.*]]
|
|
// SIMD-ONLY0: cond.false1608:
|
|
// SIMD-ONLY0-NEXT: [[TMP665:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1609:%.*]] = zext i16 [[TMP665]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1610]]
|
|
// SIMD-ONLY0: cond.end1610:
|
|
// SIMD-ONLY0-NEXT: [[COND1611:%.*]] = phi i32 [ [[CONV1607]], [[COND_TRUE1606]] ], [ [[CONV1609]], [[COND_FALSE1608]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1612:%.*]] = trunc i32 [[COND1611]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1612]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP666:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1613:%.*]] = zext i16 [[TMP666]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP667:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1614:%.*]] = zext i16 [[TMP667]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1615:%.*]] = icmp eq i32 [[CONV1613]], [[CONV1614]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1615]], label [[IF_THEN1617:%.*]], label [[IF_END1618:%.*]]
|
|
// SIMD-ONLY0: if.then1617:
|
|
// SIMD-ONLY0-NEXT: [[TMP668:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP668]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1618]]
|
|
// SIMD-ONLY0: if.end1618:
|
|
// SIMD-ONLY0-NEXT: [[TMP669:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1619:%.*]] = zext i16 [[TMP669]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP670:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1620:%.*]] = zext i16 [[TMP670]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1621:%.*]] = icmp eq i32 [[CONV1619]], [[CONV1620]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1621]], label [[IF_THEN1623:%.*]], label [[IF_END1624:%.*]]
|
|
// SIMD-ONLY0: if.then1623:
|
|
// SIMD-ONLY0-NEXT: [[TMP671:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP671]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1624]]
|
|
// SIMD-ONLY0: if.end1624:
|
|
// SIMD-ONLY0-NEXT: [[TMP672:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1625:%.*]] = sext i16 [[TMP672]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP673:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1626:%.*]] = sext i16 [[TMP673]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1627:%.*]] = icmp sgt i32 [[CONV1625]], [[CONV1626]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1627]], label [[COND_TRUE1629:%.*]], label [[COND_FALSE1631:%.*]]
|
|
// SIMD-ONLY0: cond.true1629:
|
|
// SIMD-ONLY0-NEXT: [[TMP674:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1630:%.*]] = sext i16 [[TMP674]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1633:%.*]]
|
|
// SIMD-ONLY0: cond.false1631:
|
|
// SIMD-ONLY0-NEXT: [[TMP675:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1632:%.*]] = sext i16 [[TMP675]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1633]]
|
|
// SIMD-ONLY0: cond.end1633:
|
|
// SIMD-ONLY0-NEXT: [[COND1634:%.*]] = phi i32 [ [[CONV1630]], [[COND_TRUE1629]] ], [ [[CONV1632]], [[COND_FALSE1631]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1635:%.*]] = trunc i32 [[COND1634]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1635]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP676:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1636:%.*]] = sext i16 [[TMP676]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP677:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1637:%.*]] = sext i16 [[TMP677]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1638:%.*]] = icmp slt i32 [[CONV1636]], [[CONV1637]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1638]], label [[COND_TRUE1640:%.*]], label [[COND_FALSE1642:%.*]]
|
|
// SIMD-ONLY0: cond.true1640:
|
|
// SIMD-ONLY0-NEXT: [[TMP678:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1641:%.*]] = sext i16 [[TMP678]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1644:%.*]]
|
|
// SIMD-ONLY0: cond.false1642:
|
|
// SIMD-ONLY0-NEXT: [[TMP679:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1643:%.*]] = sext i16 [[TMP679]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1644]]
|
|
// SIMD-ONLY0: cond.end1644:
|
|
// SIMD-ONLY0-NEXT: [[COND1645:%.*]] = phi i32 [ [[CONV1641]], [[COND_TRUE1640]] ], [ [[CONV1643]], [[COND_FALSE1642]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1646:%.*]] = trunc i32 [[COND1645]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1646]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP680:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1647:%.*]] = sext i16 [[TMP680]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP681:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1648:%.*]] = sext i16 [[TMP681]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1649:%.*]] = icmp sgt i32 [[CONV1647]], [[CONV1648]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1649]], label [[COND_TRUE1651:%.*]], label [[COND_FALSE1653:%.*]]
|
|
// SIMD-ONLY0: cond.true1651:
|
|
// SIMD-ONLY0-NEXT: [[TMP682:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1652:%.*]] = sext i16 [[TMP682]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1655:%.*]]
|
|
// SIMD-ONLY0: cond.false1653:
|
|
// SIMD-ONLY0-NEXT: [[TMP683:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1654:%.*]] = sext i16 [[TMP683]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1655]]
|
|
// SIMD-ONLY0: cond.end1655:
|
|
// SIMD-ONLY0-NEXT: [[COND1656:%.*]] = phi i32 [ [[CONV1652]], [[COND_TRUE1651]] ], [ [[CONV1654]], [[COND_FALSE1653]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1657:%.*]] = trunc i32 [[COND1656]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1657]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP684:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1658:%.*]] = sext i16 [[TMP684]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP685:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1659:%.*]] = sext i16 [[TMP685]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1660:%.*]] = icmp slt i32 [[CONV1658]], [[CONV1659]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1660]], label [[COND_TRUE1662:%.*]], label [[COND_FALSE1664:%.*]]
|
|
// SIMD-ONLY0: cond.true1662:
|
|
// SIMD-ONLY0-NEXT: [[TMP686:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1663:%.*]] = sext i16 [[TMP686]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1666:%.*]]
|
|
// SIMD-ONLY0: cond.false1664:
|
|
// SIMD-ONLY0-NEXT: [[TMP687:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1665:%.*]] = sext i16 [[TMP687]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1666]]
|
|
// SIMD-ONLY0: cond.end1666:
|
|
// SIMD-ONLY0-NEXT: [[COND1667:%.*]] = phi i32 [ [[CONV1663]], [[COND_TRUE1662]] ], [ [[CONV1665]], [[COND_FALSE1664]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1668:%.*]] = trunc i32 [[COND1667]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1668]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP688:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1669:%.*]] = sext i16 [[TMP688]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP689:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1670:%.*]] = sext i16 [[TMP689]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1671:%.*]] = icmp sgt i32 [[CONV1669]], [[CONV1670]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1671]], label [[IF_THEN1673:%.*]], label [[IF_END1674:%.*]]
|
|
// SIMD-ONLY0: if.then1673:
|
|
// SIMD-ONLY0-NEXT: [[TMP690:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP690]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1674]]
|
|
// SIMD-ONLY0: if.end1674:
|
|
// SIMD-ONLY0-NEXT: [[TMP691:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1675:%.*]] = sext i16 [[TMP691]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP692:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1676:%.*]] = sext i16 [[TMP692]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1677:%.*]] = icmp slt i32 [[CONV1675]], [[CONV1676]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1677]], label [[IF_THEN1679:%.*]], label [[IF_END1680:%.*]]
|
|
// SIMD-ONLY0: if.then1679:
|
|
// SIMD-ONLY0-NEXT: [[TMP693:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP693]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1680]]
|
|
// SIMD-ONLY0: if.end1680:
|
|
// SIMD-ONLY0-NEXT: [[TMP694:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1681:%.*]] = sext i16 [[TMP694]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP695:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1682:%.*]] = sext i16 [[TMP695]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1683:%.*]] = icmp sgt i32 [[CONV1681]], [[CONV1682]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1683]], label [[IF_THEN1685:%.*]], label [[IF_END1686:%.*]]
|
|
// SIMD-ONLY0: if.then1685:
|
|
// SIMD-ONLY0-NEXT: [[TMP696:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP696]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1686]]
|
|
// SIMD-ONLY0: if.end1686:
|
|
// SIMD-ONLY0-NEXT: [[TMP697:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1687:%.*]] = sext i16 [[TMP697]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP698:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1688:%.*]] = sext i16 [[TMP698]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1689:%.*]] = icmp slt i32 [[CONV1687]], [[CONV1688]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1689]], label [[IF_THEN1691:%.*]], label [[IF_END1692:%.*]]
|
|
// SIMD-ONLY0: if.then1691:
|
|
// SIMD-ONLY0-NEXT: [[TMP699:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP699]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1692]]
|
|
// SIMD-ONLY0: if.end1692:
|
|
// SIMD-ONLY0-NEXT: [[TMP700:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1693:%.*]] = sext i16 [[TMP700]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP701:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1694:%.*]] = sext i16 [[TMP701]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1695:%.*]] = icmp eq i32 [[CONV1693]], [[CONV1694]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1695]], label [[COND_TRUE1697:%.*]], label [[COND_FALSE1699:%.*]]
|
|
// SIMD-ONLY0: cond.true1697:
|
|
// SIMD-ONLY0-NEXT: [[TMP702:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1698:%.*]] = sext i16 [[TMP702]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1701:%.*]]
|
|
// SIMD-ONLY0: cond.false1699:
|
|
// SIMD-ONLY0-NEXT: [[TMP703:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1700:%.*]] = sext i16 [[TMP703]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1701]]
|
|
// SIMD-ONLY0: cond.end1701:
|
|
// SIMD-ONLY0-NEXT: [[COND1702:%.*]] = phi i32 [ [[CONV1698]], [[COND_TRUE1697]] ], [ [[CONV1700]], [[COND_FALSE1699]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1703:%.*]] = trunc i32 [[COND1702]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1703]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP704:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1704:%.*]] = sext i16 [[TMP704]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP705:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1705:%.*]] = sext i16 [[TMP705]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1706:%.*]] = icmp eq i32 [[CONV1704]], [[CONV1705]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1706]], label [[COND_TRUE1708:%.*]], label [[COND_FALSE1710:%.*]]
|
|
// SIMD-ONLY0: cond.true1708:
|
|
// SIMD-ONLY0-NEXT: [[TMP706:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1709:%.*]] = sext i16 [[TMP706]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1712:%.*]]
|
|
// SIMD-ONLY0: cond.false1710:
|
|
// SIMD-ONLY0-NEXT: [[TMP707:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1711:%.*]] = sext i16 [[TMP707]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1712]]
|
|
// SIMD-ONLY0: cond.end1712:
|
|
// SIMD-ONLY0-NEXT: [[COND1713:%.*]] = phi i32 [ [[CONV1709]], [[COND_TRUE1708]] ], [ [[CONV1711]], [[COND_FALSE1710]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1714:%.*]] = trunc i32 [[COND1713]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1714]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP708:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1715:%.*]] = sext i16 [[TMP708]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP709:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1716:%.*]] = sext i16 [[TMP709]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1717:%.*]] = icmp eq i32 [[CONV1715]], [[CONV1716]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1717]], label [[IF_THEN1719:%.*]], label [[IF_END1720:%.*]]
|
|
// SIMD-ONLY0: if.then1719:
|
|
// SIMD-ONLY0-NEXT: [[TMP710:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP710]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1720]]
|
|
// SIMD-ONLY0: if.end1720:
|
|
// SIMD-ONLY0-NEXT: [[TMP711:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1721:%.*]] = sext i16 [[TMP711]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP712:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1722:%.*]] = sext i16 [[TMP712]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1723:%.*]] = icmp eq i32 [[CONV1721]], [[CONV1722]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1723]], label [[IF_THEN1725:%.*]], label [[IF_END1726:%.*]]
|
|
// SIMD-ONLY0: if.then1725:
|
|
// SIMD-ONLY0-NEXT: [[TMP713:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP713]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1726]]
|
|
// SIMD-ONLY0: if.end1726:
|
|
// SIMD-ONLY0-NEXT: [[TMP714:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1727:%.*]] = zext i16 [[TMP714]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP715:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1728:%.*]] = zext i16 [[TMP715]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1729:%.*]] = icmp sgt i32 [[CONV1727]], [[CONV1728]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1729]], label [[COND_TRUE1731:%.*]], label [[COND_FALSE1733:%.*]]
|
|
// SIMD-ONLY0: cond.true1731:
|
|
// SIMD-ONLY0-NEXT: [[TMP716:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1732:%.*]] = zext i16 [[TMP716]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1735:%.*]]
|
|
// SIMD-ONLY0: cond.false1733:
|
|
// SIMD-ONLY0-NEXT: [[TMP717:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1734:%.*]] = zext i16 [[TMP717]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1735]]
|
|
// SIMD-ONLY0: cond.end1735:
|
|
// SIMD-ONLY0-NEXT: [[COND1736:%.*]] = phi i32 [ [[CONV1732]], [[COND_TRUE1731]] ], [ [[CONV1734]], [[COND_FALSE1733]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1737:%.*]] = trunc i32 [[COND1736]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1737]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP718:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1738:%.*]] = zext i16 [[TMP718]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP719:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1739:%.*]] = zext i16 [[TMP719]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1740:%.*]] = icmp slt i32 [[CONV1738]], [[CONV1739]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1740]], label [[COND_TRUE1742:%.*]], label [[COND_FALSE1744:%.*]]
|
|
// SIMD-ONLY0: cond.true1742:
|
|
// SIMD-ONLY0-NEXT: [[TMP720:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1743:%.*]] = zext i16 [[TMP720]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1746:%.*]]
|
|
// SIMD-ONLY0: cond.false1744:
|
|
// SIMD-ONLY0-NEXT: [[TMP721:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1745:%.*]] = zext i16 [[TMP721]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1746]]
|
|
// SIMD-ONLY0: cond.end1746:
|
|
// SIMD-ONLY0-NEXT: [[COND1747:%.*]] = phi i32 [ [[CONV1743]], [[COND_TRUE1742]] ], [ [[CONV1745]], [[COND_FALSE1744]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1748:%.*]] = trunc i32 [[COND1747]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1748]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP722:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1749:%.*]] = zext i16 [[TMP722]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP723:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1750:%.*]] = zext i16 [[TMP723]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1751:%.*]] = icmp sgt i32 [[CONV1749]], [[CONV1750]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1751]], label [[COND_TRUE1753:%.*]], label [[COND_FALSE1755:%.*]]
|
|
// SIMD-ONLY0: cond.true1753:
|
|
// SIMD-ONLY0-NEXT: [[TMP724:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1754:%.*]] = zext i16 [[TMP724]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1757:%.*]]
|
|
// SIMD-ONLY0: cond.false1755:
|
|
// SIMD-ONLY0-NEXT: [[TMP725:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1756:%.*]] = zext i16 [[TMP725]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1757]]
|
|
// SIMD-ONLY0: cond.end1757:
|
|
// SIMD-ONLY0-NEXT: [[COND1758:%.*]] = phi i32 [ [[CONV1754]], [[COND_TRUE1753]] ], [ [[CONV1756]], [[COND_FALSE1755]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1759:%.*]] = trunc i32 [[COND1758]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1759]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP726:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1760:%.*]] = zext i16 [[TMP726]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP727:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1761:%.*]] = zext i16 [[TMP727]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1762:%.*]] = icmp slt i32 [[CONV1760]], [[CONV1761]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1762]], label [[COND_TRUE1764:%.*]], label [[COND_FALSE1766:%.*]]
|
|
// SIMD-ONLY0: cond.true1764:
|
|
// SIMD-ONLY0-NEXT: [[TMP728:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1765:%.*]] = zext i16 [[TMP728]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1768:%.*]]
|
|
// SIMD-ONLY0: cond.false1766:
|
|
// SIMD-ONLY0-NEXT: [[TMP729:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1767:%.*]] = zext i16 [[TMP729]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1768]]
|
|
// SIMD-ONLY0: cond.end1768:
|
|
// SIMD-ONLY0-NEXT: [[COND1769:%.*]] = phi i32 [ [[CONV1765]], [[COND_TRUE1764]] ], [ [[CONV1767]], [[COND_FALSE1766]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1770:%.*]] = trunc i32 [[COND1769]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1770]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP730:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1771:%.*]] = zext i16 [[TMP730]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP731:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1772:%.*]] = zext i16 [[TMP731]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1773:%.*]] = icmp sgt i32 [[CONV1771]], [[CONV1772]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1773]], label [[IF_THEN1775:%.*]], label [[IF_END1776:%.*]]
|
|
// SIMD-ONLY0: if.then1775:
|
|
// SIMD-ONLY0-NEXT: [[TMP732:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP732]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1776]]
|
|
// SIMD-ONLY0: if.end1776:
|
|
// SIMD-ONLY0-NEXT: [[TMP733:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1777:%.*]] = zext i16 [[TMP733]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP734:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1778:%.*]] = zext i16 [[TMP734]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1779:%.*]] = icmp slt i32 [[CONV1777]], [[CONV1778]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1779]], label [[IF_THEN1781:%.*]], label [[IF_END1782:%.*]]
|
|
// SIMD-ONLY0: if.then1781:
|
|
// SIMD-ONLY0-NEXT: [[TMP735:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP735]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1782]]
|
|
// SIMD-ONLY0: if.end1782:
|
|
// SIMD-ONLY0-NEXT: [[TMP736:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1783:%.*]] = zext i16 [[TMP736]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP737:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1784:%.*]] = zext i16 [[TMP737]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1785:%.*]] = icmp sgt i32 [[CONV1783]], [[CONV1784]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1785]], label [[IF_THEN1787:%.*]], label [[IF_END1788:%.*]]
|
|
// SIMD-ONLY0: if.then1787:
|
|
// SIMD-ONLY0-NEXT: [[TMP738:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP738]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1788]]
|
|
// SIMD-ONLY0: if.end1788:
|
|
// SIMD-ONLY0-NEXT: [[TMP739:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1789:%.*]] = zext i16 [[TMP739]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP740:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1790:%.*]] = zext i16 [[TMP740]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1791:%.*]] = icmp slt i32 [[CONV1789]], [[CONV1790]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1791]], label [[IF_THEN1793:%.*]], label [[IF_END1794:%.*]]
|
|
// SIMD-ONLY0: if.then1793:
|
|
// SIMD-ONLY0-NEXT: [[TMP741:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP741]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1794]]
|
|
// SIMD-ONLY0: if.end1794:
|
|
// SIMD-ONLY0-NEXT: [[TMP742:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1795:%.*]] = zext i16 [[TMP742]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP743:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1796:%.*]] = zext i16 [[TMP743]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1797:%.*]] = icmp eq i32 [[CONV1795]], [[CONV1796]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1797]], label [[COND_TRUE1799:%.*]], label [[COND_FALSE1801:%.*]]
|
|
// SIMD-ONLY0: cond.true1799:
|
|
// SIMD-ONLY0-NEXT: [[TMP744:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1800:%.*]] = zext i16 [[TMP744]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1803:%.*]]
|
|
// SIMD-ONLY0: cond.false1801:
|
|
// SIMD-ONLY0-NEXT: [[TMP745:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1802:%.*]] = zext i16 [[TMP745]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1803]]
|
|
// SIMD-ONLY0: cond.end1803:
|
|
// SIMD-ONLY0-NEXT: [[COND1804:%.*]] = phi i32 [ [[CONV1800]], [[COND_TRUE1799]] ], [ [[CONV1802]], [[COND_FALSE1801]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1805:%.*]] = trunc i32 [[COND1804]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1805]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP746:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1806:%.*]] = zext i16 [[TMP746]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP747:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1807:%.*]] = zext i16 [[TMP747]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1808:%.*]] = icmp eq i32 [[CONV1806]], [[CONV1807]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1808]], label [[COND_TRUE1810:%.*]], label [[COND_FALSE1812:%.*]]
|
|
// SIMD-ONLY0: cond.true1810:
|
|
// SIMD-ONLY0-NEXT: [[TMP748:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1811:%.*]] = zext i16 [[TMP748]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1814:%.*]]
|
|
// SIMD-ONLY0: cond.false1812:
|
|
// SIMD-ONLY0-NEXT: [[TMP749:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1813:%.*]] = zext i16 [[TMP749]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1814]]
|
|
// SIMD-ONLY0: cond.end1814:
|
|
// SIMD-ONLY0-NEXT: [[COND1815:%.*]] = phi i32 [ [[CONV1811]], [[COND_TRUE1810]] ], [ [[CONV1813]], [[COND_FALSE1812]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1816:%.*]] = trunc i32 [[COND1815]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1816]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP750:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1817:%.*]] = zext i16 [[TMP750]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP751:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1818:%.*]] = zext i16 [[TMP751]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1819:%.*]] = icmp eq i32 [[CONV1817]], [[CONV1818]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1819]], label [[IF_THEN1821:%.*]], label [[IF_END1822:%.*]]
|
|
// SIMD-ONLY0: if.then1821:
|
|
// SIMD-ONLY0-NEXT: [[TMP752:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP752]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1822]]
|
|
// SIMD-ONLY0: if.end1822:
|
|
// SIMD-ONLY0-NEXT: [[TMP753:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1823:%.*]] = zext i16 [[TMP753]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP754:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1824:%.*]] = zext i16 [[TMP754]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1825:%.*]] = icmp eq i32 [[CONV1823]], [[CONV1824]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1825]], label [[IF_THEN1827:%.*]], label [[IF_END1828:%.*]]
|
|
// SIMD-ONLY0: if.then1827:
|
|
// SIMD-ONLY0-NEXT: [[TMP755:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP755]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1828]]
|
|
// SIMD-ONLY0: if.end1828:
|
|
// SIMD-ONLY0-NEXT: [[TMP756:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1829:%.*]] = sext i16 [[TMP756]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP757:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1830:%.*]] = sext i16 [[TMP757]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1831:%.*]] = icmp sgt i32 [[CONV1829]], [[CONV1830]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1831]], label [[COND_TRUE1833:%.*]], label [[COND_FALSE1835:%.*]]
|
|
// SIMD-ONLY0: cond.true1833:
|
|
// SIMD-ONLY0-NEXT: [[TMP758:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1834:%.*]] = sext i16 [[TMP758]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1837:%.*]]
|
|
// SIMD-ONLY0: cond.false1835:
|
|
// SIMD-ONLY0-NEXT: [[TMP759:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1836:%.*]] = sext i16 [[TMP759]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1837]]
|
|
// SIMD-ONLY0: cond.end1837:
|
|
// SIMD-ONLY0-NEXT: [[COND1838:%.*]] = phi i32 [ [[CONV1834]], [[COND_TRUE1833]] ], [ [[CONV1836]], [[COND_FALSE1835]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1839:%.*]] = trunc i32 [[COND1838]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1839]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP760:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1840:%.*]] = sext i16 [[TMP760]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP761:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1841:%.*]] = sext i16 [[TMP761]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1842:%.*]] = icmp slt i32 [[CONV1840]], [[CONV1841]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1842]], label [[COND_TRUE1844:%.*]], label [[COND_FALSE1846:%.*]]
|
|
// SIMD-ONLY0: cond.true1844:
|
|
// SIMD-ONLY0-NEXT: [[TMP762:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1845:%.*]] = sext i16 [[TMP762]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1848:%.*]]
|
|
// SIMD-ONLY0: cond.false1846:
|
|
// SIMD-ONLY0-NEXT: [[TMP763:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1847:%.*]] = sext i16 [[TMP763]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1848]]
|
|
// SIMD-ONLY0: cond.end1848:
|
|
// SIMD-ONLY0-NEXT: [[COND1849:%.*]] = phi i32 [ [[CONV1845]], [[COND_TRUE1844]] ], [ [[CONV1847]], [[COND_FALSE1846]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1850:%.*]] = trunc i32 [[COND1849]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1850]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP764:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1851:%.*]] = sext i16 [[TMP764]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP765:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1852:%.*]] = sext i16 [[TMP765]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1853:%.*]] = icmp sgt i32 [[CONV1851]], [[CONV1852]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1853]], label [[COND_TRUE1855:%.*]], label [[COND_FALSE1857:%.*]]
|
|
// SIMD-ONLY0: cond.true1855:
|
|
// SIMD-ONLY0-NEXT: [[TMP766:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1856:%.*]] = sext i16 [[TMP766]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1859:%.*]]
|
|
// SIMD-ONLY0: cond.false1857:
|
|
// SIMD-ONLY0-NEXT: [[TMP767:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1858:%.*]] = sext i16 [[TMP767]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1859]]
|
|
// SIMD-ONLY0: cond.end1859:
|
|
// SIMD-ONLY0-NEXT: [[COND1860:%.*]] = phi i32 [ [[CONV1856]], [[COND_TRUE1855]] ], [ [[CONV1858]], [[COND_FALSE1857]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1861:%.*]] = trunc i32 [[COND1860]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1861]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP768:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1862:%.*]] = sext i16 [[TMP768]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP769:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1863:%.*]] = sext i16 [[TMP769]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1864:%.*]] = icmp slt i32 [[CONV1862]], [[CONV1863]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1864]], label [[COND_TRUE1866:%.*]], label [[COND_FALSE1868:%.*]]
|
|
// SIMD-ONLY0: cond.true1866:
|
|
// SIMD-ONLY0-NEXT: [[TMP770:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1867:%.*]] = sext i16 [[TMP770]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1870:%.*]]
|
|
// SIMD-ONLY0: cond.false1868:
|
|
// SIMD-ONLY0-NEXT: [[TMP771:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1869:%.*]] = sext i16 [[TMP771]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1870]]
|
|
// SIMD-ONLY0: cond.end1870:
|
|
// SIMD-ONLY0-NEXT: [[COND1871:%.*]] = phi i32 [ [[CONV1867]], [[COND_TRUE1866]] ], [ [[CONV1869]], [[COND_FALSE1868]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1872:%.*]] = trunc i32 [[COND1871]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1872]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP772:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1873:%.*]] = sext i16 [[TMP772]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP773:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1874:%.*]] = sext i16 [[TMP773]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1875:%.*]] = icmp sgt i32 [[CONV1873]], [[CONV1874]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1875]], label [[IF_THEN1877:%.*]], label [[IF_END1878:%.*]]
|
|
// SIMD-ONLY0: if.then1877:
|
|
// SIMD-ONLY0-NEXT: [[TMP774:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP774]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1878]]
|
|
// SIMD-ONLY0: if.end1878:
|
|
// SIMD-ONLY0-NEXT: [[TMP775:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1879:%.*]] = sext i16 [[TMP775]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP776:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1880:%.*]] = sext i16 [[TMP776]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1881:%.*]] = icmp slt i32 [[CONV1879]], [[CONV1880]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1881]], label [[IF_THEN1883:%.*]], label [[IF_END1884:%.*]]
|
|
// SIMD-ONLY0: if.then1883:
|
|
// SIMD-ONLY0-NEXT: [[TMP777:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP777]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1884]]
|
|
// SIMD-ONLY0: if.end1884:
|
|
// SIMD-ONLY0-NEXT: [[TMP778:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1885:%.*]] = sext i16 [[TMP778]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP779:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1886:%.*]] = sext i16 [[TMP779]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1887:%.*]] = icmp sgt i32 [[CONV1885]], [[CONV1886]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1887]], label [[IF_THEN1889:%.*]], label [[IF_END1890:%.*]]
|
|
// SIMD-ONLY0: if.then1889:
|
|
// SIMD-ONLY0-NEXT: [[TMP780:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP780]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1890]]
|
|
// SIMD-ONLY0: if.end1890:
|
|
// SIMD-ONLY0-NEXT: [[TMP781:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1891:%.*]] = sext i16 [[TMP781]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP782:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1892:%.*]] = sext i16 [[TMP782]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1893:%.*]] = icmp slt i32 [[CONV1891]], [[CONV1892]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1893]], label [[IF_THEN1895:%.*]], label [[IF_END1896:%.*]]
|
|
// SIMD-ONLY0: if.then1895:
|
|
// SIMD-ONLY0-NEXT: [[TMP783:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP783]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1896]]
|
|
// SIMD-ONLY0: if.end1896:
|
|
// SIMD-ONLY0-NEXT: [[TMP784:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1897:%.*]] = sext i16 [[TMP784]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP785:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1898:%.*]] = sext i16 [[TMP785]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1899:%.*]] = icmp eq i32 [[CONV1897]], [[CONV1898]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1899]], label [[COND_TRUE1901:%.*]], label [[COND_FALSE1903:%.*]]
|
|
// SIMD-ONLY0: cond.true1901:
|
|
// SIMD-ONLY0-NEXT: [[TMP786:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1902:%.*]] = sext i16 [[TMP786]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1905:%.*]]
|
|
// SIMD-ONLY0: cond.false1903:
|
|
// SIMD-ONLY0-NEXT: [[TMP787:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1904:%.*]] = sext i16 [[TMP787]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1905]]
|
|
// SIMD-ONLY0: cond.end1905:
|
|
// SIMD-ONLY0-NEXT: [[COND1906:%.*]] = phi i32 [ [[CONV1902]], [[COND_TRUE1901]] ], [ [[CONV1904]], [[COND_FALSE1903]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1907:%.*]] = trunc i32 [[COND1906]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1907]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP788:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1908:%.*]] = sext i16 [[TMP788]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP789:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1909:%.*]] = sext i16 [[TMP789]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1910:%.*]] = icmp eq i32 [[CONV1908]], [[CONV1909]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1910]], label [[COND_TRUE1912:%.*]], label [[COND_FALSE1914:%.*]]
|
|
// SIMD-ONLY0: cond.true1912:
|
|
// SIMD-ONLY0-NEXT: [[TMP790:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1913:%.*]] = sext i16 [[TMP790]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1916:%.*]]
|
|
// SIMD-ONLY0: cond.false1914:
|
|
// SIMD-ONLY0-NEXT: [[TMP791:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1915:%.*]] = sext i16 [[TMP791]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1916]]
|
|
// SIMD-ONLY0: cond.end1916:
|
|
// SIMD-ONLY0-NEXT: [[COND1917:%.*]] = phi i32 [ [[CONV1913]], [[COND_TRUE1912]] ], [ [[CONV1915]], [[COND_FALSE1914]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1918:%.*]] = trunc i32 [[COND1917]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1918]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP792:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1919:%.*]] = sext i16 [[TMP792]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP793:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1920:%.*]] = sext i16 [[TMP793]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1921:%.*]] = icmp eq i32 [[CONV1919]], [[CONV1920]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1921]], label [[IF_THEN1923:%.*]], label [[IF_END1924:%.*]]
|
|
// SIMD-ONLY0: if.then1923:
|
|
// SIMD-ONLY0-NEXT: [[TMP794:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP794]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1924]]
|
|
// SIMD-ONLY0: if.end1924:
|
|
// SIMD-ONLY0-NEXT: [[TMP795:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1925:%.*]] = sext i16 [[TMP795]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP796:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1926:%.*]] = sext i16 [[TMP796]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1927:%.*]] = icmp eq i32 [[CONV1925]], [[CONV1926]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1927]], label [[IF_THEN1929:%.*]], label [[IF_END1930:%.*]]
|
|
// SIMD-ONLY0: if.then1929:
|
|
// SIMD-ONLY0-NEXT: [[TMP797:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP797]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1930]]
|
|
// SIMD-ONLY0: if.end1930:
|
|
// SIMD-ONLY0-NEXT: [[TMP798:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1931:%.*]] = zext i16 [[TMP798]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP799:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1932:%.*]] = zext i16 [[TMP799]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1933:%.*]] = icmp sgt i32 [[CONV1931]], [[CONV1932]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1933]], label [[COND_TRUE1935:%.*]], label [[COND_FALSE1937:%.*]]
|
|
// SIMD-ONLY0: cond.true1935:
|
|
// SIMD-ONLY0-NEXT: [[TMP800:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1936:%.*]] = zext i16 [[TMP800]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1939:%.*]]
|
|
// SIMD-ONLY0: cond.false1937:
|
|
// SIMD-ONLY0-NEXT: [[TMP801:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1938:%.*]] = zext i16 [[TMP801]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1939]]
|
|
// SIMD-ONLY0: cond.end1939:
|
|
// SIMD-ONLY0-NEXT: [[COND1940:%.*]] = phi i32 [ [[CONV1936]], [[COND_TRUE1935]] ], [ [[CONV1938]], [[COND_FALSE1937]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1941:%.*]] = trunc i32 [[COND1940]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1941]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP802:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1942:%.*]] = zext i16 [[TMP802]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP803:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1943:%.*]] = zext i16 [[TMP803]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1944:%.*]] = icmp slt i32 [[CONV1942]], [[CONV1943]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1944]], label [[COND_TRUE1946:%.*]], label [[COND_FALSE1948:%.*]]
|
|
// SIMD-ONLY0: cond.true1946:
|
|
// SIMD-ONLY0-NEXT: [[TMP804:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1947:%.*]] = zext i16 [[TMP804]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1950:%.*]]
|
|
// SIMD-ONLY0: cond.false1948:
|
|
// SIMD-ONLY0-NEXT: [[TMP805:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1949:%.*]] = zext i16 [[TMP805]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1950]]
|
|
// SIMD-ONLY0: cond.end1950:
|
|
// SIMD-ONLY0-NEXT: [[COND1951:%.*]] = phi i32 [ [[CONV1947]], [[COND_TRUE1946]] ], [ [[CONV1949]], [[COND_FALSE1948]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1952:%.*]] = trunc i32 [[COND1951]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1952]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP806:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1953:%.*]] = zext i16 [[TMP806]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP807:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1954:%.*]] = zext i16 [[TMP807]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1955:%.*]] = icmp sgt i32 [[CONV1953]], [[CONV1954]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1955]], label [[COND_TRUE1957:%.*]], label [[COND_FALSE1959:%.*]]
|
|
// SIMD-ONLY0: cond.true1957:
|
|
// SIMD-ONLY0-NEXT: [[TMP808:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1958:%.*]] = zext i16 [[TMP808]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1961:%.*]]
|
|
// SIMD-ONLY0: cond.false1959:
|
|
// SIMD-ONLY0-NEXT: [[TMP809:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1960:%.*]] = zext i16 [[TMP809]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1961]]
|
|
// SIMD-ONLY0: cond.end1961:
|
|
// SIMD-ONLY0-NEXT: [[COND1962:%.*]] = phi i32 [ [[CONV1958]], [[COND_TRUE1957]] ], [ [[CONV1960]], [[COND_FALSE1959]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1963:%.*]] = trunc i32 [[COND1962]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1963]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP810:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1964:%.*]] = zext i16 [[TMP810]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP811:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1965:%.*]] = zext i16 [[TMP811]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1966:%.*]] = icmp slt i32 [[CONV1964]], [[CONV1965]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1966]], label [[COND_TRUE1968:%.*]], label [[COND_FALSE1970:%.*]]
|
|
// SIMD-ONLY0: cond.true1968:
|
|
// SIMD-ONLY0-NEXT: [[TMP812:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1969:%.*]] = zext i16 [[TMP812]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1972:%.*]]
|
|
// SIMD-ONLY0: cond.false1970:
|
|
// SIMD-ONLY0-NEXT: [[TMP813:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1971:%.*]] = zext i16 [[TMP813]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END1972]]
|
|
// SIMD-ONLY0: cond.end1972:
|
|
// SIMD-ONLY0-NEXT: [[COND1973:%.*]] = phi i32 [ [[CONV1969]], [[COND_TRUE1968]] ], [ [[CONV1971]], [[COND_FALSE1970]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV1974:%.*]] = trunc i32 [[COND1973]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1974]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP814:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1975:%.*]] = zext i16 [[TMP814]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP815:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1976:%.*]] = zext i16 [[TMP815]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1977:%.*]] = icmp sgt i32 [[CONV1975]], [[CONV1976]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1977]], label [[IF_THEN1979:%.*]], label [[IF_END1980:%.*]]
|
|
// SIMD-ONLY0: if.then1979:
|
|
// SIMD-ONLY0-NEXT: [[TMP816:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP816]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1980]]
|
|
// SIMD-ONLY0: if.end1980:
|
|
// SIMD-ONLY0-NEXT: [[TMP817:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1981:%.*]] = zext i16 [[TMP817]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP818:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1982:%.*]] = zext i16 [[TMP818]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1983:%.*]] = icmp slt i32 [[CONV1981]], [[CONV1982]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1983]], label [[IF_THEN1985:%.*]], label [[IF_END1986:%.*]]
|
|
// SIMD-ONLY0: if.then1985:
|
|
// SIMD-ONLY0-NEXT: [[TMP819:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP819]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1986]]
|
|
// SIMD-ONLY0: if.end1986:
|
|
// SIMD-ONLY0-NEXT: [[TMP820:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1987:%.*]] = zext i16 [[TMP820]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP821:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1988:%.*]] = zext i16 [[TMP821]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1989:%.*]] = icmp sgt i32 [[CONV1987]], [[CONV1988]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1989]], label [[IF_THEN1991:%.*]], label [[IF_END1992:%.*]]
|
|
// SIMD-ONLY0: if.then1991:
|
|
// SIMD-ONLY0-NEXT: [[TMP822:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP822]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1992]]
|
|
// SIMD-ONLY0: if.end1992:
|
|
// SIMD-ONLY0-NEXT: [[TMP823:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1993:%.*]] = zext i16 [[TMP823]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP824:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1994:%.*]] = zext i16 [[TMP824]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1995:%.*]] = icmp slt i32 [[CONV1993]], [[CONV1994]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1995]], label [[IF_THEN1997:%.*]], label [[IF_END1998:%.*]]
|
|
// SIMD-ONLY0: if.then1997:
|
|
// SIMD-ONLY0-NEXT: [[TMP825:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP825]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1998]]
|
|
// SIMD-ONLY0: if.end1998:
|
|
// SIMD-ONLY0-NEXT: [[TMP826:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1999:%.*]] = zext i16 [[TMP826]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP827:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2000:%.*]] = zext i16 [[TMP827]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2001:%.*]] = icmp eq i32 [[CONV1999]], [[CONV2000]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2001]], label [[COND_TRUE2003:%.*]], label [[COND_FALSE2005:%.*]]
|
|
// SIMD-ONLY0: cond.true2003:
|
|
// SIMD-ONLY0-NEXT: [[TMP828:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2004:%.*]] = zext i16 [[TMP828]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2007:%.*]]
|
|
// SIMD-ONLY0: cond.false2005:
|
|
// SIMD-ONLY0-NEXT: [[TMP829:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2006:%.*]] = zext i16 [[TMP829]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2007]]
|
|
// SIMD-ONLY0: cond.end2007:
|
|
// SIMD-ONLY0-NEXT: [[COND2008:%.*]] = phi i32 [ [[CONV2004]], [[COND_TRUE2003]] ], [ [[CONV2006]], [[COND_FALSE2005]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2009:%.*]] = trunc i32 [[COND2008]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2009]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP830:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2010:%.*]] = zext i16 [[TMP830]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP831:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2011:%.*]] = zext i16 [[TMP831]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2012:%.*]] = icmp eq i32 [[CONV2010]], [[CONV2011]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2012]], label [[COND_TRUE2014:%.*]], label [[COND_FALSE2016:%.*]]
|
|
// SIMD-ONLY0: cond.true2014:
|
|
// SIMD-ONLY0-NEXT: [[TMP832:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2015:%.*]] = zext i16 [[TMP832]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2018:%.*]]
|
|
// SIMD-ONLY0: cond.false2016:
|
|
// SIMD-ONLY0-NEXT: [[TMP833:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2017:%.*]] = zext i16 [[TMP833]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2018]]
|
|
// SIMD-ONLY0: cond.end2018:
|
|
// SIMD-ONLY0-NEXT: [[COND2019:%.*]] = phi i32 [ [[CONV2015]], [[COND_TRUE2014]] ], [ [[CONV2017]], [[COND_FALSE2016]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2020:%.*]] = trunc i32 [[COND2019]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2020]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP834:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2021:%.*]] = zext i16 [[TMP834]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP835:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2022:%.*]] = zext i16 [[TMP835]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2023:%.*]] = icmp eq i32 [[CONV2021]], [[CONV2022]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2023]], label [[IF_THEN2025:%.*]], label [[IF_END2026:%.*]]
|
|
// SIMD-ONLY0: if.then2025:
|
|
// SIMD-ONLY0-NEXT: [[TMP836:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP836]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2026]]
|
|
// SIMD-ONLY0: if.end2026:
|
|
// SIMD-ONLY0-NEXT: [[TMP837:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2027:%.*]] = zext i16 [[TMP837]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP838:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2028:%.*]] = zext i16 [[TMP838]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2029:%.*]] = icmp eq i32 [[CONV2027]], [[CONV2028]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2029]], label [[IF_THEN2031:%.*]], label [[IF_END2032:%.*]]
|
|
// SIMD-ONLY0: if.then2031:
|
|
// SIMD-ONLY0-NEXT: [[TMP839:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP839]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2032]]
|
|
// SIMD-ONLY0: if.end2032:
|
|
// SIMD-ONLY0-NEXT: [[TMP840:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2033:%.*]] = sext i16 [[TMP840]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP841:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2034:%.*]] = sext i16 [[TMP841]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2035:%.*]] = icmp sgt i32 [[CONV2033]], [[CONV2034]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2035]], label [[COND_TRUE2037:%.*]], label [[COND_FALSE2039:%.*]]
|
|
// SIMD-ONLY0: cond.true2037:
|
|
// SIMD-ONLY0-NEXT: [[TMP842:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2038:%.*]] = sext i16 [[TMP842]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2041:%.*]]
|
|
// SIMD-ONLY0: cond.false2039:
|
|
// SIMD-ONLY0-NEXT: [[TMP843:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2040:%.*]] = sext i16 [[TMP843]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2041]]
|
|
// SIMD-ONLY0: cond.end2041:
|
|
// SIMD-ONLY0-NEXT: [[COND2042:%.*]] = phi i32 [ [[CONV2038]], [[COND_TRUE2037]] ], [ [[CONV2040]], [[COND_FALSE2039]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2043:%.*]] = trunc i32 [[COND2042]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2043]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP844:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2044:%.*]] = sext i16 [[TMP844]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP845:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2045:%.*]] = sext i16 [[TMP845]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2046:%.*]] = icmp slt i32 [[CONV2044]], [[CONV2045]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2046]], label [[COND_TRUE2048:%.*]], label [[COND_FALSE2050:%.*]]
|
|
// SIMD-ONLY0: cond.true2048:
|
|
// SIMD-ONLY0-NEXT: [[TMP846:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2049:%.*]] = sext i16 [[TMP846]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2052:%.*]]
|
|
// SIMD-ONLY0: cond.false2050:
|
|
// SIMD-ONLY0-NEXT: [[TMP847:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2051:%.*]] = sext i16 [[TMP847]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2052]]
|
|
// SIMD-ONLY0: cond.end2052:
|
|
// SIMD-ONLY0-NEXT: [[COND2053:%.*]] = phi i32 [ [[CONV2049]], [[COND_TRUE2048]] ], [ [[CONV2051]], [[COND_FALSE2050]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2054:%.*]] = trunc i32 [[COND2053]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2054]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP848:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2055:%.*]] = sext i16 [[TMP848]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP849:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2056:%.*]] = sext i16 [[TMP849]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2057:%.*]] = icmp sgt i32 [[CONV2055]], [[CONV2056]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2057]], label [[COND_TRUE2059:%.*]], label [[COND_FALSE2061:%.*]]
|
|
// SIMD-ONLY0: cond.true2059:
|
|
// SIMD-ONLY0-NEXT: [[TMP850:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2060:%.*]] = sext i16 [[TMP850]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2063:%.*]]
|
|
// SIMD-ONLY0: cond.false2061:
|
|
// SIMD-ONLY0-NEXT: [[TMP851:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2062:%.*]] = sext i16 [[TMP851]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2063]]
|
|
// SIMD-ONLY0: cond.end2063:
|
|
// SIMD-ONLY0-NEXT: [[COND2064:%.*]] = phi i32 [ [[CONV2060]], [[COND_TRUE2059]] ], [ [[CONV2062]], [[COND_FALSE2061]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2065:%.*]] = trunc i32 [[COND2064]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2065]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP852:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2066:%.*]] = sext i16 [[TMP852]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP853:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2067:%.*]] = sext i16 [[TMP853]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2068:%.*]] = icmp slt i32 [[CONV2066]], [[CONV2067]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2068]], label [[COND_TRUE2070:%.*]], label [[COND_FALSE2072:%.*]]
|
|
// SIMD-ONLY0: cond.true2070:
|
|
// SIMD-ONLY0-NEXT: [[TMP854:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2071:%.*]] = sext i16 [[TMP854]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2074:%.*]]
|
|
// SIMD-ONLY0: cond.false2072:
|
|
// SIMD-ONLY0-NEXT: [[TMP855:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2073:%.*]] = sext i16 [[TMP855]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2074]]
|
|
// SIMD-ONLY0: cond.end2074:
|
|
// SIMD-ONLY0-NEXT: [[COND2075:%.*]] = phi i32 [ [[CONV2071]], [[COND_TRUE2070]] ], [ [[CONV2073]], [[COND_FALSE2072]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2076:%.*]] = trunc i32 [[COND2075]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2076]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP856:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2077:%.*]] = sext i16 [[TMP856]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP857:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2078:%.*]] = sext i16 [[TMP857]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2079:%.*]] = icmp sgt i32 [[CONV2077]], [[CONV2078]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2079]], label [[IF_THEN2081:%.*]], label [[IF_END2082:%.*]]
|
|
// SIMD-ONLY0: if.then2081:
|
|
// SIMD-ONLY0-NEXT: [[TMP858:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP858]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2082]]
|
|
// SIMD-ONLY0: if.end2082:
|
|
// SIMD-ONLY0-NEXT: [[TMP859:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2083:%.*]] = sext i16 [[TMP859]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP860:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2084:%.*]] = sext i16 [[TMP860]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2085:%.*]] = icmp slt i32 [[CONV2083]], [[CONV2084]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2085]], label [[IF_THEN2087:%.*]], label [[IF_END2088:%.*]]
|
|
// SIMD-ONLY0: if.then2087:
|
|
// SIMD-ONLY0-NEXT: [[TMP861:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP861]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2088]]
|
|
// SIMD-ONLY0: if.end2088:
|
|
// SIMD-ONLY0-NEXT: [[TMP862:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2089:%.*]] = sext i16 [[TMP862]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP863:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2090:%.*]] = sext i16 [[TMP863]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2091:%.*]] = icmp sgt i32 [[CONV2089]], [[CONV2090]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2091]], label [[IF_THEN2093:%.*]], label [[IF_END2094:%.*]]
|
|
// SIMD-ONLY0: if.then2093:
|
|
// SIMD-ONLY0-NEXT: [[TMP864:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP864]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2094]]
|
|
// SIMD-ONLY0: if.end2094:
|
|
// SIMD-ONLY0-NEXT: [[TMP865:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2095:%.*]] = sext i16 [[TMP865]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP866:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2096:%.*]] = sext i16 [[TMP866]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2097:%.*]] = icmp slt i32 [[CONV2095]], [[CONV2096]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2097]], label [[IF_THEN2099:%.*]], label [[IF_END2100:%.*]]
|
|
// SIMD-ONLY0: if.then2099:
|
|
// SIMD-ONLY0-NEXT: [[TMP867:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP867]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2100]]
|
|
// SIMD-ONLY0: if.end2100:
|
|
// SIMD-ONLY0-NEXT: [[TMP868:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2101:%.*]] = sext i16 [[TMP868]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP869:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2102:%.*]] = sext i16 [[TMP869]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2103:%.*]] = icmp eq i32 [[CONV2101]], [[CONV2102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2103]], label [[COND_TRUE2105:%.*]], label [[COND_FALSE2107:%.*]]
|
|
// SIMD-ONLY0: cond.true2105:
|
|
// SIMD-ONLY0-NEXT: [[TMP870:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2106:%.*]] = sext i16 [[TMP870]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2109:%.*]]
|
|
// SIMD-ONLY0: cond.false2107:
|
|
// SIMD-ONLY0-NEXT: [[TMP871:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2108:%.*]] = sext i16 [[TMP871]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2109]]
|
|
// SIMD-ONLY0: cond.end2109:
|
|
// SIMD-ONLY0-NEXT: [[COND2110:%.*]] = phi i32 [ [[CONV2106]], [[COND_TRUE2105]] ], [ [[CONV2108]], [[COND_FALSE2107]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2111:%.*]] = trunc i32 [[COND2110]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2111]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP872:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2112:%.*]] = sext i16 [[TMP872]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP873:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2113:%.*]] = sext i16 [[TMP873]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2114:%.*]] = icmp eq i32 [[CONV2112]], [[CONV2113]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2114]], label [[COND_TRUE2116:%.*]], label [[COND_FALSE2118:%.*]]
|
|
// SIMD-ONLY0: cond.true2116:
|
|
// SIMD-ONLY0-NEXT: [[TMP874:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2117:%.*]] = sext i16 [[TMP874]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2120:%.*]]
|
|
// SIMD-ONLY0: cond.false2118:
|
|
// SIMD-ONLY0-NEXT: [[TMP875:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2119:%.*]] = sext i16 [[TMP875]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2120]]
|
|
// SIMD-ONLY0: cond.end2120:
|
|
// SIMD-ONLY0-NEXT: [[COND2121:%.*]] = phi i32 [ [[CONV2117]], [[COND_TRUE2116]] ], [ [[CONV2119]], [[COND_FALSE2118]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2122:%.*]] = trunc i32 [[COND2121]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2122]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP876:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2123:%.*]] = sext i16 [[TMP876]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP877:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2124:%.*]] = sext i16 [[TMP877]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2125:%.*]] = icmp eq i32 [[CONV2123]], [[CONV2124]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2125]], label [[IF_THEN2127:%.*]], label [[IF_END2128:%.*]]
|
|
// SIMD-ONLY0: if.then2127:
|
|
// SIMD-ONLY0-NEXT: [[TMP878:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP878]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2128]]
|
|
// SIMD-ONLY0: if.end2128:
|
|
// SIMD-ONLY0-NEXT: [[TMP879:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2129:%.*]] = sext i16 [[TMP879]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP880:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2130:%.*]] = sext i16 [[TMP880]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2131:%.*]] = icmp eq i32 [[CONV2129]], [[CONV2130]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2131]], label [[IF_THEN2133:%.*]], label [[IF_END2134:%.*]]
|
|
// SIMD-ONLY0: if.then2133:
|
|
// SIMD-ONLY0-NEXT: [[TMP881:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP881]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2134]]
|
|
// SIMD-ONLY0: if.end2134:
|
|
// SIMD-ONLY0-NEXT: [[TMP882:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2135:%.*]] = zext i16 [[TMP882]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP883:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2136:%.*]] = zext i16 [[TMP883]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2137:%.*]] = icmp sgt i32 [[CONV2135]], [[CONV2136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2137]], label [[COND_TRUE2139:%.*]], label [[COND_FALSE2141:%.*]]
|
|
// SIMD-ONLY0: cond.true2139:
|
|
// SIMD-ONLY0-NEXT: [[TMP884:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2140:%.*]] = zext i16 [[TMP884]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2143:%.*]]
|
|
// SIMD-ONLY0: cond.false2141:
|
|
// SIMD-ONLY0-NEXT: [[TMP885:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2142:%.*]] = zext i16 [[TMP885]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2143]]
|
|
// SIMD-ONLY0: cond.end2143:
|
|
// SIMD-ONLY0-NEXT: [[COND2144:%.*]] = phi i32 [ [[CONV2140]], [[COND_TRUE2139]] ], [ [[CONV2142]], [[COND_FALSE2141]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2145:%.*]] = trunc i32 [[COND2144]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2145]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP886:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2146:%.*]] = zext i16 [[TMP886]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP887:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2147:%.*]] = zext i16 [[TMP887]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2148:%.*]] = icmp slt i32 [[CONV2146]], [[CONV2147]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2148]], label [[COND_TRUE2150:%.*]], label [[COND_FALSE2152:%.*]]
|
|
// SIMD-ONLY0: cond.true2150:
|
|
// SIMD-ONLY0-NEXT: [[TMP888:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2151:%.*]] = zext i16 [[TMP888]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2154:%.*]]
|
|
// SIMD-ONLY0: cond.false2152:
|
|
// SIMD-ONLY0-NEXT: [[TMP889:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2153:%.*]] = zext i16 [[TMP889]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2154]]
|
|
// SIMD-ONLY0: cond.end2154:
|
|
// SIMD-ONLY0-NEXT: [[COND2155:%.*]] = phi i32 [ [[CONV2151]], [[COND_TRUE2150]] ], [ [[CONV2153]], [[COND_FALSE2152]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2156:%.*]] = trunc i32 [[COND2155]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2156]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP890:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2157:%.*]] = zext i16 [[TMP890]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP891:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2158:%.*]] = zext i16 [[TMP891]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2159:%.*]] = icmp sgt i32 [[CONV2157]], [[CONV2158]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2159]], label [[COND_TRUE2161:%.*]], label [[COND_FALSE2163:%.*]]
|
|
// SIMD-ONLY0: cond.true2161:
|
|
// SIMD-ONLY0-NEXT: [[TMP892:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2162:%.*]] = zext i16 [[TMP892]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2165:%.*]]
|
|
// SIMD-ONLY0: cond.false2163:
|
|
// SIMD-ONLY0-NEXT: [[TMP893:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2164:%.*]] = zext i16 [[TMP893]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2165]]
|
|
// SIMD-ONLY0: cond.end2165:
|
|
// SIMD-ONLY0-NEXT: [[COND2166:%.*]] = phi i32 [ [[CONV2162]], [[COND_TRUE2161]] ], [ [[CONV2164]], [[COND_FALSE2163]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2167:%.*]] = trunc i32 [[COND2166]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2167]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP894:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2168:%.*]] = zext i16 [[TMP894]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP895:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2169:%.*]] = zext i16 [[TMP895]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2170:%.*]] = icmp slt i32 [[CONV2168]], [[CONV2169]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2170]], label [[COND_TRUE2172:%.*]], label [[COND_FALSE2174:%.*]]
|
|
// SIMD-ONLY0: cond.true2172:
|
|
// SIMD-ONLY0-NEXT: [[TMP896:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2173:%.*]] = zext i16 [[TMP896]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2176:%.*]]
|
|
// SIMD-ONLY0: cond.false2174:
|
|
// SIMD-ONLY0-NEXT: [[TMP897:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2175:%.*]] = zext i16 [[TMP897]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2176]]
|
|
// SIMD-ONLY0: cond.end2176:
|
|
// SIMD-ONLY0-NEXT: [[COND2177:%.*]] = phi i32 [ [[CONV2173]], [[COND_TRUE2172]] ], [ [[CONV2175]], [[COND_FALSE2174]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2178:%.*]] = trunc i32 [[COND2177]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2178]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP898:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2179:%.*]] = zext i16 [[TMP898]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP899:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2180:%.*]] = zext i16 [[TMP899]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2181:%.*]] = icmp sgt i32 [[CONV2179]], [[CONV2180]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2181]], label [[IF_THEN2183:%.*]], label [[IF_END2184:%.*]]
|
|
// SIMD-ONLY0: if.then2183:
|
|
// SIMD-ONLY0-NEXT: [[TMP900:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP900]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2184]]
|
|
// SIMD-ONLY0: if.end2184:
|
|
// SIMD-ONLY0-NEXT: [[TMP901:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2185:%.*]] = zext i16 [[TMP901]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP902:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2186:%.*]] = zext i16 [[TMP902]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2187:%.*]] = icmp slt i32 [[CONV2185]], [[CONV2186]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2187]], label [[IF_THEN2189:%.*]], label [[IF_END2190:%.*]]
|
|
// SIMD-ONLY0: if.then2189:
|
|
// SIMD-ONLY0-NEXT: [[TMP903:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP903]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2190]]
|
|
// SIMD-ONLY0: if.end2190:
|
|
// SIMD-ONLY0-NEXT: [[TMP904:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2191:%.*]] = zext i16 [[TMP904]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP905:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2192:%.*]] = zext i16 [[TMP905]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2193:%.*]] = icmp sgt i32 [[CONV2191]], [[CONV2192]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2193]], label [[IF_THEN2195:%.*]], label [[IF_END2196:%.*]]
|
|
// SIMD-ONLY0: if.then2195:
|
|
// SIMD-ONLY0-NEXT: [[TMP906:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP906]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2196]]
|
|
// SIMD-ONLY0: if.end2196:
|
|
// SIMD-ONLY0-NEXT: [[TMP907:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2197:%.*]] = zext i16 [[TMP907]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP908:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2198:%.*]] = zext i16 [[TMP908]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2199:%.*]] = icmp slt i32 [[CONV2197]], [[CONV2198]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2199]], label [[IF_THEN2201:%.*]], label [[IF_END2202:%.*]]
|
|
// SIMD-ONLY0: if.then2201:
|
|
// SIMD-ONLY0-NEXT: [[TMP909:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP909]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2202]]
|
|
// SIMD-ONLY0: if.end2202:
|
|
// SIMD-ONLY0-NEXT: [[TMP910:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2203:%.*]] = zext i16 [[TMP910]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP911:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2204:%.*]] = zext i16 [[TMP911]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2205:%.*]] = icmp eq i32 [[CONV2203]], [[CONV2204]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2205]], label [[COND_TRUE2207:%.*]], label [[COND_FALSE2209:%.*]]
|
|
// SIMD-ONLY0: cond.true2207:
|
|
// SIMD-ONLY0-NEXT: [[TMP912:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2208:%.*]] = zext i16 [[TMP912]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2211:%.*]]
|
|
// SIMD-ONLY0: cond.false2209:
|
|
// SIMD-ONLY0-NEXT: [[TMP913:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2210:%.*]] = zext i16 [[TMP913]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2211]]
|
|
// SIMD-ONLY0: cond.end2211:
|
|
// SIMD-ONLY0-NEXT: [[COND2212:%.*]] = phi i32 [ [[CONV2208]], [[COND_TRUE2207]] ], [ [[CONV2210]], [[COND_FALSE2209]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2213:%.*]] = trunc i32 [[COND2212]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2213]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP914:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2214:%.*]] = zext i16 [[TMP914]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP915:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2215:%.*]] = zext i16 [[TMP915]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2216:%.*]] = icmp eq i32 [[CONV2214]], [[CONV2215]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2216]], label [[COND_TRUE2218:%.*]], label [[COND_FALSE2220:%.*]]
|
|
// SIMD-ONLY0: cond.true2218:
|
|
// SIMD-ONLY0-NEXT: [[TMP916:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2219:%.*]] = zext i16 [[TMP916]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2222:%.*]]
|
|
// SIMD-ONLY0: cond.false2220:
|
|
// SIMD-ONLY0-NEXT: [[TMP917:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2221:%.*]] = zext i16 [[TMP917]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2222]]
|
|
// SIMD-ONLY0: cond.end2222:
|
|
// SIMD-ONLY0-NEXT: [[COND2223:%.*]] = phi i32 [ [[CONV2219]], [[COND_TRUE2218]] ], [ [[CONV2221]], [[COND_FALSE2220]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2224:%.*]] = trunc i32 [[COND2223]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2224]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP918:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2225:%.*]] = zext i16 [[TMP918]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP919:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2226:%.*]] = zext i16 [[TMP919]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2227:%.*]] = icmp eq i32 [[CONV2225]], [[CONV2226]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2227]], label [[IF_THEN2229:%.*]], label [[IF_END2230:%.*]]
|
|
// SIMD-ONLY0: if.then2229:
|
|
// SIMD-ONLY0-NEXT: [[TMP920:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP920]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2230]]
|
|
// SIMD-ONLY0: if.end2230:
|
|
// SIMD-ONLY0-NEXT: [[TMP921:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2231:%.*]] = zext i16 [[TMP921]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP922:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2232:%.*]] = zext i16 [[TMP922]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2233:%.*]] = icmp eq i32 [[CONV2231]], [[CONV2232]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2233]], label [[IF_THEN2235:%.*]], label [[IF_END2236:%.*]]
|
|
// SIMD-ONLY0: if.then2235:
|
|
// SIMD-ONLY0-NEXT: [[TMP923:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP923]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2236]]
|
|
// SIMD-ONLY0: if.end2236:
|
|
// SIMD-ONLY0-NEXT: [[TMP924:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2237:%.*]] = sext i16 [[TMP924]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP925:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2238:%.*]] = sext i16 [[TMP925]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2239:%.*]] = icmp sgt i32 [[CONV2237]], [[CONV2238]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2239]], label [[COND_TRUE2241:%.*]], label [[COND_FALSE2243:%.*]]
|
|
// SIMD-ONLY0: cond.true2241:
|
|
// SIMD-ONLY0-NEXT: [[TMP926:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2242:%.*]] = sext i16 [[TMP926]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2245:%.*]]
|
|
// SIMD-ONLY0: cond.false2243:
|
|
// SIMD-ONLY0-NEXT: [[TMP927:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2244:%.*]] = sext i16 [[TMP927]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2245]]
|
|
// SIMD-ONLY0: cond.end2245:
|
|
// SIMD-ONLY0-NEXT: [[COND2246:%.*]] = phi i32 [ [[CONV2242]], [[COND_TRUE2241]] ], [ [[CONV2244]], [[COND_FALSE2243]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2247:%.*]] = trunc i32 [[COND2246]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2247]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP928:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2248:%.*]] = sext i16 [[TMP928]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP929:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2249:%.*]] = sext i16 [[TMP929]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2250:%.*]] = icmp slt i32 [[CONV2248]], [[CONV2249]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2250]], label [[COND_TRUE2252:%.*]], label [[COND_FALSE2254:%.*]]
|
|
// SIMD-ONLY0: cond.true2252:
|
|
// SIMD-ONLY0-NEXT: [[TMP930:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2253:%.*]] = sext i16 [[TMP930]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2256:%.*]]
|
|
// SIMD-ONLY0: cond.false2254:
|
|
// SIMD-ONLY0-NEXT: [[TMP931:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2255:%.*]] = sext i16 [[TMP931]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2256]]
|
|
// SIMD-ONLY0: cond.end2256:
|
|
// SIMD-ONLY0-NEXT: [[COND2257:%.*]] = phi i32 [ [[CONV2253]], [[COND_TRUE2252]] ], [ [[CONV2255]], [[COND_FALSE2254]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2258:%.*]] = trunc i32 [[COND2257]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2258]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP932:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2259:%.*]] = sext i16 [[TMP932]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP933:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2260:%.*]] = sext i16 [[TMP933]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2261:%.*]] = icmp sgt i32 [[CONV2259]], [[CONV2260]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2261]], label [[COND_TRUE2263:%.*]], label [[COND_FALSE2265:%.*]]
|
|
// SIMD-ONLY0: cond.true2263:
|
|
// SIMD-ONLY0-NEXT: [[TMP934:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2264:%.*]] = sext i16 [[TMP934]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2267:%.*]]
|
|
// SIMD-ONLY0: cond.false2265:
|
|
// SIMD-ONLY0-NEXT: [[TMP935:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2266:%.*]] = sext i16 [[TMP935]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2267]]
|
|
// SIMD-ONLY0: cond.end2267:
|
|
// SIMD-ONLY0-NEXT: [[COND2268:%.*]] = phi i32 [ [[CONV2264]], [[COND_TRUE2263]] ], [ [[CONV2266]], [[COND_FALSE2265]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2269:%.*]] = trunc i32 [[COND2268]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2269]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP936:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2270:%.*]] = sext i16 [[TMP936]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP937:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2271:%.*]] = sext i16 [[TMP937]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2272:%.*]] = icmp slt i32 [[CONV2270]], [[CONV2271]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2272]], label [[COND_TRUE2274:%.*]], label [[COND_FALSE2276:%.*]]
|
|
// SIMD-ONLY0: cond.true2274:
|
|
// SIMD-ONLY0-NEXT: [[TMP938:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2275:%.*]] = sext i16 [[TMP938]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2278:%.*]]
|
|
// SIMD-ONLY0: cond.false2276:
|
|
// SIMD-ONLY0-NEXT: [[TMP939:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2277:%.*]] = sext i16 [[TMP939]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2278]]
|
|
// SIMD-ONLY0: cond.end2278:
|
|
// SIMD-ONLY0-NEXT: [[COND2279:%.*]] = phi i32 [ [[CONV2275]], [[COND_TRUE2274]] ], [ [[CONV2277]], [[COND_FALSE2276]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2280:%.*]] = trunc i32 [[COND2279]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2280]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP940:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2281:%.*]] = sext i16 [[TMP940]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP941:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2282:%.*]] = sext i16 [[TMP941]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2283:%.*]] = icmp sgt i32 [[CONV2281]], [[CONV2282]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2283]], label [[IF_THEN2285:%.*]], label [[IF_END2286:%.*]]
|
|
// SIMD-ONLY0: if.then2285:
|
|
// SIMD-ONLY0-NEXT: [[TMP942:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP942]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2286]]
|
|
// SIMD-ONLY0: if.end2286:
|
|
// SIMD-ONLY0-NEXT: [[TMP943:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2287:%.*]] = sext i16 [[TMP943]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP944:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2288:%.*]] = sext i16 [[TMP944]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2289:%.*]] = icmp slt i32 [[CONV2287]], [[CONV2288]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2289]], label [[IF_THEN2291:%.*]], label [[IF_END2292:%.*]]
|
|
// SIMD-ONLY0: if.then2291:
|
|
// SIMD-ONLY0-NEXT: [[TMP945:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP945]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2292]]
|
|
// SIMD-ONLY0: if.end2292:
|
|
// SIMD-ONLY0-NEXT: [[TMP946:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2293:%.*]] = sext i16 [[TMP946]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP947:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2294:%.*]] = sext i16 [[TMP947]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2295:%.*]] = icmp sgt i32 [[CONV2293]], [[CONV2294]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2295]], label [[IF_THEN2297:%.*]], label [[IF_END2298:%.*]]
|
|
// SIMD-ONLY0: if.then2297:
|
|
// SIMD-ONLY0-NEXT: [[TMP948:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP948]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2298]]
|
|
// SIMD-ONLY0: if.end2298:
|
|
// SIMD-ONLY0-NEXT: [[TMP949:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2299:%.*]] = sext i16 [[TMP949]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP950:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2300:%.*]] = sext i16 [[TMP950]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2301:%.*]] = icmp slt i32 [[CONV2299]], [[CONV2300]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2301]], label [[IF_THEN2303:%.*]], label [[IF_END2304:%.*]]
|
|
// SIMD-ONLY0: if.then2303:
|
|
// SIMD-ONLY0-NEXT: [[TMP951:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP951]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2304]]
|
|
// SIMD-ONLY0: if.end2304:
|
|
// SIMD-ONLY0-NEXT: [[TMP952:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2305:%.*]] = sext i16 [[TMP952]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP953:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2306:%.*]] = sext i16 [[TMP953]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2307:%.*]] = icmp eq i32 [[CONV2305]], [[CONV2306]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2307]], label [[COND_TRUE2309:%.*]], label [[COND_FALSE2311:%.*]]
|
|
// SIMD-ONLY0: cond.true2309:
|
|
// SIMD-ONLY0-NEXT: [[TMP954:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2310:%.*]] = sext i16 [[TMP954]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2313:%.*]]
|
|
// SIMD-ONLY0: cond.false2311:
|
|
// SIMD-ONLY0-NEXT: [[TMP955:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2312:%.*]] = sext i16 [[TMP955]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2313]]
|
|
// SIMD-ONLY0: cond.end2313:
|
|
// SIMD-ONLY0-NEXT: [[COND2314:%.*]] = phi i32 [ [[CONV2310]], [[COND_TRUE2309]] ], [ [[CONV2312]], [[COND_FALSE2311]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2315:%.*]] = trunc i32 [[COND2314]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2315]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP956:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2316:%.*]] = sext i16 [[TMP956]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP957:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2317:%.*]] = sext i16 [[TMP957]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2318:%.*]] = icmp eq i32 [[CONV2316]], [[CONV2317]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2318]], label [[COND_TRUE2320:%.*]], label [[COND_FALSE2322:%.*]]
|
|
// SIMD-ONLY0: cond.true2320:
|
|
// SIMD-ONLY0-NEXT: [[TMP958:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2321:%.*]] = sext i16 [[TMP958]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2324:%.*]]
|
|
// SIMD-ONLY0: cond.false2322:
|
|
// SIMD-ONLY0-NEXT: [[TMP959:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2323:%.*]] = sext i16 [[TMP959]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2324]]
|
|
// SIMD-ONLY0: cond.end2324:
|
|
// SIMD-ONLY0-NEXT: [[COND2325:%.*]] = phi i32 [ [[CONV2321]], [[COND_TRUE2320]] ], [ [[CONV2323]], [[COND_FALSE2322]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2326:%.*]] = trunc i32 [[COND2325]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2326]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP960:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2327:%.*]] = sext i16 [[TMP960]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP961:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2328:%.*]] = sext i16 [[TMP961]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2329:%.*]] = icmp eq i32 [[CONV2327]], [[CONV2328]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2329]], label [[IF_THEN2331:%.*]], label [[IF_END2332:%.*]]
|
|
// SIMD-ONLY0: if.then2331:
|
|
// SIMD-ONLY0-NEXT: [[TMP962:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP962]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2332]]
|
|
// SIMD-ONLY0: if.end2332:
|
|
// SIMD-ONLY0-NEXT: [[TMP963:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2333:%.*]] = sext i16 [[TMP963]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP964:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2334:%.*]] = sext i16 [[TMP964]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2335:%.*]] = icmp eq i32 [[CONV2333]], [[CONV2334]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2335]], label [[IF_THEN2337:%.*]], label [[IF_END2338:%.*]]
|
|
// SIMD-ONLY0: if.then2337:
|
|
// SIMD-ONLY0-NEXT: [[TMP965:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP965]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2338]]
|
|
// SIMD-ONLY0: if.end2338:
|
|
// SIMD-ONLY0-NEXT: [[TMP966:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2339:%.*]] = zext i16 [[TMP966]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP967:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2340:%.*]] = zext i16 [[TMP967]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2341:%.*]] = icmp sgt i32 [[CONV2339]], [[CONV2340]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2341]], label [[COND_TRUE2343:%.*]], label [[COND_FALSE2345:%.*]]
|
|
// SIMD-ONLY0: cond.true2343:
|
|
// SIMD-ONLY0-NEXT: [[TMP968:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2344:%.*]] = zext i16 [[TMP968]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2347:%.*]]
|
|
// SIMD-ONLY0: cond.false2345:
|
|
// SIMD-ONLY0-NEXT: [[TMP969:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2346:%.*]] = zext i16 [[TMP969]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2347]]
|
|
// SIMD-ONLY0: cond.end2347:
|
|
// SIMD-ONLY0-NEXT: [[COND2348:%.*]] = phi i32 [ [[CONV2344]], [[COND_TRUE2343]] ], [ [[CONV2346]], [[COND_FALSE2345]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2349:%.*]] = trunc i32 [[COND2348]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2349]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP970:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2350:%.*]] = zext i16 [[TMP970]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP971:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2351:%.*]] = zext i16 [[TMP971]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2352:%.*]] = icmp slt i32 [[CONV2350]], [[CONV2351]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2352]], label [[COND_TRUE2354:%.*]], label [[COND_FALSE2356:%.*]]
|
|
// SIMD-ONLY0: cond.true2354:
|
|
// SIMD-ONLY0-NEXT: [[TMP972:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2355:%.*]] = zext i16 [[TMP972]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2358:%.*]]
|
|
// SIMD-ONLY0: cond.false2356:
|
|
// SIMD-ONLY0-NEXT: [[TMP973:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2357:%.*]] = zext i16 [[TMP973]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2358]]
|
|
// SIMD-ONLY0: cond.end2358:
|
|
// SIMD-ONLY0-NEXT: [[COND2359:%.*]] = phi i32 [ [[CONV2355]], [[COND_TRUE2354]] ], [ [[CONV2357]], [[COND_FALSE2356]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2360:%.*]] = trunc i32 [[COND2359]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2360]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP974:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2361:%.*]] = zext i16 [[TMP974]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP975:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2362:%.*]] = zext i16 [[TMP975]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2363:%.*]] = icmp sgt i32 [[CONV2361]], [[CONV2362]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2363]], label [[COND_TRUE2365:%.*]], label [[COND_FALSE2367:%.*]]
|
|
// SIMD-ONLY0: cond.true2365:
|
|
// SIMD-ONLY0-NEXT: [[TMP976:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2366:%.*]] = zext i16 [[TMP976]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2369:%.*]]
|
|
// SIMD-ONLY0: cond.false2367:
|
|
// SIMD-ONLY0-NEXT: [[TMP977:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2368:%.*]] = zext i16 [[TMP977]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2369]]
|
|
// SIMD-ONLY0: cond.end2369:
|
|
// SIMD-ONLY0-NEXT: [[COND2370:%.*]] = phi i32 [ [[CONV2366]], [[COND_TRUE2365]] ], [ [[CONV2368]], [[COND_FALSE2367]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2371:%.*]] = trunc i32 [[COND2370]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2371]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP978:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2372:%.*]] = zext i16 [[TMP978]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP979:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2373:%.*]] = zext i16 [[TMP979]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2374:%.*]] = icmp slt i32 [[CONV2372]], [[CONV2373]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2374]], label [[COND_TRUE2376:%.*]], label [[COND_FALSE2378:%.*]]
|
|
// SIMD-ONLY0: cond.true2376:
|
|
// SIMD-ONLY0-NEXT: [[TMP980:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2377:%.*]] = zext i16 [[TMP980]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2380:%.*]]
|
|
// SIMD-ONLY0: cond.false2378:
|
|
// SIMD-ONLY0-NEXT: [[TMP981:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2379:%.*]] = zext i16 [[TMP981]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2380]]
|
|
// SIMD-ONLY0: cond.end2380:
|
|
// SIMD-ONLY0-NEXT: [[COND2381:%.*]] = phi i32 [ [[CONV2377]], [[COND_TRUE2376]] ], [ [[CONV2379]], [[COND_FALSE2378]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2382:%.*]] = trunc i32 [[COND2381]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2382]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP982:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2383:%.*]] = zext i16 [[TMP982]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP983:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2384:%.*]] = zext i16 [[TMP983]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2385:%.*]] = icmp sgt i32 [[CONV2383]], [[CONV2384]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2385]], label [[IF_THEN2387:%.*]], label [[IF_END2388:%.*]]
|
|
// SIMD-ONLY0: if.then2387:
|
|
// SIMD-ONLY0-NEXT: [[TMP984:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP984]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2388]]
|
|
// SIMD-ONLY0: if.end2388:
|
|
// SIMD-ONLY0-NEXT: [[TMP985:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2389:%.*]] = zext i16 [[TMP985]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP986:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2390:%.*]] = zext i16 [[TMP986]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2391:%.*]] = icmp slt i32 [[CONV2389]], [[CONV2390]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2391]], label [[IF_THEN2393:%.*]], label [[IF_END2394:%.*]]
|
|
// SIMD-ONLY0: if.then2393:
|
|
// SIMD-ONLY0-NEXT: [[TMP987:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP987]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2394]]
|
|
// SIMD-ONLY0: if.end2394:
|
|
// SIMD-ONLY0-NEXT: [[TMP988:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2395:%.*]] = zext i16 [[TMP988]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP989:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2396:%.*]] = zext i16 [[TMP989]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2397:%.*]] = icmp sgt i32 [[CONV2395]], [[CONV2396]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2397]], label [[IF_THEN2399:%.*]], label [[IF_END2400:%.*]]
|
|
// SIMD-ONLY0: if.then2399:
|
|
// SIMD-ONLY0-NEXT: [[TMP990:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP990]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2400]]
|
|
// SIMD-ONLY0: if.end2400:
|
|
// SIMD-ONLY0-NEXT: [[TMP991:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2401:%.*]] = zext i16 [[TMP991]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP992:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2402:%.*]] = zext i16 [[TMP992]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2403:%.*]] = icmp slt i32 [[CONV2401]], [[CONV2402]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2403]], label [[IF_THEN2405:%.*]], label [[IF_END2406:%.*]]
|
|
// SIMD-ONLY0: if.then2405:
|
|
// SIMD-ONLY0-NEXT: [[TMP993:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP993]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2406]]
|
|
// SIMD-ONLY0: if.end2406:
|
|
// SIMD-ONLY0-NEXT: [[TMP994:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2407:%.*]] = zext i16 [[TMP994]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP995:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2408:%.*]] = zext i16 [[TMP995]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2409:%.*]] = icmp eq i32 [[CONV2407]], [[CONV2408]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2409]], label [[COND_TRUE2411:%.*]], label [[COND_FALSE2413:%.*]]
|
|
// SIMD-ONLY0: cond.true2411:
|
|
// SIMD-ONLY0-NEXT: [[TMP996:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2412:%.*]] = zext i16 [[TMP996]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2415:%.*]]
|
|
// SIMD-ONLY0: cond.false2413:
|
|
// SIMD-ONLY0-NEXT: [[TMP997:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2414:%.*]] = zext i16 [[TMP997]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2415]]
|
|
// SIMD-ONLY0: cond.end2415:
|
|
// SIMD-ONLY0-NEXT: [[COND2416:%.*]] = phi i32 [ [[CONV2412]], [[COND_TRUE2411]] ], [ [[CONV2414]], [[COND_FALSE2413]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2417:%.*]] = trunc i32 [[COND2416]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2417]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP998:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2418:%.*]] = zext i16 [[TMP998]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP999:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2419:%.*]] = zext i16 [[TMP999]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2420:%.*]] = icmp eq i32 [[CONV2418]], [[CONV2419]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2420]], label [[COND_TRUE2422:%.*]], label [[COND_FALSE2424:%.*]]
|
|
// SIMD-ONLY0: cond.true2422:
|
|
// SIMD-ONLY0-NEXT: [[TMP1000:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2423:%.*]] = zext i16 [[TMP1000]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2426:%.*]]
|
|
// SIMD-ONLY0: cond.false2424:
|
|
// SIMD-ONLY0-NEXT: [[TMP1001:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2425:%.*]] = zext i16 [[TMP1001]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2426]]
|
|
// SIMD-ONLY0: cond.end2426:
|
|
// SIMD-ONLY0-NEXT: [[COND2427:%.*]] = phi i32 [ [[CONV2423]], [[COND_TRUE2422]] ], [ [[CONV2425]], [[COND_FALSE2424]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV2428:%.*]] = trunc i32 [[COND2427]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2428]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1002:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2429:%.*]] = zext i16 [[TMP1002]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1003:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2430:%.*]] = zext i16 [[TMP1003]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2431:%.*]] = icmp eq i32 [[CONV2429]], [[CONV2430]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2431]], label [[IF_THEN2433:%.*]], label [[IF_END2434:%.*]]
|
|
// SIMD-ONLY0: if.then2433:
|
|
// SIMD-ONLY0-NEXT: [[TMP1004:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1004]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2434]]
|
|
// SIMD-ONLY0: if.end2434:
|
|
// SIMD-ONLY0-NEXT: [[TMP1005:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2435:%.*]] = zext i16 [[TMP1005]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1006:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2436:%.*]] = zext i16 [[TMP1006]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2437:%.*]] = icmp eq i32 [[CONV2435]], [[CONV2436]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2437]], label [[IF_THEN2439:%.*]], label [[IF_END2440:%.*]]
|
|
// SIMD-ONLY0: if.then2439:
|
|
// SIMD-ONLY0-NEXT: [[TMP1007:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1007]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2440]]
|
|
// SIMD-ONLY0: if.end2440:
|
|
// SIMD-ONLY0-NEXT: [[TMP1008:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1009:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2441:%.*]] = icmp sgt i32 [[TMP1008]], [[TMP1009]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2441]], label [[COND_TRUE2443:%.*]], label [[COND_FALSE2444:%.*]]
|
|
// SIMD-ONLY0: cond.true2443:
|
|
// SIMD-ONLY0-NEXT: [[TMP1010:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2445:%.*]]
|
|
// SIMD-ONLY0: cond.false2444:
|
|
// SIMD-ONLY0-NEXT: [[TMP1011:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2445]]
|
|
// SIMD-ONLY0: cond.end2445:
|
|
// SIMD-ONLY0-NEXT: [[COND2446:%.*]] = phi i32 [ [[TMP1010]], [[COND_TRUE2443]] ], [ [[TMP1011]], [[COND_FALSE2444]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2446]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1012:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1013:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2447:%.*]] = icmp slt i32 [[TMP1012]], [[TMP1013]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2447]], label [[COND_TRUE2449:%.*]], label [[COND_FALSE2450:%.*]]
|
|
// SIMD-ONLY0: cond.true2449:
|
|
// SIMD-ONLY0-NEXT: [[TMP1014:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2451:%.*]]
|
|
// SIMD-ONLY0: cond.false2450:
|
|
// SIMD-ONLY0-NEXT: [[TMP1015:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2451]]
|
|
// SIMD-ONLY0: cond.end2451:
|
|
// SIMD-ONLY0-NEXT: [[COND2452:%.*]] = phi i32 [ [[TMP1014]], [[COND_TRUE2449]] ], [ [[TMP1015]], [[COND_FALSE2450]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2452]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1016:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1017:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2453:%.*]] = icmp sgt i32 [[TMP1016]], [[TMP1017]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2453]], label [[COND_TRUE2455:%.*]], label [[COND_FALSE2456:%.*]]
|
|
// SIMD-ONLY0: cond.true2455:
|
|
// SIMD-ONLY0-NEXT: [[TMP1018:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2457:%.*]]
|
|
// SIMD-ONLY0: cond.false2456:
|
|
// SIMD-ONLY0-NEXT: [[TMP1019:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2457]]
|
|
// SIMD-ONLY0: cond.end2457:
|
|
// SIMD-ONLY0-NEXT: [[COND2458:%.*]] = phi i32 [ [[TMP1018]], [[COND_TRUE2455]] ], [ [[TMP1019]], [[COND_FALSE2456]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2458]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1020:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1021:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2459:%.*]] = icmp slt i32 [[TMP1020]], [[TMP1021]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2459]], label [[COND_TRUE2461:%.*]], label [[COND_FALSE2462:%.*]]
|
|
// SIMD-ONLY0: cond.true2461:
|
|
// SIMD-ONLY0-NEXT: [[TMP1022:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2463:%.*]]
|
|
// SIMD-ONLY0: cond.false2462:
|
|
// SIMD-ONLY0-NEXT: [[TMP1023:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2463]]
|
|
// SIMD-ONLY0: cond.end2463:
|
|
// SIMD-ONLY0-NEXT: [[COND2464:%.*]] = phi i32 [ [[TMP1022]], [[COND_TRUE2461]] ], [ [[TMP1023]], [[COND_FALSE2462]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2464]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1024:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1025:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2465:%.*]] = icmp sgt i32 [[TMP1024]], [[TMP1025]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2465]], label [[IF_THEN2467:%.*]], label [[IF_END2468:%.*]]
|
|
// SIMD-ONLY0: if.then2467:
|
|
// SIMD-ONLY0-NEXT: [[TMP1026:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1026]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2468]]
|
|
// SIMD-ONLY0: if.end2468:
|
|
// SIMD-ONLY0-NEXT: [[TMP1027:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1028:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2469:%.*]] = icmp slt i32 [[TMP1027]], [[TMP1028]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2469]], label [[IF_THEN2471:%.*]], label [[IF_END2472:%.*]]
|
|
// SIMD-ONLY0: if.then2471:
|
|
// SIMD-ONLY0-NEXT: [[TMP1029:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1029]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2472]]
|
|
// SIMD-ONLY0: if.end2472:
|
|
// SIMD-ONLY0-NEXT: [[TMP1030:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1031:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2473:%.*]] = icmp sgt i32 [[TMP1030]], [[TMP1031]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2473]], label [[IF_THEN2475:%.*]], label [[IF_END2476:%.*]]
|
|
// SIMD-ONLY0: if.then2475:
|
|
// SIMD-ONLY0-NEXT: [[TMP1032:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1032]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2476]]
|
|
// SIMD-ONLY0: if.end2476:
|
|
// SIMD-ONLY0-NEXT: [[TMP1033:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1034:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2477:%.*]] = icmp slt i32 [[TMP1033]], [[TMP1034]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2477]], label [[IF_THEN2479:%.*]], label [[IF_END2480:%.*]]
|
|
// SIMD-ONLY0: if.then2479:
|
|
// SIMD-ONLY0-NEXT: [[TMP1035:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1035]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2480]]
|
|
// SIMD-ONLY0: if.end2480:
|
|
// SIMD-ONLY0-NEXT: [[TMP1036:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1037:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2481:%.*]] = icmp eq i32 [[TMP1036]], [[TMP1037]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2481]], label [[COND_TRUE2483:%.*]], label [[COND_FALSE2484:%.*]]
|
|
// SIMD-ONLY0: cond.true2483:
|
|
// SIMD-ONLY0-NEXT: [[TMP1038:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2485:%.*]]
|
|
// SIMD-ONLY0: cond.false2484:
|
|
// SIMD-ONLY0-NEXT: [[TMP1039:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2485]]
|
|
// SIMD-ONLY0: cond.end2485:
|
|
// SIMD-ONLY0-NEXT: [[COND2486:%.*]] = phi i32 [ [[TMP1038]], [[COND_TRUE2483]] ], [ [[TMP1039]], [[COND_FALSE2484]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2486]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1040:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1041:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2487:%.*]] = icmp eq i32 [[TMP1040]], [[TMP1041]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2487]], label [[COND_TRUE2489:%.*]], label [[COND_FALSE2490:%.*]]
|
|
// SIMD-ONLY0: cond.true2489:
|
|
// SIMD-ONLY0-NEXT: [[TMP1042:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2491:%.*]]
|
|
// SIMD-ONLY0: cond.false2490:
|
|
// SIMD-ONLY0-NEXT: [[TMP1043:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2491]]
|
|
// SIMD-ONLY0: cond.end2491:
|
|
// SIMD-ONLY0-NEXT: [[COND2492:%.*]] = phi i32 [ [[TMP1042]], [[COND_TRUE2489]] ], [ [[TMP1043]], [[COND_FALSE2490]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2492]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1044:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1045:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2493:%.*]] = icmp eq i32 [[TMP1044]], [[TMP1045]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2493]], label [[IF_THEN2495:%.*]], label [[IF_END2496:%.*]]
|
|
// SIMD-ONLY0: if.then2495:
|
|
// SIMD-ONLY0-NEXT: [[TMP1046:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1046]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2496]]
|
|
// SIMD-ONLY0: if.end2496:
|
|
// SIMD-ONLY0-NEXT: [[TMP1047:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1048:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2497:%.*]] = icmp eq i32 [[TMP1047]], [[TMP1048]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2497]], label [[IF_THEN2499:%.*]], label [[IF_END2500:%.*]]
|
|
// SIMD-ONLY0: if.then2499:
|
|
// SIMD-ONLY0-NEXT: [[TMP1049:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1049]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2500]]
|
|
// SIMD-ONLY0: if.end2500:
|
|
// SIMD-ONLY0-NEXT: [[TMP1050:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1051:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2501:%.*]] = icmp ugt i32 [[TMP1050]], [[TMP1051]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2501]], label [[COND_TRUE2503:%.*]], label [[COND_FALSE2504:%.*]]
|
|
// SIMD-ONLY0: cond.true2503:
|
|
// SIMD-ONLY0-NEXT: [[TMP1052:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2505:%.*]]
|
|
// SIMD-ONLY0: cond.false2504:
|
|
// SIMD-ONLY0-NEXT: [[TMP1053:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2505]]
|
|
// SIMD-ONLY0: cond.end2505:
|
|
// SIMD-ONLY0-NEXT: [[COND2506:%.*]] = phi i32 [ [[TMP1052]], [[COND_TRUE2503]] ], [ [[TMP1053]], [[COND_FALSE2504]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2506]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1054:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1055:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2507:%.*]] = icmp ult i32 [[TMP1054]], [[TMP1055]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2507]], label [[COND_TRUE2509:%.*]], label [[COND_FALSE2510:%.*]]
|
|
// SIMD-ONLY0: cond.true2509:
|
|
// SIMD-ONLY0-NEXT: [[TMP1056:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2511:%.*]]
|
|
// SIMD-ONLY0: cond.false2510:
|
|
// SIMD-ONLY0-NEXT: [[TMP1057:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2511]]
|
|
// SIMD-ONLY0: cond.end2511:
|
|
// SIMD-ONLY0-NEXT: [[COND2512:%.*]] = phi i32 [ [[TMP1056]], [[COND_TRUE2509]] ], [ [[TMP1057]], [[COND_FALSE2510]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2512]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1058:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1059:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2513:%.*]] = icmp ugt i32 [[TMP1058]], [[TMP1059]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2513]], label [[COND_TRUE2515:%.*]], label [[COND_FALSE2516:%.*]]
|
|
// SIMD-ONLY0: cond.true2515:
|
|
// SIMD-ONLY0-NEXT: [[TMP1060:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2517:%.*]]
|
|
// SIMD-ONLY0: cond.false2516:
|
|
// SIMD-ONLY0-NEXT: [[TMP1061:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2517]]
|
|
// SIMD-ONLY0: cond.end2517:
|
|
// SIMD-ONLY0-NEXT: [[COND2518:%.*]] = phi i32 [ [[TMP1060]], [[COND_TRUE2515]] ], [ [[TMP1061]], [[COND_FALSE2516]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2518]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1062:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1063:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2519:%.*]] = icmp ult i32 [[TMP1062]], [[TMP1063]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2519]], label [[COND_TRUE2521:%.*]], label [[COND_FALSE2522:%.*]]
|
|
// SIMD-ONLY0: cond.true2521:
|
|
// SIMD-ONLY0-NEXT: [[TMP1064:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2523:%.*]]
|
|
// SIMD-ONLY0: cond.false2522:
|
|
// SIMD-ONLY0-NEXT: [[TMP1065:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2523]]
|
|
// SIMD-ONLY0: cond.end2523:
|
|
// SIMD-ONLY0-NEXT: [[COND2524:%.*]] = phi i32 [ [[TMP1064]], [[COND_TRUE2521]] ], [ [[TMP1065]], [[COND_FALSE2522]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2524]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1066:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1067:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2525:%.*]] = icmp ugt i32 [[TMP1066]], [[TMP1067]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2525]], label [[IF_THEN2527:%.*]], label [[IF_END2528:%.*]]
|
|
// SIMD-ONLY0: if.then2527:
|
|
// SIMD-ONLY0-NEXT: [[TMP1068:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1068]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2528]]
|
|
// SIMD-ONLY0: if.end2528:
|
|
// SIMD-ONLY0-NEXT: [[TMP1069:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1070:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2529:%.*]] = icmp ult i32 [[TMP1069]], [[TMP1070]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2529]], label [[IF_THEN2531:%.*]], label [[IF_END2532:%.*]]
|
|
// SIMD-ONLY0: if.then2531:
|
|
// SIMD-ONLY0-NEXT: [[TMP1071:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1071]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2532]]
|
|
// SIMD-ONLY0: if.end2532:
|
|
// SIMD-ONLY0-NEXT: [[TMP1072:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1073:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2533:%.*]] = icmp ugt i32 [[TMP1072]], [[TMP1073]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2533]], label [[IF_THEN2535:%.*]], label [[IF_END2536:%.*]]
|
|
// SIMD-ONLY0: if.then2535:
|
|
// SIMD-ONLY0-NEXT: [[TMP1074:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1074]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2536]]
|
|
// SIMD-ONLY0: if.end2536:
|
|
// SIMD-ONLY0-NEXT: [[TMP1075:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1076:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2537:%.*]] = icmp ult i32 [[TMP1075]], [[TMP1076]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2537]], label [[IF_THEN2539:%.*]], label [[IF_END2540:%.*]]
|
|
// SIMD-ONLY0: if.then2539:
|
|
// SIMD-ONLY0-NEXT: [[TMP1077:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1077]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2540]]
|
|
// SIMD-ONLY0: if.end2540:
|
|
// SIMD-ONLY0-NEXT: [[TMP1078:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1079:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2541:%.*]] = icmp eq i32 [[TMP1078]], [[TMP1079]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2541]], label [[COND_TRUE2543:%.*]], label [[COND_FALSE2544:%.*]]
|
|
// SIMD-ONLY0: cond.true2543:
|
|
// SIMD-ONLY0-NEXT: [[TMP1080:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2545:%.*]]
|
|
// SIMD-ONLY0: cond.false2544:
|
|
// SIMD-ONLY0-NEXT: [[TMP1081:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2545]]
|
|
// SIMD-ONLY0: cond.end2545:
|
|
// SIMD-ONLY0-NEXT: [[COND2546:%.*]] = phi i32 [ [[TMP1080]], [[COND_TRUE2543]] ], [ [[TMP1081]], [[COND_FALSE2544]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2546]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1082:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1083:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2547:%.*]] = icmp eq i32 [[TMP1082]], [[TMP1083]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2547]], label [[COND_TRUE2549:%.*]], label [[COND_FALSE2550:%.*]]
|
|
// SIMD-ONLY0: cond.true2549:
|
|
// SIMD-ONLY0-NEXT: [[TMP1084:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2551:%.*]]
|
|
// SIMD-ONLY0: cond.false2550:
|
|
// SIMD-ONLY0-NEXT: [[TMP1085:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2551]]
|
|
// SIMD-ONLY0: cond.end2551:
|
|
// SIMD-ONLY0-NEXT: [[COND2552:%.*]] = phi i32 [ [[TMP1084]], [[COND_TRUE2549]] ], [ [[TMP1085]], [[COND_FALSE2550]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2552]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1086:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1087:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2553:%.*]] = icmp eq i32 [[TMP1086]], [[TMP1087]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2553]], label [[IF_THEN2555:%.*]], label [[IF_END2556:%.*]]
|
|
// SIMD-ONLY0: if.then2555:
|
|
// SIMD-ONLY0-NEXT: [[TMP1088:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1088]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2556]]
|
|
// SIMD-ONLY0: if.end2556:
|
|
// SIMD-ONLY0-NEXT: [[TMP1089:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1090:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2557:%.*]] = icmp eq i32 [[TMP1089]], [[TMP1090]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2557]], label [[IF_THEN2559:%.*]], label [[IF_END2560:%.*]]
|
|
// SIMD-ONLY0: if.then2559:
|
|
// SIMD-ONLY0-NEXT: [[TMP1091:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1091]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2560]]
|
|
// SIMD-ONLY0: if.end2560:
|
|
// SIMD-ONLY0-NEXT: [[TMP1092:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1093:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2561:%.*]] = icmp sgt i32 [[TMP1092]], [[TMP1093]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2561]], label [[COND_TRUE2563:%.*]], label [[COND_FALSE2564:%.*]]
|
|
// SIMD-ONLY0: cond.true2563:
|
|
// SIMD-ONLY0-NEXT: [[TMP1094:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2565:%.*]]
|
|
// SIMD-ONLY0: cond.false2564:
|
|
// SIMD-ONLY0-NEXT: [[TMP1095:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2565]]
|
|
// SIMD-ONLY0: cond.end2565:
|
|
// SIMD-ONLY0-NEXT: [[COND2566:%.*]] = phi i32 [ [[TMP1094]], [[COND_TRUE2563]] ], [ [[TMP1095]], [[COND_FALSE2564]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2566]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1096:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1097:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2567:%.*]] = icmp slt i32 [[TMP1096]], [[TMP1097]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2567]], label [[COND_TRUE2569:%.*]], label [[COND_FALSE2570:%.*]]
|
|
// SIMD-ONLY0: cond.true2569:
|
|
// SIMD-ONLY0-NEXT: [[TMP1098:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2571:%.*]]
|
|
// SIMD-ONLY0: cond.false2570:
|
|
// SIMD-ONLY0-NEXT: [[TMP1099:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2571]]
|
|
// SIMD-ONLY0: cond.end2571:
|
|
// SIMD-ONLY0-NEXT: [[COND2572:%.*]] = phi i32 [ [[TMP1098]], [[COND_TRUE2569]] ], [ [[TMP1099]], [[COND_FALSE2570]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2572]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1100:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1101:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2573:%.*]] = icmp sgt i32 [[TMP1100]], [[TMP1101]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2573]], label [[COND_TRUE2575:%.*]], label [[COND_FALSE2576:%.*]]
|
|
// SIMD-ONLY0: cond.true2575:
|
|
// SIMD-ONLY0-NEXT: [[TMP1102:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2577:%.*]]
|
|
// SIMD-ONLY0: cond.false2576:
|
|
// SIMD-ONLY0-NEXT: [[TMP1103:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2577]]
|
|
// SIMD-ONLY0: cond.end2577:
|
|
// SIMD-ONLY0-NEXT: [[COND2578:%.*]] = phi i32 [ [[TMP1102]], [[COND_TRUE2575]] ], [ [[TMP1103]], [[COND_FALSE2576]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2578]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1104:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1105:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2579:%.*]] = icmp slt i32 [[TMP1104]], [[TMP1105]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2579]], label [[COND_TRUE2581:%.*]], label [[COND_FALSE2582:%.*]]
|
|
// SIMD-ONLY0: cond.true2581:
|
|
// SIMD-ONLY0-NEXT: [[TMP1106:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2583:%.*]]
|
|
// SIMD-ONLY0: cond.false2582:
|
|
// SIMD-ONLY0-NEXT: [[TMP1107:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2583]]
|
|
// SIMD-ONLY0: cond.end2583:
|
|
// SIMD-ONLY0-NEXT: [[COND2584:%.*]] = phi i32 [ [[TMP1106]], [[COND_TRUE2581]] ], [ [[TMP1107]], [[COND_FALSE2582]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2584]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1108:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1109:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2585:%.*]] = icmp sgt i32 [[TMP1108]], [[TMP1109]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2585]], label [[IF_THEN2587:%.*]], label [[IF_END2588:%.*]]
|
|
// SIMD-ONLY0: if.then2587:
|
|
// SIMD-ONLY0-NEXT: [[TMP1110:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1110]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2588]]
|
|
// SIMD-ONLY0: if.end2588:
|
|
// SIMD-ONLY0-NEXT: [[TMP1111:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1112:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2589:%.*]] = icmp slt i32 [[TMP1111]], [[TMP1112]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2589]], label [[IF_THEN2591:%.*]], label [[IF_END2592:%.*]]
|
|
// SIMD-ONLY0: if.then2591:
|
|
// SIMD-ONLY0-NEXT: [[TMP1113:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1113]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2592]]
|
|
// SIMD-ONLY0: if.end2592:
|
|
// SIMD-ONLY0-NEXT: [[TMP1114:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1115:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2593:%.*]] = icmp sgt i32 [[TMP1114]], [[TMP1115]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2593]], label [[IF_THEN2595:%.*]], label [[IF_END2596:%.*]]
|
|
// SIMD-ONLY0: if.then2595:
|
|
// SIMD-ONLY0-NEXT: [[TMP1116:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1116]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2596]]
|
|
// SIMD-ONLY0: if.end2596:
|
|
// SIMD-ONLY0-NEXT: [[TMP1117:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1118:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2597:%.*]] = icmp slt i32 [[TMP1117]], [[TMP1118]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2597]], label [[IF_THEN2599:%.*]], label [[IF_END2600:%.*]]
|
|
// SIMD-ONLY0: if.then2599:
|
|
// SIMD-ONLY0-NEXT: [[TMP1119:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1119]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2600]]
|
|
// SIMD-ONLY0: if.end2600:
|
|
// SIMD-ONLY0-NEXT: [[TMP1120:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1121:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2601:%.*]] = icmp eq i32 [[TMP1120]], [[TMP1121]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2601]], label [[COND_TRUE2603:%.*]], label [[COND_FALSE2604:%.*]]
|
|
// SIMD-ONLY0: cond.true2603:
|
|
// SIMD-ONLY0-NEXT: [[TMP1122:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2605:%.*]]
|
|
// SIMD-ONLY0: cond.false2604:
|
|
// SIMD-ONLY0-NEXT: [[TMP1123:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2605]]
|
|
// SIMD-ONLY0: cond.end2605:
|
|
// SIMD-ONLY0-NEXT: [[COND2606:%.*]] = phi i32 [ [[TMP1122]], [[COND_TRUE2603]] ], [ [[TMP1123]], [[COND_FALSE2604]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2606]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1124:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1125:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2607:%.*]] = icmp eq i32 [[TMP1124]], [[TMP1125]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2607]], label [[COND_TRUE2609:%.*]], label [[COND_FALSE2610:%.*]]
|
|
// SIMD-ONLY0: cond.true2609:
|
|
// SIMD-ONLY0-NEXT: [[TMP1126:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2611:%.*]]
|
|
// SIMD-ONLY0: cond.false2610:
|
|
// SIMD-ONLY0-NEXT: [[TMP1127:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2611]]
|
|
// SIMD-ONLY0: cond.end2611:
|
|
// SIMD-ONLY0-NEXT: [[COND2612:%.*]] = phi i32 [ [[TMP1126]], [[COND_TRUE2609]] ], [ [[TMP1127]], [[COND_FALSE2610]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2612]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1128:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1129:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2613:%.*]] = icmp eq i32 [[TMP1128]], [[TMP1129]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2613]], label [[IF_THEN2615:%.*]], label [[IF_END2616:%.*]]
|
|
// SIMD-ONLY0: if.then2615:
|
|
// SIMD-ONLY0-NEXT: [[TMP1130:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1130]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2616]]
|
|
// SIMD-ONLY0: if.end2616:
|
|
// SIMD-ONLY0-NEXT: [[TMP1131:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1132:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2617:%.*]] = icmp eq i32 [[TMP1131]], [[TMP1132]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2617]], label [[IF_THEN2619:%.*]], label [[IF_END2620:%.*]]
|
|
// SIMD-ONLY0: if.then2619:
|
|
// SIMD-ONLY0-NEXT: [[TMP1133:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1133]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2620]]
|
|
// SIMD-ONLY0: if.end2620:
|
|
// SIMD-ONLY0-NEXT: [[TMP1134:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1135:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2621:%.*]] = icmp ugt i32 [[TMP1134]], [[TMP1135]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2621]], label [[COND_TRUE2623:%.*]], label [[COND_FALSE2624:%.*]]
|
|
// SIMD-ONLY0: cond.true2623:
|
|
// SIMD-ONLY0-NEXT: [[TMP1136:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2625:%.*]]
|
|
// SIMD-ONLY0: cond.false2624:
|
|
// SIMD-ONLY0-NEXT: [[TMP1137:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2625]]
|
|
// SIMD-ONLY0: cond.end2625:
|
|
// SIMD-ONLY0-NEXT: [[COND2626:%.*]] = phi i32 [ [[TMP1136]], [[COND_TRUE2623]] ], [ [[TMP1137]], [[COND_FALSE2624]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2626]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1138:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1139:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2627:%.*]] = icmp ult i32 [[TMP1138]], [[TMP1139]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2627]], label [[COND_TRUE2629:%.*]], label [[COND_FALSE2630:%.*]]
|
|
// SIMD-ONLY0: cond.true2629:
|
|
// SIMD-ONLY0-NEXT: [[TMP1140:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2631:%.*]]
|
|
// SIMD-ONLY0: cond.false2630:
|
|
// SIMD-ONLY0-NEXT: [[TMP1141:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2631]]
|
|
// SIMD-ONLY0: cond.end2631:
|
|
// SIMD-ONLY0-NEXT: [[COND2632:%.*]] = phi i32 [ [[TMP1140]], [[COND_TRUE2629]] ], [ [[TMP1141]], [[COND_FALSE2630]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2632]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1142:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1143:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2633:%.*]] = icmp ugt i32 [[TMP1142]], [[TMP1143]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2633]], label [[COND_TRUE2635:%.*]], label [[COND_FALSE2636:%.*]]
|
|
// SIMD-ONLY0: cond.true2635:
|
|
// SIMD-ONLY0-NEXT: [[TMP1144:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2637:%.*]]
|
|
// SIMD-ONLY0: cond.false2636:
|
|
// SIMD-ONLY0-NEXT: [[TMP1145:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2637]]
|
|
// SIMD-ONLY0: cond.end2637:
|
|
// SIMD-ONLY0-NEXT: [[COND2638:%.*]] = phi i32 [ [[TMP1144]], [[COND_TRUE2635]] ], [ [[TMP1145]], [[COND_FALSE2636]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2638]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1146:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1147:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2639:%.*]] = icmp ult i32 [[TMP1146]], [[TMP1147]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2639]], label [[COND_TRUE2641:%.*]], label [[COND_FALSE2642:%.*]]
|
|
// SIMD-ONLY0: cond.true2641:
|
|
// SIMD-ONLY0-NEXT: [[TMP1148:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2643:%.*]]
|
|
// SIMD-ONLY0: cond.false2642:
|
|
// SIMD-ONLY0-NEXT: [[TMP1149:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2643]]
|
|
// SIMD-ONLY0: cond.end2643:
|
|
// SIMD-ONLY0-NEXT: [[COND2644:%.*]] = phi i32 [ [[TMP1148]], [[COND_TRUE2641]] ], [ [[TMP1149]], [[COND_FALSE2642]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2644]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1150:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1151:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2645:%.*]] = icmp ugt i32 [[TMP1150]], [[TMP1151]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2645]], label [[IF_THEN2647:%.*]], label [[IF_END2648:%.*]]
|
|
// SIMD-ONLY0: if.then2647:
|
|
// SIMD-ONLY0-NEXT: [[TMP1152:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1152]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2648]]
|
|
// SIMD-ONLY0: if.end2648:
|
|
// SIMD-ONLY0-NEXT: [[TMP1153:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1154:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2649:%.*]] = icmp ult i32 [[TMP1153]], [[TMP1154]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2649]], label [[IF_THEN2651:%.*]], label [[IF_END2652:%.*]]
|
|
// SIMD-ONLY0: if.then2651:
|
|
// SIMD-ONLY0-NEXT: [[TMP1155:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1155]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2652]]
|
|
// SIMD-ONLY0: if.end2652:
|
|
// SIMD-ONLY0-NEXT: [[TMP1156:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1157:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2653:%.*]] = icmp ugt i32 [[TMP1156]], [[TMP1157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2653]], label [[IF_THEN2655:%.*]], label [[IF_END2656:%.*]]
|
|
// SIMD-ONLY0: if.then2655:
|
|
// SIMD-ONLY0-NEXT: [[TMP1158:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1158]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2656]]
|
|
// SIMD-ONLY0: if.end2656:
|
|
// SIMD-ONLY0-NEXT: [[TMP1159:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1160:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2657:%.*]] = icmp ult i32 [[TMP1159]], [[TMP1160]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2657]], label [[IF_THEN2659:%.*]], label [[IF_END2660:%.*]]
|
|
// SIMD-ONLY0: if.then2659:
|
|
// SIMD-ONLY0-NEXT: [[TMP1161:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1161]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2660]]
|
|
// SIMD-ONLY0: if.end2660:
|
|
// SIMD-ONLY0-NEXT: [[TMP1162:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1163:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2661:%.*]] = icmp eq i32 [[TMP1162]], [[TMP1163]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2661]], label [[COND_TRUE2663:%.*]], label [[COND_FALSE2664:%.*]]
|
|
// SIMD-ONLY0: cond.true2663:
|
|
// SIMD-ONLY0-NEXT: [[TMP1164:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2665:%.*]]
|
|
// SIMD-ONLY0: cond.false2664:
|
|
// SIMD-ONLY0-NEXT: [[TMP1165:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2665]]
|
|
// SIMD-ONLY0: cond.end2665:
|
|
// SIMD-ONLY0-NEXT: [[COND2666:%.*]] = phi i32 [ [[TMP1164]], [[COND_TRUE2663]] ], [ [[TMP1165]], [[COND_FALSE2664]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2666]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1166:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1167:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2667:%.*]] = icmp eq i32 [[TMP1166]], [[TMP1167]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2667]], label [[COND_TRUE2669:%.*]], label [[COND_FALSE2670:%.*]]
|
|
// SIMD-ONLY0: cond.true2669:
|
|
// SIMD-ONLY0-NEXT: [[TMP1168:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2671:%.*]]
|
|
// SIMD-ONLY0: cond.false2670:
|
|
// SIMD-ONLY0-NEXT: [[TMP1169:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2671]]
|
|
// SIMD-ONLY0: cond.end2671:
|
|
// SIMD-ONLY0-NEXT: [[COND2672:%.*]] = phi i32 [ [[TMP1168]], [[COND_TRUE2669]] ], [ [[TMP1169]], [[COND_FALSE2670]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2672]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1170:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1171:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2673:%.*]] = icmp eq i32 [[TMP1170]], [[TMP1171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2673]], label [[IF_THEN2675:%.*]], label [[IF_END2676:%.*]]
|
|
// SIMD-ONLY0: if.then2675:
|
|
// SIMD-ONLY0-NEXT: [[TMP1172:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1172]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2676]]
|
|
// SIMD-ONLY0: if.end2676:
|
|
// SIMD-ONLY0-NEXT: [[TMP1173:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1174:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2677:%.*]] = icmp eq i32 [[TMP1173]], [[TMP1174]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2677]], label [[IF_THEN2679:%.*]], label [[IF_END2680:%.*]]
|
|
// SIMD-ONLY0: if.then2679:
|
|
// SIMD-ONLY0-NEXT: [[TMP1175:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1175]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2680]]
|
|
// SIMD-ONLY0: if.end2680:
|
|
// SIMD-ONLY0-NEXT: [[TMP1176:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1177:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2681:%.*]] = icmp sgt i32 [[TMP1176]], [[TMP1177]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2681]], label [[COND_TRUE2683:%.*]], label [[COND_FALSE2684:%.*]]
|
|
// SIMD-ONLY0: cond.true2683:
|
|
// SIMD-ONLY0-NEXT: [[TMP1178:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2685:%.*]]
|
|
// SIMD-ONLY0: cond.false2684:
|
|
// SIMD-ONLY0-NEXT: [[TMP1179:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2685]]
|
|
// SIMD-ONLY0: cond.end2685:
|
|
// SIMD-ONLY0-NEXT: [[COND2686:%.*]] = phi i32 [ [[TMP1178]], [[COND_TRUE2683]] ], [ [[TMP1179]], [[COND_FALSE2684]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2686]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1180:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1181:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2687:%.*]] = icmp slt i32 [[TMP1180]], [[TMP1181]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2687]], label [[COND_TRUE2689:%.*]], label [[COND_FALSE2690:%.*]]
|
|
// SIMD-ONLY0: cond.true2689:
|
|
// SIMD-ONLY0-NEXT: [[TMP1182:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2691:%.*]]
|
|
// SIMD-ONLY0: cond.false2690:
|
|
// SIMD-ONLY0-NEXT: [[TMP1183:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2691]]
|
|
// SIMD-ONLY0: cond.end2691:
|
|
// SIMD-ONLY0-NEXT: [[COND2692:%.*]] = phi i32 [ [[TMP1182]], [[COND_TRUE2689]] ], [ [[TMP1183]], [[COND_FALSE2690]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2692]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1184:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1185:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2693:%.*]] = icmp sgt i32 [[TMP1184]], [[TMP1185]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2693]], label [[COND_TRUE2695:%.*]], label [[COND_FALSE2696:%.*]]
|
|
// SIMD-ONLY0: cond.true2695:
|
|
// SIMD-ONLY0-NEXT: [[TMP1186:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2697:%.*]]
|
|
// SIMD-ONLY0: cond.false2696:
|
|
// SIMD-ONLY0-NEXT: [[TMP1187:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2697]]
|
|
// SIMD-ONLY0: cond.end2697:
|
|
// SIMD-ONLY0-NEXT: [[COND2698:%.*]] = phi i32 [ [[TMP1186]], [[COND_TRUE2695]] ], [ [[TMP1187]], [[COND_FALSE2696]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2698]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1188:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1189:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2699:%.*]] = icmp slt i32 [[TMP1188]], [[TMP1189]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2699]], label [[COND_TRUE2701:%.*]], label [[COND_FALSE2702:%.*]]
|
|
// SIMD-ONLY0: cond.true2701:
|
|
// SIMD-ONLY0-NEXT: [[TMP1190:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2703:%.*]]
|
|
// SIMD-ONLY0: cond.false2702:
|
|
// SIMD-ONLY0-NEXT: [[TMP1191:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2703]]
|
|
// SIMD-ONLY0: cond.end2703:
|
|
// SIMD-ONLY0-NEXT: [[COND2704:%.*]] = phi i32 [ [[TMP1190]], [[COND_TRUE2701]] ], [ [[TMP1191]], [[COND_FALSE2702]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2704]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1192:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1193:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2705:%.*]] = icmp sgt i32 [[TMP1192]], [[TMP1193]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2705]], label [[IF_THEN2707:%.*]], label [[IF_END2708:%.*]]
|
|
// SIMD-ONLY0: if.then2707:
|
|
// SIMD-ONLY0-NEXT: [[TMP1194:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1194]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2708]]
|
|
// SIMD-ONLY0: if.end2708:
|
|
// SIMD-ONLY0-NEXT: [[TMP1195:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1196:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2709:%.*]] = icmp slt i32 [[TMP1195]], [[TMP1196]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2709]], label [[IF_THEN2711:%.*]], label [[IF_END2712:%.*]]
|
|
// SIMD-ONLY0: if.then2711:
|
|
// SIMD-ONLY0-NEXT: [[TMP1197:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1197]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2712]]
|
|
// SIMD-ONLY0: if.end2712:
|
|
// SIMD-ONLY0-NEXT: [[TMP1198:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1199:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2713:%.*]] = icmp sgt i32 [[TMP1198]], [[TMP1199]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2713]], label [[IF_THEN2715:%.*]], label [[IF_END2716:%.*]]
|
|
// SIMD-ONLY0: if.then2715:
|
|
// SIMD-ONLY0-NEXT: [[TMP1200:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1200]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2716]]
|
|
// SIMD-ONLY0: if.end2716:
|
|
// SIMD-ONLY0-NEXT: [[TMP1201:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1202:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2717:%.*]] = icmp slt i32 [[TMP1201]], [[TMP1202]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2717]], label [[IF_THEN2719:%.*]], label [[IF_END2720:%.*]]
|
|
// SIMD-ONLY0: if.then2719:
|
|
// SIMD-ONLY0-NEXT: [[TMP1203:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1203]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2720]]
|
|
// SIMD-ONLY0: if.end2720:
|
|
// SIMD-ONLY0-NEXT: [[TMP1204:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1205:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2721:%.*]] = icmp eq i32 [[TMP1204]], [[TMP1205]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2721]], label [[COND_TRUE2723:%.*]], label [[COND_FALSE2724:%.*]]
|
|
// SIMD-ONLY0: cond.true2723:
|
|
// SIMD-ONLY0-NEXT: [[TMP1206:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2725:%.*]]
|
|
// SIMD-ONLY0: cond.false2724:
|
|
// SIMD-ONLY0-NEXT: [[TMP1207:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2725]]
|
|
// SIMD-ONLY0: cond.end2725:
|
|
// SIMD-ONLY0-NEXT: [[COND2726:%.*]] = phi i32 [ [[TMP1206]], [[COND_TRUE2723]] ], [ [[TMP1207]], [[COND_FALSE2724]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2726]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1208:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1209:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2727:%.*]] = icmp eq i32 [[TMP1208]], [[TMP1209]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2727]], label [[COND_TRUE2729:%.*]], label [[COND_FALSE2730:%.*]]
|
|
// SIMD-ONLY0: cond.true2729:
|
|
// SIMD-ONLY0-NEXT: [[TMP1210:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2731:%.*]]
|
|
// SIMD-ONLY0: cond.false2730:
|
|
// SIMD-ONLY0-NEXT: [[TMP1211:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2731]]
|
|
// SIMD-ONLY0: cond.end2731:
|
|
// SIMD-ONLY0-NEXT: [[COND2732:%.*]] = phi i32 [ [[TMP1210]], [[COND_TRUE2729]] ], [ [[TMP1211]], [[COND_FALSE2730]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2732]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1212:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1213:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2733:%.*]] = icmp eq i32 [[TMP1212]], [[TMP1213]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2733]], label [[IF_THEN2735:%.*]], label [[IF_END2736:%.*]]
|
|
// SIMD-ONLY0: if.then2735:
|
|
// SIMD-ONLY0-NEXT: [[TMP1214:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1214]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2736]]
|
|
// SIMD-ONLY0: if.end2736:
|
|
// SIMD-ONLY0-NEXT: [[TMP1215:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1216:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2737:%.*]] = icmp eq i32 [[TMP1215]], [[TMP1216]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2737]], label [[IF_THEN2739:%.*]], label [[IF_END2740:%.*]]
|
|
// SIMD-ONLY0: if.then2739:
|
|
// SIMD-ONLY0-NEXT: [[TMP1217:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1217]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2740]]
|
|
// SIMD-ONLY0: if.end2740:
|
|
// SIMD-ONLY0-NEXT: [[TMP1218:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1219:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2741:%.*]] = icmp ugt i32 [[TMP1218]], [[TMP1219]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2741]], label [[COND_TRUE2743:%.*]], label [[COND_FALSE2744:%.*]]
|
|
// SIMD-ONLY0: cond.true2743:
|
|
// SIMD-ONLY0-NEXT: [[TMP1220:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2745:%.*]]
|
|
// SIMD-ONLY0: cond.false2744:
|
|
// SIMD-ONLY0-NEXT: [[TMP1221:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2745]]
|
|
// SIMD-ONLY0: cond.end2745:
|
|
// SIMD-ONLY0-NEXT: [[COND2746:%.*]] = phi i32 [ [[TMP1220]], [[COND_TRUE2743]] ], [ [[TMP1221]], [[COND_FALSE2744]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2746]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1222:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1223:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2747:%.*]] = icmp ult i32 [[TMP1222]], [[TMP1223]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2747]], label [[COND_TRUE2749:%.*]], label [[COND_FALSE2750:%.*]]
|
|
// SIMD-ONLY0: cond.true2749:
|
|
// SIMD-ONLY0-NEXT: [[TMP1224:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2751:%.*]]
|
|
// SIMD-ONLY0: cond.false2750:
|
|
// SIMD-ONLY0-NEXT: [[TMP1225:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2751]]
|
|
// SIMD-ONLY0: cond.end2751:
|
|
// SIMD-ONLY0-NEXT: [[COND2752:%.*]] = phi i32 [ [[TMP1224]], [[COND_TRUE2749]] ], [ [[TMP1225]], [[COND_FALSE2750]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2752]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1226:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1227:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2753:%.*]] = icmp ugt i32 [[TMP1226]], [[TMP1227]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2753]], label [[COND_TRUE2755:%.*]], label [[COND_FALSE2756:%.*]]
|
|
// SIMD-ONLY0: cond.true2755:
|
|
// SIMD-ONLY0-NEXT: [[TMP1228:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2757:%.*]]
|
|
// SIMD-ONLY0: cond.false2756:
|
|
// SIMD-ONLY0-NEXT: [[TMP1229:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2757]]
|
|
// SIMD-ONLY0: cond.end2757:
|
|
// SIMD-ONLY0-NEXT: [[COND2758:%.*]] = phi i32 [ [[TMP1228]], [[COND_TRUE2755]] ], [ [[TMP1229]], [[COND_FALSE2756]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2758]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1230:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1231:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2759:%.*]] = icmp ult i32 [[TMP1230]], [[TMP1231]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2759]], label [[COND_TRUE2761:%.*]], label [[COND_FALSE2762:%.*]]
|
|
// SIMD-ONLY0: cond.true2761:
|
|
// SIMD-ONLY0-NEXT: [[TMP1232:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2763:%.*]]
|
|
// SIMD-ONLY0: cond.false2762:
|
|
// SIMD-ONLY0-NEXT: [[TMP1233:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2763]]
|
|
// SIMD-ONLY0: cond.end2763:
|
|
// SIMD-ONLY0-NEXT: [[COND2764:%.*]] = phi i32 [ [[TMP1232]], [[COND_TRUE2761]] ], [ [[TMP1233]], [[COND_FALSE2762]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2764]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1234:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1235:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2765:%.*]] = icmp ugt i32 [[TMP1234]], [[TMP1235]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2765]], label [[IF_THEN2767:%.*]], label [[IF_END2768:%.*]]
|
|
// SIMD-ONLY0: if.then2767:
|
|
// SIMD-ONLY0-NEXT: [[TMP1236:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1236]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2768]]
|
|
// SIMD-ONLY0: if.end2768:
|
|
// SIMD-ONLY0-NEXT: [[TMP1237:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1238:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2769:%.*]] = icmp ult i32 [[TMP1237]], [[TMP1238]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2769]], label [[IF_THEN2771:%.*]], label [[IF_END2772:%.*]]
|
|
// SIMD-ONLY0: if.then2771:
|
|
// SIMD-ONLY0-NEXT: [[TMP1239:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1239]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2772]]
|
|
// SIMD-ONLY0: if.end2772:
|
|
// SIMD-ONLY0-NEXT: [[TMP1240:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1241:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2773:%.*]] = icmp ugt i32 [[TMP1240]], [[TMP1241]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2773]], label [[IF_THEN2775:%.*]], label [[IF_END2776:%.*]]
|
|
// SIMD-ONLY0: if.then2775:
|
|
// SIMD-ONLY0-NEXT: [[TMP1242:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1242]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2776]]
|
|
// SIMD-ONLY0: if.end2776:
|
|
// SIMD-ONLY0-NEXT: [[TMP1243:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1244:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2777:%.*]] = icmp ult i32 [[TMP1243]], [[TMP1244]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2777]], label [[IF_THEN2779:%.*]], label [[IF_END2780:%.*]]
|
|
// SIMD-ONLY0: if.then2779:
|
|
// SIMD-ONLY0-NEXT: [[TMP1245:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1245]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2780]]
|
|
// SIMD-ONLY0: if.end2780:
|
|
// SIMD-ONLY0-NEXT: [[TMP1246:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1247:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2781:%.*]] = icmp eq i32 [[TMP1246]], [[TMP1247]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2781]], label [[COND_TRUE2783:%.*]], label [[COND_FALSE2784:%.*]]
|
|
// SIMD-ONLY0: cond.true2783:
|
|
// SIMD-ONLY0-NEXT: [[TMP1248:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2785:%.*]]
|
|
// SIMD-ONLY0: cond.false2784:
|
|
// SIMD-ONLY0-NEXT: [[TMP1249:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2785]]
|
|
// SIMD-ONLY0: cond.end2785:
|
|
// SIMD-ONLY0-NEXT: [[COND2786:%.*]] = phi i32 [ [[TMP1248]], [[COND_TRUE2783]] ], [ [[TMP1249]], [[COND_FALSE2784]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2786]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1250:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1251:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2787:%.*]] = icmp eq i32 [[TMP1250]], [[TMP1251]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2787]], label [[COND_TRUE2789:%.*]], label [[COND_FALSE2790:%.*]]
|
|
// SIMD-ONLY0: cond.true2789:
|
|
// SIMD-ONLY0-NEXT: [[TMP1252:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2791:%.*]]
|
|
// SIMD-ONLY0: cond.false2790:
|
|
// SIMD-ONLY0-NEXT: [[TMP1253:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2791]]
|
|
// SIMD-ONLY0: cond.end2791:
|
|
// SIMD-ONLY0-NEXT: [[COND2792:%.*]] = phi i32 [ [[TMP1252]], [[COND_TRUE2789]] ], [ [[TMP1253]], [[COND_FALSE2790]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2792]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1254:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1255:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2793:%.*]] = icmp eq i32 [[TMP1254]], [[TMP1255]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2793]], label [[IF_THEN2795:%.*]], label [[IF_END2796:%.*]]
|
|
// SIMD-ONLY0: if.then2795:
|
|
// SIMD-ONLY0-NEXT: [[TMP1256:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1256]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2796]]
|
|
// SIMD-ONLY0: if.end2796:
|
|
// SIMD-ONLY0-NEXT: [[TMP1257:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1258:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2797:%.*]] = icmp eq i32 [[TMP1257]], [[TMP1258]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2797]], label [[IF_THEN2799:%.*]], label [[IF_END2800:%.*]]
|
|
// SIMD-ONLY0: if.then2799:
|
|
// SIMD-ONLY0-NEXT: [[TMP1259:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1259]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2800]]
|
|
// SIMD-ONLY0: if.end2800:
|
|
// SIMD-ONLY0-NEXT: [[TMP1260:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1261:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2801:%.*]] = icmp sgt i32 [[TMP1260]], [[TMP1261]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2801]], label [[COND_TRUE2803:%.*]], label [[COND_FALSE2804:%.*]]
|
|
// SIMD-ONLY0: cond.true2803:
|
|
// SIMD-ONLY0-NEXT: [[TMP1262:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2805:%.*]]
|
|
// SIMD-ONLY0: cond.false2804:
|
|
// SIMD-ONLY0-NEXT: [[TMP1263:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2805]]
|
|
// SIMD-ONLY0: cond.end2805:
|
|
// SIMD-ONLY0-NEXT: [[COND2806:%.*]] = phi i32 [ [[TMP1262]], [[COND_TRUE2803]] ], [ [[TMP1263]], [[COND_FALSE2804]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2806]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1264:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1265:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2807:%.*]] = icmp slt i32 [[TMP1264]], [[TMP1265]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2807]], label [[COND_TRUE2809:%.*]], label [[COND_FALSE2810:%.*]]
|
|
// SIMD-ONLY0: cond.true2809:
|
|
// SIMD-ONLY0-NEXT: [[TMP1266:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2811:%.*]]
|
|
// SIMD-ONLY0: cond.false2810:
|
|
// SIMD-ONLY0-NEXT: [[TMP1267:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2811]]
|
|
// SIMD-ONLY0: cond.end2811:
|
|
// SIMD-ONLY0-NEXT: [[COND2812:%.*]] = phi i32 [ [[TMP1266]], [[COND_TRUE2809]] ], [ [[TMP1267]], [[COND_FALSE2810]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2812]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1268:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1269:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2813:%.*]] = icmp sgt i32 [[TMP1268]], [[TMP1269]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2813]], label [[COND_TRUE2815:%.*]], label [[COND_FALSE2816:%.*]]
|
|
// SIMD-ONLY0: cond.true2815:
|
|
// SIMD-ONLY0-NEXT: [[TMP1270:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2817:%.*]]
|
|
// SIMD-ONLY0: cond.false2816:
|
|
// SIMD-ONLY0-NEXT: [[TMP1271:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2817]]
|
|
// SIMD-ONLY0: cond.end2817:
|
|
// SIMD-ONLY0-NEXT: [[COND2818:%.*]] = phi i32 [ [[TMP1270]], [[COND_TRUE2815]] ], [ [[TMP1271]], [[COND_FALSE2816]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2818]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1272:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1273:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2819:%.*]] = icmp slt i32 [[TMP1272]], [[TMP1273]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2819]], label [[COND_TRUE2821:%.*]], label [[COND_FALSE2822:%.*]]
|
|
// SIMD-ONLY0: cond.true2821:
|
|
// SIMD-ONLY0-NEXT: [[TMP1274:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2823:%.*]]
|
|
// SIMD-ONLY0: cond.false2822:
|
|
// SIMD-ONLY0-NEXT: [[TMP1275:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2823]]
|
|
// SIMD-ONLY0: cond.end2823:
|
|
// SIMD-ONLY0-NEXT: [[COND2824:%.*]] = phi i32 [ [[TMP1274]], [[COND_TRUE2821]] ], [ [[TMP1275]], [[COND_FALSE2822]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2824]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1276:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1277:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2825:%.*]] = icmp sgt i32 [[TMP1276]], [[TMP1277]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2825]], label [[IF_THEN2827:%.*]], label [[IF_END2828:%.*]]
|
|
// SIMD-ONLY0: if.then2827:
|
|
// SIMD-ONLY0-NEXT: [[TMP1278:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1278]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2828]]
|
|
// SIMD-ONLY0: if.end2828:
|
|
// SIMD-ONLY0-NEXT: [[TMP1279:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1280:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2829:%.*]] = icmp slt i32 [[TMP1279]], [[TMP1280]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2829]], label [[IF_THEN2831:%.*]], label [[IF_END2832:%.*]]
|
|
// SIMD-ONLY0: if.then2831:
|
|
// SIMD-ONLY0-NEXT: [[TMP1281:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1281]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2832]]
|
|
// SIMD-ONLY0: if.end2832:
|
|
// SIMD-ONLY0-NEXT: [[TMP1282:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1283:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2833:%.*]] = icmp sgt i32 [[TMP1282]], [[TMP1283]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2833]], label [[IF_THEN2835:%.*]], label [[IF_END2836:%.*]]
|
|
// SIMD-ONLY0: if.then2835:
|
|
// SIMD-ONLY0-NEXT: [[TMP1284:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1284]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2836]]
|
|
// SIMD-ONLY0: if.end2836:
|
|
// SIMD-ONLY0-NEXT: [[TMP1285:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1286:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2837:%.*]] = icmp slt i32 [[TMP1285]], [[TMP1286]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2837]], label [[IF_THEN2839:%.*]], label [[IF_END2840:%.*]]
|
|
// SIMD-ONLY0: if.then2839:
|
|
// SIMD-ONLY0-NEXT: [[TMP1287:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1287]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2840]]
|
|
// SIMD-ONLY0: if.end2840:
|
|
// SIMD-ONLY0-NEXT: [[TMP1288:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1289:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2841:%.*]] = icmp eq i32 [[TMP1288]], [[TMP1289]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2841]], label [[COND_TRUE2843:%.*]], label [[COND_FALSE2844:%.*]]
|
|
// SIMD-ONLY0: cond.true2843:
|
|
// SIMD-ONLY0-NEXT: [[TMP1290:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2845:%.*]]
|
|
// SIMD-ONLY0: cond.false2844:
|
|
// SIMD-ONLY0-NEXT: [[TMP1291:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2845]]
|
|
// SIMD-ONLY0: cond.end2845:
|
|
// SIMD-ONLY0-NEXT: [[COND2846:%.*]] = phi i32 [ [[TMP1290]], [[COND_TRUE2843]] ], [ [[TMP1291]], [[COND_FALSE2844]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2846]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1292:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1293:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2847:%.*]] = icmp eq i32 [[TMP1292]], [[TMP1293]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2847]], label [[COND_TRUE2849:%.*]], label [[COND_FALSE2850:%.*]]
|
|
// SIMD-ONLY0: cond.true2849:
|
|
// SIMD-ONLY0-NEXT: [[TMP1294:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2851:%.*]]
|
|
// SIMD-ONLY0: cond.false2850:
|
|
// SIMD-ONLY0-NEXT: [[TMP1295:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2851]]
|
|
// SIMD-ONLY0: cond.end2851:
|
|
// SIMD-ONLY0-NEXT: [[COND2852:%.*]] = phi i32 [ [[TMP1294]], [[COND_TRUE2849]] ], [ [[TMP1295]], [[COND_FALSE2850]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2852]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1296:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1297:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2853:%.*]] = icmp eq i32 [[TMP1296]], [[TMP1297]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2853]], label [[IF_THEN2855:%.*]], label [[IF_END2856:%.*]]
|
|
// SIMD-ONLY0: if.then2855:
|
|
// SIMD-ONLY0-NEXT: [[TMP1298:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1298]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2856]]
|
|
// SIMD-ONLY0: if.end2856:
|
|
// SIMD-ONLY0-NEXT: [[TMP1299:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1300:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2857:%.*]] = icmp eq i32 [[TMP1299]], [[TMP1300]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2857]], label [[IF_THEN2859:%.*]], label [[IF_END2860:%.*]]
|
|
// SIMD-ONLY0: if.then2859:
|
|
// SIMD-ONLY0-NEXT: [[TMP1301:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1301]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2860]]
|
|
// SIMD-ONLY0: if.end2860:
|
|
// SIMD-ONLY0-NEXT: [[TMP1302:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1303:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2861:%.*]] = icmp ugt i32 [[TMP1302]], [[TMP1303]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2861]], label [[COND_TRUE2863:%.*]], label [[COND_FALSE2864:%.*]]
|
|
// SIMD-ONLY0: cond.true2863:
|
|
// SIMD-ONLY0-NEXT: [[TMP1304:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2865:%.*]]
|
|
// SIMD-ONLY0: cond.false2864:
|
|
// SIMD-ONLY0-NEXT: [[TMP1305:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2865]]
|
|
// SIMD-ONLY0: cond.end2865:
|
|
// SIMD-ONLY0-NEXT: [[COND2866:%.*]] = phi i32 [ [[TMP1304]], [[COND_TRUE2863]] ], [ [[TMP1305]], [[COND_FALSE2864]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2866]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1306:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1307:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2867:%.*]] = icmp ult i32 [[TMP1306]], [[TMP1307]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2867]], label [[COND_TRUE2869:%.*]], label [[COND_FALSE2870:%.*]]
|
|
// SIMD-ONLY0: cond.true2869:
|
|
// SIMD-ONLY0-NEXT: [[TMP1308:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2871:%.*]]
|
|
// SIMD-ONLY0: cond.false2870:
|
|
// SIMD-ONLY0-NEXT: [[TMP1309:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2871]]
|
|
// SIMD-ONLY0: cond.end2871:
|
|
// SIMD-ONLY0-NEXT: [[COND2872:%.*]] = phi i32 [ [[TMP1308]], [[COND_TRUE2869]] ], [ [[TMP1309]], [[COND_FALSE2870]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2872]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1310:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1311:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2873:%.*]] = icmp ugt i32 [[TMP1310]], [[TMP1311]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2873]], label [[COND_TRUE2875:%.*]], label [[COND_FALSE2876:%.*]]
|
|
// SIMD-ONLY0: cond.true2875:
|
|
// SIMD-ONLY0-NEXT: [[TMP1312:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2877:%.*]]
|
|
// SIMD-ONLY0: cond.false2876:
|
|
// SIMD-ONLY0-NEXT: [[TMP1313:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2877]]
|
|
// SIMD-ONLY0: cond.end2877:
|
|
// SIMD-ONLY0-NEXT: [[COND2878:%.*]] = phi i32 [ [[TMP1312]], [[COND_TRUE2875]] ], [ [[TMP1313]], [[COND_FALSE2876]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2878]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1314:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1315:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2879:%.*]] = icmp ult i32 [[TMP1314]], [[TMP1315]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2879]], label [[COND_TRUE2881:%.*]], label [[COND_FALSE2882:%.*]]
|
|
// SIMD-ONLY0: cond.true2881:
|
|
// SIMD-ONLY0-NEXT: [[TMP1316:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2883:%.*]]
|
|
// SIMD-ONLY0: cond.false2882:
|
|
// SIMD-ONLY0-NEXT: [[TMP1317:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2883]]
|
|
// SIMD-ONLY0: cond.end2883:
|
|
// SIMD-ONLY0-NEXT: [[COND2884:%.*]] = phi i32 [ [[TMP1316]], [[COND_TRUE2881]] ], [ [[TMP1317]], [[COND_FALSE2882]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2884]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1318:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1319:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2885:%.*]] = icmp ugt i32 [[TMP1318]], [[TMP1319]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2885]], label [[IF_THEN2887:%.*]], label [[IF_END2888:%.*]]
|
|
// SIMD-ONLY0: if.then2887:
|
|
// SIMD-ONLY0-NEXT: [[TMP1320:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1320]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2888]]
|
|
// SIMD-ONLY0: if.end2888:
|
|
// SIMD-ONLY0-NEXT: [[TMP1321:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1322:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2889:%.*]] = icmp ult i32 [[TMP1321]], [[TMP1322]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2889]], label [[IF_THEN2891:%.*]], label [[IF_END2892:%.*]]
|
|
// SIMD-ONLY0: if.then2891:
|
|
// SIMD-ONLY0-NEXT: [[TMP1323:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1323]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2892]]
|
|
// SIMD-ONLY0: if.end2892:
|
|
// SIMD-ONLY0-NEXT: [[TMP1324:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1325:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2893:%.*]] = icmp ugt i32 [[TMP1324]], [[TMP1325]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2893]], label [[IF_THEN2895:%.*]], label [[IF_END2896:%.*]]
|
|
// SIMD-ONLY0: if.then2895:
|
|
// SIMD-ONLY0-NEXT: [[TMP1326:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1326]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2896]]
|
|
// SIMD-ONLY0: if.end2896:
|
|
// SIMD-ONLY0-NEXT: [[TMP1327:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1328:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2897:%.*]] = icmp ult i32 [[TMP1327]], [[TMP1328]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2897]], label [[IF_THEN2899:%.*]], label [[IF_END2900:%.*]]
|
|
// SIMD-ONLY0: if.then2899:
|
|
// SIMD-ONLY0-NEXT: [[TMP1329:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1329]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2900]]
|
|
// SIMD-ONLY0: if.end2900:
|
|
// SIMD-ONLY0-NEXT: [[TMP1330:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1331:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2901:%.*]] = icmp eq i32 [[TMP1330]], [[TMP1331]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2901]], label [[COND_TRUE2903:%.*]], label [[COND_FALSE2904:%.*]]
|
|
// SIMD-ONLY0: cond.true2903:
|
|
// SIMD-ONLY0-NEXT: [[TMP1332:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2905:%.*]]
|
|
// SIMD-ONLY0: cond.false2904:
|
|
// SIMD-ONLY0-NEXT: [[TMP1333:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2905]]
|
|
// SIMD-ONLY0: cond.end2905:
|
|
// SIMD-ONLY0-NEXT: [[COND2906:%.*]] = phi i32 [ [[TMP1332]], [[COND_TRUE2903]] ], [ [[TMP1333]], [[COND_FALSE2904]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2906]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1334:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1335:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2907:%.*]] = icmp eq i32 [[TMP1334]], [[TMP1335]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2907]], label [[COND_TRUE2909:%.*]], label [[COND_FALSE2910:%.*]]
|
|
// SIMD-ONLY0: cond.true2909:
|
|
// SIMD-ONLY0-NEXT: [[TMP1336:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2911:%.*]]
|
|
// SIMD-ONLY0: cond.false2910:
|
|
// SIMD-ONLY0-NEXT: [[TMP1337:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2911]]
|
|
// SIMD-ONLY0: cond.end2911:
|
|
// SIMD-ONLY0-NEXT: [[COND2912:%.*]] = phi i32 [ [[TMP1336]], [[COND_TRUE2909]] ], [ [[TMP1337]], [[COND_FALSE2910]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2912]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1338:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1339:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2913:%.*]] = icmp eq i32 [[TMP1338]], [[TMP1339]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2913]], label [[IF_THEN2915:%.*]], label [[IF_END2916:%.*]]
|
|
// SIMD-ONLY0: if.then2915:
|
|
// SIMD-ONLY0-NEXT: [[TMP1340:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1340]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2916]]
|
|
// SIMD-ONLY0: if.end2916:
|
|
// SIMD-ONLY0-NEXT: [[TMP1341:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1342:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2917:%.*]] = icmp eq i32 [[TMP1341]], [[TMP1342]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2917]], label [[IF_THEN2919:%.*]], label [[IF_END2920:%.*]]
|
|
// SIMD-ONLY0: if.then2919:
|
|
// SIMD-ONLY0-NEXT: [[TMP1343:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1343]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2920]]
|
|
// SIMD-ONLY0: if.end2920:
|
|
// SIMD-ONLY0-NEXT: [[TMP1344:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1345:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2921:%.*]] = icmp sgt i32 [[TMP1344]], [[TMP1345]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2921]], label [[COND_TRUE2923:%.*]], label [[COND_FALSE2924:%.*]]
|
|
// SIMD-ONLY0: cond.true2923:
|
|
// SIMD-ONLY0-NEXT: [[TMP1346:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2925:%.*]]
|
|
// SIMD-ONLY0: cond.false2924:
|
|
// SIMD-ONLY0-NEXT: [[TMP1347:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2925]]
|
|
// SIMD-ONLY0: cond.end2925:
|
|
// SIMD-ONLY0-NEXT: [[COND2926:%.*]] = phi i32 [ [[TMP1346]], [[COND_TRUE2923]] ], [ [[TMP1347]], [[COND_FALSE2924]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2926]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1348:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1349:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2927:%.*]] = icmp slt i32 [[TMP1348]], [[TMP1349]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2927]], label [[COND_TRUE2929:%.*]], label [[COND_FALSE2930:%.*]]
|
|
// SIMD-ONLY0: cond.true2929:
|
|
// SIMD-ONLY0-NEXT: [[TMP1350:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2931:%.*]]
|
|
// SIMD-ONLY0: cond.false2930:
|
|
// SIMD-ONLY0-NEXT: [[TMP1351:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2931]]
|
|
// SIMD-ONLY0: cond.end2931:
|
|
// SIMD-ONLY0-NEXT: [[COND2932:%.*]] = phi i32 [ [[TMP1350]], [[COND_TRUE2929]] ], [ [[TMP1351]], [[COND_FALSE2930]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2932]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1352:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1353:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2933:%.*]] = icmp sgt i32 [[TMP1352]], [[TMP1353]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2933]], label [[COND_TRUE2935:%.*]], label [[COND_FALSE2936:%.*]]
|
|
// SIMD-ONLY0: cond.true2935:
|
|
// SIMD-ONLY0-NEXT: [[TMP1354:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2937:%.*]]
|
|
// SIMD-ONLY0: cond.false2936:
|
|
// SIMD-ONLY0-NEXT: [[TMP1355:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2937]]
|
|
// SIMD-ONLY0: cond.end2937:
|
|
// SIMD-ONLY0-NEXT: [[COND2938:%.*]] = phi i32 [ [[TMP1354]], [[COND_TRUE2935]] ], [ [[TMP1355]], [[COND_FALSE2936]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2938]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1356:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1357:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2939:%.*]] = icmp slt i32 [[TMP1356]], [[TMP1357]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2939]], label [[COND_TRUE2941:%.*]], label [[COND_FALSE2942:%.*]]
|
|
// SIMD-ONLY0: cond.true2941:
|
|
// SIMD-ONLY0-NEXT: [[TMP1358:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2943:%.*]]
|
|
// SIMD-ONLY0: cond.false2942:
|
|
// SIMD-ONLY0-NEXT: [[TMP1359:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2943]]
|
|
// SIMD-ONLY0: cond.end2943:
|
|
// SIMD-ONLY0-NEXT: [[COND2944:%.*]] = phi i32 [ [[TMP1358]], [[COND_TRUE2941]] ], [ [[TMP1359]], [[COND_FALSE2942]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2944]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1360:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1361:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2945:%.*]] = icmp sgt i32 [[TMP1360]], [[TMP1361]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2945]], label [[IF_THEN2947:%.*]], label [[IF_END2948:%.*]]
|
|
// SIMD-ONLY0: if.then2947:
|
|
// SIMD-ONLY0-NEXT: [[TMP1362:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1362]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2948]]
|
|
// SIMD-ONLY0: if.end2948:
|
|
// SIMD-ONLY0-NEXT: [[TMP1363:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1364:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2949:%.*]] = icmp slt i32 [[TMP1363]], [[TMP1364]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2949]], label [[IF_THEN2951:%.*]], label [[IF_END2952:%.*]]
|
|
// SIMD-ONLY0: if.then2951:
|
|
// SIMD-ONLY0-NEXT: [[TMP1365:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1365]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2952]]
|
|
// SIMD-ONLY0: if.end2952:
|
|
// SIMD-ONLY0-NEXT: [[TMP1366:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1367:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2953:%.*]] = icmp sgt i32 [[TMP1366]], [[TMP1367]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2953]], label [[IF_THEN2955:%.*]], label [[IF_END2956:%.*]]
|
|
// SIMD-ONLY0: if.then2955:
|
|
// SIMD-ONLY0-NEXT: [[TMP1368:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1368]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2956]]
|
|
// SIMD-ONLY0: if.end2956:
|
|
// SIMD-ONLY0-NEXT: [[TMP1369:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1370:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2957:%.*]] = icmp slt i32 [[TMP1369]], [[TMP1370]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2957]], label [[IF_THEN2959:%.*]], label [[IF_END2960:%.*]]
|
|
// SIMD-ONLY0: if.then2959:
|
|
// SIMD-ONLY0-NEXT: [[TMP1371:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1371]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2960]]
|
|
// SIMD-ONLY0: if.end2960:
|
|
// SIMD-ONLY0-NEXT: [[TMP1372:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1373:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2961:%.*]] = icmp eq i32 [[TMP1372]], [[TMP1373]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2961]], label [[COND_TRUE2963:%.*]], label [[COND_FALSE2964:%.*]]
|
|
// SIMD-ONLY0: cond.true2963:
|
|
// SIMD-ONLY0-NEXT: [[TMP1374:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2965:%.*]]
|
|
// SIMD-ONLY0: cond.false2964:
|
|
// SIMD-ONLY0-NEXT: [[TMP1375:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2965]]
|
|
// SIMD-ONLY0: cond.end2965:
|
|
// SIMD-ONLY0-NEXT: [[COND2966:%.*]] = phi i32 [ [[TMP1374]], [[COND_TRUE2963]] ], [ [[TMP1375]], [[COND_FALSE2964]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2966]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1376:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1377:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2967:%.*]] = icmp eq i32 [[TMP1376]], [[TMP1377]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2967]], label [[COND_TRUE2969:%.*]], label [[COND_FALSE2970:%.*]]
|
|
// SIMD-ONLY0: cond.true2969:
|
|
// SIMD-ONLY0-NEXT: [[TMP1378:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2971:%.*]]
|
|
// SIMD-ONLY0: cond.false2970:
|
|
// SIMD-ONLY0-NEXT: [[TMP1379:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2971]]
|
|
// SIMD-ONLY0: cond.end2971:
|
|
// SIMD-ONLY0-NEXT: [[COND2972:%.*]] = phi i32 [ [[TMP1378]], [[COND_TRUE2969]] ], [ [[TMP1379]], [[COND_FALSE2970]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2972]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1380:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1381:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2973:%.*]] = icmp eq i32 [[TMP1380]], [[TMP1381]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2973]], label [[IF_THEN2975:%.*]], label [[IF_END2976:%.*]]
|
|
// SIMD-ONLY0: if.then2975:
|
|
// SIMD-ONLY0-NEXT: [[TMP1382:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1382]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2976]]
|
|
// SIMD-ONLY0: if.end2976:
|
|
// SIMD-ONLY0-NEXT: [[TMP1383:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1384:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2977:%.*]] = icmp eq i32 [[TMP1383]], [[TMP1384]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2977]], label [[IF_THEN2979:%.*]], label [[IF_END2980:%.*]]
|
|
// SIMD-ONLY0: if.then2979:
|
|
// SIMD-ONLY0-NEXT: [[TMP1385:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1385]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2980]]
|
|
// SIMD-ONLY0: if.end2980:
|
|
// SIMD-ONLY0-NEXT: [[TMP1386:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1387:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2981:%.*]] = icmp ugt i32 [[TMP1386]], [[TMP1387]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2981]], label [[COND_TRUE2983:%.*]], label [[COND_FALSE2984:%.*]]
|
|
// SIMD-ONLY0: cond.true2983:
|
|
// SIMD-ONLY0-NEXT: [[TMP1388:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2985:%.*]]
|
|
// SIMD-ONLY0: cond.false2984:
|
|
// SIMD-ONLY0-NEXT: [[TMP1389:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2985]]
|
|
// SIMD-ONLY0: cond.end2985:
|
|
// SIMD-ONLY0-NEXT: [[COND2986:%.*]] = phi i32 [ [[TMP1388]], [[COND_TRUE2983]] ], [ [[TMP1389]], [[COND_FALSE2984]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2986]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1390:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1391:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2987:%.*]] = icmp ult i32 [[TMP1390]], [[TMP1391]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2987]], label [[COND_TRUE2989:%.*]], label [[COND_FALSE2990:%.*]]
|
|
// SIMD-ONLY0: cond.true2989:
|
|
// SIMD-ONLY0-NEXT: [[TMP1392:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2991:%.*]]
|
|
// SIMD-ONLY0: cond.false2990:
|
|
// SIMD-ONLY0-NEXT: [[TMP1393:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2991]]
|
|
// SIMD-ONLY0: cond.end2991:
|
|
// SIMD-ONLY0-NEXT: [[COND2992:%.*]] = phi i32 [ [[TMP1392]], [[COND_TRUE2989]] ], [ [[TMP1393]], [[COND_FALSE2990]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2992]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1394:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1395:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2993:%.*]] = icmp ugt i32 [[TMP1394]], [[TMP1395]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2993]], label [[COND_TRUE2995:%.*]], label [[COND_FALSE2996:%.*]]
|
|
// SIMD-ONLY0: cond.true2995:
|
|
// SIMD-ONLY0-NEXT: [[TMP1396:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2997:%.*]]
|
|
// SIMD-ONLY0: cond.false2996:
|
|
// SIMD-ONLY0-NEXT: [[TMP1397:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END2997]]
|
|
// SIMD-ONLY0: cond.end2997:
|
|
// SIMD-ONLY0-NEXT: [[COND2998:%.*]] = phi i32 [ [[TMP1396]], [[COND_TRUE2995]] ], [ [[TMP1397]], [[COND_FALSE2996]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND2998]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1398:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1399:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2999:%.*]] = icmp ult i32 [[TMP1398]], [[TMP1399]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2999]], label [[COND_TRUE3001:%.*]], label [[COND_FALSE3002:%.*]]
|
|
// SIMD-ONLY0: cond.true3001:
|
|
// SIMD-ONLY0-NEXT: [[TMP1400:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3003:%.*]]
|
|
// SIMD-ONLY0: cond.false3002:
|
|
// SIMD-ONLY0-NEXT: [[TMP1401:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3003]]
|
|
// SIMD-ONLY0: cond.end3003:
|
|
// SIMD-ONLY0-NEXT: [[COND3004:%.*]] = phi i32 [ [[TMP1400]], [[COND_TRUE3001]] ], [ [[TMP1401]], [[COND_FALSE3002]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3004]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1402:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1403:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3005:%.*]] = icmp ugt i32 [[TMP1402]], [[TMP1403]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3005]], label [[IF_THEN3007:%.*]], label [[IF_END3008:%.*]]
|
|
// SIMD-ONLY0: if.then3007:
|
|
// SIMD-ONLY0-NEXT: [[TMP1404:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1404]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3008]]
|
|
// SIMD-ONLY0: if.end3008:
|
|
// SIMD-ONLY0-NEXT: [[TMP1405:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1406:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3009:%.*]] = icmp ult i32 [[TMP1405]], [[TMP1406]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3009]], label [[IF_THEN3011:%.*]], label [[IF_END3012:%.*]]
|
|
// SIMD-ONLY0: if.then3011:
|
|
// SIMD-ONLY0-NEXT: [[TMP1407:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1407]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3012]]
|
|
// SIMD-ONLY0: if.end3012:
|
|
// SIMD-ONLY0-NEXT: [[TMP1408:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1409:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3013:%.*]] = icmp ugt i32 [[TMP1408]], [[TMP1409]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3013]], label [[IF_THEN3015:%.*]], label [[IF_END3016:%.*]]
|
|
// SIMD-ONLY0: if.then3015:
|
|
// SIMD-ONLY0-NEXT: [[TMP1410:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1410]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3016]]
|
|
// SIMD-ONLY0: if.end3016:
|
|
// SIMD-ONLY0-NEXT: [[TMP1411:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1412:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3017:%.*]] = icmp ult i32 [[TMP1411]], [[TMP1412]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3017]], label [[IF_THEN3019:%.*]], label [[IF_END3020:%.*]]
|
|
// SIMD-ONLY0: if.then3019:
|
|
// SIMD-ONLY0-NEXT: [[TMP1413:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1413]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3020]]
|
|
// SIMD-ONLY0: if.end3020:
|
|
// SIMD-ONLY0-NEXT: [[TMP1414:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1415:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3021:%.*]] = icmp eq i32 [[TMP1414]], [[TMP1415]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3021]], label [[COND_TRUE3023:%.*]], label [[COND_FALSE3024:%.*]]
|
|
// SIMD-ONLY0: cond.true3023:
|
|
// SIMD-ONLY0-NEXT: [[TMP1416:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3025:%.*]]
|
|
// SIMD-ONLY0: cond.false3024:
|
|
// SIMD-ONLY0-NEXT: [[TMP1417:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3025]]
|
|
// SIMD-ONLY0: cond.end3025:
|
|
// SIMD-ONLY0-NEXT: [[COND3026:%.*]] = phi i32 [ [[TMP1416]], [[COND_TRUE3023]] ], [ [[TMP1417]], [[COND_FALSE3024]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3026]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1418:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1419:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3027:%.*]] = icmp eq i32 [[TMP1418]], [[TMP1419]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3027]], label [[COND_TRUE3029:%.*]], label [[COND_FALSE3030:%.*]]
|
|
// SIMD-ONLY0: cond.true3029:
|
|
// SIMD-ONLY0-NEXT: [[TMP1420:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3031:%.*]]
|
|
// SIMD-ONLY0: cond.false3030:
|
|
// SIMD-ONLY0-NEXT: [[TMP1421:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3031]]
|
|
// SIMD-ONLY0: cond.end3031:
|
|
// SIMD-ONLY0-NEXT: [[COND3032:%.*]] = phi i32 [ [[TMP1420]], [[COND_TRUE3029]] ], [ [[TMP1421]], [[COND_FALSE3030]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3032]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1422:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1423:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3033:%.*]] = icmp eq i32 [[TMP1422]], [[TMP1423]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3033]], label [[IF_THEN3035:%.*]], label [[IF_END3036:%.*]]
|
|
// SIMD-ONLY0: if.then3035:
|
|
// SIMD-ONLY0-NEXT: [[TMP1424:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1424]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3036]]
|
|
// SIMD-ONLY0: if.end3036:
|
|
// SIMD-ONLY0-NEXT: [[TMP1425:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1426:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3037:%.*]] = icmp eq i32 [[TMP1425]], [[TMP1426]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3037]], label [[IF_THEN3039:%.*]], label [[IF_END3040:%.*]]
|
|
// SIMD-ONLY0: if.then3039:
|
|
// SIMD-ONLY0-NEXT: [[TMP1427:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1427]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3040]]
|
|
// SIMD-ONLY0: if.end3040:
|
|
// SIMD-ONLY0-NEXT: [[TMP1428:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1429:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3041:%.*]] = icmp sgt i32 [[TMP1428]], [[TMP1429]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3041]], label [[COND_TRUE3043:%.*]], label [[COND_FALSE3044:%.*]]
|
|
// SIMD-ONLY0: cond.true3043:
|
|
// SIMD-ONLY0-NEXT: [[TMP1430:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3045:%.*]]
|
|
// SIMD-ONLY0: cond.false3044:
|
|
// SIMD-ONLY0-NEXT: [[TMP1431:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3045]]
|
|
// SIMD-ONLY0: cond.end3045:
|
|
// SIMD-ONLY0-NEXT: [[COND3046:%.*]] = phi i32 [ [[TMP1430]], [[COND_TRUE3043]] ], [ [[TMP1431]], [[COND_FALSE3044]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3046]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1432:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1433:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3047:%.*]] = icmp slt i32 [[TMP1432]], [[TMP1433]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3047]], label [[COND_TRUE3049:%.*]], label [[COND_FALSE3050:%.*]]
|
|
// SIMD-ONLY0: cond.true3049:
|
|
// SIMD-ONLY0-NEXT: [[TMP1434:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3051:%.*]]
|
|
// SIMD-ONLY0: cond.false3050:
|
|
// SIMD-ONLY0-NEXT: [[TMP1435:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3051]]
|
|
// SIMD-ONLY0: cond.end3051:
|
|
// SIMD-ONLY0-NEXT: [[COND3052:%.*]] = phi i32 [ [[TMP1434]], [[COND_TRUE3049]] ], [ [[TMP1435]], [[COND_FALSE3050]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3052]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1436:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1437:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3053:%.*]] = icmp sgt i32 [[TMP1436]], [[TMP1437]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3053]], label [[COND_TRUE3055:%.*]], label [[COND_FALSE3056:%.*]]
|
|
// SIMD-ONLY0: cond.true3055:
|
|
// SIMD-ONLY0-NEXT: [[TMP1438:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3057:%.*]]
|
|
// SIMD-ONLY0: cond.false3056:
|
|
// SIMD-ONLY0-NEXT: [[TMP1439:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3057]]
|
|
// SIMD-ONLY0: cond.end3057:
|
|
// SIMD-ONLY0-NEXT: [[COND3058:%.*]] = phi i32 [ [[TMP1438]], [[COND_TRUE3055]] ], [ [[TMP1439]], [[COND_FALSE3056]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3058]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1440:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1441:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3059:%.*]] = icmp slt i32 [[TMP1440]], [[TMP1441]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3059]], label [[COND_TRUE3061:%.*]], label [[COND_FALSE3062:%.*]]
|
|
// SIMD-ONLY0: cond.true3061:
|
|
// SIMD-ONLY0-NEXT: [[TMP1442:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3063:%.*]]
|
|
// SIMD-ONLY0: cond.false3062:
|
|
// SIMD-ONLY0-NEXT: [[TMP1443:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3063]]
|
|
// SIMD-ONLY0: cond.end3063:
|
|
// SIMD-ONLY0-NEXT: [[COND3064:%.*]] = phi i32 [ [[TMP1442]], [[COND_TRUE3061]] ], [ [[TMP1443]], [[COND_FALSE3062]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3064]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1444:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1445:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3065:%.*]] = icmp sgt i32 [[TMP1444]], [[TMP1445]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3065]], label [[IF_THEN3067:%.*]], label [[IF_END3068:%.*]]
|
|
// SIMD-ONLY0: if.then3067:
|
|
// SIMD-ONLY0-NEXT: [[TMP1446:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1446]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3068]]
|
|
// SIMD-ONLY0: if.end3068:
|
|
// SIMD-ONLY0-NEXT: [[TMP1447:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1448:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3069:%.*]] = icmp slt i32 [[TMP1447]], [[TMP1448]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3069]], label [[IF_THEN3071:%.*]], label [[IF_END3072:%.*]]
|
|
// SIMD-ONLY0: if.then3071:
|
|
// SIMD-ONLY0-NEXT: [[TMP1449:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1449]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3072]]
|
|
// SIMD-ONLY0: if.end3072:
|
|
// SIMD-ONLY0-NEXT: [[TMP1450:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1451:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3073:%.*]] = icmp sgt i32 [[TMP1450]], [[TMP1451]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3073]], label [[IF_THEN3075:%.*]], label [[IF_END3076:%.*]]
|
|
// SIMD-ONLY0: if.then3075:
|
|
// SIMD-ONLY0-NEXT: [[TMP1452:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1452]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3076]]
|
|
// SIMD-ONLY0: if.end3076:
|
|
// SIMD-ONLY0-NEXT: [[TMP1453:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1454:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3077:%.*]] = icmp slt i32 [[TMP1453]], [[TMP1454]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3077]], label [[IF_THEN3079:%.*]], label [[IF_END3080:%.*]]
|
|
// SIMD-ONLY0: if.then3079:
|
|
// SIMD-ONLY0-NEXT: [[TMP1455:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1455]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3080]]
|
|
// SIMD-ONLY0: if.end3080:
|
|
// SIMD-ONLY0-NEXT: [[TMP1456:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1457:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3081:%.*]] = icmp eq i32 [[TMP1456]], [[TMP1457]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3081]], label [[COND_TRUE3083:%.*]], label [[COND_FALSE3084:%.*]]
|
|
// SIMD-ONLY0: cond.true3083:
|
|
// SIMD-ONLY0-NEXT: [[TMP1458:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3085:%.*]]
|
|
// SIMD-ONLY0: cond.false3084:
|
|
// SIMD-ONLY0-NEXT: [[TMP1459:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3085]]
|
|
// SIMD-ONLY0: cond.end3085:
|
|
// SIMD-ONLY0-NEXT: [[COND3086:%.*]] = phi i32 [ [[TMP1458]], [[COND_TRUE3083]] ], [ [[TMP1459]], [[COND_FALSE3084]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3086]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1460:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1461:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3087:%.*]] = icmp eq i32 [[TMP1460]], [[TMP1461]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3087]], label [[COND_TRUE3089:%.*]], label [[COND_FALSE3090:%.*]]
|
|
// SIMD-ONLY0: cond.true3089:
|
|
// SIMD-ONLY0-NEXT: [[TMP1462:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3091:%.*]]
|
|
// SIMD-ONLY0: cond.false3090:
|
|
// SIMD-ONLY0-NEXT: [[TMP1463:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3091]]
|
|
// SIMD-ONLY0: cond.end3091:
|
|
// SIMD-ONLY0-NEXT: [[COND3092:%.*]] = phi i32 [ [[TMP1462]], [[COND_TRUE3089]] ], [ [[TMP1463]], [[COND_FALSE3090]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3092]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1464:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1465:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3093:%.*]] = icmp eq i32 [[TMP1464]], [[TMP1465]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3093]], label [[IF_THEN3095:%.*]], label [[IF_END3096:%.*]]
|
|
// SIMD-ONLY0: if.then3095:
|
|
// SIMD-ONLY0-NEXT: [[TMP1466:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1466]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3096]]
|
|
// SIMD-ONLY0: if.end3096:
|
|
// SIMD-ONLY0-NEXT: [[TMP1467:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1468:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3097:%.*]] = icmp eq i32 [[TMP1467]], [[TMP1468]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3097]], label [[IF_THEN3099:%.*]], label [[IF_END3100:%.*]]
|
|
// SIMD-ONLY0: if.then3099:
|
|
// SIMD-ONLY0-NEXT: [[TMP1469:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1469]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3100]]
|
|
// SIMD-ONLY0: if.end3100:
|
|
// SIMD-ONLY0-NEXT: [[TMP1470:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1471:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3101:%.*]] = icmp ugt i32 [[TMP1470]], [[TMP1471]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3101]], label [[COND_TRUE3103:%.*]], label [[COND_FALSE3104:%.*]]
|
|
// SIMD-ONLY0: cond.true3103:
|
|
// SIMD-ONLY0-NEXT: [[TMP1472:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3105:%.*]]
|
|
// SIMD-ONLY0: cond.false3104:
|
|
// SIMD-ONLY0-NEXT: [[TMP1473:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3105]]
|
|
// SIMD-ONLY0: cond.end3105:
|
|
// SIMD-ONLY0-NEXT: [[COND3106:%.*]] = phi i32 [ [[TMP1472]], [[COND_TRUE3103]] ], [ [[TMP1473]], [[COND_FALSE3104]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3106]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1474:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1475:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3107:%.*]] = icmp ult i32 [[TMP1474]], [[TMP1475]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3107]], label [[COND_TRUE3109:%.*]], label [[COND_FALSE3110:%.*]]
|
|
// SIMD-ONLY0: cond.true3109:
|
|
// SIMD-ONLY0-NEXT: [[TMP1476:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3111:%.*]]
|
|
// SIMD-ONLY0: cond.false3110:
|
|
// SIMD-ONLY0-NEXT: [[TMP1477:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3111]]
|
|
// SIMD-ONLY0: cond.end3111:
|
|
// SIMD-ONLY0-NEXT: [[COND3112:%.*]] = phi i32 [ [[TMP1476]], [[COND_TRUE3109]] ], [ [[TMP1477]], [[COND_FALSE3110]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3112]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1478:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1479:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3113:%.*]] = icmp ugt i32 [[TMP1478]], [[TMP1479]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3113]], label [[COND_TRUE3115:%.*]], label [[COND_FALSE3116:%.*]]
|
|
// SIMD-ONLY0: cond.true3115:
|
|
// SIMD-ONLY0-NEXT: [[TMP1480:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3117:%.*]]
|
|
// SIMD-ONLY0: cond.false3116:
|
|
// SIMD-ONLY0-NEXT: [[TMP1481:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3117]]
|
|
// SIMD-ONLY0: cond.end3117:
|
|
// SIMD-ONLY0-NEXT: [[COND3118:%.*]] = phi i32 [ [[TMP1480]], [[COND_TRUE3115]] ], [ [[TMP1481]], [[COND_FALSE3116]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3118]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1482:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1483:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3119:%.*]] = icmp ult i32 [[TMP1482]], [[TMP1483]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3119]], label [[COND_TRUE3121:%.*]], label [[COND_FALSE3122:%.*]]
|
|
// SIMD-ONLY0: cond.true3121:
|
|
// SIMD-ONLY0-NEXT: [[TMP1484:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3123:%.*]]
|
|
// SIMD-ONLY0: cond.false3122:
|
|
// SIMD-ONLY0-NEXT: [[TMP1485:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3123]]
|
|
// SIMD-ONLY0: cond.end3123:
|
|
// SIMD-ONLY0-NEXT: [[COND3124:%.*]] = phi i32 [ [[TMP1484]], [[COND_TRUE3121]] ], [ [[TMP1485]], [[COND_FALSE3122]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3124]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1486:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1487:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3125:%.*]] = icmp ugt i32 [[TMP1486]], [[TMP1487]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3125]], label [[IF_THEN3127:%.*]], label [[IF_END3128:%.*]]
|
|
// SIMD-ONLY0: if.then3127:
|
|
// SIMD-ONLY0-NEXT: [[TMP1488:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1488]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3128]]
|
|
// SIMD-ONLY0: if.end3128:
|
|
// SIMD-ONLY0-NEXT: [[TMP1489:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1490:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3129:%.*]] = icmp ult i32 [[TMP1489]], [[TMP1490]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3129]], label [[IF_THEN3131:%.*]], label [[IF_END3132:%.*]]
|
|
// SIMD-ONLY0: if.then3131:
|
|
// SIMD-ONLY0-NEXT: [[TMP1491:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1491]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3132]]
|
|
// SIMD-ONLY0: if.end3132:
|
|
// SIMD-ONLY0-NEXT: [[TMP1492:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1493:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3133:%.*]] = icmp ugt i32 [[TMP1492]], [[TMP1493]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3133]], label [[IF_THEN3135:%.*]], label [[IF_END3136:%.*]]
|
|
// SIMD-ONLY0: if.then3135:
|
|
// SIMD-ONLY0-NEXT: [[TMP1494:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1494]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3136]]
|
|
// SIMD-ONLY0: if.end3136:
|
|
// SIMD-ONLY0-NEXT: [[TMP1495:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1496:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3137:%.*]] = icmp ult i32 [[TMP1495]], [[TMP1496]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3137]], label [[IF_THEN3139:%.*]], label [[IF_END3140:%.*]]
|
|
// SIMD-ONLY0: if.then3139:
|
|
// SIMD-ONLY0-NEXT: [[TMP1497:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1497]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3140]]
|
|
// SIMD-ONLY0: if.end3140:
|
|
// SIMD-ONLY0-NEXT: [[TMP1498:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1499:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3141:%.*]] = icmp eq i32 [[TMP1498]], [[TMP1499]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3141]], label [[COND_TRUE3143:%.*]], label [[COND_FALSE3144:%.*]]
|
|
// SIMD-ONLY0: cond.true3143:
|
|
// SIMD-ONLY0-NEXT: [[TMP1500:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3145:%.*]]
|
|
// SIMD-ONLY0: cond.false3144:
|
|
// SIMD-ONLY0-NEXT: [[TMP1501:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3145]]
|
|
// SIMD-ONLY0: cond.end3145:
|
|
// SIMD-ONLY0-NEXT: [[COND3146:%.*]] = phi i32 [ [[TMP1500]], [[COND_TRUE3143]] ], [ [[TMP1501]], [[COND_FALSE3144]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3146]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1502:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1503:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3147:%.*]] = icmp eq i32 [[TMP1502]], [[TMP1503]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3147]], label [[COND_TRUE3149:%.*]], label [[COND_FALSE3150:%.*]]
|
|
// SIMD-ONLY0: cond.true3149:
|
|
// SIMD-ONLY0-NEXT: [[TMP1504:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3151:%.*]]
|
|
// SIMD-ONLY0: cond.false3150:
|
|
// SIMD-ONLY0-NEXT: [[TMP1505:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3151]]
|
|
// SIMD-ONLY0: cond.end3151:
|
|
// SIMD-ONLY0-NEXT: [[COND3152:%.*]] = phi i32 [ [[TMP1504]], [[COND_TRUE3149]] ], [ [[TMP1505]], [[COND_FALSE3150]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND3152]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1506:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1507:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3153:%.*]] = icmp eq i32 [[TMP1506]], [[TMP1507]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3153]], label [[IF_THEN3155:%.*]], label [[IF_END3156:%.*]]
|
|
// SIMD-ONLY0: if.then3155:
|
|
// SIMD-ONLY0-NEXT: [[TMP1508:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1508]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3156]]
|
|
// SIMD-ONLY0: if.end3156:
|
|
// SIMD-ONLY0-NEXT: [[TMP1509:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1510:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3157:%.*]] = icmp eq i32 [[TMP1509]], [[TMP1510]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3157]], label [[IF_THEN3159:%.*]], label [[IF_END3160:%.*]]
|
|
// SIMD-ONLY0: if.then3159:
|
|
// SIMD-ONLY0-NEXT: [[TMP1511:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1511]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3160]]
|
|
// SIMD-ONLY0: if.end3160:
|
|
// SIMD-ONLY0-NEXT: [[TMP1512:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1513:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3161:%.*]] = icmp sgt i64 [[TMP1512]], [[TMP1513]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3161]], label [[COND_TRUE3163:%.*]], label [[COND_FALSE3164:%.*]]
|
|
// SIMD-ONLY0: cond.true3163:
|
|
// SIMD-ONLY0-NEXT: [[TMP1514:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3165:%.*]]
|
|
// SIMD-ONLY0: cond.false3164:
|
|
// SIMD-ONLY0-NEXT: [[TMP1515:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3165]]
|
|
// SIMD-ONLY0: cond.end3165:
|
|
// SIMD-ONLY0-NEXT: [[COND3166:%.*]] = phi i64 [ [[TMP1514]], [[COND_TRUE3163]] ], [ [[TMP1515]], [[COND_FALSE3164]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3166]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1516:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1517:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3167:%.*]] = icmp slt i64 [[TMP1516]], [[TMP1517]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3167]], label [[COND_TRUE3169:%.*]], label [[COND_FALSE3170:%.*]]
|
|
// SIMD-ONLY0: cond.true3169:
|
|
// SIMD-ONLY0-NEXT: [[TMP1518:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3171:%.*]]
|
|
// SIMD-ONLY0: cond.false3170:
|
|
// SIMD-ONLY0-NEXT: [[TMP1519:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3171]]
|
|
// SIMD-ONLY0: cond.end3171:
|
|
// SIMD-ONLY0-NEXT: [[COND3172:%.*]] = phi i64 [ [[TMP1518]], [[COND_TRUE3169]] ], [ [[TMP1519]], [[COND_FALSE3170]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3172]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1520:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1521:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3173:%.*]] = icmp sgt i64 [[TMP1520]], [[TMP1521]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3173]], label [[COND_TRUE3175:%.*]], label [[COND_FALSE3176:%.*]]
|
|
// SIMD-ONLY0: cond.true3175:
|
|
// SIMD-ONLY0-NEXT: [[TMP1522:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3177:%.*]]
|
|
// SIMD-ONLY0: cond.false3176:
|
|
// SIMD-ONLY0-NEXT: [[TMP1523:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3177]]
|
|
// SIMD-ONLY0: cond.end3177:
|
|
// SIMD-ONLY0-NEXT: [[COND3178:%.*]] = phi i64 [ [[TMP1522]], [[COND_TRUE3175]] ], [ [[TMP1523]], [[COND_FALSE3176]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3178]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1524:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1525:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3179:%.*]] = icmp slt i64 [[TMP1524]], [[TMP1525]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3179]], label [[COND_TRUE3181:%.*]], label [[COND_FALSE3182:%.*]]
|
|
// SIMD-ONLY0: cond.true3181:
|
|
// SIMD-ONLY0-NEXT: [[TMP1526:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3183:%.*]]
|
|
// SIMD-ONLY0: cond.false3182:
|
|
// SIMD-ONLY0-NEXT: [[TMP1527:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3183]]
|
|
// SIMD-ONLY0: cond.end3183:
|
|
// SIMD-ONLY0-NEXT: [[COND3184:%.*]] = phi i64 [ [[TMP1526]], [[COND_TRUE3181]] ], [ [[TMP1527]], [[COND_FALSE3182]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3184]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1528:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1529:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3185:%.*]] = icmp sgt i64 [[TMP1528]], [[TMP1529]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3185]], label [[IF_THEN3187:%.*]], label [[IF_END3188:%.*]]
|
|
// SIMD-ONLY0: if.then3187:
|
|
// SIMD-ONLY0-NEXT: [[TMP1530:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1530]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3188]]
|
|
// SIMD-ONLY0: if.end3188:
|
|
// SIMD-ONLY0-NEXT: [[TMP1531:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1532:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3189:%.*]] = icmp slt i64 [[TMP1531]], [[TMP1532]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3189]], label [[IF_THEN3191:%.*]], label [[IF_END3192:%.*]]
|
|
// SIMD-ONLY0: if.then3191:
|
|
// SIMD-ONLY0-NEXT: [[TMP1533:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1533]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3192]]
|
|
// SIMD-ONLY0: if.end3192:
|
|
// SIMD-ONLY0-NEXT: [[TMP1534:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1535:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3193:%.*]] = icmp sgt i64 [[TMP1534]], [[TMP1535]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3193]], label [[IF_THEN3195:%.*]], label [[IF_END3196:%.*]]
|
|
// SIMD-ONLY0: if.then3195:
|
|
// SIMD-ONLY0-NEXT: [[TMP1536:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1536]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3196]]
|
|
// SIMD-ONLY0: if.end3196:
|
|
// SIMD-ONLY0-NEXT: [[TMP1537:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1538:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3197:%.*]] = icmp slt i64 [[TMP1537]], [[TMP1538]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3197]], label [[IF_THEN3199:%.*]], label [[IF_END3200:%.*]]
|
|
// SIMD-ONLY0: if.then3199:
|
|
// SIMD-ONLY0-NEXT: [[TMP1539:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1539]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3200]]
|
|
// SIMD-ONLY0: if.end3200:
|
|
// SIMD-ONLY0-NEXT: [[TMP1540:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1541:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3201:%.*]] = icmp eq i64 [[TMP1540]], [[TMP1541]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3201]], label [[COND_TRUE3203:%.*]], label [[COND_FALSE3204:%.*]]
|
|
// SIMD-ONLY0: cond.true3203:
|
|
// SIMD-ONLY0-NEXT: [[TMP1542:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3205:%.*]]
|
|
// SIMD-ONLY0: cond.false3204:
|
|
// SIMD-ONLY0-NEXT: [[TMP1543:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3205]]
|
|
// SIMD-ONLY0: cond.end3205:
|
|
// SIMD-ONLY0-NEXT: [[COND3206:%.*]] = phi i64 [ [[TMP1542]], [[COND_TRUE3203]] ], [ [[TMP1543]], [[COND_FALSE3204]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3206]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1544:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1545:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3207:%.*]] = icmp eq i64 [[TMP1544]], [[TMP1545]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3207]], label [[COND_TRUE3209:%.*]], label [[COND_FALSE3210:%.*]]
|
|
// SIMD-ONLY0: cond.true3209:
|
|
// SIMD-ONLY0-NEXT: [[TMP1546:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3211:%.*]]
|
|
// SIMD-ONLY0: cond.false3210:
|
|
// SIMD-ONLY0-NEXT: [[TMP1547:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3211]]
|
|
// SIMD-ONLY0: cond.end3211:
|
|
// SIMD-ONLY0-NEXT: [[COND3212:%.*]] = phi i64 [ [[TMP1546]], [[COND_TRUE3209]] ], [ [[TMP1547]], [[COND_FALSE3210]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3212]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1548:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1549:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3213:%.*]] = icmp eq i64 [[TMP1548]], [[TMP1549]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3213]], label [[IF_THEN3215:%.*]], label [[IF_END3216:%.*]]
|
|
// SIMD-ONLY0: if.then3215:
|
|
// SIMD-ONLY0-NEXT: [[TMP1550:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1550]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3216]]
|
|
// SIMD-ONLY0: if.end3216:
|
|
// SIMD-ONLY0-NEXT: [[TMP1551:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1552:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3217:%.*]] = icmp eq i64 [[TMP1551]], [[TMP1552]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3217]], label [[IF_THEN3219:%.*]], label [[IF_END3220:%.*]]
|
|
// SIMD-ONLY0: if.then3219:
|
|
// SIMD-ONLY0-NEXT: [[TMP1553:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1553]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3220]]
|
|
// SIMD-ONLY0: if.end3220:
|
|
// SIMD-ONLY0-NEXT: [[TMP1554:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1555:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3221:%.*]] = icmp ugt i64 [[TMP1554]], [[TMP1555]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3221]], label [[COND_TRUE3223:%.*]], label [[COND_FALSE3224:%.*]]
|
|
// SIMD-ONLY0: cond.true3223:
|
|
// SIMD-ONLY0-NEXT: [[TMP1556:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3225:%.*]]
|
|
// SIMD-ONLY0: cond.false3224:
|
|
// SIMD-ONLY0-NEXT: [[TMP1557:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3225]]
|
|
// SIMD-ONLY0: cond.end3225:
|
|
// SIMD-ONLY0-NEXT: [[COND3226:%.*]] = phi i64 [ [[TMP1556]], [[COND_TRUE3223]] ], [ [[TMP1557]], [[COND_FALSE3224]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3226]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1558:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1559:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3227:%.*]] = icmp ult i64 [[TMP1558]], [[TMP1559]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3227]], label [[COND_TRUE3229:%.*]], label [[COND_FALSE3230:%.*]]
|
|
// SIMD-ONLY0: cond.true3229:
|
|
// SIMD-ONLY0-NEXT: [[TMP1560:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3231:%.*]]
|
|
// SIMD-ONLY0: cond.false3230:
|
|
// SIMD-ONLY0-NEXT: [[TMP1561:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3231]]
|
|
// SIMD-ONLY0: cond.end3231:
|
|
// SIMD-ONLY0-NEXT: [[COND3232:%.*]] = phi i64 [ [[TMP1560]], [[COND_TRUE3229]] ], [ [[TMP1561]], [[COND_FALSE3230]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3232]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1562:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1563:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3233:%.*]] = icmp ugt i64 [[TMP1562]], [[TMP1563]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3233]], label [[COND_TRUE3235:%.*]], label [[COND_FALSE3236:%.*]]
|
|
// SIMD-ONLY0: cond.true3235:
|
|
// SIMD-ONLY0-NEXT: [[TMP1564:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3237:%.*]]
|
|
// SIMD-ONLY0: cond.false3236:
|
|
// SIMD-ONLY0-NEXT: [[TMP1565:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3237]]
|
|
// SIMD-ONLY0: cond.end3237:
|
|
// SIMD-ONLY0-NEXT: [[COND3238:%.*]] = phi i64 [ [[TMP1564]], [[COND_TRUE3235]] ], [ [[TMP1565]], [[COND_FALSE3236]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3238]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1566:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1567:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3239:%.*]] = icmp ult i64 [[TMP1566]], [[TMP1567]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3239]], label [[COND_TRUE3241:%.*]], label [[COND_FALSE3242:%.*]]
|
|
// SIMD-ONLY0: cond.true3241:
|
|
// SIMD-ONLY0-NEXT: [[TMP1568:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3243:%.*]]
|
|
// SIMD-ONLY0: cond.false3242:
|
|
// SIMD-ONLY0-NEXT: [[TMP1569:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3243]]
|
|
// SIMD-ONLY0: cond.end3243:
|
|
// SIMD-ONLY0-NEXT: [[COND3244:%.*]] = phi i64 [ [[TMP1568]], [[COND_TRUE3241]] ], [ [[TMP1569]], [[COND_FALSE3242]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3244]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1570:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1571:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3245:%.*]] = icmp ugt i64 [[TMP1570]], [[TMP1571]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3245]], label [[IF_THEN3247:%.*]], label [[IF_END3248:%.*]]
|
|
// SIMD-ONLY0: if.then3247:
|
|
// SIMD-ONLY0-NEXT: [[TMP1572:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1572]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3248]]
|
|
// SIMD-ONLY0: if.end3248:
|
|
// SIMD-ONLY0-NEXT: [[TMP1573:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1574:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3249:%.*]] = icmp ult i64 [[TMP1573]], [[TMP1574]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3249]], label [[IF_THEN3251:%.*]], label [[IF_END3252:%.*]]
|
|
// SIMD-ONLY0: if.then3251:
|
|
// SIMD-ONLY0-NEXT: [[TMP1575:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1575]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3252]]
|
|
// SIMD-ONLY0: if.end3252:
|
|
// SIMD-ONLY0-NEXT: [[TMP1576:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1577:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3253:%.*]] = icmp ugt i64 [[TMP1576]], [[TMP1577]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3253]], label [[IF_THEN3255:%.*]], label [[IF_END3256:%.*]]
|
|
// SIMD-ONLY0: if.then3255:
|
|
// SIMD-ONLY0-NEXT: [[TMP1578:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1578]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3256]]
|
|
// SIMD-ONLY0: if.end3256:
|
|
// SIMD-ONLY0-NEXT: [[TMP1579:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1580:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3257:%.*]] = icmp ult i64 [[TMP1579]], [[TMP1580]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3257]], label [[IF_THEN3259:%.*]], label [[IF_END3260:%.*]]
|
|
// SIMD-ONLY0: if.then3259:
|
|
// SIMD-ONLY0-NEXT: [[TMP1581:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1581]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3260]]
|
|
// SIMD-ONLY0: if.end3260:
|
|
// SIMD-ONLY0-NEXT: [[TMP1582:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1583:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3261:%.*]] = icmp eq i64 [[TMP1582]], [[TMP1583]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3261]], label [[COND_TRUE3263:%.*]], label [[COND_FALSE3264:%.*]]
|
|
// SIMD-ONLY0: cond.true3263:
|
|
// SIMD-ONLY0-NEXT: [[TMP1584:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3265:%.*]]
|
|
// SIMD-ONLY0: cond.false3264:
|
|
// SIMD-ONLY0-NEXT: [[TMP1585:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3265]]
|
|
// SIMD-ONLY0: cond.end3265:
|
|
// SIMD-ONLY0-NEXT: [[COND3266:%.*]] = phi i64 [ [[TMP1584]], [[COND_TRUE3263]] ], [ [[TMP1585]], [[COND_FALSE3264]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3266]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1586:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1587:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3267:%.*]] = icmp eq i64 [[TMP1586]], [[TMP1587]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3267]], label [[COND_TRUE3269:%.*]], label [[COND_FALSE3270:%.*]]
|
|
// SIMD-ONLY0: cond.true3269:
|
|
// SIMD-ONLY0-NEXT: [[TMP1588:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3271:%.*]]
|
|
// SIMD-ONLY0: cond.false3270:
|
|
// SIMD-ONLY0-NEXT: [[TMP1589:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3271]]
|
|
// SIMD-ONLY0: cond.end3271:
|
|
// SIMD-ONLY0-NEXT: [[COND3272:%.*]] = phi i64 [ [[TMP1588]], [[COND_TRUE3269]] ], [ [[TMP1589]], [[COND_FALSE3270]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3272]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1590:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1591:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3273:%.*]] = icmp eq i64 [[TMP1590]], [[TMP1591]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3273]], label [[IF_THEN3275:%.*]], label [[IF_END3276:%.*]]
|
|
// SIMD-ONLY0: if.then3275:
|
|
// SIMD-ONLY0-NEXT: [[TMP1592:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1592]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3276]]
|
|
// SIMD-ONLY0: if.end3276:
|
|
// SIMD-ONLY0-NEXT: [[TMP1593:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1594:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3277:%.*]] = icmp eq i64 [[TMP1593]], [[TMP1594]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3277]], label [[IF_THEN3279:%.*]], label [[IF_END3280:%.*]]
|
|
// SIMD-ONLY0: if.then3279:
|
|
// SIMD-ONLY0-NEXT: [[TMP1595:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1595]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3280]]
|
|
// SIMD-ONLY0: if.end3280:
|
|
// SIMD-ONLY0-NEXT: [[TMP1596:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1597:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3281:%.*]] = icmp sgt i64 [[TMP1596]], [[TMP1597]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3281]], label [[COND_TRUE3283:%.*]], label [[COND_FALSE3284:%.*]]
|
|
// SIMD-ONLY0: cond.true3283:
|
|
// SIMD-ONLY0-NEXT: [[TMP1598:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3285:%.*]]
|
|
// SIMD-ONLY0: cond.false3284:
|
|
// SIMD-ONLY0-NEXT: [[TMP1599:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3285]]
|
|
// SIMD-ONLY0: cond.end3285:
|
|
// SIMD-ONLY0-NEXT: [[COND3286:%.*]] = phi i64 [ [[TMP1598]], [[COND_TRUE3283]] ], [ [[TMP1599]], [[COND_FALSE3284]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3286]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1600:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1601:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3287:%.*]] = icmp slt i64 [[TMP1600]], [[TMP1601]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3287]], label [[COND_TRUE3289:%.*]], label [[COND_FALSE3290:%.*]]
|
|
// SIMD-ONLY0: cond.true3289:
|
|
// SIMD-ONLY0-NEXT: [[TMP1602:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3291:%.*]]
|
|
// SIMD-ONLY0: cond.false3290:
|
|
// SIMD-ONLY0-NEXT: [[TMP1603:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3291]]
|
|
// SIMD-ONLY0: cond.end3291:
|
|
// SIMD-ONLY0-NEXT: [[COND3292:%.*]] = phi i64 [ [[TMP1602]], [[COND_TRUE3289]] ], [ [[TMP1603]], [[COND_FALSE3290]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3292]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1604:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1605:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3293:%.*]] = icmp sgt i64 [[TMP1604]], [[TMP1605]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3293]], label [[COND_TRUE3295:%.*]], label [[COND_FALSE3296:%.*]]
|
|
// SIMD-ONLY0: cond.true3295:
|
|
// SIMD-ONLY0-NEXT: [[TMP1606:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3297:%.*]]
|
|
// SIMD-ONLY0: cond.false3296:
|
|
// SIMD-ONLY0-NEXT: [[TMP1607:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3297]]
|
|
// SIMD-ONLY0: cond.end3297:
|
|
// SIMD-ONLY0-NEXT: [[COND3298:%.*]] = phi i64 [ [[TMP1606]], [[COND_TRUE3295]] ], [ [[TMP1607]], [[COND_FALSE3296]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3298]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1608:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1609:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3299:%.*]] = icmp slt i64 [[TMP1608]], [[TMP1609]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3299]], label [[COND_TRUE3301:%.*]], label [[COND_FALSE3302:%.*]]
|
|
// SIMD-ONLY0: cond.true3301:
|
|
// SIMD-ONLY0-NEXT: [[TMP1610:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3303:%.*]]
|
|
// SIMD-ONLY0: cond.false3302:
|
|
// SIMD-ONLY0-NEXT: [[TMP1611:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3303]]
|
|
// SIMD-ONLY0: cond.end3303:
|
|
// SIMD-ONLY0-NEXT: [[COND3304:%.*]] = phi i64 [ [[TMP1610]], [[COND_TRUE3301]] ], [ [[TMP1611]], [[COND_FALSE3302]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3304]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1612:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1613:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3305:%.*]] = icmp sgt i64 [[TMP1612]], [[TMP1613]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3305]], label [[IF_THEN3307:%.*]], label [[IF_END3308:%.*]]
|
|
// SIMD-ONLY0: if.then3307:
|
|
// SIMD-ONLY0-NEXT: [[TMP1614:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1614]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3308]]
|
|
// SIMD-ONLY0: if.end3308:
|
|
// SIMD-ONLY0-NEXT: [[TMP1615:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1616:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3309:%.*]] = icmp slt i64 [[TMP1615]], [[TMP1616]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3309]], label [[IF_THEN3311:%.*]], label [[IF_END3312:%.*]]
|
|
// SIMD-ONLY0: if.then3311:
|
|
// SIMD-ONLY0-NEXT: [[TMP1617:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1617]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3312]]
|
|
// SIMD-ONLY0: if.end3312:
|
|
// SIMD-ONLY0-NEXT: [[TMP1618:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1619:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3313:%.*]] = icmp sgt i64 [[TMP1618]], [[TMP1619]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3313]], label [[IF_THEN3315:%.*]], label [[IF_END3316:%.*]]
|
|
// SIMD-ONLY0: if.then3315:
|
|
// SIMD-ONLY0-NEXT: [[TMP1620:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1620]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3316]]
|
|
// SIMD-ONLY0: if.end3316:
|
|
// SIMD-ONLY0-NEXT: [[TMP1621:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1622:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3317:%.*]] = icmp slt i64 [[TMP1621]], [[TMP1622]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3317]], label [[IF_THEN3319:%.*]], label [[IF_END3320:%.*]]
|
|
// SIMD-ONLY0: if.then3319:
|
|
// SIMD-ONLY0-NEXT: [[TMP1623:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1623]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3320]]
|
|
// SIMD-ONLY0: if.end3320:
|
|
// SIMD-ONLY0-NEXT: [[TMP1624:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1625:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3321:%.*]] = icmp eq i64 [[TMP1624]], [[TMP1625]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3321]], label [[COND_TRUE3323:%.*]], label [[COND_FALSE3324:%.*]]
|
|
// SIMD-ONLY0: cond.true3323:
|
|
// SIMD-ONLY0-NEXT: [[TMP1626:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3325:%.*]]
|
|
// SIMD-ONLY0: cond.false3324:
|
|
// SIMD-ONLY0-NEXT: [[TMP1627:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3325]]
|
|
// SIMD-ONLY0: cond.end3325:
|
|
// SIMD-ONLY0-NEXT: [[COND3326:%.*]] = phi i64 [ [[TMP1626]], [[COND_TRUE3323]] ], [ [[TMP1627]], [[COND_FALSE3324]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3326]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1628:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1629:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3327:%.*]] = icmp eq i64 [[TMP1628]], [[TMP1629]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3327]], label [[COND_TRUE3329:%.*]], label [[COND_FALSE3330:%.*]]
|
|
// SIMD-ONLY0: cond.true3329:
|
|
// SIMD-ONLY0-NEXT: [[TMP1630:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3331:%.*]]
|
|
// SIMD-ONLY0: cond.false3330:
|
|
// SIMD-ONLY0-NEXT: [[TMP1631:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3331]]
|
|
// SIMD-ONLY0: cond.end3331:
|
|
// SIMD-ONLY0-NEXT: [[COND3332:%.*]] = phi i64 [ [[TMP1630]], [[COND_TRUE3329]] ], [ [[TMP1631]], [[COND_FALSE3330]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3332]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1632:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1633:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3333:%.*]] = icmp eq i64 [[TMP1632]], [[TMP1633]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3333]], label [[IF_THEN3335:%.*]], label [[IF_END3336:%.*]]
|
|
// SIMD-ONLY0: if.then3335:
|
|
// SIMD-ONLY0-NEXT: [[TMP1634:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1634]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3336]]
|
|
// SIMD-ONLY0: if.end3336:
|
|
// SIMD-ONLY0-NEXT: [[TMP1635:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1636:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3337:%.*]] = icmp eq i64 [[TMP1635]], [[TMP1636]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3337]], label [[IF_THEN3339:%.*]], label [[IF_END3340:%.*]]
|
|
// SIMD-ONLY0: if.then3339:
|
|
// SIMD-ONLY0-NEXT: [[TMP1637:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1637]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3340]]
|
|
// SIMD-ONLY0: if.end3340:
|
|
// SIMD-ONLY0-NEXT: [[TMP1638:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1639:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3341:%.*]] = icmp ugt i64 [[TMP1638]], [[TMP1639]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3341]], label [[COND_TRUE3343:%.*]], label [[COND_FALSE3344:%.*]]
|
|
// SIMD-ONLY0: cond.true3343:
|
|
// SIMD-ONLY0-NEXT: [[TMP1640:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3345:%.*]]
|
|
// SIMD-ONLY0: cond.false3344:
|
|
// SIMD-ONLY0-NEXT: [[TMP1641:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3345]]
|
|
// SIMD-ONLY0: cond.end3345:
|
|
// SIMD-ONLY0-NEXT: [[COND3346:%.*]] = phi i64 [ [[TMP1640]], [[COND_TRUE3343]] ], [ [[TMP1641]], [[COND_FALSE3344]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3346]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1642:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1643:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3347:%.*]] = icmp ult i64 [[TMP1642]], [[TMP1643]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3347]], label [[COND_TRUE3349:%.*]], label [[COND_FALSE3350:%.*]]
|
|
// SIMD-ONLY0: cond.true3349:
|
|
// SIMD-ONLY0-NEXT: [[TMP1644:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3351:%.*]]
|
|
// SIMD-ONLY0: cond.false3350:
|
|
// SIMD-ONLY0-NEXT: [[TMP1645:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3351]]
|
|
// SIMD-ONLY0: cond.end3351:
|
|
// SIMD-ONLY0-NEXT: [[COND3352:%.*]] = phi i64 [ [[TMP1644]], [[COND_TRUE3349]] ], [ [[TMP1645]], [[COND_FALSE3350]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3352]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1646:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1647:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3353:%.*]] = icmp ugt i64 [[TMP1646]], [[TMP1647]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3353]], label [[COND_TRUE3355:%.*]], label [[COND_FALSE3356:%.*]]
|
|
// SIMD-ONLY0: cond.true3355:
|
|
// SIMD-ONLY0-NEXT: [[TMP1648:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3357:%.*]]
|
|
// SIMD-ONLY0: cond.false3356:
|
|
// SIMD-ONLY0-NEXT: [[TMP1649:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3357]]
|
|
// SIMD-ONLY0: cond.end3357:
|
|
// SIMD-ONLY0-NEXT: [[COND3358:%.*]] = phi i64 [ [[TMP1648]], [[COND_TRUE3355]] ], [ [[TMP1649]], [[COND_FALSE3356]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3358]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1650:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1651:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3359:%.*]] = icmp ult i64 [[TMP1650]], [[TMP1651]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3359]], label [[COND_TRUE3361:%.*]], label [[COND_FALSE3362:%.*]]
|
|
// SIMD-ONLY0: cond.true3361:
|
|
// SIMD-ONLY0-NEXT: [[TMP1652:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3363:%.*]]
|
|
// SIMD-ONLY0: cond.false3362:
|
|
// SIMD-ONLY0-NEXT: [[TMP1653:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3363]]
|
|
// SIMD-ONLY0: cond.end3363:
|
|
// SIMD-ONLY0-NEXT: [[COND3364:%.*]] = phi i64 [ [[TMP1652]], [[COND_TRUE3361]] ], [ [[TMP1653]], [[COND_FALSE3362]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3364]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1654:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1655:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3365:%.*]] = icmp ugt i64 [[TMP1654]], [[TMP1655]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3365]], label [[IF_THEN3367:%.*]], label [[IF_END3368:%.*]]
|
|
// SIMD-ONLY0: if.then3367:
|
|
// SIMD-ONLY0-NEXT: [[TMP1656:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1656]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3368]]
|
|
// SIMD-ONLY0: if.end3368:
|
|
// SIMD-ONLY0-NEXT: [[TMP1657:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1658:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3369:%.*]] = icmp ult i64 [[TMP1657]], [[TMP1658]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3369]], label [[IF_THEN3371:%.*]], label [[IF_END3372:%.*]]
|
|
// SIMD-ONLY0: if.then3371:
|
|
// SIMD-ONLY0-NEXT: [[TMP1659:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1659]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3372]]
|
|
// SIMD-ONLY0: if.end3372:
|
|
// SIMD-ONLY0-NEXT: [[TMP1660:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1661:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3373:%.*]] = icmp ugt i64 [[TMP1660]], [[TMP1661]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3373]], label [[IF_THEN3375:%.*]], label [[IF_END3376:%.*]]
|
|
// SIMD-ONLY0: if.then3375:
|
|
// SIMD-ONLY0-NEXT: [[TMP1662:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1662]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3376]]
|
|
// SIMD-ONLY0: if.end3376:
|
|
// SIMD-ONLY0-NEXT: [[TMP1663:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1664:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3377:%.*]] = icmp ult i64 [[TMP1663]], [[TMP1664]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3377]], label [[IF_THEN3379:%.*]], label [[IF_END3380:%.*]]
|
|
// SIMD-ONLY0: if.then3379:
|
|
// SIMD-ONLY0-NEXT: [[TMP1665:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1665]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3380]]
|
|
// SIMD-ONLY0: if.end3380:
|
|
// SIMD-ONLY0-NEXT: [[TMP1666:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1667:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3381:%.*]] = icmp eq i64 [[TMP1666]], [[TMP1667]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3381]], label [[COND_TRUE3383:%.*]], label [[COND_FALSE3384:%.*]]
|
|
// SIMD-ONLY0: cond.true3383:
|
|
// SIMD-ONLY0-NEXT: [[TMP1668:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3385:%.*]]
|
|
// SIMD-ONLY0: cond.false3384:
|
|
// SIMD-ONLY0-NEXT: [[TMP1669:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3385]]
|
|
// SIMD-ONLY0: cond.end3385:
|
|
// SIMD-ONLY0-NEXT: [[COND3386:%.*]] = phi i64 [ [[TMP1668]], [[COND_TRUE3383]] ], [ [[TMP1669]], [[COND_FALSE3384]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3386]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1670:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1671:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3387:%.*]] = icmp eq i64 [[TMP1670]], [[TMP1671]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3387]], label [[COND_TRUE3389:%.*]], label [[COND_FALSE3390:%.*]]
|
|
// SIMD-ONLY0: cond.true3389:
|
|
// SIMD-ONLY0-NEXT: [[TMP1672:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3391:%.*]]
|
|
// SIMD-ONLY0: cond.false3390:
|
|
// SIMD-ONLY0-NEXT: [[TMP1673:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3391]]
|
|
// SIMD-ONLY0: cond.end3391:
|
|
// SIMD-ONLY0-NEXT: [[COND3392:%.*]] = phi i64 [ [[TMP1672]], [[COND_TRUE3389]] ], [ [[TMP1673]], [[COND_FALSE3390]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3392]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1674:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1675:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3393:%.*]] = icmp eq i64 [[TMP1674]], [[TMP1675]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3393]], label [[IF_THEN3395:%.*]], label [[IF_END3396:%.*]]
|
|
// SIMD-ONLY0: if.then3395:
|
|
// SIMD-ONLY0-NEXT: [[TMP1676:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1676]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3396]]
|
|
// SIMD-ONLY0: if.end3396:
|
|
// SIMD-ONLY0-NEXT: [[TMP1677:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1678:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3397:%.*]] = icmp eq i64 [[TMP1677]], [[TMP1678]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3397]], label [[IF_THEN3399:%.*]], label [[IF_END3400:%.*]]
|
|
// SIMD-ONLY0: if.then3399:
|
|
// SIMD-ONLY0-NEXT: [[TMP1679:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1679]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3400]]
|
|
// SIMD-ONLY0: if.end3400:
|
|
// SIMD-ONLY0-NEXT: [[TMP1680:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1681:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3401:%.*]] = icmp sgt i64 [[TMP1680]], [[TMP1681]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3401]], label [[COND_TRUE3403:%.*]], label [[COND_FALSE3404:%.*]]
|
|
// SIMD-ONLY0: cond.true3403:
|
|
// SIMD-ONLY0-NEXT: [[TMP1682:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3405:%.*]]
|
|
// SIMD-ONLY0: cond.false3404:
|
|
// SIMD-ONLY0-NEXT: [[TMP1683:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3405]]
|
|
// SIMD-ONLY0: cond.end3405:
|
|
// SIMD-ONLY0-NEXT: [[COND3406:%.*]] = phi i64 [ [[TMP1682]], [[COND_TRUE3403]] ], [ [[TMP1683]], [[COND_FALSE3404]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3406]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1684:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1685:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3407:%.*]] = icmp slt i64 [[TMP1684]], [[TMP1685]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3407]], label [[COND_TRUE3409:%.*]], label [[COND_FALSE3410:%.*]]
|
|
// SIMD-ONLY0: cond.true3409:
|
|
// SIMD-ONLY0-NEXT: [[TMP1686:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3411:%.*]]
|
|
// SIMD-ONLY0: cond.false3410:
|
|
// SIMD-ONLY0-NEXT: [[TMP1687:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3411]]
|
|
// SIMD-ONLY0: cond.end3411:
|
|
// SIMD-ONLY0-NEXT: [[COND3412:%.*]] = phi i64 [ [[TMP1686]], [[COND_TRUE3409]] ], [ [[TMP1687]], [[COND_FALSE3410]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3412]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1688:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1689:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3413:%.*]] = icmp sgt i64 [[TMP1688]], [[TMP1689]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3413]], label [[COND_TRUE3415:%.*]], label [[COND_FALSE3416:%.*]]
|
|
// SIMD-ONLY0: cond.true3415:
|
|
// SIMD-ONLY0-NEXT: [[TMP1690:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3417:%.*]]
|
|
// SIMD-ONLY0: cond.false3416:
|
|
// SIMD-ONLY0-NEXT: [[TMP1691:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3417]]
|
|
// SIMD-ONLY0: cond.end3417:
|
|
// SIMD-ONLY0-NEXT: [[COND3418:%.*]] = phi i64 [ [[TMP1690]], [[COND_TRUE3415]] ], [ [[TMP1691]], [[COND_FALSE3416]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3418]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1692:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1693:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3419:%.*]] = icmp slt i64 [[TMP1692]], [[TMP1693]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3419]], label [[COND_TRUE3421:%.*]], label [[COND_FALSE3422:%.*]]
|
|
// SIMD-ONLY0: cond.true3421:
|
|
// SIMD-ONLY0-NEXT: [[TMP1694:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3423:%.*]]
|
|
// SIMD-ONLY0: cond.false3422:
|
|
// SIMD-ONLY0-NEXT: [[TMP1695:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3423]]
|
|
// SIMD-ONLY0: cond.end3423:
|
|
// SIMD-ONLY0-NEXT: [[COND3424:%.*]] = phi i64 [ [[TMP1694]], [[COND_TRUE3421]] ], [ [[TMP1695]], [[COND_FALSE3422]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3424]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1696:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1697:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3425:%.*]] = icmp sgt i64 [[TMP1696]], [[TMP1697]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3425]], label [[IF_THEN3427:%.*]], label [[IF_END3428:%.*]]
|
|
// SIMD-ONLY0: if.then3427:
|
|
// SIMD-ONLY0-NEXT: [[TMP1698:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1698]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3428]]
|
|
// SIMD-ONLY0: if.end3428:
|
|
// SIMD-ONLY0-NEXT: [[TMP1699:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1700:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3429:%.*]] = icmp slt i64 [[TMP1699]], [[TMP1700]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3429]], label [[IF_THEN3431:%.*]], label [[IF_END3432:%.*]]
|
|
// SIMD-ONLY0: if.then3431:
|
|
// SIMD-ONLY0-NEXT: [[TMP1701:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1701]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3432]]
|
|
// SIMD-ONLY0: if.end3432:
|
|
// SIMD-ONLY0-NEXT: [[TMP1702:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1703:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3433:%.*]] = icmp sgt i64 [[TMP1702]], [[TMP1703]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3433]], label [[IF_THEN3435:%.*]], label [[IF_END3436:%.*]]
|
|
// SIMD-ONLY0: if.then3435:
|
|
// SIMD-ONLY0-NEXT: [[TMP1704:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1704]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3436]]
|
|
// SIMD-ONLY0: if.end3436:
|
|
// SIMD-ONLY0-NEXT: [[TMP1705:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1706:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3437:%.*]] = icmp slt i64 [[TMP1705]], [[TMP1706]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3437]], label [[IF_THEN3439:%.*]], label [[IF_END3440:%.*]]
|
|
// SIMD-ONLY0: if.then3439:
|
|
// SIMD-ONLY0-NEXT: [[TMP1707:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1707]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3440]]
|
|
// SIMD-ONLY0: if.end3440:
|
|
// SIMD-ONLY0-NEXT: [[TMP1708:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1709:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3441:%.*]] = icmp eq i64 [[TMP1708]], [[TMP1709]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3441]], label [[COND_TRUE3443:%.*]], label [[COND_FALSE3444:%.*]]
|
|
// SIMD-ONLY0: cond.true3443:
|
|
// SIMD-ONLY0-NEXT: [[TMP1710:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3445:%.*]]
|
|
// SIMD-ONLY0: cond.false3444:
|
|
// SIMD-ONLY0-NEXT: [[TMP1711:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3445]]
|
|
// SIMD-ONLY0: cond.end3445:
|
|
// SIMD-ONLY0-NEXT: [[COND3446:%.*]] = phi i64 [ [[TMP1710]], [[COND_TRUE3443]] ], [ [[TMP1711]], [[COND_FALSE3444]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3446]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1712:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1713:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3447:%.*]] = icmp eq i64 [[TMP1712]], [[TMP1713]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3447]], label [[COND_TRUE3449:%.*]], label [[COND_FALSE3450:%.*]]
|
|
// SIMD-ONLY0: cond.true3449:
|
|
// SIMD-ONLY0-NEXT: [[TMP1714:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3451:%.*]]
|
|
// SIMD-ONLY0: cond.false3450:
|
|
// SIMD-ONLY0-NEXT: [[TMP1715:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3451]]
|
|
// SIMD-ONLY0: cond.end3451:
|
|
// SIMD-ONLY0-NEXT: [[COND3452:%.*]] = phi i64 [ [[TMP1714]], [[COND_TRUE3449]] ], [ [[TMP1715]], [[COND_FALSE3450]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3452]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1716:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1717:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3453:%.*]] = icmp eq i64 [[TMP1716]], [[TMP1717]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3453]], label [[IF_THEN3455:%.*]], label [[IF_END3456:%.*]]
|
|
// SIMD-ONLY0: if.then3455:
|
|
// SIMD-ONLY0-NEXT: [[TMP1718:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1718]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3456]]
|
|
// SIMD-ONLY0: if.end3456:
|
|
// SIMD-ONLY0-NEXT: [[TMP1719:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1720:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3457:%.*]] = icmp eq i64 [[TMP1719]], [[TMP1720]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3457]], label [[IF_THEN3459:%.*]], label [[IF_END3460:%.*]]
|
|
// SIMD-ONLY0: if.then3459:
|
|
// SIMD-ONLY0-NEXT: [[TMP1721:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1721]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3460]]
|
|
// SIMD-ONLY0: if.end3460:
|
|
// SIMD-ONLY0-NEXT: [[TMP1722:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1723:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3461:%.*]] = icmp ugt i64 [[TMP1722]], [[TMP1723]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3461]], label [[COND_TRUE3463:%.*]], label [[COND_FALSE3464:%.*]]
|
|
// SIMD-ONLY0: cond.true3463:
|
|
// SIMD-ONLY0-NEXT: [[TMP1724:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3465:%.*]]
|
|
// SIMD-ONLY0: cond.false3464:
|
|
// SIMD-ONLY0-NEXT: [[TMP1725:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3465]]
|
|
// SIMD-ONLY0: cond.end3465:
|
|
// SIMD-ONLY0-NEXT: [[COND3466:%.*]] = phi i64 [ [[TMP1724]], [[COND_TRUE3463]] ], [ [[TMP1725]], [[COND_FALSE3464]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3466]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1726:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1727:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3467:%.*]] = icmp ult i64 [[TMP1726]], [[TMP1727]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3467]], label [[COND_TRUE3469:%.*]], label [[COND_FALSE3470:%.*]]
|
|
// SIMD-ONLY0: cond.true3469:
|
|
// SIMD-ONLY0-NEXT: [[TMP1728:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3471:%.*]]
|
|
// SIMD-ONLY0: cond.false3470:
|
|
// SIMD-ONLY0-NEXT: [[TMP1729:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3471]]
|
|
// SIMD-ONLY0: cond.end3471:
|
|
// SIMD-ONLY0-NEXT: [[COND3472:%.*]] = phi i64 [ [[TMP1728]], [[COND_TRUE3469]] ], [ [[TMP1729]], [[COND_FALSE3470]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3472]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1730:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1731:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3473:%.*]] = icmp ugt i64 [[TMP1730]], [[TMP1731]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3473]], label [[COND_TRUE3475:%.*]], label [[COND_FALSE3476:%.*]]
|
|
// SIMD-ONLY0: cond.true3475:
|
|
// SIMD-ONLY0-NEXT: [[TMP1732:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3477:%.*]]
|
|
// SIMD-ONLY0: cond.false3476:
|
|
// SIMD-ONLY0-NEXT: [[TMP1733:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3477]]
|
|
// SIMD-ONLY0: cond.end3477:
|
|
// SIMD-ONLY0-NEXT: [[COND3478:%.*]] = phi i64 [ [[TMP1732]], [[COND_TRUE3475]] ], [ [[TMP1733]], [[COND_FALSE3476]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3478]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1734:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1735:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3479:%.*]] = icmp ult i64 [[TMP1734]], [[TMP1735]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3479]], label [[COND_TRUE3481:%.*]], label [[COND_FALSE3482:%.*]]
|
|
// SIMD-ONLY0: cond.true3481:
|
|
// SIMD-ONLY0-NEXT: [[TMP1736:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3483:%.*]]
|
|
// SIMD-ONLY0: cond.false3482:
|
|
// SIMD-ONLY0-NEXT: [[TMP1737:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3483]]
|
|
// SIMD-ONLY0: cond.end3483:
|
|
// SIMD-ONLY0-NEXT: [[COND3484:%.*]] = phi i64 [ [[TMP1736]], [[COND_TRUE3481]] ], [ [[TMP1737]], [[COND_FALSE3482]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3484]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1738:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1739:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3485:%.*]] = icmp ugt i64 [[TMP1738]], [[TMP1739]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3485]], label [[IF_THEN3487:%.*]], label [[IF_END3488:%.*]]
|
|
// SIMD-ONLY0: if.then3487:
|
|
// SIMD-ONLY0-NEXT: [[TMP1740:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1740]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3488]]
|
|
// SIMD-ONLY0: if.end3488:
|
|
// SIMD-ONLY0-NEXT: [[TMP1741:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1742:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3489:%.*]] = icmp ult i64 [[TMP1741]], [[TMP1742]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3489]], label [[IF_THEN3491:%.*]], label [[IF_END3492:%.*]]
|
|
// SIMD-ONLY0: if.then3491:
|
|
// SIMD-ONLY0-NEXT: [[TMP1743:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1743]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3492]]
|
|
// SIMD-ONLY0: if.end3492:
|
|
// SIMD-ONLY0-NEXT: [[TMP1744:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1745:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3493:%.*]] = icmp ugt i64 [[TMP1744]], [[TMP1745]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3493]], label [[IF_THEN3495:%.*]], label [[IF_END3496:%.*]]
|
|
// SIMD-ONLY0: if.then3495:
|
|
// SIMD-ONLY0-NEXT: [[TMP1746:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1746]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3496]]
|
|
// SIMD-ONLY0: if.end3496:
|
|
// SIMD-ONLY0-NEXT: [[TMP1747:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1748:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3497:%.*]] = icmp ult i64 [[TMP1747]], [[TMP1748]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3497]], label [[IF_THEN3499:%.*]], label [[IF_END3500:%.*]]
|
|
// SIMD-ONLY0: if.then3499:
|
|
// SIMD-ONLY0-NEXT: [[TMP1749:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1749]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3500]]
|
|
// SIMD-ONLY0: if.end3500:
|
|
// SIMD-ONLY0-NEXT: [[TMP1750:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1751:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3501:%.*]] = icmp eq i64 [[TMP1750]], [[TMP1751]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3501]], label [[COND_TRUE3503:%.*]], label [[COND_FALSE3504:%.*]]
|
|
// SIMD-ONLY0: cond.true3503:
|
|
// SIMD-ONLY0-NEXT: [[TMP1752:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3505:%.*]]
|
|
// SIMD-ONLY0: cond.false3504:
|
|
// SIMD-ONLY0-NEXT: [[TMP1753:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3505]]
|
|
// SIMD-ONLY0: cond.end3505:
|
|
// SIMD-ONLY0-NEXT: [[COND3506:%.*]] = phi i64 [ [[TMP1752]], [[COND_TRUE3503]] ], [ [[TMP1753]], [[COND_FALSE3504]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3506]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1754:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1755:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3507:%.*]] = icmp eq i64 [[TMP1754]], [[TMP1755]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3507]], label [[COND_TRUE3509:%.*]], label [[COND_FALSE3510:%.*]]
|
|
// SIMD-ONLY0: cond.true3509:
|
|
// SIMD-ONLY0-NEXT: [[TMP1756:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3511:%.*]]
|
|
// SIMD-ONLY0: cond.false3510:
|
|
// SIMD-ONLY0-NEXT: [[TMP1757:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3511]]
|
|
// SIMD-ONLY0: cond.end3511:
|
|
// SIMD-ONLY0-NEXT: [[COND3512:%.*]] = phi i64 [ [[TMP1756]], [[COND_TRUE3509]] ], [ [[TMP1757]], [[COND_FALSE3510]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3512]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1758:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1759:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3513:%.*]] = icmp eq i64 [[TMP1758]], [[TMP1759]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3513]], label [[IF_THEN3515:%.*]], label [[IF_END3516:%.*]]
|
|
// SIMD-ONLY0: if.then3515:
|
|
// SIMD-ONLY0-NEXT: [[TMP1760:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1760]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3516]]
|
|
// SIMD-ONLY0: if.end3516:
|
|
// SIMD-ONLY0-NEXT: [[TMP1761:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1762:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3517:%.*]] = icmp eq i64 [[TMP1761]], [[TMP1762]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3517]], label [[IF_THEN3519:%.*]], label [[IF_END3520:%.*]]
|
|
// SIMD-ONLY0: if.then3519:
|
|
// SIMD-ONLY0-NEXT: [[TMP1763:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1763]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3520]]
|
|
// SIMD-ONLY0: if.end3520:
|
|
// SIMD-ONLY0-NEXT: [[TMP1764:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1765:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3521:%.*]] = icmp sgt i64 [[TMP1764]], [[TMP1765]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3521]], label [[COND_TRUE3523:%.*]], label [[COND_FALSE3524:%.*]]
|
|
// SIMD-ONLY0: cond.true3523:
|
|
// SIMD-ONLY0-NEXT: [[TMP1766:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3525:%.*]]
|
|
// SIMD-ONLY0: cond.false3524:
|
|
// SIMD-ONLY0-NEXT: [[TMP1767:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3525]]
|
|
// SIMD-ONLY0: cond.end3525:
|
|
// SIMD-ONLY0-NEXT: [[COND3526:%.*]] = phi i64 [ [[TMP1766]], [[COND_TRUE3523]] ], [ [[TMP1767]], [[COND_FALSE3524]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3526]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1768:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1769:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3527:%.*]] = icmp slt i64 [[TMP1768]], [[TMP1769]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3527]], label [[COND_TRUE3529:%.*]], label [[COND_FALSE3530:%.*]]
|
|
// SIMD-ONLY0: cond.true3529:
|
|
// SIMD-ONLY0-NEXT: [[TMP1770:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3531:%.*]]
|
|
// SIMD-ONLY0: cond.false3530:
|
|
// SIMD-ONLY0-NEXT: [[TMP1771:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3531]]
|
|
// SIMD-ONLY0: cond.end3531:
|
|
// SIMD-ONLY0-NEXT: [[COND3532:%.*]] = phi i64 [ [[TMP1770]], [[COND_TRUE3529]] ], [ [[TMP1771]], [[COND_FALSE3530]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3532]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1772:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1773:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3533:%.*]] = icmp sgt i64 [[TMP1772]], [[TMP1773]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3533]], label [[COND_TRUE3535:%.*]], label [[COND_FALSE3536:%.*]]
|
|
// SIMD-ONLY0: cond.true3535:
|
|
// SIMD-ONLY0-NEXT: [[TMP1774:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3537:%.*]]
|
|
// SIMD-ONLY0: cond.false3536:
|
|
// SIMD-ONLY0-NEXT: [[TMP1775:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3537]]
|
|
// SIMD-ONLY0: cond.end3537:
|
|
// SIMD-ONLY0-NEXT: [[COND3538:%.*]] = phi i64 [ [[TMP1774]], [[COND_TRUE3535]] ], [ [[TMP1775]], [[COND_FALSE3536]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3538]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1776:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1777:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3539:%.*]] = icmp slt i64 [[TMP1776]], [[TMP1777]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3539]], label [[COND_TRUE3541:%.*]], label [[COND_FALSE3542:%.*]]
|
|
// SIMD-ONLY0: cond.true3541:
|
|
// SIMD-ONLY0-NEXT: [[TMP1778:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3543:%.*]]
|
|
// SIMD-ONLY0: cond.false3542:
|
|
// SIMD-ONLY0-NEXT: [[TMP1779:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3543]]
|
|
// SIMD-ONLY0: cond.end3543:
|
|
// SIMD-ONLY0-NEXT: [[COND3544:%.*]] = phi i64 [ [[TMP1778]], [[COND_TRUE3541]] ], [ [[TMP1779]], [[COND_FALSE3542]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3544]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1780:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1781:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3545:%.*]] = icmp sgt i64 [[TMP1780]], [[TMP1781]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3545]], label [[IF_THEN3547:%.*]], label [[IF_END3548:%.*]]
|
|
// SIMD-ONLY0: if.then3547:
|
|
// SIMD-ONLY0-NEXT: [[TMP1782:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1782]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3548]]
|
|
// SIMD-ONLY0: if.end3548:
|
|
// SIMD-ONLY0-NEXT: [[TMP1783:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1784:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3549:%.*]] = icmp slt i64 [[TMP1783]], [[TMP1784]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3549]], label [[IF_THEN3551:%.*]], label [[IF_END3552:%.*]]
|
|
// SIMD-ONLY0: if.then3551:
|
|
// SIMD-ONLY0-NEXT: [[TMP1785:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1785]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3552]]
|
|
// SIMD-ONLY0: if.end3552:
|
|
// SIMD-ONLY0-NEXT: [[TMP1786:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1787:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3553:%.*]] = icmp sgt i64 [[TMP1786]], [[TMP1787]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3553]], label [[IF_THEN3555:%.*]], label [[IF_END3556:%.*]]
|
|
// SIMD-ONLY0: if.then3555:
|
|
// SIMD-ONLY0-NEXT: [[TMP1788:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1788]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3556]]
|
|
// SIMD-ONLY0: if.end3556:
|
|
// SIMD-ONLY0-NEXT: [[TMP1789:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1790:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3557:%.*]] = icmp slt i64 [[TMP1789]], [[TMP1790]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3557]], label [[IF_THEN3559:%.*]], label [[IF_END3560:%.*]]
|
|
// SIMD-ONLY0: if.then3559:
|
|
// SIMD-ONLY0-NEXT: [[TMP1791:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1791]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3560]]
|
|
// SIMD-ONLY0: if.end3560:
|
|
// SIMD-ONLY0-NEXT: [[TMP1792:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1793:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3561:%.*]] = icmp eq i64 [[TMP1792]], [[TMP1793]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3561]], label [[COND_TRUE3563:%.*]], label [[COND_FALSE3564:%.*]]
|
|
// SIMD-ONLY0: cond.true3563:
|
|
// SIMD-ONLY0-NEXT: [[TMP1794:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3565:%.*]]
|
|
// SIMD-ONLY0: cond.false3564:
|
|
// SIMD-ONLY0-NEXT: [[TMP1795:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3565]]
|
|
// SIMD-ONLY0: cond.end3565:
|
|
// SIMD-ONLY0-NEXT: [[COND3566:%.*]] = phi i64 [ [[TMP1794]], [[COND_TRUE3563]] ], [ [[TMP1795]], [[COND_FALSE3564]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3566]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1796:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1797:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3567:%.*]] = icmp eq i64 [[TMP1796]], [[TMP1797]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3567]], label [[COND_TRUE3569:%.*]], label [[COND_FALSE3570:%.*]]
|
|
// SIMD-ONLY0: cond.true3569:
|
|
// SIMD-ONLY0-NEXT: [[TMP1798:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3571:%.*]]
|
|
// SIMD-ONLY0: cond.false3570:
|
|
// SIMD-ONLY0-NEXT: [[TMP1799:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3571]]
|
|
// SIMD-ONLY0: cond.end3571:
|
|
// SIMD-ONLY0-NEXT: [[COND3572:%.*]] = phi i64 [ [[TMP1798]], [[COND_TRUE3569]] ], [ [[TMP1799]], [[COND_FALSE3570]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3572]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1800:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1801:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3573:%.*]] = icmp eq i64 [[TMP1800]], [[TMP1801]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3573]], label [[IF_THEN3575:%.*]], label [[IF_END3576:%.*]]
|
|
// SIMD-ONLY0: if.then3575:
|
|
// SIMD-ONLY0-NEXT: [[TMP1802:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1802]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3576]]
|
|
// SIMD-ONLY0: if.end3576:
|
|
// SIMD-ONLY0-NEXT: [[TMP1803:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1804:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3577:%.*]] = icmp eq i64 [[TMP1803]], [[TMP1804]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3577]], label [[IF_THEN3579:%.*]], label [[IF_END3580:%.*]]
|
|
// SIMD-ONLY0: if.then3579:
|
|
// SIMD-ONLY0-NEXT: [[TMP1805:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1805]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3580]]
|
|
// SIMD-ONLY0: if.end3580:
|
|
// SIMD-ONLY0-NEXT: [[TMP1806:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1807:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3581:%.*]] = icmp ugt i64 [[TMP1806]], [[TMP1807]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3581]], label [[COND_TRUE3583:%.*]], label [[COND_FALSE3584:%.*]]
|
|
// SIMD-ONLY0: cond.true3583:
|
|
// SIMD-ONLY0-NEXT: [[TMP1808:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3585:%.*]]
|
|
// SIMD-ONLY0: cond.false3584:
|
|
// SIMD-ONLY0-NEXT: [[TMP1809:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3585]]
|
|
// SIMD-ONLY0: cond.end3585:
|
|
// SIMD-ONLY0-NEXT: [[COND3586:%.*]] = phi i64 [ [[TMP1808]], [[COND_TRUE3583]] ], [ [[TMP1809]], [[COND_FALSE3584]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3586]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1810:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1811:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3587:%.*]] = icmp ult i64 [[TMP1810]], [[TMP1811]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3587]], label [[COND_TRUE3589:%.*]], label [[COND_FALSE3590:%.*]]
|
|
// SIMD-ONLY0: cond.true3589:
|
|
// SIMD-ONLY0-NEXT: [[TMP1812:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3591:%.*]]
|
|
// SIMD-ONLY0: cond.false3590:
|
|
// SIMD-ONLY0-NEXT: [[TMP1813:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3591]]
|
|
// SIMD-ONLY0: cond.end3591:
|
|
// SIMD-ONLY0-NEXT: [[COND3592:%.*]] = phi i64 [ [[TMP1812]], [[COND_TRUE3589]] ], [ [[TMP1813]], [[COND_FALSE3590]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3592]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1814:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1815:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3593:%.*]] = icmp ugt i64 [[TMP1814]], [[TMP1815]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3593]], label [[COND_TRUE3595:%.*]], label [[COND_FALSE3596:%.*]]
|
|
// SIMD-ONLY0: cond.true3595:
|
|
// SIMD-ONLY0-NEXT: [[TMP1816:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3597:%.*]]
|
|
// SIMD-ONLY0: cond.false3596:
|
|
// SIMD-ONLY0-NEXT: [[TMP1817:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3597]]
|
|
// SIMD-ONLY0: cond.end3597:
|
|
// SIMD-ONLY0-NEXT: [[COND3598:%.*]] = phi i64 [ [[TMP1816]], [[COND_TRUE3595]] ], [ [[TMP1817]], [[COND_FALSE3596]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3598]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1818:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1819:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3599:%.*]] = icmp ult i64 [[TMP1818]], [[TMP1819]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3599]], label [[COND_TRUE3601:%.*]], label [[COND_FALSE3602:%.*]]
|
|
// SIMD-ONLY0: cond.true3601:
|
|
// SIMD-ONLY0-NEXT: [[TMP1820:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3603:%.*]]
|
|
// SIMD-ONLY0: cond.false3602:
|
|
// SIMD-ONLY0-NEXT: [[TMP1821:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3603]]
|
|
// SIMD-ONLY0: cond.end3603:
|
|
// SIMD-ONLY0-NEXT: [[COND3604:%.*]] = phi i64 [ [[TMP1820]], [[COND_TRUE3601]] ], [ [[TMP1821]], [[COND_FALSE3602]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3604]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1822:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1823:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3605:%.*]] = icmp ugt i64 [[TMP1822]], [[TMP1823]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3605]], label [[IF_THEN3607:%.*]], label [[IF_END3608:%.*]]
|
|
// SIMD-ONLY0: if.then3607:
|
|
// SIMD-ONLY0-NEXT: [[TMP1824:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1824]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3608]]
|
|
// SIMD-ONLY0: if.end3608:
|
|
// SIMD-ONLY0-NEXT: [[TMP1825:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1826:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3609:%.*]] = icmp ult i64 [[TMP1825]], [[TMP1826]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3609]], label [[IF_THEN3611:%.*]], label [[IF_END3612:%.*]]
|
|
// SIMD-ONLY0: if.then3611:
|
|
// SIMD-ONLY0-NEXT: [[TMP1827:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1827]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3612]]
|
|
// SIMD-ONLY0: if.end3612:
|
|
// SIMD-ONLY0-NEXT: [[TMP1828:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1829:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3613:%.*]] = icmp ugt i64 [[TMP1828]], [[TMP1829]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3613]], label [[IF_THEN3615:%.*]], label [[IF_END3616:%.*]]
|
|
// SIMD-ONLY0: if.then3615:
|
|
// SIMD-ONLY0-NEXT: [[TMP1830:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1830]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3616]]
|
|
// SIMD-ONLY0: if.end3616:
|
|
// SIMD-ONLY0-NEXT: [[TMP1831:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1832:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3617:%.*]] = icmp ult i64 [[TMP1831]], [[TMP1832]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3617]], label [[IF_THEN3619:%.*]], label [[IF_END3620:%.*]]
|
|
// SIMD-ONLY0: if.then3619:
|
|
// SIMD-ONLY0-NEXT: [[TMP1833:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1833]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3620]]
|
|
// SIMD-ONLY0: if.end3620:
|
|
// SIMD-ONLY0-NEXT: [[TMP1834:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1835:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3621:%.*]] = icmp eq i64 [[TMP1834]], [[TMP1835]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3621]], label [[COND_TRUE3623:%.*]], label [[COND_FALSE3624:%.*]]
|
|
// SIMD-ONLY0: cond.true3623:
|
|
// SIMD-ONLY0-NEXT: [[TMP1836:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3625:%.*]]
|
|
// SIMD-ONLY0: cond.false3624:
|
|
// SIMD-ONLY0-NEXT: [[TMP1837:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3625]]
|
|
// SIMD-ONLY0: cond.end3625:
|
|
// SIMD-ONLY0-NEXT: [[COND3626:%.*]] = phi i64 [ [[TMP1836]], [[COND_TRUE3623]] ], [ [[TMP1837]], [[COND_FALSE3624]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3626]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1838:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1839:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3627:%.*]] = icmp eq i64 [[TMP1838]], [[TMP1839]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3627]], label [[COND_TRUE3629:%.*]], label [[COND_FALSE3630:%.*]]
|
|
// SIMD-ONLY0: cond.true3629:
|
|
// SIMD-ONLY0-NEXT: [[TMP1840:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3631:%.*]]
|
|
// SIMD-ONLY0: cond.false3630:
|
|
// SIMD-ONLY0-NEXT: [[TMP1841:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3631]]
|
|
// SIMD-ONLY0: cond.end3631:
|
|
// SIMD-ONLY0-NEXT: [[COND3632:%.*]] = phi i64 [ [[TMP1840]], [[COND_TRUE3629]] ], [ [[TMP1841]], [[COND_FALSE3630]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3632]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1842:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1843:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3633:%.*]] = icmp eq i64 [[TMP1842]], [[TMP1843]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3633]], label [[IF_THEN3635:%.*]], label [[IF_END3636:%.*]]
|
|
// SIMD-ONLY0: if.then3635:
|
|
// SIMD-ONLY0-NEXT: [[TMP1844:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1844]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3636]]
|
|
// SIMD-ONLY0: if.end3636:
|
|
// SIMD-ONLY0-NEXT: [[TMP1845:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1846:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3637:%.*]] = icmp eq i64 [[TMP1845]], [[TMP1846]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3637]], label [[IF_THEN3639:%.*]], label [[IF_END3640:%.*]]
|
|
// SIMD-ONLY0: if.then3639:
|
|
// SIMD-ONLY0-NEXT: [[TMP1847:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1847]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3640]]
|
|
// SIMD-ONLY0: if.end3640:
|
|
// SIMD-ONLY0-NEXT: [[TMP1848:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1849:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3641:%.*]] = icmp sgt i64 [[TMP1848]], [[TMP1849]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3641]], label [[COND_TRUE3643:%.*]], label [[COND_FALSE3644:%.*]]
|
|
// SIMD-ONLY0: cond.true3643:
|
|
// SIMD-ONLY0-NEXT: [[TMP1850:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3645:%.*]]
|
|
// SIMD-ONLY0: cond.false3644:
|
|
// SIMD-ONLY0-NEXT: [[TMP1851:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3645]]
|
|
// SIMD-ONLY0: cond.end3645:
|
|
// SIMD-ONLY0-NEXT: [[COND3646:%.*]] = phi i64 [ [[TMP1850]], [[COND_TRUE3643]] ], [ [[TMP1851]], [[COND_FALSE3644]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3646]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1852:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1853:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3647:%.*]] = icmp slt i64 [[TMP1852]], [[TMP1853]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3647]], label [[COND_TRUE3649:%.*]], label [[COND_FALSE3650:%.*]]
|
|
// SIMD-ONLY0: cond.true3649:
|
|
// SIMD-ONLY0-NEXT: [[TMP1854:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3651:%.*]]
|
|
// SIMD-ONLY0: cond.false3650:
|
|
// SIMD-ONLY0-NEXT: [[TMP1855:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3651]]
|
|
// SIMD-ONLY0: cond.end3651:
|
|
// SIMD-ONLY0-NEXT: [[COND3652:%.*]] = phi i64 [ [[TMP1854]], [[COND_TRUE3649]] ], [ [[TMP1855]], [[COND_FALSE3650]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3652]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1856:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1857:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3653:%.*]] = icmp sgt i64 [[TMP1856]], [[TMP1857]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3653]], label [[COND_TRUE3655:%.*]], label [[COND_FALSE3656:%.*]]
|
|
// SIMD-ONLY0: cond.true3655:
|
|
// SIMD-ONLY0-NEXT: [[TMP1858:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3657:%.*]]
|
|
// SIMD-ONLY0: cond.false3656:
|
|
// SIMD-ONLY0-NEXT: [[TMP1859:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3657]]
|
|
// SIMD-ONLY0: cond.end3657:
|
|
// SIMD-ONLY0-NEXT: [[COND3658:%.*]] = phi i64 [ [[TMP1858]], [[COND_TRUE3655]] ], [ [[TMP1859]], [[COND_FALSE3656]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3658]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1860:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1861:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3659:%.*]] = icmp slt i64 [[TMP1860]], [[TMP1861]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3659]], label [[COND_TRUE3661:%.*]], label [[COND_FALSE3662:%.*]]
|
|
// SIMD-ONLY0: cond.true3661:
|
|
// SIMD-ONLY0-NEXT: [[TMP1862:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3663:%.*]]
|
|
// SIMD-ONLY0: cond.false3662:
|
|
// SIMD-ONLY0-NEXT: [[TMP1863:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3663]]
|
|
// SIMD-ONLY0: cond.end3663:
|
|
// SIMD-ONLY0-NEXT: [[COND3664:%.*]] = phi i64 [ [[TMP1862]], [[COND_TRUE3661]] ], [ [[TMP1863]], [[COND_FALSE3662]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3664]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1864:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1865:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3665:%.*]] = icmp sgt i64 [[TMP1864]], [[TMP1865]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3665]], label [[IF_THEN3667:%.*]], label [[IF_END3668:%.*]]
|
|
// SIMD-ONLY0: if.then3667:
|
|
// SIMD-ONLY0-NEXT: [[TMP1866:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1866]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3668]]
|
|
// SIMD-ONLY0: if.end3668:
|
|
// SIMD-ONLY0-NEXT: [[TMP1867:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1868:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3669:%.*]] = icmp slt i64 [[TMP1867]], [[TMP1868]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3669]], label [[IF_THEN3671:%.*]], label [[IF_END3672:%.*]]
|
|
// SIMD-ONLY0: if.then3671:
|
|
// SIMD-ONLY0-NEXT: [[TMP1869:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1869]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3672]]
|
|
// SIMD-ONLY0: if.end3672:
|
|
// SIMD-ONLY0-NEXT: [[TMP1870:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1871:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3673:%.*]] = icmp sgt i64 [[TMP1870]], [[TMP1871]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3673]], label [[IF_THEN3675:%.*]], label [[IF_END3676:%.*]]
|
|
// SIMD-ONLY0: if.then3675:
|
|
// SIMD-ONLY0-NEXT: [[TMP1872:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1872]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3676]]
|
|
// SIMD-ONLY0: if.end3676:
|
|
// SIMD-ONLY0-NEXT: [[TMP1873:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1874:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3677:%.*]] = icmp slt i64 [[TMP1873]], [[TMP1874]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3677]], label [[IF_THEN3679:%.*]], label [[IF_END3680:%.*]]
|
|
// SIMD-ONLY0: if.then3679:
|
|
// SIMD-ONLY0-NEXT: [[TMP1875:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1875]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3680]]
|
|
// SIMD-ONLY0: if.end3680:
|
|
// SIMD-ONLY0-NEXT: [[TMP1876:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1877:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3681:%.*]] = icmp eq i64 [[TMP1876]], [[TMP1877]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3681]], label [[COND_TRUE3683:%.*]], label [[COND_FALSE3684:%.*]]
|
|
// SIMD-ONLY0: cond.true3683:
|
|
// SIMD-ONLY0-NEXT: [[TMP1878:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3685:%.*]]
|
|
// SIMD-ONLY0: cond.false3684:
|
|
// SIMD-ONLY0-NEXT: [[TMP1879:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3685]]
|
|
// SIMD-ONLY0: cond.end3685:
|
|
// SIMD-ONLY0-NEXT: [[COND3686:%.*]] = phi i64 [ [[TMP1878]], [[COND_TRUE3683]] ], [ [[TMP1879]], [[COND_FALSE3684]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3686]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1880:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1881:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3687:%.*]] = icmp eq i64 [[TMP1880]], [[TMP1881]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3687]], label [[COND_TRUE3689:%.*]], label [[COND_FALSE3690:%.*]]
|
|
// SIMD-ONLY0: cond.true3689:
|
|
// SIMD-ONLY0-NEXT: [[TMP1882:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3691:%.*]]
|
|
// SIMD-ONLY0: cond.false3690:
|
|
// SIMD-ONLY0-NEXT: [[TMP1883:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3691]]
|
|
// SIMD-ONLY0: cond.end3691:
|
|
// SIMD-ONLY0-NEXT: [[COND3692:%.*]] = phi i64 [ [[TMP1882]], [[COND_TRUE3689]] ], [ [[TMP1883]], [[COND_FALSE3690]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3692]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1884:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1885:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3693:%.*]] = icmp eq i64 [[TMP1884]], [[TMP1885]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3693]], label [[IF_THEN3695:%.*]], label [[IF_END3696:%.*]]
|
|
// SIMD-ONLY0: if.then3695:
|
|
// SIMD-ONLY0-NEXT: [[TMP1886:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1886]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3696]]
|
|
// SIMD-ONLY0: if.end3696:
|
|
// SIMD-ONLY0-NEXT: [[TMP1887:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1888:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3697:%.*]] = icmp eq i64 [[TMP1887]], [[TMP1888]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3697]], label [[IF_THEN3699:%.*]], label [[IF_END3700:%.*]]
|
|
// SIMD-ONLY0: if.then3699:
|
|
// SIMD-ONLY0-NEXT: [[TMP1889:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1889]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3700]]
|
|
// SIMD-ONLY0: if.end3700:
|
|
// SIMD-ONLY0-NEXT: [[TMP1890:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1891:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3701:%.*]] = icmp ugt i64 [[TMP1890]], [[TMP1891]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3701]], label [[COND_TRUE3703:%.*]], label [[COND_FALSE3704:%.*]]
|
|
// SIMD-ONLY0: cond.true3703:
|
|
// SIMD-ONLY0-NEXT: [[TMP1892:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3705:%.*]]
|
|
// SIMD-ONLY0: cond.false3704:
|
|
// SIMD-ONLY0-NEXT: [[TMP1893:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3705]]
|
|
// SIMD-ONLY0: cond.end3705:
|
|
// SIMD-ONLY0-NEXT: [[COND3706:%.*]] = phi i64 [ [[TMP1892]], [[COND_TRUE3703]] ], [ [[TMP1893]], [[COND_FALSE3704]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3706]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1894:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1895:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3707:%.*]] = icmp ult i64 [[TMP1894]], [[TMP1895]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3707]], label [[COND_TRUE3709:%.*]], label [[COND_FALSE3710:%.*]]
|
|
// SIMD-ONLY0: cond.true3709:
|
|
// SIMD-ONLY0-NEXT: [[TMP1896:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3711:%.*]]
|
|
// SIMD-ONLY0: cond.false3710:
|
|
// SIMD-ONLY0-NEXT: [[TMP1897:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3711]]
|
|
// SIMD-ONLY0: cond.end3711:
|
|
// SIMD-ONLY0-NEXT: [[COND3712:%.*]] = phi i64 [ [[TMP1896]], [[COND_TRUE3709]] ], [ [[TMP1897]], [[COND_FALSE3710]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3712]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1898:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1899:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3713:%.*]] = icmp ugt i64 [[TMP1898]], [[TMP1899]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3713]], label [[COND_TRUE3715:%.*]], label [[COND_FALSE3716:%.*]]
|
|
// SIMD-ONLY0: cond.true3715:
|
|
// SIMD-ONLY0-NEXT: [[TMP1900:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3717:%.*]]
|
|
// SIMD-ONLY0: cond.false3716:
|
|
// SIMD-ONLY0-NEXT: [[TMP1901:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3717]]
|
|
// SIMD-ONLY0: cond.end3717:
|
|
// SIMD-ONLY0-NEXT: [[COND3718:%.*]] = phi i64 [ [[TMP1900]], [[COND_TRUE3715]] ], [ [[TMP1901]], [[COND_FALSE3716]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3718]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1902:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1903:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3719:%.*]] = icmp ult i64 [[TMP1902]], [[TMP1903]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3719]], label [[COND_TRUE3721:%.*]], label [[COND_FALSE3722:%.*]]
|
|
// SIMD-ONLY0: cond.true3721:
|
|
// SIMD-ONLY0-NEXT: [[TMP1904:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3723:%.*]]
|
|
// SIMD-ONLY0: cond.false3722:
|
|
// SIMD-ONLY0-NEXT: [[TMP1905:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3723]]
|
|
// SIMD-ONLY0: cond.end3723:
|
|
// SIMD-ONLY0-NEXT: [[COND3724:%.*]] = phi i64 [ [[TMP1904]], [[COND_TRUE3721]] ], [ [[TMP1905]], [[COND_FALSE3722]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3724]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1906:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1907:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3725:%.*]] = icmp ugt i64 [[TMP1906]], [[TMP1907]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3725]], label [[IF_THEN3727:%.*]], label [[IF_END3728:%.*]]
|
|
// SIMD-ONLY0: if.then3727:
|
|
// SIMD-ONLY0-NEXT: [[TMP1908:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1908]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3728]]
|
|
// SIMD-ONLY0: if.end3728:
|
|
// SIMD-ONLY0-NEXT: [[TMP1909:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1910:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3729:%.*]] = icmp ult i64 [[TMP1909]], [[TMP1910]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3729]], label [[IF_THEN3731:%.*]], label [[IF_END3732:%.*]]
|
|
// SIMD-ONLY0: if.then3731:
|
|
// SIMD-ONLY0-NEXT: [[TMP1911:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1911]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3732]]
|
|
// SIMD-ONLY0: if.end3732:
|
|
// SIMD-ONLY0-NEXT: [[TMP1912:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1913:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3733:%.*]] = icmp ugt i64 [[TMP1912]], [[TMP1913]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3733]], label [[IF_THEN3735:%.*]], label [[IF_END3736:%.*]]
|
|
// SIMD-ONLY0: if.then3735:
|
|
// SIMD-ONLY0-NEXT: [[TMP1914:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1914]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3736]]
|
|
// SIMD-ONLY0: if.end3736:
|
|
// SIMD-ONLY0-NEXT: [[TMP1915:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1916:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3737:%.*]] = icmp ult i64 [[TMP1915]], [[TMP1916]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3737]], label [[IF_THEN3739:%.*]], label [[IF_END3740:%.*]]
|
|
// SIMD-ONLY0: if.then3739:
|
|
// SIMD-ONLY0-NEXT: [[TMP1917:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1917]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3740]]
|
|
// SIMD-ONLY0: if.end3740:
|
|
// SIMD-ONLY0-NEXT: [[TMP1918:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1919:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3741:%.*]] = icmp eq i64 [[TMP1918]], [[TMP1919]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3741]], label [[COND_TRUE3743:%.*]], label [[COND_FALSE3744:%.*]]
|
|
// SIMD-ONLY0: cond.true3743:
|
|
// SIMD-ONLY0-NEXT: [[TMP1920:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3745:%.*]]
|
|
// SIMD-ONLY0: cond.false3744:
|
|
// SIMD-ONLY0-NEXT: [[TMP1921:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3745]]
|
|
// SIMD-ONLY0: cond.end3745:
|
|
// SIMD-ONLY0-NEXT: [[COND3746:%.*]] = phi i64 [ [[TMP1920]], [[COND_TRUE3743]] ], [ [[TMP1921]], [[COND_FALSE3744]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3746]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1922:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1923:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3747:%.*]] = icmp eq i64 [[TMP1922]], [[TMP1923]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3747]], label [[COND_TRUE3749:%.*]], label [[COND_FALSE3750:%.*]]
|
|
// SIMD-ONLY0: cond.true3749:
|
|
// SIMD-ONLY0-NEXT: [[TMP1924:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3751:%.*]]
|
|
// SIMD-ONLY0: cond.false3750:
|
|
// SIMD-ONLY0-NEXT: [[TMP1925:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3751]]
|
|
// SIMD-ONLY0: cond.end3751:
|
|
// SIMD-ONLY0-NEXT: [[COND3752:%.*]] = phi i64 [ [[TMP1924]], [[COND_TRUE3749]] ], [ [[TMP1925]], [[COND_FALSE3750]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3752]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1926:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1927:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3753:%.*]] = icmp eq i64 [[TMP1926]], [[TMP1927]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3753]], label [[IF_THEN3755:%.*]], label [[IF_END3756:%.*]]
|
|
// SIMD-ONLY0: if.then3755:
|
|
// SIMD-ONLY0-NEXT: [[TMP1928:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1928]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3756]]
|
|
// SIMD-ONLY0: if.end3756:
|
|
// SIMD-ONLY0-NEXT: [[TMP1929:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1930:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3757:%.*]] = icmp eq i64 [[TMP1929]], [[TMP1930]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3757]], label [[IF_THEN3759:%.*]], label [[IF_END3760:%.*]]
|
|
// SIMD-ONLY0: if.then3759:
|
|
// SIMD-ONLY0-NEXT: [[TMP1931:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1931]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3760]]
|
|
// SIMD-ONLY0: if.end3760:
|
|
// SIMD-ONLY0-NEXT: [[TMP1932:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1933:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3761:%.*]] = icmp sgt i64 [[TMP1932]], [[TMP1933]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3761]], label [[COND_TRUE3763:%.*]], label [[COND_FALSE3764:%.*]]
|
|
// SIMD-ONLY0: cond.true3763:
|
|
// SIMD-ONLY0-NEXT: [[TMP1934:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3765:%.*]]
|
|
// SIMD-ONLY0: cond.false3764:
|
|
// SIMD-ONLY0-NEXT: [[TMP1935:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3765]]
|
|
// SIMD-ONLY0: cond.end3765:
|
|
// SIMD-ONLY0-NEXT: [[COND3766:%.*]] = phi i64 [ [[TMP1934]], [[COND_TRUE3763]] ], [ [[TMP1935]], [[COND_FALSE3764]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3766]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1936:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1937:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3767:%.*]] = icmp slt i64 [[TMP1936]], [[TMP1937]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3767]], label [[COND_TRUE3769:%.*]], label [[COND_FALSE3770:%.*]]
|
|
// SIMD-ONLY0: cond.true3769:
|
|
// SIMD-ONLY0-NEXT: [[TMP1938:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3771:%.*]]
|
|
// SIMD-ONLY0: cond.false3770:
|
|
// SIMD-ONLY0-NEXT: [[TMP1939:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3771]]
|
|
// SIMD-ONLY0: cond.end3771:
|
|
// SIMD-ONLY0-NEXT: [[COND3772:%.*]] = phi i64 [ [[TMP1938]], [[COND_TRUE3769]] ], [ [[TMP1939]], [[COND_FALSE3770]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3772]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1940:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1941:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3773:%.*]] = icmp sgt i64 [[TMP1940]], [[TMP1941]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3773]], label [[COND_TRUE3775:%.*]], label [[COND_FALSE3776:%.*]]
|
|
// SIMD-ONLY0: cond.true3775:
|
|
// SIMD-ONLY0-NEXT: [[TMP1942:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3777:%.*]]
|
|
// SIMD-ONLY0: cond.false3776:
|
|
// SIMD-ONLY0-NEXT: [[TMP1943:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3777]]
|
|
// SIMD-ONLY0: cond.end3777:
|
|
// SIMD-ONLY0-NEXT: [[COND3778:%.*]] = phi i64 [ [[TMP1942]], [[COND_TRUE3775]] ], [ [[TMP1943]], [[COND_FALSE3776]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3778]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1944:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1945:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3779:%.*]] = icmp slt i64 [[TMP1944]], [[TMP1945]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3779]], label [[COND_TRUE3781:%.*]], label [[COND_FALSE3782:%.*]]
|
|
// SIMD-ONLY0: cond.true3781:
|
|
// SIMD-ONLY0-NEXT: [[TMP1946:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3783:%.*]]
|
|
// SIMD-ONLY0: cond.false3782:
|
|
// SIMD-ONLY0-NEXT: [[TMP1947:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3783]]
|
|
// SIMD-ONLY0: cond.end3783:
|
|
// SIMD-ONLY0-NEXT: [[COND3784:%.*]] = phi i64 [ [[TMP1946]], [[COND_TRUE3781]] ], [ [[TMP1947]], [[COND_FALSE3782]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3784]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1948:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1949:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3785:%.*]] = icmp sgt i64 [[TMP1948]], [[TMP1949]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3785]], label [[IF_THEN3787:%.*]], label [[IF_END3788:%.*]]
|
|
// SIMD-ONLY0: if.then3787:
|
|
// SIMD-ONLY0-NEXT: [[TMP1950:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1950]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3788]]
|
|
// SIMD-ONLY0: if.end3788:
|
|
// SIMD-ONLY0-NEXT: [[TMP1951:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1952:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3789:%.*]] = icmp slt i64 [[TMP1951]], [[TMP1952]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3789]], label [[IF_THEN3791:%.*]], label [[IF_END3792:%.*]]
|
|
// SIMD-ONLY0: if.then3791:
|
|
// SIMD-ONLY0-NEXT: [[TMP1953:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1953]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3792]]
|
|
// SIMD-ONLY0: if.end3792:
|
|
// SIMD-ONLY0-NEXT: [[TMP1954:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1955:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3793:%.*]] = icmp sgt i64 [[TMP1954]], [[TMP1955]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3793]], label [[IF_THEN3795:%.*]], label [[IF_END3796:%.*]]
|
|
// SIMD-ONLY0: if.then3795:
|
|
// SIMD-ONLY0-NEXT: [[TMP1956:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1956]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3796]]
|
|
// SIMD-ONLY0: if.end3796:
|
|
// SIMD-ONLY0-NEXT: [[TMP1957:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1958:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3797:%.*]] = icmp slt i64 [[TMP1957]], [[TMP1958]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3797]], label [[IF_THEN3799:%.*]], label [[IF_END3800:%.*]]
|
|
// SIMD-ONLY0: if.then3799:
|
|
// SIMD-ONLY0-NEXT: [[TMP1959:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1959]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3800]]
|
|
// SIMD-ONLY0: if.end3800:
|
|
// SIMD-ONLY0-NEXT: [[TMP1960:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1961:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3801:%.*]] = icmp eq i64 [[TMP1960]], [[TMP1961]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3801]], label [[COND_TRUE3803:%.*]], label [[COND_FALSE3804:%.*]]
|
|
// SIMD-ONLY0: cond.true3803:
|
|
// SIMD-ONLY0-NEXT: [[TMP1962:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3805:%.*]]
|
|
// SIMD-ONLY0: cond.false3804:
|
|
// SIMD-ONLY0-NEXT: [[TMP1963:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3805]]
|
|
// SIMD-ONLY0: cond.end3805:
|
|
// SIMD-ONLY0-NEXT: [[COND3806:%.*]] = phi i64 [ [[TMP1962]], [[COND_TRUE3803]] ], [ [[TMP1963]], [[COND_FALSE3804]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3806]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1964:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1965:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3807:%.*]] = icmp eq i64 [[TMP1964]], [[TMP1965]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3807]], label [[COND_TRUE3809:%.*]], label [[COND_FALSE3810:%.*]]
|
|
// SIMD-ONLY0: cond.true3809:
|
|
// SIMD-ONLY0-NEXT: [[TMP1966:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3811:%.*]]
|
|
// SIMD-ONLY0: cond.false3810:
|
|
// SIMD-ONLY0-NEXT: [[TMP1967:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3811]]
|
|
// SIMD-ONLY0: cond.end3811:
|
|
// SIMD-ONLY0-NEXT: [[COND3812:%.*]] = phi i64 [ [[TMP1966]], [[COND_TRUE3809]] ], [ [[TMP1967]], [[COND_FALSE3810]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3812]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1968:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1969:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3813:%.*]] = icmp eq i64 [[TMP1968]], [[TMP1969]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3813]], label [[IF_THEN3815:%.*]], label [[IF_END3816:%.*]]
|
|
// SIMD-ONLY0: if.then3815:
|
|
// SIMD-ONLY0-NEXT: [[TMP1970:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1970]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3816]]
|
|
// SIMD-ONLY0: if.end3816:
|
|
// SIMD-ONLY0-NEXT: [[TMP1971:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1972:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3817:%.*]] = icmp eq i64 [[TMP1971]], [[TMP1972]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3817]], label [[IF_THEN3819:%.*]], label [[IF_END3820:%.*]]
|
|
// SIMD-ONLY0: if.then3819:
|
|
// SIMD-ONLY0-NEXT: [[TMP1973:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1973]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3820]]
|
|
// SIMD-ONLY0: if.end3820:
|
|
// SIMD-ONLY0-NEXT: [[TMP1974:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1975:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3821:%.*]] = icmp ugt i64 [[TMP1974]], [[TMP1975]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3821]], label [[COND_TRUE3823:%.*]], label [[COND_FALSE3824:%.*]]
|
|
// SIMD-ONLY0: cond.true3823:
|
|
// SIMD-ONLY0-NEXT: [[TMP1976:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3825:%.*]]
|
|
// SIMD-ONLY0: cond.false3824:
|
|
// SIMD-ONLY0-NEXT: [[TMP1977:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3825]]
|
|
// SIMD-ONLY0: cond.end3825:
|
|
// SIMD-ONLY0-NEXT: [[COND3826:%.*]] = phi i64 [ [[TMP1976]], [[COND_TRUE3823]] ], [ [[TMP1977]], [[COND_FALSE3824]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3826]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1978:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1979:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3827:%.*]] = icmp ult i64 [[TMP1978]], [[TMP1979]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3827]], label [[COND_TRUE3829:%.*]], label [[COND_FALSE3830:%.*]]
|
|
// SIMD-ONLY0: cond.true3829:
|
|
// SIMD-ONLY0-NEXT: [[TMP1980:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3831:%.*]]
|
|
// SIMD-ONLY0: cond.false3830:
|
|
// SIMD-ONLY0-NEXT: [[TMP1981:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3831]]
|
|
// SIMD-ONLY0: cond.end3831:
|
|
// SIMD-ONLY0-NEXT: [[COND3832:%.*]] = phi i64 [ [[TMP1980]], [[COND_TRUE3829]] ], [ [[TMP1981]], [[COND_FALSE3830]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3832]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1982:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1983:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3833:%.*]] = icmp ugt i64 [[TMP1982]], [[TMP1983]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3833]], label [[COND_TRUE3835:%.*]], label [[COND_FALSE3836:%.*]]
|
|
// SIMD-ONLY0: cond.true3835:
|
|
// SIMD-ONLY0-NEXT: [[TMP1984:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3837:%.*]]
|
|
// SIMD-ONLY0: cond.false3836:
|
|
// SIMD-ONLY0-NEXT: [[TMP1985:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3837]]
|
|
// SIMD-ONLY0: cond.end3837:
|
|
// SIMD-ONLY0-NEXT: [[COND3838:%.*]] = phi i64 [ [[TMP1984]], [[COND_TRUE3835]] ], [ [[TMP1985]], [[COND_FALSE3836]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3838]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1986:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1987:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3839:%.*]] = icmp ult i64 [[TMP1986]], [[TMP1987]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3839]], label [[COND_TRUE3841:%.*]], label [[COND_FALSE3842:%.*]]
|
|
// SIMD-ONLY0: cond.true3841:
|
|
// SIMD-ONLY0-NEXT: [[TMP1988:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3843:%.*]]
|
|
// SIMD-ONLY0: cond.false3842:
|
|
// SIMD-ONLY0-NEXT: [[TMP1989:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3843]]
|
|
// SIMD-ONLY0: cond.end3843:
|
|
// SIMD-ONLY0-NEXT: [[COND3844:%.*]] = phi i64 [ [[TMP1988]], [[COND_TRUE3841]] ], [ [[TMP1989]], [[COND_FALSE3842]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3844]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1990:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1991:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3845:%.*]] = icmp ugt i64 [[TMP1990]], [[TMP1991]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3845]], label [[IF_THEN3847:%.*]], label [[IF_END3848:%.*]]
|
|
// SIMD-ONLY0: if.then3847:
|
|
// SIMD-ONLY0-NEXT: [[TMP1992:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1992]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3848]]
|
|
// SIMD-ONLY0: if.end3848:
|
|
// SIMD-ONLY0-NEXT: [[TMP1993:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1994:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3849:%.*]] = icmp ult i64 [[TMP1993]], [[TMP1994]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3849]], label [[IF_THEN3851:%.*]], label [[IF_END3852:%.*]]
|
|
// SIMD-ONLY0: if.then3851:
|
|
// SIMD-ONLY0-NEXT: [[TMP1995:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1995]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3852]]
|
|
// SIMD-ONLY0: if.end3852:
|
|
// SIMD-ONLY0-NEXT: [[TMP1996:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1997:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3853:%.*]] = icmp ugt i64 [[TMP1996]], [[TMP1997]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3853]], label [[IF_THEN3855:%.*]], label [[IF_END3856:%.*]]
|
|
// SIMD-ONLY0: if.then3855:
|
|
// SIMD-ONLY0-NEXT: [[TMP1998:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP1998]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3856]]
|
|
// SIMD-ONLY0: if.end3856:
|
|
// SIMD-ONLY0-NEXT: [[TMP1999:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2000:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3857:%.*]] = icmp ult i64 [[TMP1999]], [[TMP2000]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3857]], label [[IF_THEN3859:%.*]], label [[IF_END3860:%.*]]
|
|
// SIMD-ONLY0: if.then3859:
|
|
// SIMD-ONLY0-NEXT: [[TMP2001:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2001]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3860]]
|
|
// SIMD-ONLY0: if.end3860:
|
|
// SIMD-ONLY0-NEXT: [[TMP2002:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2003:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3861:%.*]] = icmp eq i64 [[TMP2002]], [[TMP2003]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3861]], label [[COND_TRUE3863:%.*]], label [[COND_FALSE3864:%.*]]
|
|
// SIMD-ONLY0: cond.true3863:
|
|
// SIMD-ONLY0-NEXT: [[TMP2004:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3865:%.*]]
|
|
// SIMD-ONLY0: cond.false3864:
|
|
// SIMD-ONLY0-NEXT: [[TMP2005:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3865]]
|
|
// SIMD-ONLY0: cond.end3865:
|
|
// SIMD-ONLY0-NEXT: [[COND3866:%.*]] = phi i64 [ [[TMP2004]], [[COND_TRUE3863]] ], [ [[TMP2005]], [[COND_FALSE3864]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3866]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2006:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2007:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3867:%.*]] = icmp eq i64 [[TMP2006]], [[TMP2007]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3867]], label [[COND_TRUE3869:%.*]], label [[COND_FALSE3870:%.*]]
|
|
// SIMD-ONLY0: cond.true3869:
|
|
// SIMD-ONLY0-NEXT: [[TMP2008:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3871:%.*]]
|
|
// SIMD-ONLY0: cond.false3870:
|
|
// SIMD-ONLY0-NEXT: [[TMP2009:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3871]]
|
|
// SIMD-ONLY0: cond.end3871:
|
|
// SIMD-ONLY0-NEXT: [[COND3872:%.*]] = phi i64 [ [[TMP2008]], [[COND_TRUE3869]] ], [ [[TMP2009]], [[COND_FALSE3870]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3872]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2010:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2011:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3873:%.*]] = icmp eq i64 [[TMP2010]], [[TMP2011]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3873]], label [[IF_THEN3875:%.*]], label [[IF_END3876:%.*]]
|
|
// SIMD-ONLY0: if.then3875:
|
|
// SIMD-ONLY0-NEXT: [[TMP2012:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2012]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3876]]
|
|
// SIMD-ONLY0: if.end3876:
|
|
// SIMD-ONLY0-NEXT: [[TMP2013:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2014:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3877:%.*]] = icmp eq i64 [[TMP2013]], [[TMP2014]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3877]], label [[IF_THEN3879:%.*]], label [[IF_END3880:%.*]]
|
|
// SIMD-ONLY0: if.then3879:
|
|
// SIMD-ONLY0-NEXT: [[TMP2015:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2015]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3880]]
|
|
// SIMD-ONLY0: if.end3880:
|
|
// SIMD-ONLY0-NEXT: [[TMP2016:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2017:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3881:%.*]] = icmp sgt i64 [[TMP2016]], [[TMP2017]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3881]], label [[COND_TRUE3883:%.*]], label [[COND_FALSE3884:%.*]]
|
|
// SIMD-ONLY0: cond.true3883:
|
|
// SIMD-ONLY0-NEXT: [[TMP2018:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3885:%.*]]
|
|
// SIMD-ONLY0: cond.false3884:
|
|
// SIMD-ONLY0-NEXT: [[TMP2019:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3885]]
|
|
// SIMD-ONLY0: cond.end3885:
|
|
// SIMD-ONLY0-NEXT: [[COND3886:%.*]] = phi i64 [ [[TMP2018]], [[COND_TRUE3883]] ], [ [[TMP2019]], [[COND_FALSE3884]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3886]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2020:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2021:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3887:%.*]] = icmp slt i64 [[TMP2020]], [[TMP2021]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3887]], label [[COND_TRUE3889:%.*]], label [[COND_FALSE3890:%.*]]
|
|
// SIMD-ONLY0: cond.true3889:
|
|
// SIMD-ONLY0-NEXT: [[TMP2022:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3891:%.*]]
|
|
// SIMD-ONLY0: cond.false3890:
|
|
// SIMD-ONLY0-NEXT: [[TMP2023:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3891]]
|
|
// SIMD-ONLY0: cond.end3891:
|
|
// SIMD-ONLY0-NEXT: [[COND3892:%.*]] = phi i64 [ [[TMP2022]], [[COND_TRUE3889]] ], [ [[TMP2023]], [[COND_FALSE3890]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3892]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2024:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2025:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3893:%.*]] = icmp sgt i64 [[TMP2024]], [[TMP2025]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3893]], label [[COND_TRUE3895:%.*]], label [[COND_FALSE3896:%.*]]
|
|
// SIMD-ONLY0: cond.true3895:
|
|
// SIMD-ONLY0-NEXT: [[TMP2026:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3897:%.*]]
|
|
// SIMD-ONLY0: cond.false3896:
|
|
// SIMD-ONLY0-NEXT: [[TMP2027:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3897]]
|
|
// SIMD-ONLY0: cond.end3897:
|
|
// SIMD-ONLY0-NEXT: [[COND3898:%.*]] = phi i64 [ [[TMP2026]], [[COND_TRUE3895]] ], [ [[TMP2027]], [[COND_FALSE3896]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3898]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2028:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2029:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3899:%.*]] = icmp slt i64 [[TMP2028]], [[TMP2029]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3899]], label [[COND_TRUE3901:%.*]], label [[COND_FALSE3902:%.*]]
|
|
// SIMD-ONLY0: cond.true3901:
|
|
// SIMD-ONLY0-NEXT: [[TMP2030:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3903:%.*]]
|
|
// SIMD-ONLY0: cond.false3902:
|
|
// SIMD-ONLY0-NEXT: [[TMP2031:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3903]]
|
|
// SIMD-ONLY0: cond.end3903:
|
|
// SIMD-ONLY0-NEXT: [[COND3904:%.*]] = phi i64 [ [[TMP2030]], [[COND_TRUE3901]] ], [ [[TMP2031]], [[COND_FALSE3902]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3904]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2032:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2033:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3905:%.*]] = icmp sgt i64 [[TMP2032]], [[TMP2033]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3905]], label [[IF_THEN3907:%.*]], label [[IF_END3908:%.*]]
|
|
// SIMD-ONLY0: if.then3907:
|
|
// SIMD-ONLY0-NEXT: [[TMP2034:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2034]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3908]]
|
|
// SIMD-ONLY0: if.end3908:
|
|
// SIMD-ONLY0-NEXT: [[TMP2035:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2036:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3909:%.*]] = icmp slt i64 [[TMP2035]], [[TMP2036]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3909]], label [[IF_THEN3911:%.*]], label [[IF_END3912:%.*]]
|
|
// SIMD-ONLY0: if.then3911:
|
|
// SIMD-ONLY0-NEXT: [[TMP2037:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2037]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3912]]
|
|
// SIMD-ONLY0: if.end3912:
|
|
// SIMD-ONLY0-NEXT: [[TMP2038:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2039:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3913:%.*]] = icmp sgt i64 [[TMP2038]], [[TMP2039]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3913]], label [[IF_THEN3915:%.*]], label [[IF_END3916:%.*]]
|
|
// SIMD-ONLY0: if.then3915:
|
|
// SIMD-ONLY0-NEXT: [[TMP2040:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2040]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3916]]
|
|
// SIMD-ONLY0: if.end3916:
|
|
// SIMD-ONLY0-NEXT: [[TMP2041:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2042:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3917:%.*]] = icmp slt i64 [[TMP2041]], [[TMP2042]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3917]], label [[IF_THEN3919:%.*]], label [[IF_END3920:%.*]]
|
|
// SIMD-ONLY0: if.then3919:
|
|
// SIMD-ONLY0-NEXT: [[TMP2043:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2043]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3920]]
|
|
// SIMD-ONLY0: if.end3920:
|
|
// SIMD-ONLY0-NEXT: [[TMP2044:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2045:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3921:%.*]] = icmp eq i64 [[TMP2044]], [[TMP2045]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3921]], label [[COND_TRUE3923:%.*]], label [[COND_FALSE3924:%.*]]
|
|
// SIMD-ONLY0: cond.true3923:
|
|
// SIMD-ONLY0-NEXT: [[TMP2046:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3925:%.*]]
|
|
// SIMD-ONLY0: cond.false3924:
|
|
// SIMD-ONLY0-NEXT: [[TMP2047:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3925]]
|
|
// SIMD-ONLY0: cond.end3925:
|
|
// SIMD-ONLY0-NEXT: [[COND3926:%.*]] = phi i64 [ [[TMP2046]], [[COND_TRUE3923]] ], [ [[TMP2047]], [[COND_FALSE3924]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3926]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2048:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2049:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3927:%.*]] = icmp eq i64 [[TMP2048]], [[TMP2049]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3927]], label [[COND_TRUE3929:%.*]], label [[COND_FALSE3930:%.*]]
|
|
// SIMD-ONLY0: cond.true3929:
|
|
// SIMD-ONLY0-NEXT: [[TMP2050:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3931:%.*]]
|
|
// SIMD-ONLY0: cond.false3930:
|
|
// SIMD-ONLY0-NEXT: [[TMP2051:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3931]]
|
|
// SIMD-ONLY0: cond.end3931:
|
|
// SIMD-ONLY0-NEXT: [[COND3932:%.*]] = phi i64 [ [[TMP2050]], [[COND_TRUE3929]] ], [ [[TMP2051]], [[COND_FALSE3930]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3932]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2052:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2053:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3933:%.*]] = icmp eq i64 [[TMP2052]], [[TMP2053]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3933]], label [[IF_THEN3935:%.*]], label [[IF_END3936:%.*]]
|
|
// SIMD-ONLY0: if.then3935:
|
|
// SIMD-ONLY0-NEXT: [[TMP2054:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2054]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3936]]
|
|
// SIMD-ONLY0: if.end3936:
|
|
// SIMD-ONLY0-NEXT: [[TMP2055:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2056:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3937:%.*]] = icmp eq i64 [[TMP2055]], [[TMP2056]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3937]], label [[IF_THEN3939:%.*]], label [[IF_END3940:%.*]]
|
|
// SIMD-ONLY0: if.then3939:
|
|
// SIMD-ONLY0-NEXT: [[TMP2057:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2057]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3940]]
|
|
// SIMD-ONLY0: if.end3940:
|
|
// SIMD-ONLY0-NEXT: [[TMP2058:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2059:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3941:%.*]] = icmp ugt i64 [[TMP2058]], [[TMP2059]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3941]], label [[COND_TRUE3943:%.*]], label [[COND_FALSE3944:%.*]]
|
|
// SIMD-ONLY0: cond.true3943:
|
|
// SIMD-ONLY0-NEXT: [[TMP2060:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3945:%.*]]
|
|
// SIMD-ONLY0: cond.false3944:
|
|
// SIMD-ONLY0-NEXT: [[TMP2061:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3945]]
|
|
// SIMD-ONLY0: cond.end3945:
|
|
// SIMD-ONLY0-NEXT: [[COND3946:%.*]] = phi i64 [ [[TMP2060]], [[COND_TRUE3943]] ], [ [[TMP2061]], [[COND_FALSE3944]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3946]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2062:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2063:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3947:%.*]] = icmp ult i64 [[TMP2062]], [[TMP2063]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3947]], label [[COND_TRUE3949:%.*]], label [[COND_FALSE3950:%.*]]
|
|
// SIMD-ONLY0: cond.true3949:
|
|
// SIMD-ONLY0-NEXT: [[TMP2064:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3951:%.*]]
|
|
// SIMD-ONLY0: cond.false3950:
|
|
// SIMD-ONLY0-NEXT: [[TMP2065:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3951]]
|
|
// SIMD-ONLY0: cond.end3951:
|
|
// SIMD-ONLY0-NEXT: [[COND3952:%.*]] = phi i64 [ [[TMP2064]], [[COND_TRUE3949]] ], [ [[TMP2065]], [[COND_FALSE3950]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3952]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2066:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2067:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3953:%.*]] = icmp ugt i64 [[TMP2066]], [[TMP2067]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3953]], label [[COND_TRUE3955:%.*]], label [[COND_FALSE3956:%.*]]
|
|
// SIMD-ONLY0: cond.true3955:
|
|
// SIMD-ONLY0-NEXT: [[TMP2068:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3957:%.*]]
|
|
// SIMD-ONLY0: cond.false3956:
|
|
// SIMD-ONLY0-NEXT: [[TMP2069:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3957]]
|
|
// SIMD-ONLY0: cond.end3957:
|
|
// SIMD-ONLY0-NEXT: [[COND3958:%.*]] = phi i64 [ [[TMP2068]], [[COND_TRUE3955]] ], [ [[TMP2069]], [[COND_FALSE3956]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3958]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2070:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2071:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3959:%.*]] = icmp ult i64 [[TMP2070]], [[TMP2071]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3959]], label [[COND_TRUE3961:%.*]], label [[COND_FALSE3962:%.*]]
|
|
// SIMD-ONLY0: cond.true3961:
|
|
// SIMD-ONLY0-NEXT: [[TMP2072:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3963:%.*]]
|
|
// SIMD-ONLY0: cond.false3962:
|
|
// SIMD-ONLY0-NEXT: [[TMP2073:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3963]]
|
|
// SIMD-ONLY0: cond.end3963:
|
|
// SIMD-ONLY0-NEXT: [[COND3964:%.*]] = phi i64 [ [[TMP2072]], [[COND_TRUE3961]] ], [ [[TMP2073]], [[COND_FALSE3962]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3964]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2074:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2075:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3965:%.*]] = icmp ugt i64 [[TMP2074]], [[TMP2075]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3965]], label [[IF_THEN3967:%.*]], label [[IF_END3968:%.*]]
|
|
// SIMD-ONLY0: if.then3967:
|
|
// SIMD-ONLY0-NEXT: [[TMP2076:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2076]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3968]]
|
|
// SIMD-ONLY0: if.end3968:
|
|
// SIMD-ONLY0-NEXT: [[TMP2077:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2078:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3969:%.*]] = icmp ult i64 [[TMP2077]], [[TMP2078]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3969]], label [[IF_THEN3971:%.*]], label [[IF_END3972:%.*]]
|
|
// SIMD-ONLY0: if.then3971:
|
|
// SIMD-ONLY0-NEXT: [[TMP2079:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2079]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3972]]
|
|
// SIMD-ONLY0: if.end3972:
|
|
// SIMD-ONLY0-NEXT: [[TMP2080:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2081:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3973:%.*]] = icmp ugt i64 [[TMP2080]], [[TMP2081]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3973]], label [[IF_THEN3975:%.*]], label [[IF_END3976:%.*]]
|
|
// SIMD-ONLY0: if.then3975:
|
|
// SIMD-ONLY0-NEXT: [[TMP2082:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2082]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3976]]
|
|
// SIMD-ONLY0: if.end3976:
|
|
// SIMD-ONLY0-NEXT: [[TMP2083:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2084:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3977:%.*]] = icmp ult i64 [[TMP2083]], [[TMP2084]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3977]], label [[IF_THEN3979:%.*]], label [[IF_END3980:%.*]]
|
|
// SIMD-ONLY0: if.then3979:
|
|
// SIMD-ONLY0-NEXT: [[TMP2085:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2085]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3980]]
|
|
// SIMD-ONLY0: if.end3980:
|
|
// SIMD-ONLY0-NEXT: [[TMP2086:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2087:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3981:%.*]] = icmp eq i64 [[TMP2086]], [[TMP2087]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3981]], label [[COND_TRUE3983:%.*]], label [[COND_FALSE3984:%.*]]
|
|
// SIMD-ONLY0: cond.true3983:
|
|
// SIMD-ONLY0-NEXT: [[TMP2088:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3985:%.*]]
|
|
// SIMD-ONLY0: cond.false3984:
|
|
// SIMD-ONLY0-NEXT: [[TMP2089:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3985]]
|
|
// SIMD-ONLY0: cond.end3985:
|
|
// SIMD-ONLY0-NEXT: [[COND3986:%.*]] = phi i64 [ [[TMP2088]], [[COND_TRUE3983]] ], [ [[TMP2089]], [[COND_FALSE3984]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3986]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2090:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2091:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3987:%.*]] = icmp eq i64 [[TMP2090]], [[TMP2091]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3987]], label [[COND_TRUE3989:%.*]], label [[COND_FALSE3990:%.*]]
|
|
// SIMD-ONLY0: cond.true3989:
|
|
// SIMD-ONLY0-NEXT: [[TMP2092:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3991:%.*]]
|
|
// SIMD-ONLY0: cond.false3990:
|
|
// SIMD-ONLY0-NEXT: [[TMP2093:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END3991]]
|
|
// SIMD-ONLY0: cond.end3991:
|
|
// SIMD-ONLY0-NEXT: [[COND3992:%.*]] = phi i64 [ [[TMP2092]], [[COND_TRUE3989]] ], [ [[TMP2093]], [[COND_FALSE3990]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND3992]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2094:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2095:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3993:%.*]] = icmp eq i64 [[TMP2094]], [[TMP2095]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3993]], label [[IF_THEN3995:%.*]], label [[IF_END3996:%.*]]
|
|
// SIMD-ONLY0: if.then3995:
|
|
// SIMD-ONLY0-NEXT: [[TMP2096:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2096]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3996]]
|
|
// SIMD-ONLY0: if.end3996:
|
|
// SIMD-ONLY0-NEXT: [[TMP2097:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2098:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3997:%.*]] = icmp eq i64 [[TMP2097]], [[TMP2098]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3997]], label [[IF_THEN3999:%.*]], label [[IF_END4000:%.*]]
|
|
// SIMD-ONLY0: if.then3999:
|
|
// SIMD-ONLY0-NEXT: [[TMP2099:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2099]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4000]]
|
|
// SIMD-ONLY0: if.end4000:
|
|
// SIMD-ONLY0-NEXT: [[TMP2100:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2101:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4001:%.*]] = icmp sgt i64 [[TMP2100]], [[TMP2101]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4001]], label [[COND_TRUE4003:%.*]], label [[COND_FALSE4004:%.*]]
|
|
// SIMD-ONLY0: cond.true4003:
|
|
// SIMD-ONLY0-NEXT: [[TMP2102:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4005:%.*]]
|
|
// SIMD-ONLY0: cond.false4004:
|
|
// SIMD-ONLY0-NEXT: [[TMP2103:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4005]]
|
|
// SIMD-ONLY0: cond.end4005:
|
|
// SIMD-ONLY0-NEXT: [[COND4006:%.*]] = phi i64 [ [[TMP2102]], [[COND_TRUE4003]] ], [ [[TMP2103]], [[COND_FALSE4004]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4006]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2104:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2105:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4007:%.*]] = icmp slt i64 [[TMP2104]], [[TMP2105]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4007]], label [[COND_TRUE4009:%.*]], label [[COND_FALSE4010:%.*]]
|
|
// SIMD-ONLY0: cond.true4009:
|
|
// SIMD-ONLY0-NEXT: [[TMP2106:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4011:%.*]]
|
|
// SIMD-ONLY0: cond.false4010:
|
|
// SIMD-ONLY0-NEXT: [[TMP2107:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4011]]
|
|
// SIMD-ONLY0: cond.end4011:
|
|
// SIMD-ONLY0-NEXT: [[COND4012:%.*]] = phi i64 [ [[TMP2106]], [[COND_TRUE4009]] ], [ [[TMP2107]], [[COND_FALSE4010]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4012]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2108:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2109:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4013:%.*]] = icmp sgt i64 [[TMP2108]], [[TMP2109]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4013]], label [[COND_TRUE4015:%.*]], label [[COND_FALSE4016:%.*]]
|
|
// SIMD-ONLY0: cond.true4015:
|
|
// SIMD-ONLY0-NEXT: [[TMP2110:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4017:%.*]]
|
|
// SIMD-ONLY0: cond.false4016:
|
|
// SIMD-ONLY0-NEXT: [[TMP2111:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4017]]
|
|
// SIMD-ONLY0: cond.end4017:
|
|
// SIMD-ONLY0-NEXT: [[COND4018:%.*]] = phi i64 [ [[TMP2110]], [[COND_TRUE4015]] ], [ [[TMP2111]], [[COND_FALSE4016]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4018]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2112:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2113:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4019:%.*]] = icmp slt i64 [[TMP2112]], [[TMP2113]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4019]], label [[COND_TRUE4021:%.*]], label [[COND_FALSE4022:%.*]]
|
|
// SIMD-ONLY0: cond.true4021:
|
|
// SIMD-ONLY0-NEXT: [[TMP2114:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4023:%.*]]
|
|
// SIMD-ONLY0: cond.false4022:
|
|
// SIMD-ONLY0-NEXT: [[TMP2115:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4023]]
|
|
// SIMD-ONLY0: cond.end4023:
|
|
// SIMD-ONLY0-NEXT: [[COND4024:%.*]] = phi i64 [ [[TMP2114]], [[COND_TRUE4021]] ], [ [[TMP2115]], [[COND_FALSE4022]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4024]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2116:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2117:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4025:%.*]] = icmp sgt i64 [[TMP2116]], [[TMP2117]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4025]], label [[IF_THEN4027:%.*]], label [[IF_END4028:%.*]]
|
|
// SIMD-ONLY0: if.then4027:
|
|
// SIMD-ONLY0-NEXT: [[TMP2118:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2118]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4028]]
|
|
// SIMD-ONLY0: if.end4028:
|
|
// SIMD-ONLY0-NEXT: [[TMP2119:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2120:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4029:%.*]] = icmp slt i64 [[TMP2119]], [[TMP2120]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4029]], label [[IF_THEN4031:%.*]], label [[IF_END4032:%.*]]
|
|
// SIMD-ONLY0: if.then4031:
|
|
// SIMD-ONLY0-NEXT: [[TMP2121:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2121]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4032]]
|
|
// SIMD-ONLY0: if.end4032:
|
|
// SIMD-ONLY0-NEXT: [[TMP2122:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2123:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4033:%.*]] = icmp sgt i64 [[TMP2122]], [[TMP2123]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4033]], label [[IF_THEN4035:%.*]], label [[IF_END4036:%.*]]
|
|
// SIMD-ONLY0: if.then4035:
|
|
// SIMD-ONLY0-NEXT: [[TMP2124:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2124]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4036]]
|
|
// SIMD-ONLY0: if.end4036:
|
|
// SIMD-ONLY0-NEXT: [[TMP2125:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2126:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4037:%.*]] = icmp slt i64 [[TMP2125]], [[TMP2126]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4037]], label [[IF_THEN4039:%.*]], label [[IF_END4040:%.*]]
|
|
// SIMD-ONLY0: if.then4039:
|
|
// SIMD-ONLY0-NEXT: [[TMP2127:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2127]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4040]]
|
|
// SIMD-ONLY0: if.end4040:
|
|
// SIMD-ONLY0-NEXT: [[TMP2128:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2129:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4041:%.*]] = icmp eq i64 [[TMP2128]], [[TMP2129]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4041]], label [[COND_TRUE4043:%.*]], label [[COND_FALSE4044:%.*]]
|
|
// SIMD-ONLY0: cond.true4043:
|
|
// SIMD-ONLY0-NEXT: [[TMP2130:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4045:%.*]]
|
|
// SIMD-ONLY0: cond.false4044:
|
|
// SIMD-ONLY0-NEXT: [[TMP2131:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4045]]
|
|
// SIMD-ONLY0: cond.end4045:
|
|
// SIMD-ONLY0-NEXT: [[COND4046:%.*]] = phi i64 [ [[TMP2130]], [[COND_TRUE4043]] ], [ [[TMP2131]], [[COND_FALSE4044]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4046]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2132:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2133:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4047:%.*]] = icmp eq i64 [[TMP2132]], [[TMP2133]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4047]], label [[COND_TRUE4049:%.*]], label [[COND_FALSE4050:%.*]]
|
|
// SIMD-ONLY0: cond.true4049:
|
|
// SIMD-ONLY0-NEXT: [[TMP2134:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4051:%.*]]
|
|
// SIMD-ONLY0: cond.false4050:
|
|
// SIMD-ONLY0-NEXT: [[TMP2135:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4051]]
|
|
// SIMD-ONLY0: cond.end4051:
|
|
// SIMD-ONLY0-NEXT: [[COND4052:%.*]] = phi i64 [ [[TMP2134]], [[COND_TRUE4049]] ], [ [[TMP2135]], [[COND_FALSE4050]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4052]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2136:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2137:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4053:%.*]] = icmp eq i64 [[TMP2136]], [[TMP2137]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4053]], label [[IF_THEN4055:%.*]], label [[IF_END4056:%.*]]
|
|
// SIMD-ONLY0: if.then4055:
|
|
// SIMD-ONLY0-NEXT: [[TMP2138:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2138]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4056]]
|
|
// SIMD-ONLY0: if.end4056:
|
|
// SIMD-ONLY0-NEXT: [[TMP2139:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2140:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4057:%.*]] = icmp eq i64 [[TMP2139]], [[TMP2140]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4057]], label [[IF_THEN4059:%.*]], label [[IF_END4060:%.*]]
|
|
// SIMD-ONLY0: if.then4059:
|
|
// SIMD-ONLY0-NEXT: [[TMP2141:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2141]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4060]]
|
|
// SIMD-ONLY0: if.end4060:
|
|
// SIMD-ONLY0-NEXT: [[TMP2142:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2143:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4061:%.*]] = icmp ugt i64 [[TMP2142]], [[TMP2143]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4061]], label [[COND_TRUE4063:%.*]], label [[COND_FALSE4064:%.*]]
|
|
// SIMD-ONLY0: cond.true4063:
|
|
// SIMD-ONLY0-NEXT: [[TMP2144:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4065:%.*]]
|
|
// SIMD-ONLY0: cond.false4064:
|
|
// SIMD-ONLY0-NEXT: [[TMP2145:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4065]]
|
|
// SIMD-ONLY0: cond.end4065:
|
|
// SIMD-ONLY0-NEXT: [[COND4066:%.*]] = phi i64 [ [[TMP2144]], [[COND_TRUE4063]] ], [ [[TMP2145]], [[COND_FALSE4064]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4066]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2146:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2147:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4067:%.*]] = icmp ult i64 [[TMP2146]], [[TMP2147]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4067]], label [[COND_TRUE4069:%.*]], label [[COND_FALSE4070:%.*]]
|
|
// SIMD-ONLY0: cond.true4069:
|
|
// SIMD-ONLY0-NEXT: [[TMP2148:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4071:%.*]]
|
|
// SIMD-ONLY0: cond.false4070:
|
|
// SIMD-ONLY0-NEXT: [[TMP2149:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4071]]
|
|
// SIMD-ONLY0: cond.end4071:
|
|
// SIMD-ONLY0-NEXT: [[COND4072:%.*]] = phi i64 [ [[TMP2148]], [[COND_TRUE4069]] ], [ [[TMP2149]], [[COND_FALSE4070]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4072]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2150:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2151:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4073:%.*]] = icmp ugt i64 [[TMP2150]], [[TMP2151]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4073]], label [[COND_TRUE4075:%.*]], label [[COND_FALSE4076:%.*]]
|
|
// SIMD-ONLY0: cond.true4075:
|
|
// SIMD-ONLY0-NEXT: [[TMP2152:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4077:%.*]]
|
|
// SIMD-ONLY0: cond.false4076:
|
|
// SIMD-ONLY0-NEXT: [[TMP2153:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4077]]
|
|
// SIMD-ONLY0: cond.end4077:
|
|
// SIMD-ONLY0-NEXT: [[COND4078:%.*]] = phi i64 [ [[TMP2152]], [[COND_TRUE4075]] ], [ [[TMP2153]], [[COND_FALSE4076]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4078]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2154:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2155:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4079:%.*]] = icmp ult i64 [[TMP2154]], [[TMP2155]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4079]], label [[COND_TRUE4081:%.*]], label [[COND_FALSE4082:%.*]]
|
|
// SIMD-ONLY0: cond.true4081:
|
|
// SIMD-ONLY0-NEXT: [[TMP2156:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4083:%.*]]
|
|
// SIMD-ONLY0: cond.false4082:
|
|
// SIMD-ONLY0-NEXT: [[TMP2157:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4083]]
|
|
// SIMD-ONLY0: cond.end4083:
|
|
// SIMD-ONLY0-NEXT: [[COND4084:%.*]] = phi i64 [ [[TMP2156]], [[COND_TRUE4081]] ], [ [[TMP2157]], [[COND_FALSE4082]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4084]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2158:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2159:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4085:%.*]] = icmp ugt i64 [[TMP2158]], [[TMP2159]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4085]], label [[IF_THEN4087:%.*]], label [[IF_END4088:%.*]]
|
|
// SIMD-ONLY0: if.then4087:
|
|
// SIMD-ONLY0-NEXT: [[TMP2160:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2160]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4088]]
|
|
// SIMD-ONLY0: if.end4088:
|
|
// SIMD-ONLY0-NEXT: [[TMP2161:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2162:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4089:%.*]] = icmp ult i64 [[TMP2161]], [[TMP2162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4089]], label [[IF_THEN4091:%.*]], label [[IF_END4092:%.*]]
|
|
// SIMD-ONLY0: if.then4091:
|
|
// SIMD-ONLY0-NEXT: [[TMP2163:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2163]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4092]]
|
|
// SIMD-ONLY0: if.end4092:
|
|
// SIMD-ONLY0-NEXT: [[TMP2164:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2165:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4093:%.*]] = icmp ugt i64 [[TMP2164]], [[TMP2165]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4093]], label [[IF_THEN4095:%.*]], label [[IF_END4096:%.*]]
|
|
// SIMD-ONLY0: if.then4095:
|
|
// SIMD-ONLY0-NEXT: [[TMP2166:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2166]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4096]]
|
|
// SIMD-ONLY0: if.end4096:
|
|
// SIMD-ONLY0-NEXT: [[TMP2167:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2168:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4097:%.*]] = icmp ult i64 [[TMP2167]], [[TMP2168]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4097]], label [[IF_THEN4099:%.*]], label [[IF_END4100:%.*]]
|
|
// SIMD-ONLY0: if.then4099:
|
|
// SIMD-ONLY0-NEXT: [[TMP2169:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2169]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4100]]
|
|
// SIMD-ONLY0: if.end4100:
|
|
// SIMD-ONLY0-NEXT: [[TMP2170:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2171:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4101:%.*]] = icmp eq i64 [[TMP2170]], [[TMP2171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4101]], label [[COND_TRUE4103:%.*]], label [[COND_FALSE4104:%.*]]
|
|
// SIMD-ONLY0: cond.true4103:
|
|
// SIMD-ONLY0-NEXT: [[TMP2172:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4105:%.*]]
|
|
// SIMD-ONLY0: cond.false4104:
|
|
// SIMD-ONLY0-NEXT: [[TMP2173:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4105]]
|
|
// SIMD-ONLY0: cond.end4105:
|
|
// SIMD-ONLY0-NEXT: [[COND4106:%.*]] = phi i64 [ [[TMP2172]], [[COND_TRUE4103]] ], [ [[TMP2173]], [[COND_FALSE4104]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4106]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2174:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2175:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4107:%.*]] = icmp eq i64 [[TMP2174]], [[TMP2175]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4107]], label [[COND_TRUE4109:%.*]], label [[COND_FALSE4110:%.*]]
|
|
// SIMD-ONLY0: cond.true4109:
|
|
// SIMD-ONLY0-NEXT: [[TMP2176:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4111:%.*]]
|
|
// SIMD-ONLY0: cond.false4110:
|
|
// SIMD-ONLY0-NEXT: [[TMP2177:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4111]]
|
|
// SIMD-ONLY0: cond.end4111:
|
|
// SIMD-ONLY0-NEXT: [[COND4112:%.*]] = phi i64 [ [[TMP2176]], [[COND_TRUE4109]] ], [ [[TMP2177]], [[COND_FALSE4110]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4112]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2178:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2179:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4113:%.*]] = icmp eq i64 [[TMP2178]], [[TMP2179]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4113]], label [[IF_THEN4115:%.*]], label [[IF_END4116:%.*]]
|
|
// SIMD-ONLY0: if.then4115:
|
|
// SIMD-ONLY0-NEXT: [[TMP2180:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2180]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4116]]
|
|
// SIMD-ONLY0: if.end4116:
|
|
// SIMD-ONLY0-NEXT: [[TMP2181:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2182:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4117:%.*]] = icmp eq i64 [[TMP2181]], [[TMP2182]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4117]], label [[IF_THEN4119:%.*]], label [[IF_END4120:%.*]]
|
|
// SIMD-ONLY0: if.then4119:
|
|
// SIMD-ONLY0-NEXT: [[TMP2183:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2183]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4120]]
|
|
// SIMD-ONLY0: if.end4120:
|
|
// SIMD-ONLY0-NEXT: [[TMP2184:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2185:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4121:%.*]] = icmp sgt i64 [[TMP2184]], [[TMP2185]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4121]], label [[COND_TRUE4123:%.*]], label [[COND_FALSE4124:%.*]]
|
|
// SIMD-ONLY0: cond.true4123:
|
|
// SIMD-ONLY0-NEXT: [[TMP2186:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4125:%.*]]
|
|
// SIMD-ONLY0: cond.false4124:
|
|
// SIMD-ONLY0-NEXT: [[TMP2187:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4125]]
|
|
// SIMD-ONLY0: cond.end4125:
|
|
// SIMD-ONLY0-NEXT: [[COND4126:%.*]] = phi i64 [ [[TMP2186]], [[COND_TRUE4123]] ], [ [[TMP2187]], [[COND_FALSE4124]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4126]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2188:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2189:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4127:%.*]] = icmp slt i64 [[TMP2188]], [[TMP2189]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4127]], label [[COND_TRUE4129:%.*]], label [[COND_FALSE4130:%.*]]
|
|
// SIMD-ONLY0: cond.true4129:
|
|
// SIMD-ONLY0-NEXT: [[TMP2190:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4131:%.*]]
|
|
// SIMD-ONLY0: cond.false4130:
|
|
// SIMD-ONLY0-NEXT: [[TMP2191:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4131]]
|
|
// SIMD-ONLY0: cond.end4131:
|
|
// SIMD-ONLY0-NEXT: [[COND4132:%.*]] = phi i64 [ [[TMP2190]], [[COND_TRUE4129]] ], [ [[TMP2191]], [[COND_FALSE4130]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4132]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2192:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2193:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4133:%.*]] = icmp sgt i64 [[TMP2192]], [[TMP2193]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4133]], label [[COND_TRUE4135:%.*]], label [[COND_FALSE4136:%.*]]
|
|
// SIMD-ONLY0: cond.true4135:
|
|
// SIMD-ONLY0-NEXT: [[TMP2194:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4137:%.*]]
|
|
// SIMD-ONLY0: cond.false4136:
|
|
// SIMD-ONLY0-NEXT: [[TMP2195:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4137]]
|
|
// SIMD-ONLY0: cond.end4137:
|
|
// SIMD-ONLY0-NEXT: [[COND4138:%.*]] = phi i64 [ [[TMP2194]], [[COND_TRUE4135]] ], [ [[TMP2195]], [[COND_FALSE4136]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4138]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2196:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2197:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4139:%.*]] = icmp slt i64 [[TMP2196]], [[TMP2197]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4139]], label [[COND_TRUE4141:%.*]], label [[COND_FALSE4142:%.*]]
|
|
// SIMD-ONLY0: cond.true4141:
|
|
// SIMD-ONLY0-NEXT: [[TMP2198:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4143:%.*]]
|
|
// SIMD-ONLY0: cond.false4142:
|
|
// SIMD-ONLY0-NEXT: [[TMP2199:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4143]]
|
|
// SIMD-ONLY0: cond.end4143:
|
|
// SIMD-ONLY0-NEXT: [[COND4144:%.*]] = phi i64 [ [[TMP2198]], [[COND_TRUE4141]] ], [ [[TMP2199]], [[COND_FALSE4142]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4144]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2200:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2201:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4145:%.*]] = icmp sgt i64 [[TMP2200]], [[TMP2201]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4145]], label [[IF_THEN4147:%.*]], label [[IF_END4148:%.*]]
|
|
// SIMD-ONLY0: if.then4147:
|
|
// SIMD-ONLY0-NEXT: [[TMP2202:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2202]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4148]]
|
|
// SIMD-ONLY0: if.end4148:
|
|
// SIMD-ONLY0-NEXT: [[TMP2203:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2204:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4149:%.*]] = icmp slt i64 [[TMP2203]], [[TMP2204]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4149]], label [[IF_THEN4151:%.*]], label [[IF_END4152:%.*]]
|
|
// SIMD-ONLY0: if.then4151:
|
|
// SIMD-ONLY0-NEXT: [[TMP2205:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2205]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4152]]
|
|
// SIMD-ONLY0: if.end4152:
|
|
// SIMD-ONLY0-NEXT: [[TMP2206:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2207:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4153:%.*]] = icmp sgt i64 [[TMP2206]], [[TMP2207]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4153]], label [[IF_THEN4155:%.*]], label [[IF_END4156:%.*]]
|
|
// SIMD-ONLY0: if.then4155:
|
|
// SIMD-ONLY0-NEXT: [[TMP2208:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2208]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4156]]
|
|
// SIMD-ONLY0: if.end4156:
|
|
// SIMD-ONLY0-NEXT: [[TMP2209:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2210:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4157:%.*]] = icmp slt i64 [[TMP2209]], [[TMP2210]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4157]], label [[IF_THEN4159:%.*]], label [[IF_END4160:%.*]]
|
|
// SIMD-ONLY0: if.then4159:
|
|
// SIMD-ONLY0-NEXT: [[TMP2211:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2211]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4160]]
|
|
// SIMD-ONLY0: if.end4160:
|
|
// SIMD-ONLY0-NEXT: [[TMP2212:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2213:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4161:%.*]] = icmp eq i64 [[TMP2212]], [[TMP2213]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4161]], label [[COND_TRUE4163:%.*]], label [[COND_FALSE4164:%.*]]
|
|
// SIMD-ONLY0: cond.true4163:
|
|
// SIMD-ONLY0-NEXT: [[TMP2214:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4165:%.*]]
|
|
// SIMD-ONLY0: cond.false4164:
|
|
// SIMD-ONLY0-NEXT: [[TMP2215:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4165]]
|
|
// SIMD-ONLY0: cond.end4165:
|
|
// SIMD-ONLY0-NEXT: [[COND4166:%.*]] = phi i64 [ [[TMP2214]], [[COND_TRUE4163]] ], [ [[TMP2215]], [[COND_FALSE4164]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4166]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2216:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2217:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4167:%.*]] = icmp eq i64 [[TMP2216]], [[TMP2217]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4167]], label [[COND_TRUE4169:%.*]], label [[COND_FALSE4170:%.*]]
|
|
// SIMD-ONLY0: cond.true4169:
|
|
// SIMD-ONLY0-NEXT: [[TMP2218:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4171:%.*]]
|
|
// SIMD-ONLY0: cond.false4170:
|
|
// SIMD-ONLY0-NEXT: [[TMP2219:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4171]]
|
|
// SIMD-ONLY0: cond.end4171:
|
|
// SIMD-ONLY0-NEXT: [[COND4172:%.*]] = phi i64 [ [[TMP2218]], [[COND_TRUE4169]] ], [ [[TMP2219]], [[COND_FALSE4170]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4172]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2220:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2221:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4173:%.*]] = icmp eq i64 [[TMP2220]], [[TMP2221]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4173]], label [[IF_THEN4175:%.*]], label [[IF_END4176:%.*]]
|
|
// SIMD-ONLY0: if.then4175:
|
|
// SIMD-ONLY0-NEXT: [[TMP2222:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2222]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4176]]
|
|
// SIMD-ONLY0: if.end4176:
|
|
// SIMD-ONLY0-NEXT: [[TMP2223:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2224:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4177:%.*]] = icmp eq i64 [[TMP2223]], [[TMP2224]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4177]], label [[IF_THEN4179:%.*]], label [[IF_END4180:%.*]]
|
|
// SIMD-ONLY0: if.then4179:
|
|
// SIMD-ONLY0-NEXT: [[TMP2225:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2225]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4180]]
|
|
// SIMD-ONLY0: if.end4180:
|
|
// SIMD-ONLY0-NEXT: [[TMP2226:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2227:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4181:%.*]] = icmp ugt i64 [[TMP2226]], [[TMP2227]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4181]], label [[COND_TRUE4183:%.*]], label [[COND_FALSE4184:%.*]]
|
|
// SIMD-ONLY0: cond.true4183:
|
|
// SIMD-ONLY0-NEXT: [[TMP2228:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4185:%.*]]
|
|
// SIMD-ONLY0: cond.false4184:
|
|
// SIMD-ONLY0-NEXT: [[TMP2229:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4185]]
|
|
// SIMD-ONLY0: cond.end4185:
|
|
// SIMD-ONLY0-NEXT: [[COND4186:%.*]] = phi i64 [ [[TMP2228]], [[COND_TRUE4183]] ], [ [[TMP2229]], [[COND_FALSE4184]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4186]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2230:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2231:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4187:%.*]] = icmp ult i64 [[TMP2230]], [[TMP2231]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4187]], label [[COND_TRUE4189:%.*]], label [[COND_FALSE4190:%.*]]
|
|
// SIMD-ONLY0: cond.true4189:
|
|
// SIMD-ONLY0-NEXT: [[TMP2232:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4191:%.*]]
|
|
// SIMD-ONLY0: cond.false4190:
|
|
// SIMD-ONLY0-NEXT: [[TMP2233:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4191]]
|
|
// SIMD-ONLY0: cond.end4191:
|
|
// SIMD-ONLY0-NEXT: [[COND4192:%.*]] = phi i64 [ [[TMP2232]], [[COND_TRUE4189]] ], [ [[TMP2233]], [[COND_FALSE4190]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4192]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2234:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2235:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4193:%.*]] = icmp ugt i64 [[TMP2234]], [[TMP2235]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4193]], label [[COND_TRUE4195:%.*]], label [[COND_FALSE4196:%.*]]
|
|
// SIMD-ONLY0: cond.true4195:
|
|
// SIMD-ONLY0-NEXT: [[TMP2236:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4197:%.*]]
|
|
// SIMD-ONLY0: cond.false4196:
|
|
// SIMD-ONLY0-NEXT: [[TMP2237:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4197]]
|
|
// SIMD-ONLY0: cond.end4197:
|
|
// SIMD-ONLY0-NEXT: [[COND4198:%.*]] = phi i64 [ [[TMP2236]], [[COND_TRUE4195]] ], [ [[TMP2237]], [[COND_FALSE4196]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4198]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2238:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2239:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4199:%.*]] = icmp ult i64 [[TMP2238]], [[TMP2239]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4199]], label [[COND_TRUE4201:%.*]], label [[COND_FALSE4202:%.*]]
|
|
// SIMD-ONLY0: cond.true4201:
|
|
// SIMD-ONLY0-NEXT: [[TMP2240:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4203:%.*]]
|
|
// SIMD-ONLY0: cond.false4202:
|
|
// SIMD-ONLY0-NEXT: [[TMP2241:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4203]]
|
|
// SIMD-ONLY0: cond.end4203:
|
|
// SIMD-ONLY0-NEXT: [[COND4204:%.*]] = phi i64 [ [[TMP2240]], [[COND_TRUE4201]] ], [ [[TMP2241]], [[COND_FALSE4202]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4204]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2242:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2243:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4205:%.*]] = icmp ugt i64 [[TMP2242]], [[TMP2243]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4205]], label [[IF_THEN4207:%.*]], label [[IF_END4208:%.*]]
|
|
// SIMD-ONLY0: if.then4207:
|
|
// SIMD-ONLY0-NEXT: [[TMP2244:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2244]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4208]]
|
|
// SIMD-ONLY0: if.end4208:
|
|
// SIMD-ONLY0-NEXT: [[TMP2245:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2246:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4209:%.*]] = icmp ult i64 [[TMP2245]], [[TMP2246]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4209]], label [[IF_THEN4211:%.*]], label [[IF_END4212:%.*]]
|
|
// SIMD-ONLY0: if.then4211:
|
|
// SIMD-ONLY0-NEXT: [[TMP2247:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2247]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4212]]
|
|
// SIMD-ONLY0: if.end4212:
|
|
// SIMD-ONLY0-NEXT: [[TMP2248:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2249:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4213:%.*]] = icmp ugt i64 [[TMP2248]], [[TMP2249]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4213]], label [[IF_THEN4215:%.*]], label [[IF_END4216:%.*]]
|
|
// SIMD-ONLY0: if.then4215:
|
|
// SIMD-ONLY0-NEXT: [[TMP2250:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2250]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4216]]
|
|
// SIMD-ONLY0: if.end4216:
|
|
// SIMD-ONLY0-NEXT: [[TMP2251:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2252:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4217:%.*]] = icmp ult i64 [[TMP2251]], [[TMP2252]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4217]], label [[IF_THEN4219:%.*]], label [[IF_END4220:%.*]]
|
|
// SIMD-ONLY0: if.then4219:
|
|
// SIMD-ONLY0-NEXT: [[TMP2253:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2253]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4220]]
|
|
// SIMD-ONLY0: if.end4220:
|
|
// SIMD-ONLY0-NEXT: [[TMP2254:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2255:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4221:%.*]] = icmp eq i64 [[TMP2254]], [[TMP2255]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4221]], label [[COND_TRUE4223:%.*]], label [[COND_FALSE4224:%.*]]
|
|
// SIMD-ONLY0: cond.true4223:
|
|
// SIMD-ONLY0-NEXT: [[TMP2256:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4225:%.*]]
|
|
// SIMD-ONLY0: cond.false4224:
|
|
// SIMD-ONLY0-NEXT: [[TMP2257:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4225]]
|
|
// SIMD-ONLY0: cond.end4225:
|
|
// SIMD-ONLY0-NEXT: [[COND4226:%.*]] = phi i64 [ [[TMP2256]], [[COND_TRUE4223]] ], [ [[TMP2257]], [[COND_FALSE4224]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4226]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2258:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2259:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4227:%.*]] = icmp eq i64 [[TMP2258]], [[TMP2259]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4227]], label [[COND_TRUE4229:%.*]], label [[COND_FALSE4230:%.*]]
|
|
// SIMD-ONLY0: cond.true4229:
|
|
// SIMD-ONLY0-NEXT: [[TMP2260:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4231:%.*]]
|
|
// SIMD-ONLY0: cond.false4230:
|
|
// SIMD-ONLY0-NEXT: [[TMP2261:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4231]]
|
|
// SIMD-ONLY0: cond.end4231:
|
|
// SIMD-ONLY0-NEXT: [[COND4232:%.*]] = phi i64 [ [[TMP2260]], [[COND_TRUE4229]] ], [ [[TMP2261]], [[COND_FALSE4230]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4232]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2262:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2263:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4233:%.*]] = icmp eq i64 [[TMP2262]], [[TMP2263]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4233]], label [[IF_THEN4235:%.*]], label [[IF_END4236:%.*]]
|
|
// SIMD-ONLY0: if.then4235:
|
|
// SIMD-ONLY0-NEXT: [[TMP2264:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2264]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4236]]
|
|
// SIMD-ONLY0: if.end4236:
|
|
// SIMD-ONLY0-NEXT: [[TMP2265:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2266:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4237:%.*]] = icmp eq i64 [[TMP2265]], [[TMP2266]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4237]], label [[IF_THEN4239:%.*]], label [[IF_END4240:%.*]]
|
|
// SIMD-ONLY0: if.then4239:
|
|
// SIMD-ONLY0-NEXT: [[TMP2267:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2267]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4240]]
|
|
// SIMD-ONLY0: if.end4240:
|
|
// SIMD-ONLY0-NEXT: [[TMP2268:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2269:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4241:%.*]] = icmp sgt i64 [[TMP2268]], [[TMP2269]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4241]], label [[COND_TRUE4243:%.*]], label [[COND_FALSE4244:%.*]]
|
|
// SIMD-ONLY0: cond.true4243:
|
|
// SIMD-ONLY0-NEXT: [[TMP2270:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4245:%.*]]
|
|
// SIMD-ONLY0: cond.false4244:
|
|
// SIMD-ONLY0-NEXT: [[TMP2271:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4245]]
|
|
// SIMD-ONLY0: cond.end4245:
|
|
// SIMD-ONLY0-NEXT: [[COND4246:%.*]] = phi i64 [ [[TMP2270]], [[COND_TRUE4243]] ], [ [[TMP2271]], [[COND_FALSE4244]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4246]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2272:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2273:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4247:%.*]] = icmp slt i64 [[TMP2272]], [[TMP2273]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4247]], label [[COND_TRUE4249:%.*]], label [[COND_FALSE4250:%.*]]
|
|
// SIMD-ONLY0: cond.true4249:
|
|
// SIMD-ONLY0-NEXT: [[TMP2274:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4251:%.*]]
|
|
// SIMD-ONLY0: cond.false4250:
|
|
// SIMD-ONLY0-NEXT: [[TMP2275:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4251]]
|
|
// SIMD-ONLY0: cond.end4251:
|
|
// SIMD-ONLY0-NEXT: [[COND4252:%.*]] = phi i64 [ [[TMP2274]], [[COND_TRUE4249]] ], [ [[TMP2275]], [[COND_FALSE4250]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4252]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2276:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2277:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4253:%.*]] = icmp sgt i64 [[TMP2276]], [[TMP2277]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4253]], label [[COND_TRUE4255:%.*]], label [[COND_FALSE4256:%.*]]
|
|
// SIMD-ONLY0: cond.true4255:
|
|
// SIMD-ONLY0-NEXT: [[TMP2278:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4257:%.*]]
|
|
// SIMD-ONLY0: cond.false4256:
|
|
// SIMD-ONLY0-NEXT: [[TMP2279:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4257]]
|
|
// SIMD-ONLY0: cond.end4257:
|
|
// SIMD-ONLY0-NEXT: [[COND4258:%.*]] = phi i64 [ [[TMP2278]], [[COND_TRUE4255]] ], [ [[TMP2279]], [[COND_FALSE4256]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4258]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2280:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2281:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4259:%.*]] = icmp slt i64 [[TMP2280]], [[TMP2281]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4259]], label [[COND_TRUE4261:%.*]], label [[COND_FALSE4262:%.*]]
|
|
// SIMD-ONLY0: cond.true4261:
|
|
// SIMD-ONLY0-NEXT: [[TMP2282:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4263:%.*]]
|
|
// SIMD-ONLY0: cond.false4262:
|
|
// SIMD-ONLY0-NEXT: [[TMP2283:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4263]]
|
|
// SIMD-ONLY0: cond.end4263:
|
|
// SIMD-ONLY0-NEXT: [[COND4264:%.*]] = phi i64 [ [[TMP2282]], [[COND_TRUE4261]] ], [ [[TMP2283]], [[COND_FALSE4262]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4264]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2284:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2285:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4265:%.*]] = icmp sgt i64 [[TMP2284]], [[TMP2285]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4265]], label [[IF_THEN4267:%.*]], label [[IF_END4268:%.*]]
|
|
// SIMD-ONLY0: if.then4267:
|
|
// SIMD-ONLY0-NEXT: [[TMP2286:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2286]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4268]]
|
|
// SIMD-ONLY0: if.end4268:
|
|
// SIMD-ONLY0-NEXT: [[TMP2287:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2288:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4269:%.*]] = icmp slt i64 [[TMP2287]], [[TMP2288]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4269]], label [[IF_THEN4271:%.*]], label [[IF_END4272:%.*]]
|
|
// SIMD-ONLY0: if.then4271:
|
|
// SIMD-ONLY0-NEXT: [[TMP2289:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2289]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4272]]
|
|
// SIMD-ONLY0: if.end4272:
|
|
// SIMD-ONLY0-NEXT: [[TMP2290:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2291:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4273:%.*]] = icmp sgt i64 [[TMP2290]], [[TMP2291]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4273]], label [[IF_THEN4275:%.*]], label [[IF_END4276:%.*]]
|
|
// SIMD-ONLY0: if.then4275:
|
|
// SIMD-ONLY0-NEXT: [[TMP2292:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2292]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4276]]
|
|
// SIMD-ONLY0: if.end4276:
|
|
// SIMD-ONLY0-NEXT: [[TMP2293:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2294:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4277:%.*]] = icmp slt i64 [[TMP2293]], [[TMP2294]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4277]], label [[IF_THEN4279:%.*]], label [[IF_END4280:%.*]]
|
|
// SIMD-ONLY0: if.then4279:
|
|
// SIMD-ONLY0-NEXT: [[TMP2295:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2295]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4280]]
|
|
// SIMD-ONLY0: if.end4280:
|
|
// SIMD-ONLY0-NEXT: [[TMP2296:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2297:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4281:%.*]] = icmp eq i64 [[TMP2296]], [[TMP2297]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4281]], label [[COND_TRUE4283:%.*]], label [[COND_FALSE4284:%.*]]
|
|
// SIMD-ONLY0: cond.true4283:
|
|
// SIMD-ONLY0-NEXT: [[TMP2298:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4285:%.*]]
|
|
// SIMD-ONLY0: cond.false4284:
|
|
// SIMD-ONLY0-NEXT: [[TMP2299:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4285]]
|
|
// SIMD-ONLY0: cond.end4285:
|
|
// SIMD-ONLY0-NEXT: [[COND4286:%.*]] = phi i64 [ [[TMP2298]], [[COND_TRUE4283]] ], [ [[TMP2299]], [[COND_FALSE4284]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4286]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2300:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2301:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4287:%.*]] = icmp eq i64 [[TMP2300]], [[TMP2301]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4287]], label [[COND_TRUE4289:%.*]], label [[COND_FALSE4290:%.*]]
|
|
// SIMD-ONLY0: cond.true4289:
|
|
// SIMD-ONLY0-NEXT: [[TMP2302:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4291:%.*]]
|
|
// SIMD-ONLY0: cond.false4290:
|
|
// SIMD-ONLY0-NEXT: [[TMP2303:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4291]]
|
|
// SIMD-ONLY0: cond.end4291:
|
|
// SIMD-ONLY0-NEXT: [[COND4292:%.*]] = phi i64 [ [[TMP2302]], [[COND_TRUE4289]] ], [ [[TMP2303]], [[COND_FALSE4290]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4292]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2304:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2305:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4293:%.*]] = icmp eq i64 [[TMP2304]], [[TMP2305]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4293]], label [[IF_THEN4295:%.*]], label [[IF_END4296:%.*]]
|
|
// SIMD-ONLY0: if.then4295:
|
|
// SIMD-ONLY0-NEXT: [[TMP2306:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2306]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4296]]
|
|
// SIMD-ONLY0: if.end4296:
|
|
// SIMD-ONLY0-NEXT: [[TMP2307:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2308:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4297:%.*]] = icmp eq i64 [[TMP2307]], [[TMP2308]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4297]], label [[IF_THEN4299:%.*]], label [[IF_END4300:%.*]]
|
|
// SIMD-ONLY0: if.then4299:
|
|
// SIMD-ONLY0-NEXT: [[TMP2309:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2309]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4300]]
|
|
// SIMD-ONLY0: if.end4300:
|
|
// SIMD-ONLY0-NEXT: [[TMP2310:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2311:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4301:%.*]] = icmp ugt i64 [[TMP2310]], [[TMP2311]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4301]], label [[COND_TRUE4303:%.*]], label [[COND_FALSE4304:%.*]]
|
|
// SIMD-ONLY0: cond.true4303:
|
|
// SIMD-ONLY0-NEXT: [[TMP2312:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4305:%.*]]
|
|
// SIMD-ONLY0: cond.false4304:
|
|
// SIMD-ONLY0-NEXT: [[TMP2313:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4305]]
|
|
// SIMD-ONLY0: cond.end4305:
|
|
// SIMD-ONLY0-NEXT: [[COND4306:%.*]] = phi i64 [ [[TMP2312]], [[COND_TRUE4303]] ], [ [[TMP2313]], [[COND_FALSE4304]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4306]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2314:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2315:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4307:%.*]] = icmp ult i64 [[TMP2314]], [[TMP2315]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4307]], label [[COND_TRUE4309:%.*]], label [[COND_FALSE4310:%.*]]
|
|
// SIMD-ONLY0: cond.true4309:
|
|
// SIMD-ONLY0-NEXT: [[TMP2316:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4311:%.*]]
|
|
// SIMD-ONLY0: cond.false4310:
|
|
// SIMD-ONLY0-NEXT: [[TMP2317:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4311]]
|
|
// SIMD-ONLY0: cond.end4311:
|
|
// SIMD-ONLY0-NEXT: [[COND4312:%.*]] = phi i64 [ [[TMP2316]], [[COND_TRUE4309]] ], [ [[TMP2317]], [[COND_FALSE4310]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4312]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2318:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2319:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4313:%.*]] = icmp ugt i64 [[TMP2318]], [[TMP2319]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4313]], label [[COND_TRUE4315:%.*]], label [[COND_FALSE4316:%.*]]
|
|
// SIMD-ONLY0: cond.true4315:
|
|
// SIMD-ONLY0-NEXT: [[TMP2320:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4317:%.*]]
|
|
// SIMD-ONLY0: cond.false4316:
|
|
// SIMD-ONLY0-NEXT: [[TMP2321:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4317]]
|
|
// SIMD-ONLY0: cond.end4317:
|
|
// SIMD-ONLY0-NEXT: [[COND4318:%.*]] = phi i64 [ [[TMP2320]], [[COND_TRUE4315]] ], [ [[TMP2321]], [[COND_FALSE4316]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4318]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2322:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2323:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4319:%.*]] = icmp ult i64 [[TMP2322]], [[TMP2323]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4319]], label [[COND_TRUE4321:%.*]], label [[COND_FALSE4322:%.*]]
|
|
// SIMD-ONLY0: cond.true4321:
|
|
// SIMD-ONLY0-NEXT: [[TMP2324:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4323:%.*]]
|
|
// SIMD-ONLY0: cond.false4322:
|
|
// SIMD-ONLY0-NEXT: [[TMP2325:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4323]]
|
|
// SIMD-ONLY0: cond.end4323:
|
|
// SIMD-ONLY0-NEXT: [[COND4324:%.*]] = phi i64 [ [[TMP2324]], [[COND_TRUE4321]] ], [ [[TMP2325]], [[COND_FALSE4322]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4324]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2326:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2327:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4325:%.*]] = icmp ugt i64 [[TMP2326]], [[TMP2327]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4325]], label [[IF_THEN4327:%.*]], label [[IF_END4328:%.*]]
|
|
// SIMD-ONLY0: if.then4327:
|
|
// SIMD-ONLY0-NEXT: [[TMP2328:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2328]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4328]]
|
|
// SIMD-ONLY0: if.end4328:
|
|
// SIMD-ONLY0-NEXT: [[TMP2329:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2330:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4329:%.*]] = icmp ult i64 [[TMP2329]], [[TMP2330]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4329]], label [[IF_THEN4331:%.*]], label [[IF_END4332:%.*]]
|
|
// SIMD-ONLY0: if.then4331:
|
|
// SIMD-ONLY0-NEXT: [[TMP2331:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2331]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4332]]
|
|
// SIMD-ONLY0: if.end4332:
|
|
// SIMD-ONLY0-NEXT: [[TMP2332:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2333:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4333:%.*]] = icmp ugt i64 [[TMP2332]], [[TMP2333]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4333]], label [[IF_THEN4335:%.*]], label [[IF_END4336:%.*]]
|
|
// SIMD-ONLY0: if.then4335:
|
|
// SIMD-ONLY0-NEXT: [[TMP2334:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2334]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4336]]
|
|
// SIMD-ONLY0: if.end4336:
|
|
// SIMD-ONLY0-NEXT: [[TMP2335:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2336:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4337:%.*]] = icmp ult i64 [[TMP2335]], [[TMP2336]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4337]], label [[IF_THEN4339:%.*]], label [[IF_END4340:%.*]]
|
|
// SIMD-ONLY0: if.then4339:
|
|
// SIMD-ONLY0-NEXT: [[TMP2337:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2337]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4340]]
|
|
// SIMD-ONLY0: if.end4340:
|
|
// SIMD-ONLY0-NEXT: [[TMP2338:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2339:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4341:%.*]] = icmp eq i64 [[TMP2338]], [[TMP2339]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4341]], label [[COND_TRUE4343:%.*]], label [[COND_FALSE4344:%.*]]
|
|
// SIMD-ONLY0: cond.true4343:
|
|
// SIMD-ONLY0-NEXT: [[TMP2340:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4345:%.*]]
|
|
// SIMD-ONLY0: cond.false4344:
|
|
// SIMD-ONLY0-NEXT: [[TMP2341:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4345]]
|
|
// SIMD-ONLY0: cond.end4345:
|
|
// SIMD-ONLY0-NEXT: [[COND4346:%.*]] = phi i64 [ [[TMP2340]], [[COND_TRUE4343]] ], [ [[TMP2341]], [[COND_FALSE4344]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4346]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2342:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2343:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4347:%.*]] = icmp eq i64 [[TMP2342]], [[TMP2343]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4347]], label [[COND_TRUE4349:%.*]], label [[COND_FALSE4350:%.*]]
|
|
// SIMD-ONLY0: cond.true4349:
|
|
// SIMD-ONLY0-NEXT: [[TMP2344:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4351:%.*]]
|
|
// SIMD-ONLY0: cond.false4350:
|
|
// SIMD-ONLY0-NEXT: [[TMP2345:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4351]]
|
|
// SIMD-ONLY0: cond.end4351:
|
|
// SIMD-ONLY0-NEXT: [[COND4352:%.*]] = phi i64 [ [[TMP2344]], [[COND_TRUE4349]] ], [ [[TMP2345]], [[COND_FALSE4350]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4352]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2346:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2347:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4353:%.*]] = icmp eq i64 [[TMP2346]], [[TMP2347]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4353]], label [[IF_THEN4355:%.*]], label [[IF_END4356:%.*]]
|
|
// SIMD-ONLY0: if.then4355:
|
|
// SIMD-ONLY0-NEXT: [[TMP2348:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2348]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4356]]
|
|
// SIMD-ONLY0: if.end4356:
|
|
// SIMD-ONLY0-NEXT: [[TMP2349:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2350:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4357:%.*]] = icmp eq i64 [[TMP2349]], [[TMP2350]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4357]], label [[IF_THEN4359:%.*]], label [[IF_END4360:%.*]]
|
|
// SIMD-ONLY0: if.then4359:
|
|
// SIMD-ONLY0-NEXT: [[TMP2351:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2351]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4360]]
|
|
// SIMD-ONLY0: if.end4360:
|
|
// SIMD-ONLY0-NEXT: [[TMP2352:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2353:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4361:%.*]] = icmp sgt i64 [[TMP2352]], [[TMP2353]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4361]], label [[COND_TRUE4363:%.*]], label [[COND_FALSE4364:%.*]]
|
|
// SIMD-ONLY0: cond.true4363:
|
|
// SIMD-ONLY0-NEXT: [[TMP2354:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4365:%.*]]
|
|
// SIMD-ONLY0: cond.false4364:
|
|
// SIMD-ONLY0-NEXT: [[TMP2355:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4365]]
|
|
// SIMD-ONLY0: cond.end4365:
|
|
// SIMD-ONLY0-NEXT: [[COND4366:%.*]] = phi i64 [ [[TMP2354]], [[COND_TRUE4363]] ], [ [[TMP2355]], [[COND_FALSE4364]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4366]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2356:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2357:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4367:%.*]] = icmp slt i64 [[TMP2356]], [[TMP2357]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4367]], label [[COND_TRUE4369:%.*]], label [[COND_FALSE4370:%.*]]
|
|
// SIMD-ONLY0: cond.true4369:
|
|
// SIMD-ONLY0-NEXT: [[TMP2358:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4371:%.*]]
|
|
// SIMD-ONLY0: cond.false4370:
|
|
// SIMD-ONLY0-NEXT: [[TMP2359:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4371]]
|
|
// SIMD-ONLY0: cond.end4371:
|
|
// SIMD-ONLY0-NEXT: [[COND4372:%.*]] = phi i64 [ [[TMP2358]], [[COND_TRUE4369]] ], [ [[TMP2359]], [[COND_FALSE4370]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4372]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2360:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2361:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4373:%.*]] = icmp sgt i64 [[TMP2360]], [[TMP2361]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4373]], label [[COND_TRUE4375:%.*]], label [[COND_FALSE4376:%.*]]
|
|
// SIMD-ONLY0: cond.true4375:
|
|
// SIMD-ONLY0-NEXT: [[TMP2362:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4377:%.*]]
|
|
// SIMD-ONLY0: cond.false4376:
|
|
// SIMD-ONLY0-NEXT: [[TMP2363:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4377]]
|
|
// SIMD-ONLY0: cond.end4377:
|
|
// SIMD-ONLY0-NEXT: [[COND4378:%.*]] = phi i64 [ [[TMP2362]], [[COND_TRUE4375]] ], [ [[TMP2363]], [[COND_FALSE4376]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4378]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2364:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2365:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4379:%.*]] = icmp slt i64 [[TMP2364]], [[TMP2365]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4379]], label [[COND_TRUE4381:%.*]], label [[COND_FALSE4382:%.*]]
|
|
// SIMD-ONLY0: cond.true4381:
|
|
// SIMD-ONLY0-NEXT: [[TMP2366:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4383:%.*]]
|
|
// SIMD-ONLY0: cond.false4382:
|
|
// SIMD-ONLY0-NEXT: [[TMP2367:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4383]]
|
|
// SIMD-ONLY0: cond.end4383:
|
|
// SIMD-ONLY0-NEXT: [[COND4384:%.*]] = phi i64 [ [[TMP2366]], [[COND_TRUE4381]] ], [ [[TMP2367]], [[COND_FALSE4382]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4384]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2368:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2369:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4385:%.*]] = icmp sgt i64 [[TMP2368]], [[TMP2369]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4385]], label [[IF_THEN4387:%.*]], label [[IF_END4388:%.*]]
|
|
// SIMD-ONLY0: if.then4387:
|
|
// SIMD-ONLY0-NEXT: [[TMP2370:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2370]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4388]]
|
|
// SIMD-ONLY0: if.end4388:
|
|
// SIMD-ONLY0-NEXT: [[TMP2371:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2372:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4389:%.*]] = icmp slt i64 [[TMP2371]], [[TMP2372]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4389]], label [[IF_THEN4391:%.*]], label [[IF_END4392:%.*]]
|
|
// SIMD-ONLY0: if.then4391:
|
|
// SIMD-ONLY0-NEXT: [[TMP2373:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2373]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4392]]
|
|
// SIMD-ONLY0: if.end4392:
|
|
// SIMD-ONLY0-NEXT: [[TMP2374:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2375:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4393:%.*]] = icmp sgt i64 [[TMP2374]], [[TMP2375]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4393]], label [[IF_THEN4395:%.*]], label [[IF_END4396:%.*]]
|
|
// SIMD-ONLY0: if.then4395:
|
|
// SIMD-ONLY0-NEXT: [[TMP2376:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2376]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4396]]
|
|
// SIMD-ONLY0: if.end4396:
|
|
// SIMD-ONLY0-NEXT: [[TMP2377:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2378:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4397:%.*]] = icmp slt i64 [[TMP2377]], [[TMP2378]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4397]], label [[IF_THEN4399:%.*]], label [[IF_END4400:%.*]]
|
|
// SIMD-ONLY0: if.then4399:
|
|
// SIMD-ONLY0-NEXT: [[TMP2379:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2379]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4400]]
|
|
// SIMD-ONLY0: if.end4400:
|
|
// SIMD-ONLY0-NEXT: [[TMP2380:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2381:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4401:%.*]] = icmp eq i64 [[TMP2380]], [[TMP2381]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4401]], label [[COND_TRUE4403:%.*]], label [[COND_FALSE4404:%.*]]
|
|
// SIMD-ONLY0: cond.true4403:
|
|
// SIMD-ONLY0-NEXT: [[TMP2382:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4405:%.*]]
|
|
// SIMD-ONLY0: cond.false4404:
|
|
// SIMD-ONLY0-NEXT: [[TMP2383:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4405]]
|
|
// SIMD-ONLY0: cond.end4405:
|
|
// SIMD-ONLY0-NEXT: [[COND4406:%.*]] = phi i64 [ [[TMP2382]], [[COND_TRUE4403]] ], [ [[TMP2383]], [[COND_FALSE4404]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4406]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2384:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2385:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4407:%.*]] = icmp eq i64 [[TMP2384]], [[TMP2385]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4407]], label [[COND_TRUE4409:%.*]], label [[COND_FALSE4410:%.*]]
|
|
// SIMD-ONLY0: cond.true4409:
|
|
// SIMD-ONLY0-NEXT: [[TMP2386:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4411:%.*]]
|
|
// SIMD-ONLY0: cond.false4410:
|
|
// SIMD-ONLY0-NEXT: [[TMP2387:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4411]]
|
|
// SIMD-ONLY0: cond.end4411:
|
|
// SIMD-ONLY0-NEXT: [[COND4412:%.*]] = phi i64 [ [[TMP2386]], [[COND_TRUE4409]] ], [ [[TMP2387]], [[COND_FALSE4410]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4412]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2388:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2389:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4413:%.*]] = icmp eq i64 [[TMP2388]], [[TMP2389]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4413]], label [[IF_THEN4415:%.*]], label [[IF_END4416:%.*]]
|
|
// SIMD-ONLY0: if.then4415:
|
|
// SIMD-ONLY0-NEXT: [[TMP2390:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2390]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4416]]
|
|
// SIMD-ONLY0: if.end4416:
|
|
// SIMD-ONLY0-NEXT: [[TMP2391:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2392:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4417:%.*]] = icmp eq i64 [[TMP2391]], [[TMP2392]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4417]], label [[IF_THEN4419:%.*]], label [[IF_END4420:%.*]]
|
|
// SIMD-ONLY0: if.then4419:
|
|
// SIMD-ONLY0-NEXT: [[TMP2393:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2393]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4420]]
|
|
// SIMD-ONLY0: if.end4420:
|
|
// SIMD-ONLY0-NEXT: [[TMP2394:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2395:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4421:%.*]] = icmp ugt i64 [[TMP2394]], [[TMP2395]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4421]], label [[COND_TRUE4423:%.*]], label [[COND_FALSE4424:%.*]]
|
|
// SIMD-ONLY0: cond.true4423:
|
|
// SIMD-ONLY0-NEXT: [[TMP2396:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4425:%.*]]
|
|
// SIMD-ONLY0: cond.false4424:
|
|
// SIMD-ONLY0-NEXT: [[TMP2397:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4425]]
|
|
// SIMD-ONLY0: cond.end4425:
|
|
// SIMD-ONLY0-NEXT: [[COND4426:%.*]] = phi i64 [ [[TMP2396]], [[COND_TRUE4423]] ], [ [[TMP2397]], [[COND_FALSE4424]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4426]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2398:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2399:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4427:%.*]] = icmp ult i64 [[TMP2398]], [[TMP2399]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4427]], label [[COND_TRUE4429:%.*]], label [[COND_FALSE4430:%.*]]
|
|
// SIMD-ONLY0: cond.true4429:
|
|
// SIMD-ONLY0-NEXT: [[TMP2400:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4431:%.*]]
|
|
// SIMD-ONLY0: cond.false4430:
|
|
// SIMD-ONLY0-NEXT: [[TMP2401:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4431]]
|
|
// SIMD-ONLY0: cond.end4431:
|
|
// SIMD-ONLY0-NEXT: [[COND4432:%.*]] = phi i64 [ [[TMP2400]], [[COND_TRUE4429]] ], [ [[TMP2401]], [[COND_FALSE4430]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4432]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2402:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2403:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4433:%.*]] = icmp ugt i64 [[TMP2402]], [[TMP2403]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4433]], label [[COND_TRUE4435:%.*]], label [[COND_FALSE4436:%.*]]
|
|
// SIMD-ONLY0: cond.true4435:
|
|
// SIMD-ONLY0-NEXT: [[TMP2404:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4437:%.*]]
|
|
// SIMD-ONLY0: cond.false4436:
|
|
// SIMD-ONLY0-NEXT: [[TMP2405:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4437]]
|
|
// SIMD-ONLY0: cond.end4437:
|
|
// SIMD-ONLY0-NEXT: [[COND4438:%.*]] = phi i64 [ [[TMP2404]], [[COND_TRUE4435]] ], [ [[TMP2405]], [[COND_FALSE4436]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4438]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2406:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2407:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4439:%.*]] = icmp ult i64 [[TMP2406]], [[TMP2407]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4439]], label [[COND_TRUE4441:%.*]], label [[COND_FALSE4442:%.*]]
|
|
// SIMD-ONLY0: cond.true4441:
|
|
// SIMD-ONLY0-NEXT: [[TMP2408:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4443:%.*]]
|
|
// SIMD-ONLY0: cond.false4442:
|
|
// SIMD-ONLY0-NEXT: [[TMP2409:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4443]]
|
|
// SIMD-ONLY0: cond.end4443:
|
|
// SIMD-ONLY0-NEXT: [[COND4444:%.*]] = phi i64 [ [[TMP2408]], [[COND_TRUE4441]] ], [ [[TMP2409]], [[COND_FALSE4442]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4444]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2410:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2411:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4445:%.*]] = icmp ugt i64 [[TMP2410]], [[TMP2411]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4445]], label [[IF_THEN4447:%.*]], label [[IF_END4448:%.*]]
|
|
// SIMD-ONLY0: if.then4447:
|
|
// SIMD-ONLY0-NEXT: [[TMP2412:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2412]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4448]]
|
|
// SIMD-ONLY0: if.end4448:
|
|
// SIMD-ONLY0-NEXT: [[TMP2413:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2414:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4449:%.*]] = icmp ult i64 [[TMP2413]], [[TMP2414]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4449]], label [[IF_THEN4451:%.*]], label [[IF_END4452:%.*]]
|
|
// SIMD-ONLY0: if.then4451:
|
|
// SIMD-ONLY0-NEXT: [[TMP2415:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2415]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4452]]
|
|
// SIMD-ONLY0: if.end4452:
|
|
// SIMD-ONLY0-NEXT: [[TMP2416:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2417:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4453:%.*]] = icmp ugt i64 [[TMP2416]], [[TMP2417]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4453]], label [[IF_THEN4455:%.*]], label [[IF_END4456:%.*]]
|
|
// SIMD-ONLY0: if.then4455:
|
|
// SIMD-ONLY0-NEXT: [[TMP2418:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2418]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4456]]
|
|
// SIMD-ONLY0: if.end4456:
|
|
// SIMD-ONLY0-NEXT: [[TMP2419:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2420:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4457:%.*]] = icmp ult i64 [[TMP2419]], [[TMP2420]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4457]], label [[IF_THEN4459:%.*]], label [[IF_END4460:%.*]]
|
|
// SIMD-ONLY0: if.then4459:
|
|
// SIMD-ONLY0-NEXT: [[TMP2421:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2421]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4460]]
|
|
// SIMD-ONLY0: if.end4460:
|
|
// SIMD-ONLY0-NEXT: [[TMP2422:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2423:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4461:%.*]] = icmp eq i64 [[TMP2422]], [[TMP2423]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4461]], label [[COND_TRUE4463:%.*]], label [[COND_FALSE4464:%.*]]
|
|
// SIMD-ONLY0: cond.true4463:
|
|
// SIMD-ONLY0-NEXT: [[TMP2424:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4465:%.*]]
|
|
// SIMD-ONLY0: cond.false4464:
|
|
// SIMD-ONLY0-NEXT: [[TMP2425:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4465]]
|
|
// SIMD-ONLY0: cond.end4465:
|
|
// SIMD-ONLY0-NEXT: [[COND4466:%.*]] = phi i64 [ [[TMP2424]], [[COND_TRUE4463]] ], [ [[TMP2425]], [[COND_FALSE4464]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4466]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2426:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2427:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4467:%.*]] = icmp eq i64 [[TMP2426]], [[TMP2427]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4467]], label [[COND_TRUE4469:%.*]], label [[COND_FALSE4470:%.*]]
|
|
// SIMD-ONLY0: cond.true4469:
|
|
// SIMD-ONLY0-NEXT: [[TMP2428:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4471:%.*]]
|
|
// SIMD-ONLY0: cond.false4470:
|
|
// SIMD-ONLY0-NEXT: [[TMP2429:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4471]]
|
|
// SIMD-ONLY0: cond.end4471:
|
|
// SIMD-ONLY0-NEXT: [[COND4472:%.*]] = phi i64 [ [[TMP2428]], [[COND_TRUE4469]] ], [ [[TMP2429]], [[COND_FALSE4470]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4472]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2430:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2431:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4473:%.*]] = icmp eq i64 [[TMP2430]], [[TMP2431]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4473]], label [[IF_THEN4475:%.*]], label [[IF_END4476:%.*]]
|
|
// SIMD-ONLY0: if.then4475:
|
|
// SIMD-ONLY0-NEXT: [[TMP2432:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2432]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4476]]
|
|
// SIMD-ONLY0: if.end4476:
|
|
// SIMD-ONLY0-NEXT: [[TMP2433:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2434:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4477:%.*]] = icmp eq i64 [[TMP2433]], [[TMP2434]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4477]], label [[IF_THEN4479:%.*]], label [[IF_END4480:%.*]]
|
|
// SIMD-ONLY0: if.then4479:
|
|
// SIMD-ONLY0-NEXT: [[TMP2435:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2435]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4480]]
|
|
// SIMD-ONLY0: if.end4480:
|
|
// SIMD-ONLY0-NEXT: [[TMP2436:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2437:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4481:%.*]] = icmp sgt i64 [[TMP2436]], [[TMP2437]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4481]], label [[COND_TRUE4483:%.*]], label [[COND_FALSE4484:%.*]]
|
|
// SIMD-ONLY0: cond.true4483:
|
|
// SIMD-ONLY0-NEXT: [[TMP2438:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4485:%.*]]
|
|
// SIMD-ONLY0: cond.false4484:
|
|
// SIMD-ONLY0-NEXT: [[TMP2439:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4485]]
|
|
// SIMD-ONLY0: cond.end4485:
|
|
// SIMD-ONLY0-NEXT: [[COND4486:%.*]] = phi i64 [ [[TMP2438]], [[COND_TRUE4483]] ], [ [[TMP2439]], [[COND_FALSE4484]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4486]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2440:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2441:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4487:%.*]] = icmp slt i64 [[TMP2440]], [[TMP2441]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4487]], label [[COND_TRUE4489:%.*]], label [[COND_FALSE4490:%.*]]
|
|
// SIMD-ONLY0: cond.true4489:
|
|
// SIMD-ONLY0-NEXT: [[TMP2442:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4491:%.*]]
|
|
// SIMD-ONLY0: cond.false4490:
|
|
// SIMD-ONLY0-NEXT: [[TMP2443:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4491]]
|
|
// SIMD-ONLY0: cond.end4491:
|
|
// SIMD-ONLY0-NEXT: [[COND4492:%.*]] = phi i64 [ [[TMP2442]], [[COND_TRUE4489]] ], [ [[TMP2443]], [[COND_FALSE4490]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4492]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2444:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2445:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4493:%.*]] = icmp sgt i64 [[TMP2444]], [[TMP2445]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4493]], label [[COND_TRUE4495:%.*]], label [[COND_FALSE4496:%.*]]
|
|
// SIMD-ONLY0: cond.true4495:
|
|
// SIMD-ONLY0-NEXT: [[TMP2446:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4497:%.*]]
|
|
// SIMD-ONLY0: cond.false4496:
|
|
// SIMD-ONLY0-NEXT: [[TMP2447:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4497]]
|
|
// SIMD-ONLY0: cond.end4497:
|
|
// SIMD-ONLY0-NEXT: [[COND4498:%.*]] = phi i64 [ [[TMP2446]], [[COND_TRUE4495]] ], [ [[TMP2447]], [[COND_FALSE4496]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4498]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2448:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2449:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4499:%.*]] = icmp slt i64 [[TMP2448]], [[TMP2449]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4499]], label [[COND_TRUE4501:%.*]], label [[COND_FALSE4502:%.*]]
|
|
// SIMD-ONLY0: cond.true4501:
|
|
// SIMD-ONLY0-NEXT: [[TMP2450:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4503:%.*]]
|
|
// SIMD-ONLY0: cond.false4502:
|
|
// SIMD-ONLY0-NEXT: [[TMP2451:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4503]]
|
|
// SIMD-ONLY0: cond.end4503:
|
|
// SIMD-ONLY0-NEXT: [[COND4504:%.*]] = phi i64 [ [[TMP2450]], [[COND_TRUE4501]] ], [ [[TMP2451]], [[COND_FALSE4502]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4504]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2452:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2453:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4505:%.*]] = icmp sgt i64 [[TMP2452]], [[TMP2453]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4505]], label [[IF_THEN4507:%.*]], label [[IF_END4508:%.*]]
|
|
// SIMD-ONLY0: if.then4507:
|
|
// SIMD-ONLY0-NEXT: [[TMP2454:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2454]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4508]]
|
|
// SIMD-ONLY0: if.end4508:
|
|
// SIMD-ONLY0-NEXT: [[TMP2455:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2456:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4509:%.*]] = icmp slt i64 [[TMP2455]], [[TMP2456]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4509]], label [[IF_THEN4511:%.*]], label [[IF_END4512:%.*]]
|
|
// SIMD-ONLY0: if.then4511:
|
|
// SIMD-ONLY0-NEXT: [[TMP2457:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2457]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4512]]
|
|
// SIMD-ONLY0: if.end4512:
|
|
// SIMD-ONLY0-NEXT: [[TMP2458:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2459:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4513:%.*]] = icmp sgt i64 [[TMP2458]], [[TMP2459]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4513]], label [[IF_THEN4515:%.*]], label [[IF_END4516:%.*]]
|
|
// SIMD-ONLY0: if.then4515:
|
|
// SIMD-ONLY0-NEXT: [[TMP2460:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2460]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4516]]
|
|
// SIMD-ONLY0: if.end4516:
|
|
// SIMD-ONLY0-NEXT: [[TMP2461:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2462:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4517:%.*]] = icmp slt i64 [[TMP2461]], [[TMP2462]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4517]], label [[IF_THEN4519:%.*]], label [[IF_END4520:%.*]]
|
|
// SIMD-ONLY0: if.then4519:
|
|
// SIMD-ONLY0-NEXT: [[TMP2463:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2463]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4520]]
|
|
// SIMD-ONLY0: if.end4520:
|
|
// SIMD-ONLY0-NEXT: [[TMP2464:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2465:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4521:%.*]] = icmp eq i64 [[TMP2464]], [[TMP2465]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4521]], label [[COND_TRUE4523:%.*]], label [[COND_FALSE4524:%.*]]
|
|
// SIMD-ONLY0: cond.true4523:
|
|
// SIMD-ONLY0-NEXT: [[TMP2466:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4525:%.*]]
|
|
// SIMD-ONLY0: cond.false4524:
|
|
// SIMD-ONLY0-NEXT: [[TMP2467:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4525]]
|
|
// SIMD-ONLY0: cond.end4525:
|
|
// SIMD-ONLY0-NEXT: [[COND4526:%.*]] = phi i64 [ [[TMP2466]], [[COND_TRUE4523]] ], [ [[TMP2467]], [[COND_FALSE4524]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4526]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2468:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2469:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4527:%.*]] = icmp eq i64 [[TMP2468]], [[TMP2469]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4527]], label [[COND_TRUE4529:%.*]], label [[COND_FALSE4530:%.*]]
|
|
// SIMD-ONLY0: cond.true4529:
|
|
// SIMD-ONLY0-NEXT: [[TMP2470:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4531:%.*]]
|
|
// SIMD-ONLY0: cond.false4530:
|
|
// SIMD-ONLY0-NEXT: [[TMP2471:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4531]]
|
|
// SIMD-ONLY0: cond.end4531:
|
|
// SIMD-ONLY0-NEXT: [[COND4532:%.*]] = phi i64 [ [[TMP2470]], [[COND_TRUE4529]] ], [ [[TMP2471]], [[COND_FALSE4530]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4532]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2472:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2473:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4533:%.*]] = icmp eq i64 [[TMP2472]], [[TMP2473]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4533]], label [[IF_THEN4535:%.*]], label [[IF_END4536:%.*]]
|
|
// SIMD-ONLY0: if.then4535:
|
|
// SIMD-ONLY0-NEXT: [[TMP2474:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2474]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4536]]
|
|
// SIMD-ONLY0: if.end4536:
|
|
// SIMD-ONLY0-NEXT: [[TMP2475:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2476:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4537:%.*]] = icmp eq i64 [[TMP2475]], [[TMP2476]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4537]], label [[IF_THEN4539:%.*]], label [[IF_END4540:%.*]]
|
|
// SIMD-ONLY0: if.then4539:
|
|
// SIMD-ONLY0-NEXT: [[TMP2477:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2477]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4540]]
|
|
// SIMD-ONLY0: if.end4540:
|
|
// SIMD-ONLY0-NEXT: [[TMP2478:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2479:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4541:%.*]] = icmp ugt i64 [[TMP2478]], [[TMP2479]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4541]], label [[COND_TRUE4543:%.*]], label [[COND_FALSE4544:%.*]]
|
|
// SIMD-ONLY0: cond.true4543:
|
|
// SIMD-ONLY0-NEXT: [[TMP2480:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4545:%.*]]
|
|
// SIMD-ONLY0: cond.false4544:
|
|
// SIMD-ONLY0-NEXT: [[TMP2481:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4545]]
|
|
// SIMD-ONLY0: cond.end4545:
|
|
// SIMD-ONLY0-NEXT: [[COND4546:%.*]] = phi i64 [ [[TMP2480]], [[COND_TRUE4543]] ], [ [[TMP2481]], [[COND_FALSE4544]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4546]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2482:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2483:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4547:%.*]] = icmp ult i64 [[TMP2482]], [[TMP2483]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4547]], label [[COND_TRUE4549:%.*]], label [[COND_FALSE4550:%.*]]
|
|
// SIMD-ONLY0: cond.true4549:
|
|
// SIMD-ONLY0-NEXT: [[TMP2484:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4551:%.*]]
|
|
// SIMD-ONLY0: cond.false4550:
|
|
// SIMD-ONLY0-NEXT: [[TMP2485:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4551]]
|
|
// SIMD-ONLY0: cond.end4551:
|
|
// SIMD-ONLY0-NEXT: [[COND4552:%.*]] = phi i64 [ [[TMP2484]], [[COND_TRUE4549]] ], [ [[TMP2485]], [[COND_FALSE4550]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4552]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2486:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2487:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4553:%.*]] = icmp ugt i64 [[TMP2486]], [[TMP2487]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4553]], label [[COND_TRUE4555:%.*]], label [[COND_FALSE4556:%.*]]
|
|
// SIMD-ONLY0: cond.true4555:
|
|
// SIMD-ONLY0-NEXT: [[TMP2488:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4557:%.*]]
|
|
// SIMD-ONLY0: cond.false4556:
|
|
// SIMD-ONLY0-NEXT: [[TMP2489:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4557]]
|
|
// SIMD-ONLY0: cond.end4557:
|
|
// SIMD-ONLY0-NEXT: [[COND4558:%.*]] = phi i64 [ [[TMP2488]], [[COND_TRUE4555]] ], [ [[TMP2489]], [[COND_FALSE4556]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4558]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2490:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2491:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4559:%.*]] = icmp ult i64 [[TMP2490]], [[TMP2491]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4559]], label [[COND_TRUE4561:%.*]], label [[COND_FALSE4562:%.*]]
|
|
// SIMD-ONLY0: cond.true4561:
|
|
// SIMD-ONLY0-NEXT: [[TMP2492:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4563:%.*]]
|
|
// SIMD-ONLY0: cond.false4562:
|
|
// SIMD-ONLY0-NEXT: [[TMP2493:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4563]]
|
|
// SIMD-ONLY0: cond.end4563:
|
|
// SIMD-ONLY0-NEXT: [[COND4564:%.*]] = phi i64 [ [[TMP2492]], [[COND_TRUE4561]] ], [ [[TMP2493]], [[COND_FALSE4562]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4564]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2494:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2495:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4565:%.*]] = icmp ugt i64 [[TMP2494]], [[TMP2495]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4565]], label [[IF_THEN4567:%.*]], label [[IF_END4568:%.*]]
|
|
// SIMD-ONLY0: if.then4567:
|
|
// SIMD-ONLY0-NEXT: [[TMP2496:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2496]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4568]]
|
|
// SIMD-ONLY0: if.end4568:
|
|
// SIMD-ONLY0-NEXT: [[TMP2497:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2498:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4569:%.*]] = icmp ult i64 [[TMP2497]], [[TMP2498]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4569]], label [[IF_THEN4571:%.*]], label [[IF_END4572:%.*]]
|
|
// SIMD-ONLY0: if.then4571:
|
|
// SIMD-ONLY0-NEXT: [[TMP2499:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2499]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4572]]
|
|
// SIMD-ONLY0: if.end4572:
|
|
// SIMD-ONLY0-NEXT: [[TMP2500:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2501:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4573:%.*]] = icmp ugt i64 [[TMP2500]], [[TMP2501]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4573]], label [[IF_THEN4575:%.*]], label [[IF_END4576:%.*]]
|
|
// SIMD-ONLY0: if.then4575:
|
|
// SIMD-ONLY0-NEXT: [[TMP2502:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2502]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4576]]
|
|
// SIMD-ONLY0: if.end4576:
|
|
// SIMD-ONLY0-NEXT: [[TMP2503:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2504:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4577:%.*]] = icmp ult i64 [[TMP2503]], [[TMP2504]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4577]], label [[IF_THEN4579:%.*]], label [[IF_END4580:%.*]]
|
|
// SIMD-ONLY0: if.then4579:
|
|
// SIMD-ONLY0-NEXT: [[TMP2505:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2505]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4580]]
|
|
// SIMD-ONLY0: if.end4580:
|
|
// SIMD-ONLY0-NEXT: [[TMP2506:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2507:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4581:%.*]] = icmp eq i64 [[TMP2506]], [[TMP2507]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4581]], label [[COND_TRUE4583:%.*]], label [[COND_FALSE4584:%.*]]
|
|
// SIMD-ONLY0: cond.true4583:
|
|
// SIMD-ONLY0-NEXT: [[TMP2508:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4585:%.*]]
|
|
// SIMD-ONLY0: cond.false4584:
|
|
// SIMD-ONLY0-NEXT: [[TMP2509:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4585]]
|
|
// SIMD-ONLY0: cond.end4585:
|
|
// SIMD-ONLY0-NEXT: [[COND4586:%.*]] = phi i64 [ [[TMP2508]], [[COND_TRUE4583]] ], [ [[TMP2509]], [[COND_FALSE4584]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4586]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2510:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2511:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4587:%.*]] = icmp eq i64 [[TMP2510]], [[TMP2511]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4587]], label [[COND_TRUE4589:%.*]], label [[COND_FALSE4590:%.*]]
|
|
// SIMD-ONLY0: cond.true4589:
|
|
// SIMD-ONLY0-NEXT: [[TMP2512:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4591:%.*]]
|
|
// SIMD-ONLY0: cond.false4590:
|
|
// SIMD-ONLY0-NEXT: [[TMP2513:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4591]]
|
|
// SIMD-ONLY0: cond.end4591:
|
|
// SIMD-ONLY0-NEXT: [[COND4592:%.*]] = phi i64 [ [[TMP2512]], [[COND_TRUE4589]] ], [ [[TMP2513]], [[COND_FALSE4590]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND4592]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2514:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2515:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4593:%.*]] = icmp eq i64 [[TMP2514]], [[TMP2515]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4593]], label [[IF_THEN4595:%.*]], label [[IF_END4596:%.*]]
|
|
// SIMD-ONLY0: if.then4595:
|
|
// SIMD-ONLY0-NEXT: [[TMP2516:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2516]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4596]]
|
|
// SIMD-ONLY0: if.end4596:
|
|
// SIMD-ONLY0-NEXT: [[TMP2517:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2518:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4597:%.*]] = icmp eq i64 [[TMP2517]], [[TMP2518]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4597]], label [[IF_THEN4599:%.*]], label [[IF_END4600:%.*]]
|
|
// SIMD-ONLY0: if.then4599:
|
|
// SIMD-ONLY0-NEXT: [[TMP2519:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2519]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4600]]
|
|
// SIMD-ONLY0: if.end4600:
|
|
// SIMD-ONLY0-NEXT: [[TMP2520:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2521:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4601:%.*]] = fcmp ogt float [[TMP2520]], [[TMP2521]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4601]], label [[COND_TRUE4603:%.*]], label [[COND_FALSE4604:%.*]]
|
|
// SIMD-ONLY0: cond.true4603:
|
|
// SIMD-ONLY0-NEXT: [[TMP2522:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4605:%.*]]
|
|
// SIMD-ONLY0: cond.false4604:
|
|
// SIMD-ONLY0-NEXT: [[TMP2523:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4605]]
|
|
// SIMD-ONLY0: cond.end4605:
|
|
// SIMD-ONLY0-NEXT: [[COND4606:%.*]] = phi float [ [[TMP2522]], [[COND_TRUE4603]] ], [ [[TMP2523]], [[COND_FALSE4604]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4606]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2524:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2525:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4607:%.*]] = fcmp olt float [[TMP2524]], [[TMP2525]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4607]], label [[COND_TRUE4609:%.*]], label [[COND_FALSE4610:%.*]]
|
|
// SIMD-ONLY0: cond.true4609:
|
|
// SIMD-ONLY0-NEXT: [[TMP2526:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4611:%.*]]
|
|
// SIMD-ONLY0: cond.false4610:
|
|
// SIMD-ONLY0-NEXT: [[TMP2527:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4611]]
|
|
// SIMD-ONLY0: cond.end4611:
|
|
// SIMD-ONLY0-NEXT: [[COND4612:%.*]] = phi float [ [[TMP2526]], [[COND_TRUE4609]] ], [ [[TMP2527]], [[COND_FALSE4610]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4612]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2528:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2529:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4613:%.*]] = fcmp ogt float [[TMP2528]], [[TMP2529]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4613]], label [[COND_TRUE4615:%.*]], label [[COND_FALSE4616:%.*]]
|
|
// SIMD-ONLY0: cond.true4615:
|
|
// SIMD-ONLY0-NEXT: [[TMP2530:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4617:%.*]]
|
|
// SIMD-ONLY0: cond.false4616:
|
|
// SIMD-ONLY0-NEXT: [[TMP2531:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4617]]
|
|
// SIMD-ONLY0: cond.end4617:
|
|
// SIMD-ONLY0-NEXT: [[COND4618:%.*]] = phi float [ [[TMP2530]], [[COND_TRUE4615]] ], [ [[TMP2531]], [[COND_FALSE4616]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4618]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2532:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2533:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4619:%.*]] = fcmp olt float [[TMP2532]], [[TMP2533]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4619]], label [[COND_TRUE4621:%.*]], label [[COND_FALSE4622:%.*]]
|
|
// SIMD-ONLY0: cond.true4621:
|
|
// SIMD-ONLY0-NEXT: [[TMP2534:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4623:%.*]]
|
|
// SIMD-ONLY0: cond.false4622:
|
|
// SIMD-ONLY0-NEXT: [[TMP2535:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4623]]
|
|
// SIMD-ONLY0: cond.end4623:
|
|
// SIMD-ONLY0-NEXT: [[COND4624:%.*]] = phi float [ [[TMP2534]], [[COND_TRUE4621]] ], [ [[TMP2535]], [[COND_FALSE4622]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4624]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2536:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2537:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4625:%.*]] = fcmp ogt float [[TMP2536]], [[TMP2537]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4625]], label [[IF_THEN4627:%.*]], label [[IF_END4628:%.*]]
|
|
// SIMD-ONLY0: if.then4627:
|
|
// SIMD-ONLY0-NEXT: [[TMP2538:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2538]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4628]]
|
|
// SIMD-ONLY0: if.end4628:
|
|
// SIMD-ONLY0-NEXT: [[TMP2539:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2540:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4629:%.*]] = fcmp olt float [[TMP2539]], [[TMP2540]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4629]], label [[IF_THEN4631:%.*]], label [[IF_END4632:%.*]]
|
|
// SIMD-ONLY0: if.then4631:
|
|
// SIMD-ONLY0-NEXT: [[TMP2541:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2541]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4632]]
|
|
// SIMD-ONLY0: if.end4632:
|
|
// SIMD-ONLY0-NEXT: [[TMP2542:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2543:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4633:%.*]] = fcmp ogt float [[TMP2542]], [[TMP2543]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4633]], label [[IF_THEN4635:%.*]], label [[IF_END4636:%.*]]
|
|
// SIMD-ONLY0: if.then4635:
|
|
// SIMD-ONLY0-NEXT: [[TMP2544:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2544]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4636]]
|
|
// SIMD-ONLY0: if.end4636:
|
|
// SIMD-ONLY0-NEXT: [[TMP2545:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2546:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4637:%.*]] = fcmp olt float [[TMP2545]], [[TMP2546]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4637]], label [[IF_THEN4639:%.*]], label [[IF_END4640:%.*]]
|
|
// SIMD-ONLY0: if.then4639:
|
|
// SIMD-ONLY0-NEXT: [[TMP2547:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2547]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4640]]
|
|
// SIMD-ONLY0: if.end4640:
|
|
// SIMD-ONLY0-NEXT: [[TMP2548:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2549:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4641:%.*]] = fcmp ogt float [[TMP2548]], [[TMP2549]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4641]], label [[COND_TRUE4643:%.*]], label [[COND_FALSE4644:%.*]]
|
|
// SIMD-ONLY0: cond.true4643:
|
|
// SIMD-ONLY0-NEXT: [[TMP2550:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4645:%.*]]
|
|
// SIMD-ONLY0: cond.false4644:
|
|
// SIMD-ONLY0-NEXT: [[TMP2551:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4645]]
|
|
// SIMD-ONLY0: cond.end4645:
|
|
// SIMD-ONLY0-NEXT: [[COND4646:%.*]] = phi float [ [[TMP2550]], [[COND_TRUE4643]] ], [ [[TMP2551]], [[COND_FALSE4644]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4646]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2552:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2553:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4647:%.*]] = fcmp olt float [[TMP2552]], [[TMP2553]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4647]], label [[COND_TRUE4649:%.*]], label [[COND_FALSE4650:%.*]]
|
|
// SIMD-ONLY0: cond.true4649:
|
|
// SIMD-ONLY0-NEXT: [[TMP2554:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4651:%.*]]
|
|
// SIMD-ONLY0: cond.false4650:
|
|
// SIMD-ONLY0-NEXT: [[TMP2555:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4651]]
|
|
// SIMD-ONLY0: cond.end4651:
|
|
// SIMD-ONLY0-NEXT: [[COND4652:%.*]] = phi float [ [[TMP2554]], [[COND_TRUE4649]] ], [ [[TMP2555]], [[COND_FALSE4650]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4652]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2556:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2557:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4653:%.*]] = fcmp ogt float [[TMP2556]], [[TMP2557]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4653]], label [[COND_TRUE4655:%.*]], label [[COND_FALSE4656:%.*]]
|
|
// SIMD-ONLY0: cond.true4655:
|
|
// SIMD-ONLY0-NEXT: [[TMP2558:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4657:%.*]]
|
|
// SIMD-ONLY0: cond.false4656:
|
|
// SIMD-ONLY0-NEXT: [[TMP2559:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4657]]
|
|
// SIMD-ONLY0: cond.end4657:
|
|
// SIMD-ONLY0-NEXT: [[COND4658:%.*]] = phi float [ [[TMP2558]], [[COND_TRUE4655]] ], [ [[TMP2559]], [[COND_FALSE4656]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4658]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2560:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2561:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4659:%.*]] = fcmp olt float [[TMP2560]], [[TMP2561]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4659]], label [[COND_TRUE4661:%.*]], label [[COND_FALSE4662:%.*]]
|
|
// SIMD-ONLY0: cond.true4661:
|
|
// SIMD-ONLY0-NEXT: [[TMP2562:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4663:%.*]]
|
|
// SIMD-ONLY0: cond.false4662:
|
|
// SIMD-ONLY0-NEXT: [[TMP2563:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4663]]
|
|
// SIMD-ONLY0: cond.end4663:
|
|
// SIMD-ONLY0-NEXT: [[COND4664:%.*]] = phi float [ [[TMP2562]], [[COND_TRUE4661]] ], [ [[TMP2563]], [[COND_FALSE4662]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4664]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2564:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2565:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4665:%.*]] = fcmp ogt float [[TMP2564]], [[TMP2565]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4665]], label [[IF_THEN4667:%.*]], label [[IF_END4668:%.*]]
|
|
// SIMD-ONLY0: if.then4667:
|
|
// SIMD-ONLY0-NEXT: [[TMP2566:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2566]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4668]]
|
|
// SIMD-ONLY0: if.end4668:
|
|
// SIMD-ONLY0-NEXT: [[TMP2567:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2568:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4669:%.*]] = fcmp olt float [[TMP2567]], [[TMP2568]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4669]], label [[IF_THEN4671:%.*]], label [[IF_END4672:%.*]]
|
|
// SIMD-ONLY0: if.then4671:
|
|
// SIMD-ONLY0-NEXT: [[TMP2569:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2569]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4672]]
|
|
// SIMD-ONLY0: if.end4672:
|
|
// SIMD-ONLY0-NEXT: [[TMP2570:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2571:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4673:%.*]] = fcmp ogt float [[TMP2570]], [[TMP2571]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4673]], label [[IF_THEN4675:%.*]], label [[IF_END4676:%.*]]
|
|
// SIMD-ONLY0: if.then4675:
|
|
// SIMD-ONLY0-NEXT: [[TMP2572:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2572]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4676]]
|
|
// SIMD-ONLY0: if.end4676:
|
|
// SIMD-ONLY0-NEXT: [[TMP2573:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2574:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4677:%.*]] = fcmp olt float [[TMP2573]], [[TMP2574]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4677]], label [[IF_THEN4679:%.*]], label [[IF_END4680:%.*]]
|
|
// SIMD-ONLY0: if.then4679:
|
|
// SIMD-ONLY0-NEXT: [[TMP2575:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2575]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4680]]
|
|
// SIMD-ONLY0: if.end4680:
|
|
// SIMD-ONLY0-NEXT: [[TMP2576:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2577:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4681:%.*]] = fcmp ogt float [[TMP2576]], [[TMP2577]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4681]], label [[COND_TRUE4683:%.*]], label [[COND_FALSE4684:%.*]]
|
|
// SIMD-ONLY0: cond.true4683:
|
|
// SIMD-ONLY0-NEXT: [[TMP2578:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4685:%.*]]
|
|
// SIMD-ONLY0: cond.false4684:
|
|
// SIMD-ONLY0-NEXT: [[TMP2579:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4685]]
|
|
// SIMD-ONLY0: cond.end4685:
|
|
// SIMD-ONLY0-NEXT: [[COND4686:%.*]] = phi float [ [[TMP2578]], [[COND_TRUE4683]] ], [ [[TMP2579]], [[COND_FALSE4684]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4686]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2580:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2581:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4687:%.*]] = fcmp olt float [[TMP2580]], [[TMP2581]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4687]], label [[COND_TRUE4689:%.*]], label [[COND_FALSE4690:%.*]]
|
|
// SIMD-ONLY0: cond.true4689:
|
|
// SIMD-ONLY0-NEXT: [[TMP2582:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4691:%.*]]
|
|
// SIMD-ONLY0: cond.false4690:
|
|
// SIMD-ONLY0-NEXT: [[TMP2583:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4691]]
|
|
// SIMD-ONLY0: cond.end4691:
|
|
// SIMD-ONLY0-NEXT: [[COND4692:%.*]] = phi float [ [[TMP2582]], [[COND_TRUE4689]] ], [ [[TMP2583]], [[COND_FALSE4690]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4692]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2584:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2585:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4693:%.*]] = fcmp ogt float [[TMP2584]], [[TMP2585]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4693]], label [[COND_TRUE4695:%.*]], label [[COND_FALSE4696:%.*]]
|
|
// SIMD-ONLY0: cond.true4695:
|
|
// SIMD-ONLY0-NEXT: [[TMP2586:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4697:%.*]]
|
|
// SIMD-ONLY0: cond.false4696:
|
|
// SIMD-ONLY0-NEXT: [[TMP2587:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4697]]
|
|
// SIMD-ONLY0: cond.end4697:
|
|
// SIMD-ONLY0-NEXT: [[COND4698:%.*]] = phi float [ [[TMP2586]], [[COND_TRUE4695]] ], [ [[TMP2587]], [[COND_FALSE4696]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4698]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2588:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2589:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4699:%.*]] = fcmp olt float [[TMP2588]], [[TMP2589]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4699]], label [[COND_TRUE4701:%.*]], label [[COND_FALSE4702:%.*]]
|
|
// SIMD-ONLY0: cond.true4701:
|
|
// SIMD-ONLY0-NEXT: [[TMP2590:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4703:%.*]]
|
|
// SIMD-ONLY0: cond.false4702:
|
|
// SIMD-ONLY0-NEXT: [[TMP2591:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4703]]
|
|
// SIMD-ONLY0: cond.end4703:
|
|
// SIMD-ONLY0-NEXT: [[COND4704:%.*]] = phi float [ [[TMP2590]], [[COND_TRUE4701]] ], [ [[TMP2591]], [[COND_FALSE4702]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4704]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2592:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2593:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4705:%.*]] = fcmp ogt float [[TMP2592]], [[TMP2593]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4705]], label [[IF_THEN4707:%.*]], label [[IF_END4708:%.*]]
|
|
// SIMD-ONLY0: if.then4707:
|
|
// SIMD-ONLY0-NEXT: [[TMP2594:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2594]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4708]]
|
|
// SIMD-ONLY0: if.end4708:
|
|
// SIMD-ONLY0-NEXT: [[TMP2595:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2596:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4709:%.*]] = fcmp olt float [[TMP2595]], [[TMP2596]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4709]], label [[IF_THEN4711:%.*]], label [[IF_END4712:%.*]]
|
|
// SIMD-ONLY0: if.then4711:
|
|
// SIMD-ONLY0-NEXT: [[TMP2597:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2597]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4712]]
|
|
// SIMD-ONLY0: if.end4712:
|
|
// SIMD-ONLY0-NEXT: [[TMP2598:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2599:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4713:%.*]] = fcmp ogt float [[TMP2598]], [[TMP2599]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4713]], label [[IF_THEN4715:%.*]], label [[IF_END4716:%.*]]
|
|
// SIMD-ONLY0: if.then4715:
|
|
// SIMD-ONLY0-NEXT: [[TMP2600:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2600]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4716]]
|
|
// SIMD-ONLY0: if.end4716:
|
|
// SIMD-ONLY0-NEXT: [[TMP2601:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2602:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4717:%.*]] = fcmp olt float [[TMP2601]], [[TMP2602]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4717]], label [[IF_THEN4719:%.*]], label [[IF_END4720:%.*]]
|
|
// SIMD-ONLY0: if.then4719:
|
|
// SIMD-ONLY0-NEXT: [[TMP2603:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2603]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4720]]
|
|
// SIMD-ONLY0: if.end4720:
|
|
// SIMD-ONLY0-NEXT: [[TMP2604:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2605:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4721:%.*]] = fcmp ogt float [[TMP2604]], [[TMP2605]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4721]], label [[COND_TRUE4723:%.*]], label [[COND_FALSE4724:%.*]]
|
|
// SIMD-ONLY0: cond.true4723:
|
|
// SIMD-ONLY0-NEXT: [[TMP2606:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4725:%.*]]
|
|
// SIMD-ONLY0: cond.false4724:
|
|
// SIMD-ONLY0-NEXT: [[TMP2607:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4725]]
|
|
// SIMD-ONLY0: cond.end4725:
|
|
// SIMD-ONLY0-NEXT: [[COND4726:%.*]] = phi float [ [[TMP2606]], [[COND_TRUE4723]] ], [ [[TMP2607]], [[COND_FALSE4724]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4726]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2608:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2609:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4727:%.*]] = fcmp olt float [[TMP2608]], [[TMP2609]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4727]], label [[COND_TRUE4729:%.*]], label [[COND_FALSE4730:%.*]]
|
|
// SIMD-ONLY0: cond.true4729:
|
|
// SIMD-ONLY0-NEXT: [[TMP2610:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4731:%.*]]
|
|
// SIMD-ONLY0: cond.false4730:
|
|
// SIMD-ONLY0-NEXT: [[TMP2611:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4731]]
|
|
// SIMD-ONLY0: cond.end4731:
|
|
// SIMD-ONLY0-NEXT: [[COND4732:%.*]] = phi float [ [[TMP2610]], [[COND_TRUE4729]] ], [ [[TMP2611]], [[COND_FALSE4730]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4732]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2612:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2613:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4733:%.*]] = fcmp ogt float [[TMP2612]], [[TMP2613]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4733]], label [[COND_TRUE4735:%.*]], label [[COND_FALSE4736:%.*]]
|
|
// SIMD-ONLY0: cond.true4735:
|
|
// SIMD-ONLY0-NEXT: [[TMP2614:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4737:%.*]]
|
|
// SIMD-ONLY0: cond.false4736:
|
|
// SIMD-ONLY0-NEXT: [[TMP2615:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4737]]
|
|
// SIMD-ONLY0: cond.end4737:
|
|
// SIMD-ONLY0-NEXT: [[COND4738:%.*]] = phi float [ [[TMP2614]], [[COND_TRUE4735]] ], [ [[TMP2615]], [[COND_FALSE4736]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4738]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2616:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2617:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4739:%.*]] = fcmp olt float [[TMP2616]], [[TMP2617]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4739]], label [[COND_TRUE4741:%.*]], label [[COND_FALSE4742:%.*]]
|
|
// SIMD-ONLY0: cond.true4741:
|
|
// SIMD-ONLY0-NEXT: [[TMP2618:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4743:%.*]]
|
|
// SIMD-ONLY0: cond.false4742:
|
|
// SIMD-ONLY0-NEXT: [[TMP2619:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4743]]
|
|
// SIMD-ONLY0: cond.end4743:
|
|
// SIMD-ONLY0-NEXT: [[COND4744:%.*]] = phi float [ [[TMP2618]], [[COND_TRUE4741]] ], [ [[TMP2619]], [[COND_FALSE4742]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4744]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2620:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2621:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4745:%.*]] = fcmp ogt float [[TMP2620]], [[TMP2621]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4745]], label [[IF_THEN4747:%.*]], label [[IF_END4748:%.*]]
|
|
// SIMD-ONLY0: if.then4747:
|
|
// SIMD-ONLY0-NEXT: [[TMP2622:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2622]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4748]]
|
|
// SIMD-ONLY0: if.end4748:
|
|
// SIMD-ONLY0-NEXT: [[TMP2623:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2624:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4749:%.*]] = fcmp olt float [[TMP2623]], [[TMP2624]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4749]], label [[IF_THEN4751:%.*]], label [[IF_END4752:%.*]]
|
|
// SIMD-ONLY0: if.then4751:
|
|
// SIMD-ONLY0-NEXT: [[TMP2625:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2625]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4752]]
|
|
// SIMD-ONLY0: if.end4752:
|
|
// SIMD-ONLY0-NEXT: [[TMP2626:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2627:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4753:%.*]] = fcmp ogt float [[TMP2626]], [[TMP2627]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4753]], label [[IF_THEN4755:%.*]], label [[IF_END4756:%.*]]
|
|
// SIMD-ONLY0: if.then4755:
|
|
// SIMD-ONLY0-NEXT: [[TMP2628:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2628]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4756]]
|
|
// SIMD-ONLY0: if.end4756:
|
|
// SIMD-ONLY0-NEXT: [[TMP2629:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2630:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4757:%.*]] = fcmp olt float [[TMP2629]], [[TMP2630]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4757]], label [[IF_THEN4759:%.*]], label [[IF_END4760:%.*]]
|
|
// SIMD-ONLY0: if.then4759:
|
|
// SIMD-ONLY0-NEXT: [[TMP2631:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2631]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4760]]
|
|
// SIMD-ONLY0: if.end4760:
|
|
// SIMD-ONLY0-NEXT: [[TMP2632:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2633:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4761:%.*]] = fcmp ogt float [[TMP2632]], [[TMP2633]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4761]], label [[COND_TRUE4763:%.*]], label [[COND_FALSE4764:%.*]]
|
|
// SIMD-ONLY0: cond.true4763:
|
|
// SIMD-ONLY0-NEXT: [[TMP2634:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4765:%.*]]
|
|
// SIMD-ONLY0: cond.false4764:
|
|
// SIMD-ONLY0-NEXT: [[TMP2635:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4765]]
|
|
// SIMD-ONLY0: cond.end4765:
|
|
// SIMD-ONLY0-NEXT: [[COND4766:%.*]] = phi float [ [[TMP2634]], [[COND_TRUE4763]] ], [ [[TMP2635]], [[COND_FALSE4764]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4766]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2636:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2637:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4767:%.*]] = fcmp olt float [[TMP2636]], [[TMP2637]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4767]], label [[COND_TRUE4769:%.*]], label [[COND_FALSE4770:%.*]]
|
|
// SIMD-ONLY0: cond.true4769:
|
|
// SIMD-ONLY0-NEXT: [[TMP2638:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4771:%.*]]
|
|
// SIMD-ONLY0: cond.false4770:
|
|
// SIMD-ONLY0-NEXT: [[TMP2639:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4771]]
|
|
// SIMD-ONLY0: cond.end4771:
|
|
// SIMD-ONLY0-NEXT: [[COND4772:%.*]] = phi float [ [[TMP2638]], [[COND_TRUE4769]] ], [ [[TMP2639]], [[COND_FALSE4770]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4772]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2640:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2641:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4773:%.*]] = fcmp ogt float [[TMP2640]], [[TMP2641]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4773]], label [[COND_TRUE4775:%.*]], label [[COND_FALSE4776:%.*]]
|
|
// SIMD-ONLY0: cond.true4775:
|
|
// SIMD-ONLY0-NEXT: [[TMP2642:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4777:%.*]]
|
|
// SIMD-ONLY0: cond.false4776:
|
|
// SIMD-ONLY0-NEXT: [[TMP2643:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4777]]
|
|
// SIMD-ONLY0: cond.end4777:
|
|
// SIMD-ONLY0-NEXT: [[COND4778:%.*]] = phi float [ [[TMP2642]], [[COND_TRUE4775]] ], [ [[TMP2643]], [[COND_FALSE4776]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4778]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2644:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2645:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4779:%.*]] = fcmp olt float [[TMP2644]], [[TMP2645]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4779]], label [[COND_TRUE4781:%.*]], label [[COND_FALSE4782:%.*]]
|
|
// SIMD-ONLY0: cond.true4781:
|
|
// SIMD-ONLY0-NEXT: [[TMP2646:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4783:%.*]]
|
|
// SIMD-ONLY0: cond.false4782:
|
|
// SIMD-ONLY0-NEXT: [[TMP2647:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4783]]
|
|
// SIMD-ONLY0: cond.end4783:
|
|
// SIMD-ONLY0-NEXT: [[COND4784:%.*]] = phi float [ [[TMP2646]], [[COND_TRUE4781]] ], [ [[TMP2647]], [[COND_FALSE4782]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4784]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2648:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2649:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4785:%.*]] = fcmp ogt float [[TMP2648]], [[TMP2649]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4785]], label [[IF_THEN4787:%.*]], label [[IF_END4788:%.*]]
|
|
// SIMD-ONLY0: if.then4787:
|
|
// SIMD-ONLY0-NEXT: [[TMP2650:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2650]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4788]]
|
|
// SIMD-ONLY0: if.end4788:
|
|
// SIMD-ONLY0-NEXT: [[TMP2651:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2652:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4789:%.*]] = fcmp olt float [[TMP2651]], [[TMP2652]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4789]], label [[IF_THEN4791:%.*]], label [[IF_END4792:%.*]]
|
|
// SIMD-ONLY0: if.then4791:
|
|
// SIMD-ONLY0-NEXT: [[TMP2653:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2653]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4792]]
|
|
// SIMD-ONLY0: if.end4792:
|
|
// SIMD-ONLY0-NEXT: [[TMP2654:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2655:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4793:%.*]] = fcmp ogt float [[TMP2654]], [[TMP2655]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4793]], label [[IF_THEN4795:%.*]], label [[IF_END4796:%.*]]
|
|
// SIMD-ONLY0: if.then4795:
|
|
// SIMD-ONLY0-NEXT: [[TMP2656:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2656]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4796]]
|
|
// SIMD-ONLY0: if.end4796:
|
|
// SIMD-ONLY0-NEXT: [[TMP2657:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2658:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4797:%.*]] = fcmp olt float [[TMP2657]], [[TMP2658]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4797]], label [[IF_THEN4799:%.*]], label [[IF_END4800:%.*]]
|
|
// SIMD-ONLY0: if.then4799:
|
|
// SIMD-ONLY0-NEXT: [[TMP2659:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2659]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4800]]
|
|
// SIMD-ONLY0: if.end4800:
|
|
// SIMD-ONLY0-NEXT: [[TMP2660:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2661:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4801:%.*]] = fcmp ogt float [[TMP2660]], [[TMP2661]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4801]], label [[COND_TRUE4803:%.*]], label [[COND_FALSE4804:%.*]]
|
|
// SIMD-ONLY0: cond.true4803:
|
|
// SIMD-ONLY0-NEXT: [[TMP2662:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4805:%.*]]
|
|
// SIMD-ONLY0: cond.false4804:
|
|
// SIMD-ONLY0-NEXT: [[TMP2663:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4805]]
|
|
// SIMD-ONLY0: cond.end4805:
|
|
// SIMD-ONLY0-NEXT: [[COND4806:%.*]] = phi float [ [[TMP2662]], [[COND_TRUE4803]] ], [ [[TMP2663]], [[COND_FALSE4804]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4806]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2664:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2665:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4807:%.*]] = fcmp olt float [[TMP2664]], [[TMP2665]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4807]], label [[COND_TRUE4809:%.*]], label [[COND_FALSE4810:%.*]]
|
|
// SIMD-ONLY0: cond.true4809:
|
|
// SIMD-ONLY0-NEXT: [[TMP2666:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4811:%.*]]
|
|
// SIMD-ONLY0: cond.false4810:
|
|
// SIMD-ONLY0-NEXT: [[TMP2667:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4811]]
|
|
// SIMD-ONLY0: cond.end4811:
|
|
// SIMD-ONLY0-NEXT: [[COND4812:%.*]] = phi float [ [[TMP2666]], [[COND_TRUE4809]] ], [ [[TMP2667]], [[COND_FALSE4810]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4812]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2668:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2669:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4813:%.*]] = fcmp ogt float [[TMP2668]], [[TMP2669]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4813]], label [[COND_TRUE4815:%.*]], label [[COND_FALSE4816:%.*]]
|
|
// SIMD-ONLY0: cond.true4815:
|
|
// SIMD-ONLY0-NEXT: [[TMP2670:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4817:%.*]]
|
|
// SIMD-ONLY0: cond.false4816:
|
|
// SIMD-ONLY0-NEXT: [[TMP2671:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4817]]
|
|
// SIMD-ONLY0: cond.end4817:
|
|
// SIMD-ONLY0-NEXT: [[COND4818:%.*]] = phi float [ [[TMP2670]], [[COND_TRUE4815]] ], [ [[TMP2671]], [[COND_FALSE4816]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4818]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2672:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2673:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4819:%.*]] = fcmp olt float [[TMP2672]], [[TMP2673]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4819]], label [[COND_TRUE4821:%.*]], label [[COND_FALSE4822:%.*]]
|
|
// SIMD-ONLY0: cond.true4821:
|
|
// SIMD-ONLY0-NEXT: [[TMP2674:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4823:%.*]]
|
|
// SIMD-ONLY0: cond.false4822:
|
|
// SIMD-ONLY0-NEXT: [[TMP2675:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4823]]
|
|
// SIMD-ONLY0: cond.end4823:
|
|
// SIMD-ONLY0-NEXT: [[COND4824:%.*]] = phi float [ [[TMP2674]], [[COND_TRUE4821]] ], [ [[TMP2675]], [[COND_FALSE4822]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND4824]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2676:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2677:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4825:%.*]] = fcmp ogt float [[TMP2676]], [[TMP2677]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4825]], label [[IF_THEN4827:%.*]], label [[IF_END4828:%.*]]
|
|
// SIMD-ONLY0: if.then4827:
|
|
// SIMD-ONLY0-NEXT: [[TMP2678:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2678]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4828]]
|
|
// SIMD-ONLY0: if.end4828:
|
|
// SIMD-ONLY0-NEXT: [[TMP2679:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2680:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4829:%.*]] = fcmp olt float [[TMP2679]], [[TMP2680]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4829]], label [[IF_THEN4831:%.*]], label [[IF_END4832:%.*]]
|
|
// SIMD-ONLY0: if.then4831:
|
|
// SIMD-ONLY0-NEXT: [[TMP2681:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2681]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4832]]
|
|
// SIMD-ONLY0: if.end4832:
|
|
// SIMD-ONLY0-NEXT: [[TMP2682:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2683:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4833:%.*]] = fcmp ogt float [[TMP2682]], [[TMP2683]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4833]], label [[IF_THEN4835:%.*]], label [[IF_END4836:%.*]]
|
|
// SIMD-ONLY0: if.then4835:
|
|
// SIMD-ONLY0-NEXT: [[TMP2684:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2684]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4836]]
|
|
// SIMD-ONLY0: if.end4836:
|
|
// SIMD-ONLY0-NEXT: [[TMP2685:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2686:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP4837:%.*]] = fcmp olt float [[TMP2685]], [[TMP2686]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4837]], label [[IF_THEN4839:%.*]], label [[IF_END4840:%.*]]
|
|
// SIMD-ONLY0: if.then4839:
|
|
// SIMD-ONLY0-NEXT: [[TMP2687:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP2687]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4840]]
|
|
// SIMD-ONLY0: if.end4840:
|
|
// SIMD-ONLY0-NEXT: [[TMP2688:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2689:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4841:%.*]] = fcmp ogt double [[TMP2688]], [[TMP2689]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4841]], label [[COND_TRUE4843:%.*]], label [[COND_FALSE4844:%.*]]
|
|
// SIMD-ONLY0: cond.true4843:
|
|
// SIMD-ONLY0-NEXT: [[TMP2690:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4845:%.*]]
|
|
// SIMD-ONLY0: cond.false4844:
|
|
// SIMD-ONLY0-NEXT: [[TMP2691:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4845]]
|
|
// SIMD-ONLY0: cond.end4845:
|
|
// SIMD-ONLY0-NEXT: [[COND4846:%.*]] = phi double [ [[TMP2690]], [[COND_TRUE4843]] ], [ [[TMP2691]], [[COND_FALSE4844]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4846]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2692:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2693:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4847:%.*]] = fcmp olt double [[TMP2692]], [[TMP2693]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4847]], label [[COND_TRUE4849:%.*]], label [[COND_FALSE4850:%.*]]
|
|
// SIMD-ONLY0: cond.true4849:
|
|
// SIMD-ONLY0-NEXT: [[TMP2694:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4851:%.*]]
|
|
// SIMD-ONLY0: cond.false4850:
|
|
// SIMD-ONLY0-NEXT: [[TMP2695:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4851]]
|
|
// SIMD-ONLY0: cond.end4851:
|
|
// SIMD-ONLY0-NEXT: [[COND4852:%.*]] = phi double [ [[TMP2694]], [[COND_TRUE4849]] ], [ [[TMP2695]], [[COND_FALSE4850]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4852]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2696:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2697:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4853:%.*]] = fcmp ogt double [[TMP2696]], [[TMP2697]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4853]], label [[COND_TRUE4855:%.*]], label [[COND_FALSE4856:%.*]]
|
|
// SIMD-ONLY0: cond.true4855:
|
|
// SIMD-ONLY0-NEXT: [[TMP2698:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4857:%.*]]
|
|
// SIMD-ONLY0: cond.false4856:
|
|
// SIMD-ONLY0-NEXT: [[TMP2699:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4857]]
|
|
// SIMD-ONLY0: cond.end4857:
|
|
// SIMD-ONLY0-NEXT: [[COND4858:%.*]] = phi double [ [[TMP2698]], [[COND_TRUE4855]] ], [ [[TMP2699]], [[COND_FALSE4856]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4858]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2700:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2701:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4859:%.*]] = fcmp olt double [[TMP2700]], [[TMP2701]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4859]], label [[COND_TRUE4861:%.*]], label [[COND_FALSE4862:%.*]]
|
|
// SIMD-ONLY0: cond.true4861:
|
|
// SIMD-ONLY0-NEXT: [[TMP2702:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4863:%.*]]
|
|
// SIMD-ONLY0: cond.false4862:
|
|
// SIMD-ONLY0-NEXT: [[TMP2703:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4863]]
|
|
// SIMD-ONLY0: cond.end4863:
|
|
// SIMD-ONLY0-NEXT: [[COND4864:%.*]] = phi double [ [[TMP2702]], [[COND_TRUE4861]] ], [ [[TMP2703]], [[COND_FALSE4862]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4864]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2704:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2705:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4865:%.*]] = fcmp ogt double [[TMP2704]], [[TMP2705]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4865]], label [[IF_THEN4867:%.*]], label [[IF_END4868:%.*]]
|
|
// SIMD-ONLY0: if.then4867:
|
|
// SIMD-ONLY0-NEXT: [[TMP2706:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2706]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4868]]
|
|
// SIMD-ONLY0: if.end4868:
|
|
// SIMD-ONLY0-NEXT: [[TMP2707:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2708:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4869:%.*]] = fcmp olt double [[TMP2707]], [[TMP2708]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4869]], label [[IF_THEN4871:%.*]], label [[IF_END4872:%.*]]
|
|
// SIMD-ONLY0: if.then4871:
|
|
// SIMD-ONLY0-NEXT: [[TMP2709:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2709]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4872]]
|
|
// SIMD-ONLY0: if.end4872:
|
|
// SIMD-ONLY0-NEXT: [[TMP2710:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2711:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4873:%.*]] = fcmp ogt double [[TMP2710]], [[TMP2711]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4873]], label [[IF_THEN4875:%.*]], label [[IF_END4876:%.*]]
|
|
// SIMD-ONLY0: if.then4875:
|
|
// SIMD-ONLY0-NEXT: [[TMP2712:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2712]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4876]]
|
|
// SIMD-ONLY0: if.end4876:
|
|
// SIMD-ONLY0-NEXT: [[TMP2713:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2714:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4877:%.*]] = fcmp olt double [[TMP2713]], [[TMP2714]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4877]], label [[IF_THEN4879:%.*]], label [[IF_END4880:%.*]]
|
|
// SIMD-ONLY0: if.then4879:
|
|
// SIMD-ONLY0-NEXT: [[TMP2715:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2715]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4880]]
|
|
// SIMD-ONLY0: if.end4880:
|
|
// SIMD-ONLY0-NEXT: [[TMP2716:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2717:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4881:%.*]] = fcmp ogt double [[TMP2716]], [[TMP2717]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4881]], label [[COND_TRUE4883:%.*]], label [[COND_FALSE4884:%.*]]
|
|
// SIMD-ONLY0: cond.true4883:
|
|
// SIMD-ONLY0-NEXT: [[TMP2718:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4885:%.*]]
|
|
// SIMD-ONLY0: cond.false4884:
|
|
// SIMD-ONLY0-NEXT: [[TMP2719:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4885]]
|
|
// SIMD-ONLY0: cond.end4885:
|
|
// SIMD-ONLY0-NEXT: [[COND4886:%.*]] = phi double [ [[TMP2718]], [[COND_TRUE4883]] ], [ [[TMP2719]], [[COND_FALSE4884]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4886]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2720:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2721:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4887:%.*]] = fcmp olt double [[TMP2720]], [[TMP2721]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4887]], label [[COND_TRUE4889:%.*]], label [[COND_FALSE4890:%.*]]
|
|
// SIMD-ONLY0: cond.true4889:
|
|
// SIMD-ONLY0-NEXT: [[TMP2722:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4891:%.*]]
|
|
// SIMD-ONLY0: cond.false4890:
|
|
// SIMD-ONLY0-NEXT: [[TMP2723:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4891]]
|
|
// SIMD-ONLY0: cond.end4891:
|
|
// SIMD-ONLY0-NEXT: [[COND4892:%.*]] = phi double [ [[TMP2722]], [[COND_TRUE4889]] ], [ [[TMP2723]], [[COND_FALSE4890]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4892]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2724:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2725:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4893:%.*]] = fcmp ogt double [[TMP2724]], [[TMP2725]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4893]], label [[COND_TRUE4895:%.*]], label [[COND_FALSE4896:%.*]]
|
|
// SIMD-ONLY0: cond.true4895:
|
|
// SIMD-ONLY0-NEXT: [[TMP2726:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4897:%.*]]
|
|
// SIMD-ONLY0: cond.false4896:
|
|
// SIMD-ONLY0-NEXT: [[TMP2727:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4897]]
|
|
// SIMD-ONLY0: cond.end4897:
|
|
// SIMD-ONLY0-NEXT: [[COND4898:%.*]] = phi double [ [[TMP2726]], [[COND_TRUE4895]] ], [ [[TMP2727]], [[COND_FALSE4896]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4898]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2728:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2729:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4899:%.*]] = fcmp olt double [[TMP2728]], [[TMP2729]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4899]], label [[COND_TRUE4901:%.*]], label [[COND_FALSE4902:%.*]]
|
|
// SIMD-ONLY0: cond.true4901:
|
|
// SIMD-ONLY0-NEXT: [[TMP2730:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4903:%.*]]
|
|
// SIMD-ONLY0: cond.false4902:
|
|
// SIMD-ONLY0-NEXT: [[TMP2731:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4903]]
|
|
// SIMD-ONLY0: cond.end4903:
|
|
// SIMD-ONLY0-NEXT: [[COND4904:%.*]] = phi double [ [[TMP2730]], [[COND_TRUE4901]] ], [ [[TMP2731]], [[COND_FALSE4902]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4904]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2732:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2733:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4905:%.*]] = fcmp ogt double [[TMP2732]], [[TMP2733]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4905]], label [[IF_THEN4907:%.*]], label [[IF_END4908:%.*]]
|
|
// SIMD-ONLY0: if.then4907:
|
|
// SIMD-ONLY0-NEXT: [[TMP2734:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2734]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4908]]
|
|
// SIMD-ONLY0: if.end4908:
|
|
// SIMD-ONLY0-NEXT: [[TMP2735:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2736:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4909:%.*]] = fcmp olt double [[TMP2735]], [[TMP2736]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4909]], label [[IF_THEN4911:%.*]], label [[IF_END4912:%.*]]
|
|
// SIMD-ONLY0: if.then4911:
|
|
// SIMD-ONLY0-NEXT: [[TMP2737:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2737]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4912]]
|
|
// SIMD-ONLY0: if.end4912:
|
|
// SIMD-ONLY0-NEXT: [[TMP2738:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2739:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4913:%.*]] = fcmp ogt double [[TMP2738]], [[TMP2739]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4913]], label [[IF_THEN4915:%.*]], label [[IF_END4916:%.*]]
|
|
// SIMD-ONLY0: if.then4915:
|
|
// SIMD-ONLY0-NEXT: [[TMP2740:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2740]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4916]]
|
|
// SIMD-ONLY0: if.end4916:
|
|
// SIMD-ONLY0-NEXT: [[TMP2741:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2742:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4917:%.*]] = fcmp olt double [[TMP2741]], [[TMP2742]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4917]], label [[IF_THEN4919:%.*]], label [[IF_END4920:%.*]]
|
|
// SIMD-ONLY0: if.then4919:
|
|
// SIMD-ONLY0-NEXT: [[TMP2743:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2743]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4920]]
|
|
// SIMD-ONLY0: if.end4920:
|
|
// SIMD-ONLY0-NEXT: [[TMP2744:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2745:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4921:%.*]] = fcmp ogt double [[TMP2744]], [[TMP2745]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4921]], label [[COND_TRUE4923:%.*]], label [[COND_FALSE4924:%.*]]
|
|
// SIMD-ONLY0: cond.true4923:
|
|
// SIMD-ONLY0-NEXT: [[TMP2746:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4925:%.*]]
|
|
// SIMD-ONLY0: cond.false4924:
|
|
// SIMD-ONLY0-NEXT: [[TMP2747:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4925]]
|
|
// SIMD-ONLY0: cond.end4925:
|
|
// SIMD-ONLY0-NEXT: [[COND4926:%.*]] = phi double [ [[TMP2746]], [[COND_TRUE4923]] ], [ [[TMP2747]], [[COND_FALSE4924]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4926]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2748:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2749:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4927:%.*]] = fcmp olt double [[TMP2748]], [[TMP2749]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4927]], label [[COND_TRUE4929:%.*]], label [[COND_FALSE4930:%.*]]
|
|
// SIMD-ONLY0: cond.true4929:
|
|
// SIMD-ONLY0-NEXT: [[TMP2750:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4931:%.*]]
|
|
// SIMD-ONLY0: cond.false4930:
|
|
// SIMD-ONLY0-NEXT: [[TMP2751:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4931]]
|
|
// SIMD-ONLY0: cond.end4931:
|
|
// SIMD-ONLY0-NEXT: [[COND4932:%.*]] = phi double [ [[TMP2750]], [[COND_TRUE4929]] ], [ [[TMP2751]], [[COND_FALSE4930]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4932]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2752:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2753:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4933:%.*]] = fcmp ogt double [[TMP2752]], [[TMP2753]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4933]], label [[COND_TRUE4935:%.*]], label [[COND_FALSE4936:%.*]]
|
|
// SIMD-ONLY0: cond.true4935:
|
|
// SIMD-ONLY0-NEXT: [[TMP2754:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4937:%.*]]
|
|
// SIMD-ONLY0: cond.false4936:
|
|
// SIMD-ONLY0-NEXT: [[TMP2755:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4937]]
|
|
// SIMD-ONLY0: cond.end4937:
|
|
// SIMD-ONLY0-NEXT: [[COND4938:%.*]] = phi double [ [[TMP2754]], [[COND_TRUE4935]] ], [ [[TMP2755]], [[COND_FALSE4936]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4938]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2756:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2757:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4939:%.*]] = fcmp olt double [[TMP2756]], [[TMP2757]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4939]], label [[COND_TRUE4941:%.*]], label [[COND_FALSE4942:%.*]]
|
|
// SIMD-ONLY0: cond.true4941:
|
|
// SIMD-ONLY0-NEXT: [[TMP2758:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4943:%.*]]
|
|
// SIMD-ONLY0: cond.false4942:
|
|
// SIMD-ONLY0-NEXT: [[TMP2759:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4943]]
|
|
// SIMD-ONLY0: cond.end4943:
|
|
// SIMD-ONLY0-NEXT: [[COND4944:%.*]] = phi double [ [[TMP2758]], [[COND_TRUE4941]] ], [ [[TMP2759]], [[COND_FALSE4942]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4944]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2760:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2761:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4945:%.*]] = fcmp ogt double [[TMP2760]], [[TMP2761]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4945]], label [[IF_THEN4947:%.*]], label [[IF_END4948:%.*]]
|
|
// SIMD-ONLY0: if.then4947:
|
|
// SIMD-ONLY0-NEXT: [[TMP2762:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2762]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4948]]
|
|
// SIMD-ONLY0: if.end4948:
|
|
// SIMD-ONLY0-NEXT: [[TMP2763:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2764:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4949:%.*]] = fcmp olt double [[TMP2763]], [[TMP2764]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4949]], label [[IF_THEN4951:%.*]], label [[IF_END4952:%.*]]
|
|
// SIMD-ONLY0: if.then4951:
|
|
// SIMD-ONLY0-NEXT: [[TMP2765:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2765]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4952]]
|
|
// SIMD-ONLY0: if.end4952:
|
|
// SIMD-ONLY0-NEXT: [[TMP2766:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2767:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4953:%.*]] = fcmp ogt double [[TMP2766]], [[TMP2767]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4953]], label [[IF_THEN4955:%.*]], label [[IF_END4956:%.*]]
|
|
// SIMD-ONLY0: if.then4955:
|
|
// SIMD-ONLY0-NEXT: [[TMP2768:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2768]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4956]]
|
|
// SIMD-ONLY0: if.end4956:
|
|
// SIMD-ONLY0-NEXT: [[TMP2769:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2770:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4957:%.*]] = fcmp olt double [[TMP2769]], [[TMP2770]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4957]], label [[IF_THEN4959:%.*]], label [[IF_END4960:%.*]]
|
|
// SIMD-ONLY0: if.then4959:
|
|
// SIMD-ONLY0-NEXT: [[TMP2771:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2771]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4960]]
|
|
// SIMD-ONLY0: if.end4960:
|
|
// SIMD-ONLY0-NEXT: [[TMP2772:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2773:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4961:%.*]] = fcmp ogt double [[TMP2772]], [[TMP2773]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4961]], label [[COND_TRUE4963:%.*]], label [[COND_FALSE4964:%.*]]
|
|
// SIMD-ONLY0: cond.true4963:
|
|
// SIMD-ONLY0-NEXT: [[TMP2774:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4965:%.*]]
|
|
// SIMD-ONLY0: cond.false4964:
|
|
// SIMD-ONLY0-NEXT: [[TMP2775:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4965]]
|
|
// SIMD-ONLY0: cond.end4965:
|
|
// SIMD-ONLY0-NEXT: [[COND4966:%.*]] = phi double [ [[TMP2774]], [[COND_TRUE4963]] ], [ [[TMP2775]], [[COND_FALSE4964]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4966]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2776:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2777:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4967:%.*]] = fcmp olt double [[TMP2776]], [[TMP2777]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4967]], label [[COND_TRUE4969:%.*]], label [[COND_FALSE4970:%.*]]
|
|
// SIMD-ONLY0: cond.true4969:
|
|
// SIMD-ONLY0-NEXT: [[TMP2778:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4971:%.*]]
|
|
// SIMD-ONLY0: cond.false4970:
|
|
// SIMD-ONLY0-NEXT: [[TMP2779:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4971]]
|
|
// SIMD-ONLY0: cond.end4971:
|
|
// SIMD-ONLY0-NEXT: [[COND4972:%.*]] = phi double [ [[TMP2778]], [[COND_TRUE4969]] ], [ [[TMP2779]], [[COND_FALSE4970]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4972]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2780:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2781:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4973:%.*]] = fcmp ogt double [[TMP2780]], [[TMP2781]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4973]], label [[COND_TRUE4975:%.*]], label [[COND_FALSE4976:%.*]]
|
|
// SIMD-ONLY0: cond.true4975:
|
|
// SIMD-ONLY0-NEXT: [[TMP2782:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4977:%.*]]
|
|
// SIMD-ONLY0: cond.false4976:
|
|
// SIMD-ONLY0-NEXT: [[TMP2783:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4977]]
|
|
// SIMD-ONLY0: cond.end4977:
|
|
// SIMD-ONLY0-NEXT: [[COND4978:%.*]] = phi double [ [[TMP2782]], [[COND_TRUE4975]] ], [ [[TMP2783]], [[COND_FALSE4976]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4978]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2784:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2785:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4979:%.*]] = fcmp olt double [[TMP2784]], [[TMP2785]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4979]], label [[COND_TRUE4981:%.*]], label [[COND_FALSE4982:%.*]]
|
|
// SIMD-ONLY0: cond.true4981:
|
|
// SIMD-ONLY0-NEXT: [[TMP2786:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4983:%.*]]
|
|
// SIMD-ONLY0: cond.false4982:
|
|
// SIMD-ONLY0-NEXT: [[TMP2787:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4983]]
|
|
// SIMD-ONLY0: cond.end4983:
|
|
// SIMD-ONLY0-NEXT: [[COND4984:%.*]] = phi double [ [[TMP2786]], [[COND_TRUE4981]] ], [ [[TMP2787]], [[COND_FALSE4982]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND4984]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2788:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2789:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4985:%.*]] = fcmp ogt double [[TMP2788]], [[TMP2789]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4985]], label [[IF_THEN4987:%.*]], label [[IF_END4988:%.*]]
|
|
// SIMD-ONLY0: if.then4987:
|
|
// SIMD-ONLY0-NEXT: [[TMP2790:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2790]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4988]]
|
|
// SIMD-ONLY0: if.end4988:
|
|
// SIMD-ONLY0-NEXT: [[TMP2791:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2792:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4989:%.*]] = fcmp olt double [[TMP2791]], [[TMP2792]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4989]], label [[IF_THEN4991:%.*]], label [[IF_END4992:%.*]]
|
|
// SIMD-ONLY0: if.then4991:
|
|
// SIMD-ONLY0-NEXT: [[TMP2793:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2793]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4992]]
|
|
// SIMD-ONLY0: if.end4992:
|
|
// SIMD-ONLY0-NEXT: [[TMP2794:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2795:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4993:%.*]] = fcmp ogt double [[TMP2794]], [[TMP2795]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4993]], label [[IF_THEN4995:%.*]], label [[IF_END4996:%.*]]
|
|
// SIMD-ONLY0: if.then4995:
|
|
// SIMD-ONLY0-NEXT: [[TMP2796:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2796]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4996]]
|
|
// SIMD-ONLY0: if.end4996:
|
|
// SIMD-ONLY0-NEXT: [[TMP2797:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2798:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4997:%.*]] = fcmp olt double [[TMP2797]], [[TMP2798]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4997]], label [[IF_THEN4999:%.*]], label [[IF_END5000:%.*]]
|
|
// SIMD-ONLY0: if.then4999:
|
|
// SIMD-ONLY0-NEXT: [[TMP2799:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2799]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5000]]
|
|
// SIMD-ONLY0: if.end5000:
|
|
// SIMD-ONLY0-NEXT: [[TMP2800:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2801:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5001:%.*]] = fcmp ogt double [[TMP2800]], [[TMP2801]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5001]], label [[COND_TRUE5003:%.*]], label [[COND_FALSE5004:%.*]]
|
|
// SIMD-ONLY0: cond.true5003:
|
|
// SIMD-ONLY0-NEXT: [[TMP2802:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5005:%.*]]
|
|
// SIMD-ONLY0: cond.false5004:
|
|
// SIMD-ONLY0-NEXT: [[TMP2803:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5005]]
|
|
// SIMD-ONLY0: cond.end5005:
|
|
// SIMD-ONLY0-NEXT: [[COND5006:%.*]] = phi double [ [[TMP2802]], [[COND_TRUE5003]] ], [ [[TMP2803]], [[COND_FALSE5004]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND5006]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2804:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2805:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5007:%.*]] = fcmp olt double [[TMP2804]], [[TMP2805]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5007]], label [[COND_TRUE5009:%.*]], label [[COND_FALSE5010:%.*]]
|
|
// SIMD-ONLY0: cond.true5009:
|
|
// SIMD-ONLY0-NEXT: [[TMP2806:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5011:%.*]]
|
|
// SIMD-ONLY0: cond.false5010:
|
|
// SIMD-ONLY0-NEXT: [[TMP2807:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5011]]
|
|
// SIMD-ONLY0: cond.end5011:
|
|
// SIMD-ONLY0-NEXT: [[COND5012:%.*]] = phi double [ [[TMP2806]], [[COND_TRUE5009]] ], [ [[TMP2807]], [[COND_FALSE5010]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND5012]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2808:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2809:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5013:%.*]] = fcmp ogt double [[TMP2808]], [[TMP2809]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5013]], label [[COND_TRUE5015:%.*]], label [[COND_FALSE5016:%.*]]
|
|
// SIMD-ONLY0: cond.true5015:
|
|
// SIMD-ONLY0-NEXT: [[TMP2810:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5017:%.*]]
|
|
// SIMD-ONLY0: cond.false5016:
|
|
// SIMD-ONLY0-NEXT: [[TMP2811:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5017]]
|
|
// SIMD-ONLY0: cond.end5017:
|
|
// SIMD-ONLY0-NEXT: [[COND5018:%.*]] = phi double [ [[TMP2810]], [[COND_TRUE5015]] ], [ [[TMP2811]], [[COND_FALSE5016]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND5018]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2812:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2813:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5019:%.*]] = fcmp olt double [[TMP2812]], [[TMP2813]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5019]], label [[COND_TRUE5021:%.*]], label [[COND_FALSE5022:%.*]]
|
|
// SIMD-ONLY0: cond.true5021:
|
|
// SIMD-ONLY0-NEXT: [[TMP2814:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5023:%.*]]
|
|
// SIMD-ONLY0: cond.false5022:
|
|
// SIMD-ONLY0-NEXT: [[TMP2815:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5023]]
|
|
// SIMD-ONLY0: cond.end5023:
|
|
// SIMD-ONLY0-NEXT: [[COND5024:%.*]] = phi double [ [[TMP2814]], [[COND_TRUE5021]] ], [ [[TMP2815]], [[COND_FALSE5022]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND5024]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2816:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2817:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5025:%.*]] = fcmp ogt double [[TMP2816]], [[TMP2817]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5025]], label [[IF_THEN5027:%.*]], label [[IF_END5028:%.*]]
|
|
// SIMD-ONLY0: if.then5027:
|
|
// SIMD-ONLY0-NEXT: [[TMP2818:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2818]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5028]]
|
|
// SIMD-ONLY0: if.end5028:
|
|
// SIMD-ONLY0-NEXT: [[TMP2819:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2820:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5029:%.*]] = fcmp olt double [[TMP2819]], [[TMP2820]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5029]], label [[IF_THEN5031:%.*]], label [[IF_END5032:%.*]]
|
|
// SIMD-ONLY0: if.then5031:
|
|
// SIMD-ONLY0-NEXT: [[TMP2821:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2821]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5032]]
|
|
// SIMD-ONLY0: if.end5032:
|
|
// SIMD-ONLY0-NEXT: [[TMP2822:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2823:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5033:%.*]] = fcmp ogt double [[TMP2822]], [[TMP2823]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5033]], label [[IF_THEN5035:%.*]], label [[IF_END5036:%.*]]
|
|
// SIMD-ONLY0: if.then5035:
|
|
// SIMD-ONLY0-NEXT: [[TMP2824:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2824]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5036]]
|
|
// SIMD-ONLY0: if.end5036:
|
|
// SIMD-ONLY0-NEXT: [[TMP2825:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2826:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5037:%.*]] = fcmp olt double [[TMP2825]], [[TMP2826]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5037]], label [[IF_THEN5039:%.*]], label [[IF_END5040:%.*]]
|
|
// SIMD-ONLY0: if.then5039:
|
|
// SIMD-ONLY0-NEXT: [[TMP2827:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2827]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5040]]
|
|
// SIMD-ONLY0: if.end5040:
|
|
// SIMD-ONLY0-NEXT: [[TMP2828:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2829:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5041:%.*]] = fcmp ogt double [[TMP2828]], [[TMP2829]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5041]], label [[COND_TRUE5043:%.*]], label [[COND_FALSE5044:%.*]]
|
|
// SIMD-ONLY0: cond.true5043:
|
|
// SIMD-ONLY0-NEXT: [[TMP2830:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5045:%.*]]
|
|
// SIMD-ONLY0: cond.false5044:
|
|
// SIMD-ONLY0-NEXT: [[TMP2831:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5045]]
|
|
// SIMD-ONLY0: cond.end5045:
|
|
// SIMD-ONLY0-NEXT: [[COND5046:%.*]] = phi double [ [[TMP2830]], [[COND_TRUE5043]] ], [ [[TMP2831]], [[COND_FALSE5044]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND5046]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2832:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2833:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5047:%.*]] = fcmp olt double [[TMP2832]], [[TMP2833]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5047]], label [[COND_TRUE5049:%.*]], label [[COND_FALSE5050:%.*]]
|
|
// SIMD-ONLY0: cond.true5049:
|
|
// SIMD-ONLY0-NEXT: [[TMP2834:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5051:%.*]]
|
|
// SIMD-ONLY0: cond.false5050:
|
|
// SIMD-ONLY0-NEXT: [[TMP2835:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5051]]
|
|
// SIMD-ONLY0: cond.end5051:
|
|
// SIMD-ONLY0-NEXT: [[COND5052:%.*]] = phi double [ [[TMP2834]], [[COND_TRUE5049]] ], [ [[TMP2835]], [[COND_FALSE5050]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND5052]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2836:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2837:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5053:%.*]] = fcmp ogt double [[TMP2836]], [[TMP2837]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5053]], label [[COND_TRUE5055:%.*]], label [[COND_FALSE5056:%.*]]
|
|
// SIMD-ONLY0: cond.true5055:
|
|
// SIMD-ONLY0-NEXT: [[TMP2838:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5057:%.*]]
|
|
// SIMD-ONLY0: cond.false5056:
|
|
// SIMD-ONLY0-NEXT: [[TMP2839:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5057]]
|
|
// SIMD-ONLY0: cond.end5057:
|
|
// SIMD-ONLY0-NEXT: [[COND5058:%.*]] = phi double [ [[TMP2838]], [[COND_TRUE5055]] ], [ [[TMP2839]], [[COND_FALSE5056]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND5058]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2840:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2841:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5059:%.*]] = fcmp olt double [[TMP2840]], [[TMP2841]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5059]], label [[COND_TRUE5061:%.*]], label [[COND_FALSE5062:%.*]]
|
|
// SIMD-ONLY0: cond.true5061:
|
|
// SIMD-ONLY0-NEXT: [[TMP2842:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5063:%.*]]
|
|
// SIMD-ONLY0: cond.false5062:
|
|
// SIMD-ONLY0-NEXT: [[TMP2843:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END5063]]
|
|
// SIMD-ONLY0: cond.end5063:
|
|
// SIMD-ONLY0-NEXT: [[COND5064:%.*]] = phi double [ [[TMP2842]], [[COND_TRUE5061]] ], [ [[TMP2843]], [[COND_FALSE5062]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND5064]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2844:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2845:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5065:%.*]] = fcmp ogt double [[TMP2844]], [[TMP2845]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5065]], label [[IF_THEN5067:%.*]], label [[IF_END5068:%.*]]
|
|
// SIMD-ONLY0: if.then5067:
|
|
// SIMD-ONLY0-NEXT: [[TMP2846:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2846]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5068]]
|
|
// SIMD-ONLY0: if.end5068:
|
|
// SIMD-ONLY0-NEXT: [[TMP2847:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2848:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5069:%.*]] = fcmp olt double [[TMP2847]], [[TMP2848]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5069]], label [[IF_THEN5071:%.*]], label [[IF_END5072:%.*]]
|
|
// SIMD-ONLY0: if.then5071:
|
|
// SIMD-ONLY0-NEXT: [[TMP2849:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2849]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5072]]
|
|
// SIMD-ONLY0: if.end5072:
|
|
// SIMD-ONLY0-NEXT: [[TMP2850:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2851:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5073:%.*]] = fcmp ogt double [[TMP2850]], [[TMP2851]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5073]], label [[IF_THEN5075:%.*]], label [[IF_END5076:%.*]]
|
|
// SIMD-ONLY0: if.then5075:
|
|
// SIMD-ONLY0-NEXT: [[TMP2852:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2852]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5076]]
|
|
// SIMD-ONLY0: if.end5076:
|
|
// SIMD-ONLY0-NEXT: [[TMP2853:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2854:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5077:%.*]] = fcmp olt double [[TMP2853]], [[TMP2854]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5077]], label [[IF_THEN5079:%.*]], label [[IF_END5080:%.*]]
|
|
// SIMD-ONLY0: if.then5079:
|
|
// SIMD-ONLY0-NEXT: [[TMP2855:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP2855]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5080]]
|
|
// SIMD-ONLY0: if.end5080:
|
|
// SIMD-ONLY0-NEXT: ret void
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @bar(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[CX:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[CV:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[CR:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[CE:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[CD:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCX:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCV:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCR:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCE:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCD:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[SX:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[SV:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[SR:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[SE:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[SD:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USX:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USV:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USR:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USE:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USD:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[IX:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[IV:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[IR:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[IE:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[ID:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UIX:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UIV:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UIR:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UIE:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UID:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[LX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LV:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LR:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULV:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULR:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLV:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLR:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLV:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLR:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[FX:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[FV:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[FE:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[FD:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[DX:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[DV:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[DE:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[DD:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP0]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i8 [[TMP2]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
|
|
// SIMD-ONLY0: if.then:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP3]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END]]
|
|
// SIMD-ONLY0: if.end:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP4]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV4:%.*]] = sext i8 [[TMP6]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[CONV3]], [[CONV4]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5]], label [[IF_THEN7:%.*]], label [[IF_END8:%.*]]
|
|
// SIMD-ONLY0: if.then7:
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP7]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END8]]
|
|
// SIMD-ONLY0: if.end8:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP8]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV9:%.*]] = sext i8 [[TMP9]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV10:%.*]] = sext i8 [[TMP10]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP11:%.*]] = icmp slt i32 [[CONV9]], [[CONV10]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP11]], label [[IF_THEN13:%.*]], label [[IF_END14:%.*]]
|
|
// SIMD-ONLY0: if.then13:
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP11]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END14]]
|
|
// SIMD-ONLY0: if.end14:
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP12]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV15:%.*]] = sext i8 [[TMP13]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV16:%.*]] = sext i8 [[TMP14]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP17:%.*]] = icmp slt i32 [[CONV15]], [[CONV16]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP17]], label [[IF_THEN19:%.*]], label [[IF_END20:%.*]]
|
|
// SIMD-ONLY0: if.then19:
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP15]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END20]]
|
|
// SIMD-ONLY0: if.end20:
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP16]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV21:%.*]] = sext i8 [[TMP17]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV22:%.*]] = sext i8 [[TMP18]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP23:%.*]] = icmp eq i32 [[CONV21]], [[CONV22]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP23]], label [[IF_THEN25:%.*]], label [[IF_END26:%.*]]
|
|
// SIMD-ONLY0: if.then25:
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP19]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END26]]
|
|
// SIMD-ONLY0: if.end26:
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP20]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV27:%.*]] = sext i8 [[TMP21]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV28:%.*]] = sext i8 [[TMP22]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP29:%.*]] = icmp eq i32 [[CONV27]], [[CONV28]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP29]], label [[IF_THEN31:%.*]], label [[IF_END32:%.*]]
|
|
// SIMD-ONLY0: if.then31:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP23]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END32]]
|
|
// SIMD-ONLY0: if.end32:
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV33:%.*]] = sext i8 [[TMP24]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV34:%.*]] = sext i8 [[TMP25]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP35:%.*]] = icmp sgt i32 [[CONV33]], [[CONV34]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP35]], label [[IF_THEN37:%.*]], label [[IF_END38:%.*]]
|
|
// SIMD-ONLY0: if.then37:
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP26]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END38]]
|
|
// SIMD-ONLY0: if.end38:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP27]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV39:%.*]] = sext i8 [[TMP28]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV40:%.*]] = sext i8 [[TMP29]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp sgt i32 [[CONV39]], [[CONV40]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[IF_THEN43:%.*]], label [[IF_END44:%.*]]
|
|
// SIMD-ONLY0: if.then43:
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP30]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END44]]
|
|
// SIMD-ONLY0: if.end44:
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP31]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV45:%.*]] = sext i8 [[TMP32]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV46:%.*]] = sext i8 [[TMP33]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP47:%.*]] = icmp slt i32 [[CONV45]], [[CONV46]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP47]], label [[IF_THEN49:%.*]], label [[IF_END50:%.*]]
|
|
// SIMD-ONLY0: if.then49:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP34]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END50]]
|
|
// SIMD-ONLY0: if.end50:
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP35]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV51:%.*]] = sext i8 [[TMP36]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV52:%.*]] = sext i8 [[TMP37]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP53:%.*]] = icmp slt i32 [[CONV51]], [[CONV52]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP53]], label [[IF_THEN55:%.*]], label [[IF_END56:%.*]]
|
|
// SIMD-ONLY0: if.then55:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP38]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END56]]
|
|
// SIMD-ONLY0: if.end56:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP39]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV57:%.*]] = sext i8 [[TMP40]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV58:%.*]] = sext i8 [[TMP41]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP59:%.*]] = icmp eq i32 [[CONV57]], [[CONV58]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP59]], label [[IF_THEN61:%.*]], label [[IF_END62:%.*]]
|
|
// SIMD-ONLY0: if.then61:
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP42]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END62]]
|
|
// SIMD-ONLY0: if.end62:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP43]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV63:%.*]] = sext i8 [[TMP44]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV64:%.*]] = sext i8 [[TMP45]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP65:%.*]] = icmp eq i32 [[CONV63]], [[CONV64]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP65]], label [[IF_THEN67:%.*]], label [[IF_END68:%.*]]
|
|
// SIMD-ONLY0: if.then67:
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP46]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END68]]
|
|
// SIMD-ONLY0: if.end68:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP47]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV69:%.*]] = sext i8 [[TMP48]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV70:%.*]] = sext i8 [[TMP49]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP71:%.*]] = icmp eq i32 [[CONV69]], [[CONV70]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP71]], label [[IF_THEN73:%.*]], label [[IF_ELSE:%.*]]
|
|
// SIMD-ONLY0: if.then73:
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP50]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END74:%.*]]
|
|
// SIMD-ONLY0: if.else:
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP51]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END74]]
|
|
// SIMD-ONLY0: if.end74:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV75:%.*]] = sext i8 [[TMP52]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV76:%.*]] = sext i8 [[TMP53]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP77:%.*]] = icmp eq i32 [[CONV75]], [[CONV76]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP77]], label [[IF_THEN79:%.*]], label [[IF_ELSE80:%.*]]
|
|
// SIMD-ONLY0: if.then79:
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP54]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END81:%.*]]
|
|
// SIMD-ONLY0: if.else80:
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP55]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END81]]
|
|
// SIMD-ONLY0: if.end81:
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV82:%.*]] = sext i8 [[TMP56]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV83:%.*]] = sext i8 [[TMP57]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP84:%.*]] = icmp eq i32 [[CONV82]], [[CONV83]]
|
|
// SIMD-ONLY0-NEXT: [[CONV85:%.*]] = zext i1 [[CMP84]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV86:%.*]] = trunc i32 [[CONV85]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV86]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP58]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL]], label [[IF_THEN87:%.*]], label [[IF_END88:%.*]]
|
|
// SIMD-ONLY0: if.then87:
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP59]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END88]]
|
|
// SIMD-ONLY0: if.end88:
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV89:%.*]] = sext i8 [[TMP60]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV90:%.*]] = sext i8 [[TMP61]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = icmp eq i32 [[CONV89]], [[CONV90]]
|
|
// SIMD-ONLY0-NEXT: [[CONV92:%.*]] = zext i1 [[CMP91]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV93:%.*]] = trunc i32 [[CONV92]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV93]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL94:%.*]] = icmp ne i8 [[TMP62]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL94]], label [[IF_THEN95:%.*]], label [[IF_END96:%.*]]
|
|
// SIMD-ONLY0: if.then95:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP63]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END96]]
|
|
// SIMD-ONLY0: if.end96:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV97:%.*]] = sext i8 [[TMP64]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV98:%.*]] = sext i8 [[TMP65]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP99:%.*]] = icmp eq i32 [[CONV97]], [[CONV98]]
|
|
// SIMD-ONLY0-NEXT: [[CONV100:%.*]] = zext i1 [[CMP99]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV101:%.*]] = trunc i32 [[CONV100]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV101]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL102:%.*]] = icmp ne i8 [[TMP66]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL102]], label [[IF_THEN103:%.*]], label [[IF_ELSE104:%.*]]
|
|
// SIMD-ONLY0: if.then103:
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP67]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END105:%.*]]
|
|
// SIMD-ONLY0: if.else104:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP68]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END105]]
|
|
// SIMD-ONLY0: if.end105:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV106:%.*]] = sext i8 [[TMP69]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV107:%.*]] = sext i8 [[TMP70]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP108:%.*]] = icmp eq i32 [[CONV106]], [[CONV107]]
|
|
// SIMD-ONLY0-NEXT: [[CONV109:%.*]] = zext i1 [[CMP108]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV110:%.*]] = trunc i32 [[CONV109]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV110]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL111:%.*]] = icmp ne i8 [[TMP71]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL111]], label [[IF_THEN112:%.*]], label [[IF_ELSE113:%.*]]
|
|
// SIMD-ONLY0: if.then112:
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP72]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END114:%.*]]
|
|
// SIMD-ONLY0: if.else113:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP73]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END114]]
|
|
// SIMD-ONLY0: if.end114:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP74]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV115:%.*]] = sext i8 [[TMP75]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV116:%.*]] = sext i8 [[TMP76]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP117:%.*]] = icmp sgt i32 [[CONV115]], [[CONV116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP117]], label [[IF_THEN119:%.*]], label [[IF_END120:%.*]]
|
|
// SIMD-ONLY0: if.then119:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP77]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END120]]
|
|
// SIMD-ONLY0: if.end120:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP78]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV121:%.*]] = sext i8 [[TMP79]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV122:%.*]] = sext i8 [[TMP80]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP123:%.*]] = icmp sgt i32 [[CONV121]], [[CONV122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP123]], label [[IF_THEN125:%.*]], label [[IF_END126:%.*]]
|
|
// SIMD-ONLY0: if.then125:
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP81]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END126]]
|
|
// SIMD-ONLY0: if.end126:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP82]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV127:%.*]] = sext i8 [[TMP83]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV128:%.*]] = sext i8 [[TMP84]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP129:%.*]] = icmp slt i32 [[CONV127]], [[CONV128]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP129]], label [[IF_THEN131:%.*]], label [[IF_END132:%.*]]
|
|
// SIMD-ONLY0: if.then131:
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP85]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END132]]
|
|
// SIMD-ONLY0: if.end132:
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP86]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV133:%.*]] = sext i8 [[TMP87]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV134:%.*]] = sext i8 [[TMP88]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP135:%.*]] = icmp slt i32 [[CONV133]], [[CONV134]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP135]], label [[IF_THEN137:%.*]], label [[IF_END138:%.*]]
|
|
// SIMD-ONLY0: if.then137:
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP89]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END138]]
|
|
// SIMD-ONLY0: if.end138:
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP90]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV139:%.*]] = sext i8 [[TMP91]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV140:%.*]] = sext i8 [[TMP92]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = icmp eq i32 [[CONV139]], [[CONV140]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[IF_THEN143:%.*]], label [[IF_END144:%.*]]
|
|
// SIMD-ONLY0: if.then143:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP93]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END144]]
|
|
// SIMD-ONLY0: if.end144:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP94]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV145:%.*]] = sext i8 [[TMP95]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV146:%.*]] = sext i8 [[TMP96]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP147:%.*]] = icmp eq i32 [[CONV145]], [[CONV146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP147]], label [[IF_THEN149:%.*]], label [[IF_END150:%.*]]
|
|
// SIMD-ONLY0: if.then149:
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP97]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END150]]
|
|
// SIMD-ONLY0: if.end150:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV151:%.*]] = sext i8 [[TMP98]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV152:%.*]] = sext i8 [[TMP99]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP153:%.*]] = icmp sgt i32 [[CONV151]], [[CONV152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP153]], label [[IF_THEN155:%.*]], label [[IF_END156:%.*]]
|
|
// SIMD-ONLY0: if.then155:
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP100]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END156]]
|
|
// SIMD-ONLY0: if.end156:
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP101]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV157:%.*]] = sext i8 [[TMP102]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV158:%.*]] = sext i8 [[TMP103]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP159:%.*]] = icmp sgt i32 [[CONV157]], [[CONV158]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP159]], label [[IF_THEN161:%.*]], label [[IF_END162:%.*]]
|
|
// SIMD-ONLY0: if.then161:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP104]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END162]]
|
|
// SIMD-ONLY0: if.end162:
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP105]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV163:%.*]] = sext i8 [[TMP106]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV164:%.*]] = sext i8 [[TMP107]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP165:%.*]] = icmp slt i32 [[CONV163]], [[CONV164]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP165]], label [[IF_THEN167:%.*]], label [[IF_END168:%.*]]
|
|
// SIMD-ONLY0: if.then167:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP108]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END168]]
|
|
// SIMD-ONLY0: if.end168:
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP109]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV169:%.*]] = sext i8 [[TMP110]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV170:%.*]] = sext i8 [[TMP111]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP171:%.*]] = icmp slt i32 [[CONV169]], [[CONV170]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP171]], label [[IF_THEN173:%.*]], label [[IF_END174:%.*]]
|
|
// SIMD-ONLY0: if.then173:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP112]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END174]]
|
|
// SIMD-ONLY0: if.end174:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP113]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV175:%.*]] = sext i8 [[TMP114]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV176:%.*]] = sext i8 [[TMP115]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP177:%.*]] = icmp eq i32 [[CONV175]], [[CONV176]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP177]], label [[IF_THEN179:%.*]], label [[IF_END180:%.*]]
|
|
// SIMD-ONLY0: if.then179:
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP116]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END180]]
|
|
// SIMD-ONLY0: if.end180:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP117]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV181:%.*]] = sext i8 [[TMP118]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV182:%.*]] = sext i8 [[TMP119]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP183:%.*]] = icmp eq i32 [[CONV181]], [[CONV182]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP183]], label [[IF_THEN185:%.*]], label [[IF_END186:%.*]]
|
|
// SIMD-ONLY0: if.then185:
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP120]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END186]]
|
|
// SIMD-ONLY0: if.end186:
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP121]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV187:%.*]] = sext i8 [[TMP122]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV188:%.*]] = sext i8 [[TMP123]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP189:%.*]] = icmp eq i32 [[CONV187]], [[CONV188]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP189]], label [[IF_THEN191:%.*]], label [[IF_ELSE192:%.*]]
|
|
// SIMD-ONLY0: if.then191:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP124]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END193:%.*]]
|
|
// SIMD-ONLY0: if.else192:
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP125]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END193]]
|
|
// SIMD-ONLY0: if.end193:
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV194:%.*]] = sext i8 [[TMP126]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV195:%.*]] = sext i8 [[TMP127]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP196:%.*]] = icmp eq i32 [[CONV194]], [[CONV195]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP196]], label [[IF_THEN198:%.*]], label [[IF_ELSE199:%.*]]
|
|
// SIMD-ONLY0: if.then198:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP128]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END200:%.*]]
|
|
// SIMD-ONLY0: if.else199:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP129]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END200]]
|
|
// SIMD-ONLY0: if.end200:
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV201:%.*]] = sext i8 [[TMP130]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV202:%.*]] = sext i8 [[TMP131]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP203:%.*]] = icmp eq i32 [[CONV201]], [[CONV202]]
|
|
// SIMD-ONLY0-NEXT: [[CONV204:%.*]] = zext i1 [[CMP203]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV205:%.*]] = trunc i32 [[CONV204]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV205]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL206:%.*]] = icmp ne i8 [[TMP132]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL206]], label [[IF_THEN207:%.*]], label [[IF_END208:%.*]]
|
|
// SIMD-ONLY0: if.then207:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP133]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END208]]
|
|
// SIMD-ONLY0: if.end208:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV209:%.*]] = sext i8 [[TMP134]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV210:%.*]] = sext i8 [[TMP135]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP211:%.*]] = icmp eq i32 [[CONV209]], [[CONV210]]
|
|
// SIMD-ONLY0-NEXT: [[CONV212:%.*]] = zext i1 [[CMP211]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV213:%.*]] = trunc i32 [[CONV212]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV213]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL214:%.*]] = icmp ne i8 [[TMP136]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL214]], label [[IF_THEN215:%.*]], label [[IF_END216:%.*]]
|
|
// SIMD-ONLY0: if.then215:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP137]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END216]]
|
|
// SIMD-ONLY0: if.end216:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV217:%.*]] = sext i8 [[TMP138]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV218:%.*]] = sext i8 [[TMP139]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP219:%.*]] = icmp eq i32 [[CONV217]], [[CONV218]]
|
|
// SIMD-ONLY0-NEXT: [[CONV220:%.*]] = zext i1 [[CMP219]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV221:%.*]] = trunc i32 [[CONV220]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV221]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL222:%.*]] = icmp ne i8 [[TMP140]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL222]], label [[IF_THEN223:%.*]], label [[IF_ELSE224:%.*]]
|
|
// SIMD-ONLY0: if.then223:
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP141]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END225:%.*]]
|
|
// SIMD-ONLY0: if.else224:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP142]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END225]]
|
|
// SIMD-ONLY0: if.end225:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV226:%.*]] = sext i8 [[TMP143]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV227:%.*]] = sext i8 [[TMP144]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP228:%.*]] = icmp eq i32 [[CONV226]], [[CONV227]]
|
|
// SIMD-ONLY0-NEXT: [[CONV229:%.*]] = zext i1 [[CMP228]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV230:%.*]] = trunc i32 [[CONV229]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV230]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL231:%.*]] = icmp ne i8 [[TMP145]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL231]], label [[IF_THEN232:%.*]], label [[IF_ELSE233:%.*]]
|
|
// SIMD-ONLY0: if.then232:
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP146]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END234:%.*]]
|
|
// SIMD-ONLY0: if.else233:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP147]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END234]]
|
|
// SIMD-ONLY0: if.end234:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP148]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV235:%.*]] = sext i8 [[TMP149]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV236:%.*]] = sext i8 [[TMP150]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP237:%.*]] = icmp sgt i32 [[CONV235]], [[CONV236]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP237]], label [[IF_THEN239:%.*]], label [[IF_END240:%.*]]
|
|
// SIMD-ONLY0: if.then239:
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP151]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END240]]
|
|
// SIMD-ONLY0: if.end240:
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP152]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV241:%.*]] = sext i8 [[TMP153]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV242:%.*]] = sext i8 [[TMP154]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP243:%.*]] = icmp sgt i32 [[CONV241]], [[CONV242]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP243]], label [[IF_THEN245:%.*]], label [[IF_END246:%.*]]
|
|
// SIMD-ONLY0: if.then245:
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP155]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END246]]
|
|
// SIMD-ONLY0: if.end246:
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP156]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV247:%.*]] = sext i8 [[TMP157]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV248:%.*]] = sext i8 [[TMP158]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP249:%.*]] = icmp slt i32 [[CONV247]], [[CONV248]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP249]], label [[IF_THEN251:%.*]], label [[IF_END252:%.*]]
|
|
// SIMD-ONLY0: if.then251:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP159]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END252]]
|
|
// SIMD-ONLY0: if.end252:
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP160]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV253:%.*]] = sext i8 [[TMP161]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV254:%.*]] = sext i8 [[TMP162]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP255:%.*]] = icmp slt i32 [[CONV253]], [[CONV254]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP255]], label [[IF_THEN257:%.*]], label [[IF_END258:%.*]]
|
|
// SIMD-ONLY0: if.then257:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP163]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END258]]
|
|
// SIMD-ONLY0: if.end258:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP164]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV259:%.*]] = sext i8 [[TMP165]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV260:%.*]] = sext i8 [[TMP166]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP261:%.*]] = icmp eq i32 [[CONV259]], [[CONV260]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP261]], label [[IF_THEN263:%.*]], label [[IF_END264:%.*]]
|
|
// SIMD-ONLY0: if.then263:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP167]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END264]]
|
|
// SIMD-ONLY0: if.end264:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP168]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV265:%.*]] = sext i8 [[TMP169]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV266:%.*]] = sext i8 [[TMP170]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP267:%.*]] = icmp eq i32 [[CONV265]], [[CONV266]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP267]], label [[IF_THEN269:%.*]], label [[IF_END270:%.*]]
|
|
// SIMD-ONLY0: if.then269:
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP171]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END270]]
|
|
// SIMD-ONLY0: if.end270:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV271:%.*]] = sext i8 [[TMP172]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV272:%.*]] = sext i8 [[TMP173]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP273:%.*]] = icmp sgt i32 [[CONV271]], [[CONV272]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP273]], label [[IF_THEN275:%.*]], label [[IF_END276:%.*]]
|
|
// SIMD-ONLY0: if.then275:
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP174]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END276]]
|
|
// SIMD-ONLY0: if.end276:
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP175]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV277:%.*]] = sext i8 [[TMP176]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV278:%.*]] = sext i8 [[TMP177]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP279:%.*]] = icmp sgt i32 [[CONV277]], [[CONV278]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP279]], label [[IF_THEN281:%.*]], label [[IF_END282:%.*]]
|
|
// SIMD-ONLY0: if.then281:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP178]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END282]]
|
|
// SIMD-ONLY0: if.end282:
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP179]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV283:%.*]] = sext i8 [[TMP180]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP181:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV284:%.*]] = sext i8 [[TMP181]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP285:%.*]] = icmp slt i32 [[CONV283]], [[CONV284]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP285]], label [[IF_THEN287:%.*]], label [[IF_END288:%.*]]
|
|
// SIMD-ONLY0: if.then287:
|
|
// SIMD-ONLY0-NEXT: [[TMP182:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP182]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END288]]
|
|
// SIMD-ONLY0: if.end288:
|
|
// SIMD-ONLY0-NEXT: [[TMP183:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP183]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP184:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV289:%.*]] = sext i8 [[TMP184]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP185:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV290:%.*]] = sext i8 [[TMP185]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP291:%.*]] = icmp slt i32 [[CONV289]], [[CONV290]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP291]], label [[IF_THEN293:%.*]], label [[IF_END294:%.*]]
|
|
// SIMD-ONLY0: if.then293:
|
|
// SIMD-ONLY0-NEXT: [[TMP186:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP186]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END294]]
|
|
// SIMD-ONLY0: if.end294:
|
|
// SIMD-ONLY0-NEXT: [[TMP187:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP187]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP188:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV295:%.*]] = sext i8 [[TMP188]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP189:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV296:%.*]] = sext i8 [[TMP189]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP297:%.*]] = icmp eq i32 [[CONV295]], [[CONV296]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP297]], label [[IF_THEN299:%.*]], label [[IF_END300:%.*]]
|
|
// SIMD-ONLY0: if.then299:
|
|
// SIMD-ONLY0-NEXT: [[TMP190:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP190]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END300]]
|
|
// SIMD-ONLY0: if.end300:
|
|
// SIMD-ONLY0-NEXT: [[TMP191:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP191]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP192:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV301:%.*]] = sext i8 [[TMP192]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP193:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV302:%.*]] = sext i8 [[TMP193]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP303:%.*]] = icmp eq i32 [[CONV301]], [[CONV302]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP303]], label [[IF_THEN305:%.*]], label [[IF_END306:%.*]]
|
|
// SIMD-ONLY0: if.then305:
|
|
// SIMD-ONLY0-NEXT: [[TMP194:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP194]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END306]]
|
|
// SIMD-ONLY0: if.end306:
|
|
// SIMD-ONLY0-NEXT: [[TMP195:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP195]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP196:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV307:%.*]] = sext i8 [[TMP196]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP197:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV308:%.*]] = sext i8 [[TMP197]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP309:%.*]] = icmp eq i32 [[CONV307]], [[CONV308]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP309]], label [[IF_THEN311:%.*]], label [[IF_ELSE312:%.*]]
|
|
// SIMD-ONLY0: if.then311:
|
|
// SIMD-ONLY0-NEXT: [[TMP198:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP198]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END313:%.*]]
|
|
// SIMD-ONLY0: if.else312:
|
|
// SIMD-ONLY0-NEXT: [[TMP199:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP199]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END313]]
|
|
// SIMD-ONLY0: if.end313:
|
|
// SIMD-ONLY0-NEXT: [[TMP200:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV314:%.*]] = sext i8 [[TMP200]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP201:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV315:%.*]] = sext i8 [[TMP201]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP316]], label [[IF_THEN318:%.*]], label [[IF_ELSE319:%.*]]
|
|
// SIMD-ONLY0: if.then318:
|
|
// SIMD-ONLY0-NEXT: [[TMP202:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP202]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END320:%.*]]
|
|
// SIMD-ONLY0: if.else319:
|
|
// SIMD-ONLY0-NEXT: [[TMP203:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP203]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END320]]
|
|
// SIMD-ONLY0: if.end320:
|
|
// SIMD-ONLY0-NEXT: [[TMP204:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV321:%.*]] = sext i8 [[TMP204]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP205:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV322:%.*]] = sext i8 [[TMP205]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP323:%.*]] = icmp eq i32 [[CONV321]], [[CONV322]]
|
|
// SIMD-ONLY0-NEXT: [[CONV324:%.*]] = zext i1 [[CMP323]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV325:%.*]] = trunc i32 [[CONV324]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV325]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP206:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL326:%.*]] = icmp ne i8 [[TMP206]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL326]], label [[IF_THEN327:%.*]], label [[IF_END328:%.*]]
|
|
// SIMD-ONLY0: if.then327:
|
|
// SIMD-ONLY0-NEXT: [[TMP207:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP207]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END328]]
|
|
// SIMD-ONLY0: if.end328:
|
|
// SIMD-ONLY0-NEXT: [[TMP208:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV329:%.*]] = sext i8 [[TMP208]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP209:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV330:%.*]] = sext i8 [[TMP209]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP331:%.*]] = icmp eq i32 [[CONV329]], [[CONV330]]
|
|
// SIMD-ONLY0-NEXT: [[CONV332:%.*]] = zext i1 [[CMP331]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV333:%.*]] = trunc i32 [[CONV332]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV333]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP210:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL334:%.*]] = icmp ne i8 [[TMP210]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL334]], label [[IF_THEN335:%.*]], label [[IF_END336:%.*]]
|
|
// SIMD-ONLY0: if.then335:
|
|
// SIMD-ONLY0-NEXT: [[TMP211:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP211]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END336]]
|
|
// SIMD-ONLY0: if.end336:
|
|
// SIMD-ONLY0-NEXT: [[TMP212:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV337:%.*]] = sext i8 [[TMP212]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP213:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV338:%.*]] = sext i8 [[TMP213]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP339:%.*]] = icmp eq i32 [[CONV337]], [[CONV338]]
|
|
// SIMD-ONLY0-NEXT: [[CONV340:%.*]] = zext i1 [[CMP339]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV341:%.*]] = trunc i32 [[CONV340]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV341]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP214:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL342:%.*]] = icmp ne i8 [[TMP214]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL342]], label [[IF_THEN343:%.*]], label [[IF_ELSE344:%.*]]
|
|
// SIMD-ONLY0: if.then343:
|
|
// SIMD-ONLY0-NEXT: [[TMP215:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP215]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END345:%.*]]
|
|
// SIMD-ONLY0: if.else344:
|
|
// SIMD-ONLY0-NEXT: [[TMP216:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP216]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END345]]
|
|
// SIMD-ONLY0: if.end345:
|
|
// SIMD-ONLY0-NEXT: [[TMP217:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV346:%.*]] = sext i8 [[TMP217]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP218:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV347:%.*]] = sext i8 [[TMP218]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP348:%.*]] = icmp eq i32 [[CONV346]], [[CONV347]]
|
|
// SIMD-ONLY0-NEXT: [[CONV349:%.*]] = zext i1 [[CMP348]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV350:%.*]] = trunc i32 [[CONV349]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV350]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP219:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL351:%.*]] = icmp ne i8 [[TMP219]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL351]], label [[IF_THEN352:%.*]], label [[IF_ELSE353:%.*]]
|
|
// SIMD-ONLY0: if.then352:
|
|
// SIMD-ONLY0-NEXT: [[TMP220:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP220]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END354:%.*]]
|
|
// SIMD-ONLY0: if.else353:
|
|
// SIMD-ONLY0-NEXT: [[TMP221:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP221]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END354]]
|
|
// SIMD-ONLY0: if.end354:
|
|
// SIMD-ONLY0-NEXT: [[TMP222:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP222]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP223:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV355:%.*]] = sext i8 [[TMP223]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP224:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV356:%.*]] = sext i8 [[TMP224]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP357:%.*]] = icmp sgt i32 [[CONV355]], [[CONV356]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP357]], label [[IF_THEN359:%.*]], label [[IF_END360:%.*]]
|
|
// SIMD-ONLY0: if.then359:
|
|
// SIMD-ONLY0-NEXT: [[TMP225:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP225]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END360]]
|
|
// SIMD-ONLY0: if.end360:
|
|
// SIMD-ONLY0-NEXT: [[TMP226:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP226]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP227:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV361:%.*]] = sext i8 [[TMP227]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP228:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV362:%.*]] = sext i8 [[TMP228]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP363:%.*]] = icmp sgt i32 [[CONV361]], [[CONV362]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP363]], label [[IF_THEN365:%.*]], label [[IF_END366:%.*]]
|
|
// SIMD-ONLY0: if.then365:
|
|
// SIMD-ONLY0-NEXT: [[TMP229:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP229]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END366]]
|
|
// SIMD-ONLY0: if.end366:
|
|
// SIMD-ONLY0-NEXT: [[TMP230:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP230]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP231:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV367:%.*]] = sext i8 [[TMP231]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP232:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV368:%.*]] = sext i8 [[TMP232]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP369:%.*]] = icmp slt i32 [[CONV367]], [[CONV368]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP369]], label [[IF_THEN371:%.*]], label [[IF_END372:%.*]]
|
|
// SIMD-ONLY0: if.then371:
|
|
// SIMD-ONLY0-NEXT: [[TMP233:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP233]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END372]]
|
|
// SIMD-ONLY0: if.end372:
|
|
// SIMD-ONLY0-NEXT: [[TMP234:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP234]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP235:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV373:%.*]] = sext i8 [[TMP235]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP236:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV374:%.*]] = sext i8 [[TMP236]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP375:%.*]] = icmp slt i32 [[CONV373]], [[CONV374]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP375]], label [[IF_THEN377:%.*]], label [[IF_END378:%.*]]
|
|
// SIMD-ONLY0: if.then377:
|
|
// SIMD-ONLY0-NEXT: [[TMP237:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP237]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END378]]
|
|
// SIMD-ONLY0: if.end378:
|
|
// SIMD-ONLY0-NEXT: [[TMP238:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP238]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP239:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV379:%.*]] = sext i8 [[TMP239]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP240:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV380:%.*]] = sext i8 [[TMP240]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP381:%.*]] = icmp eq i32 [[CONV379]], [[CONV380]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP381]], label [[IF_THEN383:%.*]], label [[IF_END384:%.*]]
|
|
// SIMD-ONLY0: if.then383:
|
|
// SIMD-ONLY0-NEXT: [[TMP241:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP241]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END384]]
|
|
// SIMD-ONLY0: if.end384:
|
|
// SIMD-ONLY0-NEXT: [[TMP242:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP242]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP243:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV385:%.*]] = sext i8 [[TMP243]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP244:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV386:%.*]] = sext i8 [[TMP244]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP387:%.*]] = icmp eq i32 [[CONV385]], [[CONV386]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP387]], label [[IF_THEN389:%.*]], label [[IF_END390:%.*]]
|
|
// SIMD-ONLY0: if.then389:
|
|
// SIMD-ONLY0-NEXT: [[TMP245:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP245]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END390]]
|
|
// SIMD-ONLY0: if.end390:
|
|
// SIMD-ONLY0-NEXT: [[TMP246:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV391:%.*]] = sext i8 [[TMP246]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP247:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV392:%.*]] = sext i8 [[TMP247]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP393:%.*]] = icmp sgt i32 [[CONV391]], [[CONV392]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP393]], label [[IF_THEN395:%.*]], label [[IF_END396:%.*]]
|
|
// SIMD-ONLY0: if.then395:
|
|
// SIMD-ONLY0-NEXT: [[TMP248:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP248]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END396]]
|
|
// SIMD-ONLY0: if.end396:
|
|
// SIMD-ONLY0-NEXT: [[TMP249:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP249]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP250:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV397:%.*]] = sext i8 [[TMP250]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP251:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV398:%.*]] = sext i8 [[TMP251]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP399:%.*]] = icmp sgt i32 [[CONV397]], [[CONV398]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP399]], label [[IF_THEN401:%.*]], label [[IF_END402:%.*]]
|
|
// SIMD-ONLY0: if.then401:
|
|
// SIMD-ONLY0-NEXT: [[TMP252:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP252]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END402]]
|
|
// SIMD-ONLY0: if.end402:
|
|
// SIMD-ONLY0-NEXT: [[TMP253:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP253]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP254:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV403:%.*]] = sext i8 [[TMP254]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP255:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV404:%.*]] = sext i8 [[TMP255]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP405:%.*]] = icmp slt i32 [[CONV403]], [[CONV404]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP405]], label [[IF_THEN407:%.*]], label [[IF_END408:%.*]]
|
|
// SIMD-ONLY0: if.then407:
|
|
// SIMD-ONLY0-NEXT: [[TMP256:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP256]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END408]]
|
|
// SIMD-ONLY0: if.end408:
|
|
// SIMD-ONLY0-NEXT: [[TMP257:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP257]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP258:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV409:%.*]] = sext i8 [[TMP258]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP259:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV410:%.*]] = sext i8 [[TMP259]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP411:%.*]] = icmp slt i32 [[CONV409]], [[CONV410]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP411]], label [[IF_THEN413:%.*]], label [[IF_END414:%.*]]
|
|
// SIMD-ONLY0: if.then413:
|
|
// SIMD-ONLY0-NEXT: [[TMP260:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP260]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END414]]
|
|
// SIMD-ONLY0: if.end414:
|
|
// SIMD-ONLY0-NEXT: [[TMP261:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP261]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP262:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV415:%.*]] = sext i8 [[TMP262]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP263:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV416:%.*]] = sext i8 [[TMP263]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP417:%.*]] = icmp eq i32 [[CONV415]], [[CONV416]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP417]], label [[IF_THEN419:%.*]], label [[IF_END420:%.*]]
|
|
// SIMD-ONLY0: if.then419:
|
|
// SIMD-ONLY0-NEXT: [[TMP264:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP264]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END420]]
|
|
// SIMD-ONLY0: if.end420:
|
|
// SIMD-ONLY0-NEXT: [[TMP265:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP265]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP266:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV421:%.*]] = sext i8 [[TMP266]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP267:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV422:%.*]] = sext i8 [[TMP267]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP423:%.*]] = icmp eq i32 [[CONV421]], [[CONV422]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP423]], label [[IF_THEN425:%.*]], label [[IF_END426:%.*]]
|
|
// SIMD-ONLY0: if.then425:
|
|
// SIMD-ONLY0-NEXT: [[TMP268:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP268]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END426]]
|
|
// SIMD-ONLY0: if.end426:
|
|
// SIMD-ONLY0-NEXT: [[TMP269:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP269]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP270:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV427:%.*]] = sext i8 [[TMP270]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP271:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV428:%.*]] = sext i8 [[TMP271]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP429:%.*]] = icmp eq i32 [[CONV427]], [[CONV428]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP429]], label [[IF_THEN431:%.*]], label [[IF_ELSE432:%.*]]
|
|
// SIMD-ONLY0: if.then431:
|
|
// SIMD-ONLY0-NEXT: [[TMP272:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP272]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END433:%.*]]
|
|
// SIMD-ONLY0: if.else432:
|
|
// SIMD-ONLY0-NEXT: [[TMP273:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP273]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END433]]
|
|
// SIMD-ONLY0: if.end433:
|
|
// SIMD-ONLY0-NEXT: [[TMP274:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV434:%.*]] = sext i8 [[TMP274]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP275:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV435:%.*]] = sext i8 [[TMP275]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP436:%.*]] = icmp eq i32 [[CONV434]], [[CONV435]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP436]], label [[IF_THEN438:%.*]], label [[IF_ELSE439:%.*]]
|
|
// SIMD-ONLY0: if.then438:
|
|
// SIMD-ONLY0-NEXT: [[TMP276:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP276]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END440:%.*]]
|
|
// SIMD-ONLY0: if.else439:
|
|
// SIMD-ONLY0-NEXT: [[TMP277:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP277]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END440]]
|
|
// SIMD-ONLY0: if.end440:
|
|
// SIMD-ONLY0-NEXT: [[TMP278:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV441:%.*]] = sext i8 [[TMP278]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP279:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV442:%.*]] = sext i8 [[TMP279]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP443:%.*]] = icmp eq i32 [[CONV441]], [[CONV442]]
|
|
// SIMD-ONLY0-NEXT: [[CONV444:%.*]] = zext i1 [[CMP443]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV445:%.*]] = trunc i32 [[CONV444]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV445]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP280:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL446:%.*]] = icmp ne i8 [[TMP280]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL446]], label [[IF_THEN447:%.*]], label [[IF_END448:%.*]]
|
|
// SIMD-ONLY0: if.then447:
|
|
// SIMD-ONLY0-NEXT: [[TMP281:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP281]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END448]]
|
|
// SIMD-ONLY0: if.end448:
|
|
// SIMD-ONLY0-NEXT: [[TMP282:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV449:%.*]] = sext i8 [[TMP282]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP283:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV450:%.*]] = sext i8 [[TMP283]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP451:%.*]] = icmp eq i32 [[CONV449]], [[CONV450]]
|
|
// SIMD-ONLY0-NEXT: [[CONV452:%.*]] = zext i1 [[CMP451]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV453:%.*]] = trunc i32 [[CONV452]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV453]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP284:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL454:%.*]] = icmp ne i8 [[TMP284]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL454]], label [[IF_THEN455:%.*]], label [[IF_END456:%.*]]
|
|
// SIMD-ONLY0: if.then455:
|
|
// SIMD-ONLY0-NEXT: [[TMP285:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP285]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END456]]
|
|
// SIMD-ONLY0: if.end456:
|
|
// SIMD-ONLY0-NEXT: [[TMP286:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV457:%.*]] = sext i8 [[TMP286]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP287:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV458:%.*]] = sext i8 [[TMP287]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP459:%.*]] = icmp eq i32 [[CONV457]], [[CONV458]]
|
|
// SIMD-ONLY0-NEXT: [[CONV460:%.*]] = zext i1 [[CMP459]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV461:%.*]] = trunc i32 [[CONV460]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV461]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP288:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL462:%.*]] = icmp ne i8 [[TMP288]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL462]], label [[IF_THEN463:%.*]], label [[IF_ELSE464:%.*]]
|
|
// SIMD-ONLY0: if.then463:
|
|
// SIMD-ONLY0-NEXT: [[TMP289:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP289]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END465:%.*]]
|
|
// SIMD-ONLY0: if.else464:
|
|
// SIMD-ONLY0-NEXT: [[TMP290:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP290]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END465]]
|
|
// SIMD-ONLY0: if.end465:
|
|
// SIMD-ONLY0-NEXT: [[TMP291:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV466:%.*]] = sext i8 [[TMP291]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP292:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV467:%.*]] = sext i8 [[TMP292]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP468:%.*]] = icmp eq i32 [[CONV466]], [[CONV467]]
|
|
// SIMD-ONLY0-NEXT: [[CONV469:%.*]] = zext i1 [[CMP468]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV470:%.*]] = trunc i32 [[CONV469]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV470]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP293:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL471:%.*]] = icmp ne i8 [[TMP293]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL471]], label [[IF_THEN472:%.*]], label [[IF_ELSE473:%.*]]
|
|
// SIMD-ONLY0: if.then472:
|
|
// SIMD-ONLY0-NEXT: [[TMP294:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP294]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END474:%.*]]
|
|
// SIMD-ONLY0: if.else473:
|
|
// SIMD-ONLY0-NEXT: [[TMP295:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP295]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END474]]
|
|
// SIMD-ONLY0: if.end474:
|
|
// SIMD-ONLY0-NEXT: [[TMP296:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP296]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP297:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV475:%.*]] = sext i8 [[TMP297]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP298:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV476:%.*]] = sext i8 [[TMP298]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP477:%.*]] = icmp sgt i32 [[CONV475]], [[CONV476]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP477]], label [[IF_THEN479:%.*]], label [[IF_END480:%.*]]
|
|
// SIMD-ONLY0: if.then479:
|
|
// SIMD-ONLY0-NEXT: [[TMP299:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP299]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END480]]
|
|
// SIMD-ONLY0: if.end480:
|
|
// SIMD-ONLY0-NEXT: [[TMP300:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP300]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP301:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV481:%.*]] = sext i8 [[TMP301]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP302:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV482:%.*]] = sext i8 [[TMP302]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP483:%.*]] = icmp sgt i32 [[CONV481]], [[CONV482]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP483]], label [[IF_THEN485:%.*]], label [[IF_END486:%.*]]
|
|
// SIMD-ONLY0: if.then485:
|
|
// SIMD-ONLY0-NEXT: [[TMP303:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP303]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END486]]
|
|
// SIMD-ONLY0: if.end486:
|
|
// SIMD-ONLY0-NEXT: [[TMP304:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP304]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP305:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV487:%.*]] = sext i8 [[TMP305]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP306:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV488:%.*]] = sext i8 [[TMP306]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP489:%.*]] = icmp slt i32 [[CONV487]], [[CONV488]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP489]], label [[IF_THEN491:%.*]], label [[IF_END492:%.*]]
|
|
// SIMD-ONLY0: if.then491:
|
|
// SIMD-ONLY0-NEXT: [[TMP307:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP307]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END492]]
|
|
// SIMD-ONLY0: if.end492:
|
|
// SIMD-ONLY0-NEXT: [[TMP308:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP308]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP309:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV493:%.*]] = sext i8 [[TMP309]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP310:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV494:%.*]] = sext i8 [[TMP310]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP495:%.*]] = icmp slt i32 [[CONV493]], [[CONV494]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP495]], label [[IF_THEN497:%.*]], label [[IF_END498:%.*]]
|
|
// SIMD-ONLY0: if.then497:
|
|
// SIMD-ONLY0-NEXT: [[TMP311:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP311]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END498]]
|
|
// SIMD-ONLY0: if.end498:
|
|
// SIMD-ONLY0-NEXT: [[TMP312:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP312]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP313:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV499:%.*]] = sext i8 [[TMP313]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP314:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV500:%.*]] = sext i8 [[TMP314]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP501:%.*]] = icmp eq i32 [[CONV499]], [[CONV500]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP501]], label [[IF_THEN503:%.*]], label [[IF_END504:%.*]]
|
|
// SIMD-ONLY0: if.then503:
|
|
// SIMD-ONLY0-NEXT: [[TMP315:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP315]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END504]]
|
|
// SIMD-ONLY0: if.end504:
|
|
// SIMD-ONLY0-NEXT: [[TMP316:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP316]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP317:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV505:%.*]] = sext i8 [[TMP317]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP318:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV506:%.*]] = sext i8 [[TMP318]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP507:%.*]] = icmp eq i32 [[CONV505]], [[CONV506]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP507]], label [[IF_THEN509:%.*]], label [[IF_END510:%.*]]
|
|
// SIMD-ONLY0: if.then509:
|
|
// SIMD-ONLY0-NEXT: [[TMP319:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP319]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END510]]
|
|
// SIMD-ONLY0: if.end510:
|
|
// SIMD-ONLY0-NEXT: [[TMP320:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV511:%.*]] = sext i8 [[TMP320]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP321:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV512:%.*]] = sext i8 [[TMP321]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP513:%.*]] = icmp sgt i32 [[CONV511]], [[CONV512]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP513]], label [[IF_THEN515:%.*]], label [[IF_END516:%.*]]
|
|
// SIMD-ONLY0: if.then515:
|
|
// SIMD-ONLY0-NEXT: [[TMP322:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP322]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END516]]
|
|
// SIMD-ONLY0: if.end516:
|
|
// SIMD-ONLY0-NEXT: [[TMP323:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP323]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP324:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV517:%.*]] = sext i8 [[TMP324]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP325:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV518:%.*]] = sext i8 [[TMP325]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP519:%.*]] = icmp sgt i32 [[CONV517]], [[CONV518]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP519]], label [[IF_THEN521:%.*]], label [[IF_END522:%.*]]
|
|
// SIMD-ONLY0: if.then521:
|
|
// SIMD-ONLY0-NEXT: [[TMP326:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP326]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END522]]
|
|
// SIMD-ONLY0: if.end522:
|
|
// SIMD-ONLY0-NEXT: [[TMP327:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP327]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP328:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV523:%.*]] = sext i8 [[TMP328]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP329:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV524:%.*]] = sext i8 [[TMP329]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP525:%.*]] = icmp slt i32 [[CONV523]], [[CONV524]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP525]], label [[IF_THEN527:%.*]], label [[IF_END528:%.*]]
|
|
// SIMD-ONLY0: if.then527:
|
|
// SIMD-ONLY0-NEXT: [[TMP330:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP330]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END528]]
|
|
// SIMD-ONLY0: if.end528:
|
|
// SIMD-ONLY0-NEXT: [[TMP331:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP331]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP332:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV529:%.*]] = sext i8 [[TMP332]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP333:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV530:%.*]] = sext i8 [[TMP333]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP531:%.*]] = icmp slt i32 [[CONV529]], [[CONV530]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP531]], label [[IF_THEN533:%.*]], label [[IF_END534:%.*]]
|
|
// SIMD-ONLY0: if.then533:
|
|
// SIMD-ONLY0-NEXT: [[TMP334:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP334]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END534]]
|
|
// SIMD-ONLY0: if.end534:
|
|
// SIMD-ONLY0-NEXT: [[TMP335:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP335]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP336:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV535:%.*]] = sext i8 [[TMP336]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP337:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV536:%.*]] = sext i8 [[TMP337]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP537:%.*]] = icmp eq i32 [[CONV535]], [[CONV536]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP537]], label [[IF_THEN539:%.*]], label [[IF_END540:%.*]]
|
|
// SIMD-ONLY0: if.then539:
|
|
// SIMD-ONLY0-NEXT: [[TMP338:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP338]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END540]]
|
|
// SIMD-ONLY0: if.end540:
|
|
// SIMD-ONLY0-NEXT: [[TMP339:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP339]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP340:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV541:%.*]] = sext i8 [[TMP340]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP341:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV542:%.*]] = sext i8 [[TMP341]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP543:%.*]] = icmp eq i32 [[CONV541]], [[CONV542]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP543]], label [[IF_THEN545:%.*]], label [[IF_END546:%.*]]
|
|
// SIMD-ONLY0: if.then545:
|
|
// SIMD-ONLY0-NEXT: [[TMP342:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP342]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END546]]
|
|
// SIMD-ONLY0: if.end546:
|
|
// SIMD-ONLY0-NEXT: [[TMP343:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP343]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP344:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV547:%.*]] = sext i8 [[TMP344]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP345:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV548:%.*]] = sext i8 [[TMP345]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP549:%.*]] = icmp eq i32 [[CONV547]], [[CONV548]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP549]], label [[IF_THEN551:%.*]], label [[IF_ELSE552:%.*]]
|
|
// SIMD-ONLY0: if.then551:
|
|
// SIMD-ONLY0-NEXT: [[TMP346:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP346]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END553:%.*]]
|
|
// SIMD-ONLY0: if.else552:
|
|
// SIMD-ONLY0-NEXT: [[TMP347:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP347]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END553]]
|
|
// SIMD-ONLY0: if.end553:
|
|
// SIMD-ONLY0-NEXT: [[TMP348:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV554:%.*]] = sext i8 [[TMP348]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP349:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV555:%.*]] = sext i8 [[TMP349]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP556:%.*]] = icmp eq i32 [[CONV554]], [[CONV555]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP556]], label [[IF_THEN558:%.*]], label [[IF_ELSE559:%.*]]
|
|
// SIMD-ONLY0: if.then558:
|
|
// SIMD-ONLY0-NEXT: [[TMP350:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP350]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END560:%.*]]
|
|
// SIMD-ONLY0: if.else559:
|
|
// SIMD-ONLY0-NEXT: [[TMP351:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP351]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END560]]
|
|
// SIMD-ONLY0: if.end560:
|
|
// SIMD-ONLY0-NEXT: [[TMP352:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV561:%.*]] = sext i8 [[TMP352]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP353:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV562:%.*]] = sext i8 [[TMP353]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP563:%.*]] = icmp eq i32 [[CONV561]], [[CONV562]]
|
|
// SIMD-ONLY0-NEXT: [[CONV564:%.*]] = zext i1 [[CMP563]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV565:%.*]] = trunc i32 [[CONV564]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV565]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP354:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL566:%.*]] = icmp ne i8 [[TMP354]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL566]], label [[IF_THEN567:%.*]], label [[IF_END568:%.*]]
|
|
// SIMD-ONLY0: if.then567:
|
|
// SIMD-ONLY0-NEXT: [[TMP355:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP355]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END568]]
|
|
// SIMD-ONLY0: if.end568:
|
|
// SIMD-ONLY0-NEXT: [[TMP356:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV569:%.*]] = sext i8 [[TMP356]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP357:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV570:%.*]] = sext i8 [[TMP357]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP571:%.*]] = icmp eq i32 [[CONV569]], [[CONV570]]
|
|
// SIMD-ONLY0-NEXT: [[CONV572:%.*]] = zext i1 [[CMP571]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV573:%.*]] = trunc i32 [[CONV572]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV573]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP358:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL574:%.*]] = icmp ne i8 [[TMP358]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL574]], label [[IF_THEN575:%.*]], label [[IF_END576:%.*]]
|
|
// SIMD-ONLY0: if.then575:
|
|
// SIMD-ONLY0-NEXT: [[TMP359:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP359]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END576]]
|
|
// SIMD-ONLY0: if.end576:
|
|
// SIMD-ONLY0-NEXT: [[TMP360:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV577:%.*]] = sext i8 [[TMP360]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP361:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV578:%.*]] = sext i8 [[TMP361]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP579:%.*]] = icmp eq i32 [[CONV577]], [[CONV578]]
|
|
// SIMD-ONLY0-NEXT: [[CONV580:%.*]] = zext i1 [[CMP579]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV581:%.*]] = trunc i32 [[CONV580]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV581]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP362:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL582:%.*]] = icmp ne i8 [[TMP362]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL582]], label [[IF_THEN583:%.*]], label [[IF_ELSE584:%.*]]
|
|
// SIMD-ONLY0: if.then583:
|
|
// SIMD-ONLY0-NEXT: [[TMP363:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP363]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END585:%.*]]
|
|
// SIMD-ONLY0: if.else584:
|
|
// SIMD-ONLY0-NEXT: [[TMP364:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP364]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END585]]
|
|
// SIMD-ONLY0: if.end585:
|
|
// SIMD-ONLY0-NEXT: [[TMP365:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV586:%.*]] = sext i8 [[TMP365]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP366:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV587:%.*]] = sext i8 [[TMP366]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP588:%.*]] = icmp eq i32 [[CONV586]], [[CONV587]]
|
|
// SIMD-ONLY0-NEXT: [[CONV589:%.*]] = zext i1 [[CMP588]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV590:%.*]] = trunc i32 [[CONV589]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV590]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP367:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL591:%.*]] = icmp ne i8 [[TMP367]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL591]], label [[IF_THEN592:%.*]], label [[IF_ELSE593:%.*]]
|
|
// SIMD-ONLY0: if.then592:
|
|
// SIMD-ONLY0-NEXT: [[TMP368:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP368]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END594:%.*]]
|
|
// SIMD-ONLY0: if.else593:
|
|
// SIMD-ONLY0-NEXT: [[TMP369:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP369]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END594]]
|
|
// SIMD-ONLY0: if.end594:
|
|
// SIMD-ONLY0-NEXT: [[TMP370:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP370]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP371:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV595:%.*]] = sext i8 [[TMP371]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP372:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV596:%.*]] = sext i8 [[TMP372]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP597:%.*]] = icmp sgt i32 [[CONV595]], [[CONV596]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP597]], label [[IF_THEN599:%.*]], label [[IF_END600:%.*]]
|
|
// SIMD-ONLY0: if.then599:
|
|
// SIMD-ONLY0-NEXT: [[TMP373:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP373]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END600]]
|
|
// SIMD-ONLY0: if.end600:
|
|
// SIMD-ONLY0-NEXT: [[TMP374:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP374]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP375:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV601:%.*]] = sext i8 [[TMP375]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP376:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV602:%.*]] = sext i8 [[TMP376]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP603:%.*]] = icmp sgt i32 [[CONV601]], [[CONV602]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP603]], label [[IF_THEN605:%.*]], label [[IF_END606:%.*]]
|
|
// SIMD-ONLY0: if.then605:
|
|
// SIMD-ONLY0-NEXT: [[TMP377:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP377]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END606]]
|
|
// SIMD-ONLY0: if.end606:
|
|
// SIMD-ONLY0-NEXT: [[TMP378:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP378]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP379:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV607:%.*]] = sext i8 [[TMP379]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP380:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV608:%.*]] = sext i8 [[TMP380]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP609:%.*]] = icmp slt i32 [[CONV607]], [[CONV608]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP609]], label [[IF_THEN611:%.*]], label [[IF_END612:%.*]]
|
|
// SIMD-ONLY0: if.then611:
|
|
// SIMD-ONLY0-NEXT: [[TMP381:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP381]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END612]]
|
|
// SIMD-ONLY0: if.end612:
|
|
// SIMD-ONLY0-NEXT: [[TMP382:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP382]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP383:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV613:%.*]] = sext i8 [[TMP383]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP384:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV614:%.*]] = sext i8 [[TMP384]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP615:%.*]] = icmp slt i32 [[CONV613]], [[CONV614]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP615]], label [[IF_THEN617:%.*]], label [[IF_END618:%.*]]
|
|
// SIMD-ONLY0: if.then617:
|
|
// SIMD-ONLY0-NEXT: [[TMP385:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP385]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END618]]
|
|
// SIMD-ONLY0: if.end618:
|
|
// SIMD-ONLY0-NEXT: [[TMP386:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP386]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP387:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV619:%.*]] = sext i8 [[TMP387]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP388:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV620:%.*]] = sext i8 [[TMP388]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP621:%.*]] = icmp eq i32 [[CONV619]], [[CONV620]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP621]], label [[IF_THEN623:%.*]], label [[IF_END624:%.*]]
|
|
// SIMD-ONLY0: if.then623:
|
|
// SIMD-ONLY0-NEXT: [[TMP389:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP389]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END624]]
|
|
// SIMD-ONLY0: if.end624:
|
|
// SIMD-ONLY0-NEXT: [[TMP390:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP390]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP391:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV625:%.*]] = sext i8 [[TMP391]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP392:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV626:%.*]] = sext i8 [[TMP392]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP627:%.*]] = icmp eq i32 [[CONV625]], [[CONV626]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP627]], label [[IF_THEN629:%.*]], label [[IF_END630:%.*]]
|
|
// SIMD-ONLY0: if.then629:
|
|
// SIMD-ONLY0-NEXT: [[TMP393:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP393]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END630]]
|
|
// SIMD-ONLY0: if.end630:
|
|
// SIMD-ONLY0-NEXT: [[TMP394:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV631:%.*]] = sext i8 [[TMP394]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP395:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV632:%.*]] = sext i8 [[TMP395]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP633:%.*]] = icmp sgt i32 [[CONV631]], [[CONV632]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP633]], label [[IF_THEN635:%.*]], label [[IF_END636:%.*]]
|
|
// SIMD-ONLY0: if.then635:
|
|
// SIMD-ONLY0-NEXT: [[TMP396:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP396]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END636]]
|
|
// SIMD-ONLY0: if.end636:
|
|
// SIMD-ONLY0-NEXT: [[TMP397:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP397]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP398:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV637:%.*]] = sext i8 [[TMP398]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP399:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV638:%.*]] = sext i8 [[TMP399]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP639:%.*]] = icmp sgt i32 [[CONV637]], [[CONV638]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP639]], label [[IF_THEN641:%.*]], label [[IF_END642:%.*]]
|
|
// SIMD-ONLY0: if.then641:
|
|
// SIMD-ONLY0-NEXT: [[TMP400:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP400]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END642]]
|
|
// SIMD-ONLY0: if.end642:
|
|
// SIMD-ONLY0-NEXT: [[TMP401:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP401]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP402:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV643:%.*]] = sext i8 [[TMP402]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP403:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV644:%.*]] = sext i8 [[TMP403]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP645:%.*]] = icmp slt i32 [[CONV643]], [[CONV644]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP645]], label [[IF_THEN647:%.*]], label [[IF_END648:%.*]]
|
|
// SIMD-ONLY0: if.then647:
|
|
// SIMD-ONLY0-NEXT: [[TMP404:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP404]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END648]]
|
|
// SIMD-ONLY0: if.end648:
|
|
// SIMD-ONLY0-NEXT: [[TMP405:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP405]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP406:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV649:%.*]] = sext i8 [[TMP406]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP407:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV650:%.*]] = sext i8 [[TMP407]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP651:%.*]] = icmp slt i32 [[CONV649]], [[CONV650]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP651]], label [[IF_THEN653:%.*]], label [[IF_END654:%.*]]
|
|
// SIMD-ONLY0: if.then653:
|
|
// SIMD-ONLY0-NEXT: [[TMP408:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP408]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END654]]
|
|
// SIMD-ONLY0: if.end654:
|
|
// SIMD-ONLY0-NEXT: [[TMP409:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP409]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP410:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV655:%.*]] = sext i8 [[TMP410]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP411:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV656:%.*]] = sext i8 [[TMP411]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP657:%.*]] = icmp eq i32 [[CONV655]], [[CONV656]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP657]], label [[IF_THEN659:%.*]], label [[IF_END660:%.*]]
|
|
// SIMD-ONLY0: if.then659:
|
|
// SIMD-ONLY0-NEXT: [[TMP412:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP412]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END660]]
|
|
// SIMD-ONLY0: if.end660:
|
|
// SIMD-ONLY0-NEXT: [[TMP413:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP413]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP414:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV661:%.*]] = sext i8 [[TMP414]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP415:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV662:%.*]] = sext i8 [[TMP415]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP663:%.*]] = icmp eq i32 [[CONV661]], [[CONV662]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP663]], label [[IF_THEN665:%.*]], label [[IF_END666:%.*]]
|
|
// SIMD-ONLY0: if.then665:
|
|
// SIMD-ONLY0-NEXT: [[TMP416:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP416]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END666]]
|
|
// SIMD-ONLY0: if.end666:
|
|
// SIMD-ONLY0-NEXT: [[TMP417:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP417]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP418:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV667:%.*]] = sext i8 [[TMP418]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP419:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV668:%.*]] = sext i8 [[TMP419]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP669:%.*]] = icmp eq i32 [[CONV667]], [[CONV668]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP669]], label [[IF_THEN671:%.*]], label [[IF_ELSE672:%.*]]
|
|
// SIMD-ONLY0: if.then671:
|
|
// SIMD-ONLY0-NEXT: [[TMP420:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP420]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END673:%.*]]
|
|
// SIMD-ONLY0: if.else672:
|
|
// SIMD-ONLY0-NEXT: [[TMP421:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP421]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END673]]
|
|
// SIMD-ONLY0: if.end673:
|
|
// SIMD-ONLY0-NEXT: [[TMP422:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV674:%.*]] = sext i8 [[TMP422]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP423:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV675:%.*]] = sext i8 [[TMP423]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP676:%.*]] = icmp eq i32 [[CONV674]], [[CONV675]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP676]], label [[IF_THEN678:%.*]], label [[IF_ELSE679:%.*]]
|
|
// SIMD-ONLY0: if.then678:
|
|
// SIMD-ONLY0-NEXT: [[TMP424:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP424]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END680:%.*]]
|
|
// SIMD-ONLY0: if.else679:
|
|
// SIMD-ONLY0-NEXT: [[TMP425:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP425]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END680]]
|
|
// SIMD-ONLY0: if.end680:
|
|
// SIMD-ONLY0-NEXT: [[TMP426:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV681:%.*]] = sext i8 [[TMP426]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP427:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV682:%.*]] = sext i8 [[TMP427]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP683:%.*]] = icmp eq i32 [[CONV681]], [[CONV682]]
|
|
// SIMD-ONLY0-NEXT: [[CONV684:%.*]] = zext i1 [[CMP683]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV685:%.*]] = trunc i32 [[CONV684]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV685]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP428:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL686:%.*]] = icmp ne i8 [[TMP428]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL686]], label [[IF_THEN687:%.*]], label [[IF_END688:%.*]]
|
|
// SIMD-ONLY0: if.then687:
|
|
// SIMD-ONLY0-NEXT: [[TMP429:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP429]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END688]]
|
|
// SIMD-ONLY0: if.end688:
|
|
// SIMD-ONLY0-NEXT: [[TMP430:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV689:%.*]] = sext i8 [[TMP430]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP431:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV690:%.*]] = sext i8 [[TMP431]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP691:%.*]] = icmp eq i32 [[CONV689]], [[CONV690]]
|
|
// SIMD-ONLY0-NEXT: [[CONV692:%.*]] = zext i1 [[CMP691]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV693:%.*]] = trunc i32 [[CONV692]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV693]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP432:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL694:%.*]] = icmp ne i8 [[TMP432]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL694]], label [[IF_THEN695:%.*]], label [[IF_END696:%.*]]
|
|
// SIMD-ONLY0: if.then695:
|
|
// SIMD-ONLY0-NEXT: [[TMP433:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP433]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END696]]
|
|
// SIMD-ONLY0: if.end696:
|
|
// SIMD-ONLY0-NEXT: [[TMP434:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV697:%.*]] = sext i8 [[TMP434]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP435:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV698:%.*]] = sext i8 [[TMP435]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP699:%.*]] = icmp eq i32 [[CONV697]], [[CONV698]]
|
|
// SIMD-ONLY0-NEXT: [[CONV700:%.*]] = zext i1 [[CMP699]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV701:%.*]] = trunc i32 [[CONV700]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV701]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP436:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL702:%.*]] = icmp ne i8 [[TMP436]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL702]], label [[IF_THEN703:%.*]], label [[IF_ELSE704:%.*]]
|
|
// SIMD-ONLY0: if.then703:
|
|
// SIMD-ONLY0-NEXT: [[TMP437:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP437]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END705:%.*]]
|
|
// SIMD-ONLY0: if.else704:
|
|
// SIMD-ONLY0-NEXT: [[TMP438:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP438]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END705]]
|
|
// SIMD-ONLY0: if.end705:
|
|
// SIMD-ONLY0-NEXT: [[TMP439:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV706:%.*]] = sext i8 [[TMP439]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP440:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV707:%.*]] = sext i8 [[TMP440]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP708:%.*]] = icmp eq i32 [[CONV706]], [[CONV707]]
|
|
// SIMD-ONLY0-NEXT: [[CONV709:%.*]] = zext i1 [[CMP708]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV710:%.*]] = trunc i32 [[CONV709]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV710]], ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP441:%.*]] = load i8, ptr [[CR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL711:%.*]] = icmp ne i8 [[TMP441]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL711]], label [[IF_THEN712:%.*]], label [[IF_ELSE713:%.*]]
|
|
// SIMD-ONLY0: if.then712:
|
|
// SIMD-ONLY0-NEXT: [[TMP442:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP442]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END714:%.*]]
|
|
// SIMD-ONLY0: if.else713:
|
|
// SIMD-ONLY0-NEXT: [[TMP443:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP443]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END714]]
|
|
// SIMD-ONLY0: if.end714:
|
|
// SIMD-ONLY0-NEXT: [[TMP444:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP444]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP445:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV715:%.*]] = zext i8 [[TMP445]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP446:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV716:%.*]] = zext i8 [[TMP446]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP717:%.*]] = icmp sgt i32 [[CONV715]], [[CONV716]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP717]], label [[IF_THEN719:%.*]], label [[IF_END720:%.*]]
|
|
// SIMD-ONLY0: if.then719:
|
|
// SIMD-ONLY0-NEXT: [[TMP447:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP447]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END720]]
|
|
// SIMD-ONLY0: if.end720:
|
|
// SIMD-ONLY0-NEXT: [[TMP448:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP448]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP449:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV721:%.*]] = zext i8 [[TMP449]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP450:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV722:%.*]] = zext i8 [[TMP450]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP723:%.*]] = icmp sgt i32 [[CONV721]], [[CONV722]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP723]], label [[IF_THEN725:%.*]], label [[IF_END726:%.*]]
|
|
// SIMD-ONLY0: if.then725:
|
|
// SIMD-ONLY0-NEXT: [[TMP451:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP451]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END726]]
|
|
// SIMD-ONLY0: if.end726:
|
|
// SIMD-ONLY0-NEXT: [[TMP452:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP452]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP453:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV727:%.*]] = zext i8 [[TMP453]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP454:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV728:%.*]] = zext i8 [[TMP454]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP729:%.*]] = icmp slt i32 [[CONV727]], [[CONV728]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP729]], label [[IF_THEN731:%.*]], label [[IF_END732:%.*]]
|
|
// SIMD-ONLY0: if.then731:
|
|
// SIMD-ONLY0-NEXT: [[TMP455:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP455]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END732]]
|
|
// SIMD-ONLY0: if.end732:
|
|
// SIMD-ONLY0-NEXT: [[TMP456:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP456]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP457:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV733:%.*]] = zext i8 [[TMP457]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP458:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV734:%.*]] = zext i8 [[TMP458]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP735:%.*]] = icmp slt i32 [[CONV733]], [[CONV734]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP735]], label [[IF_THEN737:%.*]], label [[IF_END738:%.*]]
|
|
// SIMD-ONLY0: if.then737:
|
|
// SIMD-ONLY0-NEXT: [[TMP459:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP459]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END738]]
|
|
// SIMD-ONLY0: if.end738:
|
|
// SIMD-ONLY0-NEXT: [[TMP460:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP460]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP461:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV739:%.*]] = zext i8 [[TMP461]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP462:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV740:%.*]] = zext i8 [[TMP462]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP741:%.*]] = icmp eq i32 [[CONV739]], [[CONV740]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP741]], label [[IF_THEN743:%.*]], label [[IF_END744:%.*]]
|
|
// SIMD-ONLY0: if.then743:
|
|
// SIMD-ONLY0-NEXT: [[TMP463:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP463]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END744]]
|
|
// SIMD-ONLY0: if.end744:
|
|
// SIMD-ONLY0-NEXT: [[TMP464:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP464]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP465:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV745:%.*]] = zext i8 [[TMP465]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP466:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV746:%.*]] = zext i8 [[TMP466]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP747:%.*]] = icmp eq i32 [[CONV745]], [[CONV746]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP747]], label [[IF_THEN749:%.*]], label [[IF_END750:%.*]]
|
|
// SIMD-ONLY0: if.then749:
|
|
// SIMD-ONLY0-NEXT: [[TMP467:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP467]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END750]]
|
|
// SIMD-ONLY0: if.end750:
|
|
// SIMD-ONLY0-NEXT: [[TMP468:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV751:%.*]] = zext i8 [[TMP468]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP469:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV752:%.*]] = zext i8 [[TMP469]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP753:%.*]] = icmp sgt i32 [[CONV751]], [[CONV752]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP753]], label [[IF_THEN755:%.*]], label [[IF_END756:%.*]]
|
|
// SIMD-ONLY0: if.then755:
|
|
// SIMD-ONLY0-NEXT: [[TMP470:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP470]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END756]]
|
|
// SIMD-ONLY0: if.end756:
|
|
// SIMD-ONLY0-NEXT: [[TMP471:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP471]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP472:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV757:%.*]] = zext i8 [[TMP472]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP473:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV758:%.*]] = zext i8 [[TMP473]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP759:%.*]] = icmp sgt i32 [[CONV757]], [[CONV758]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP759]], label [[IF_THEN761:%.*]], label [[IF_END762:%.*]]
|
|
// SIMD-ONLY0: if.then761:
|
|
// SIMD-ONLY0-NEXT: [[TMP474:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP474]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END762]]
|
|
// SIMD-ONLY0: if.end762:
|
|
// SIMD-ONLY0-NEXT: [[TMP475:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP475]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP476:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV763:%.*]] = zext i8 [[TMP476]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP477:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV764:%.*]] = zext i8 [[TMP477]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP765:%.*]] = icmp slt i32 [[CONV763]], [[CONV764]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP765]], label [[IF_THEN767:%.*]], label [[IF_END768:%.*]]
|
|
// SIMD-ONLY0: if.then767:
|
|
// SIMD-ONLY0-NEXT: [[TMP478:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP478]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END768]]
|
|
// SIMD-ONLY0: if.end768:
|
|
// SIMD-ONLY0-NEXT: [[TMP479:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP479]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP480:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV769:%.*]] = zext i8 [[TMP480]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP481:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV770:%.*]] = zext i8 [[TMP481]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP771:%.*]] = icmp slt i32 [[CONV769]], [[CONV770]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP771]], label [[IF_THEN773:%.*]], label [[IF_END774:%.*]]
|
|
// SIMD-ONLY0: if.then773:
|
|
// SIMD-ONLY0-NEXT: [[TMP482:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP482]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END774]]
|
|
// SIMD-ONLY0: if.end774:
|
|
// SIMD-ONLY0-NEXT: [[TMP483:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP483]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP484:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV775:%.*]] = zext i8 [[TMP484]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP485:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV776:%.*]] = zext i8 [[TMP485]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP777:%.*]] = icmp eq i32 [[CONV775]], [[CONV776]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP777]], label [[IF_THEN779:%.*]], label [[IF_END780:%.*]]
|
|
// SIMD-ONLY0: if.then779:
|
|
// SIMD-ONLY0-NEXT: [[TMP486:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP486]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END780]]
|
|
// SIMD-ONLY0: if.end780:
|
|
// SIMD-ONLY0-NEXT: [[TMP487:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP487]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP488:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV781:%.*]] = zext i8 [[TMP488]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP489:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV782:%.*]] = zext i8 [[TMP489]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP783:%.*]] = icmp eq i32 [[CONV781]], [[CONV782]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP783]], label [[IF_THEN785:%.*]], label [[IF_END786:%.*]]
|
|
// SIMD-ONLY0: if.then785:
|
|
// SIMD-ONLY0-NEXT: [[TMP490:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP490]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END786]]
|
|
// SIMD-ONLY0: if.end786:
|
|
// SIMD-ONLY0-NEXT: [[TMP491:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP491]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP492:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV787:%.*]] = zext i8 [[TMP492]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP493:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV788:%.*]] = zext i8 [[TMP493]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP789:%.*]] = icmp eq i32 [[CONV787]], [[CONV788]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP789]], label [[IF_THEN791:%.*]], label [[IF_ELSE792:%.*]]
|
|
// SIMD-ONLY0: if.then791:
|
|
// SIMD-ONLY0-NEXT: [[TMP494:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP494]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END793:%.*]]
|
|
// SIMD-ONLY0: if.else792:
|
|
// SIMD-ONLY0-NEXT: [[TMP495:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP495]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END793]]
|
|
// SIMD-ONLY0: if.end793:
|
|
// SIMD-ONLY0-NEXT: [[TMP496:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV794:%.*]] = zext i8 [[TMP496]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP497:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV795:%.*]] = zext i8 [[TMP497]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP796:%.*]] = icmp eq i32 [[CONV794]], [[CONV795]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP796]], label [[IF_THEN798:%.*]], label [[IF_ELSE799:%.*]]
|
|
// SIMD-ONLY0: if.then798:
|
|
// SIMD-ONLY0-NEXT: [[TMP498:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP498]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END800:%.*]]
|
|
// SIMD-ONLY0: if.else799:
|
|
// SIMD-ONLY0-NEXT: [[TMP499:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP499]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END800]]
|
|
// SIMD-ONLY0: if.end800:
|
|
// SIMD-ONLY0-NEXT: [[TMP500:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV801:%.*]] = zext i8 [[TMP500]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP501:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV802:%.*]] = zext i8 [[TMP501]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP803:%.*]] = icmp eq i32 [[CONV801]], [[CONV802]]
|
|
// SIMD-ONLY0-NEXT: [[CONV804:%.*]] = zext i1 [[CMP803]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV805:%.*]] = trunc i32 [[CONV804]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV805]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP502:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL806:%.*]] = icmp ne i8 [[TMP502]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL806]], label [[IF_THEN807:%.*]], label [[IF_END808:%.*]]
|
|
// SIMD-ONLY0: if.then807:
|
|
// SIMD-ONLY0-NEXT: [[TMP503:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP503]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END808]]
|
|
// SIMD-ONLY0: if.end808:
|
|
// SIMD-ONLY0-NEXT: [[TMP504:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV809:%.*]] = zext i8 [[TMP504]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP505:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV810:%.*]] = zext i8 [[TMP505]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP811:%.*]] = icmp eq i32 [[CONV809]], [[CONV810]]
|
|
// SIMD-ONLY0-NEXT: [[CONV812:%.*]] = zext i1 [[CMP811]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV813:%.*]] = trunc i32 [[CONV812]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV813]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP506:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL814:%.*]] = icmp ne i8 [[TMP506]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL814]], label [[IF_THEN815:%.*]], label [[IF_END816:%.*]]
|
|
// SIMD-ONLY0: if.then815:
|
|
// SIMD-ONLY0-NEXT: [[TMP507:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP507]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END816]]
|
|
// SIMD-ONLY0: if.end816:
|
|
// SIMD-ONLY0-NEXT: [[TMP508:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV817:%.*]] = zext i8 [[TMP508]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP509:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV818:%.*]] = zext i8 [[TMP509]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP819:%.*]] = icmp eq i32 [[CONV817]], [[CONV818]]
|
|
// SIMD-ONLY0-NEXT: [[CONV820:%.*]] = zext i1 [[CMP819]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV821:%.*]] = trunc i32 [[CONV820]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV821]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP510:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL822:%.*]] = icmp ne i8 [[TMP510]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL822]], label [[IF_THEN823:%.*]], label [[IF_ELSE824:%.*]]
|
|
// SIMD-ONLY0: if.then823:
|
|
// SIMD-ONLY0-NEXT: [[TMP511:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP511]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END825:%.*]]
|
|
// SIMD-ONLY0: if.else824:
|
|
// SIMD-ONLY0-NEXT: [[TMP512:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP512]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END825]]
|
|
// SIMD-ONLY0: if.end825:
|
|
// SIMD-ONLY0-NEXT: [[TMP513:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV826:%.*]] = zext i8 [[TMP513]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP514:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV827:%.*]] = zext i8 [[TMP514]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP828:%.*]] = icmp eq i32 [[CONV826]], [[CONV827]]
|
|
// SIMD-ONLY0-NEXT: [[CONV829:%.*]] = zext i1 [[CMP828]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV830:%.*]] = trunc i32 [[CONV829]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV830]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP515:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL831:%.*]] = icmp ne i8 [[TMP515]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL831]], label [[IF_THEN832:%.*]], label [[IF_ELSE833:%.*]]
|
|
// SIMD-ONLY0: if.then832:
|
|
// SIMD-ONLY0-NEXT: [[TMP516:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP516]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END834:%.*]]
|
|
// SIMD-ONLY0: if.else833:
|
|
// SIMD-ONLY0-NEXT: [[TMP517:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP517]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END834]]
|
|
// SIMD-ONLY0: if.end834:
|
|
// SIMD-ONLY0-NEXT: [[TMP518:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP518]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP519:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV835:%.*]] = zext i8 [[TMP519]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP520:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV836:%.*]] = zext i8 [[TMP520]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP837:%.*]] = icmp sgt i32 [[CONV835]], [[CONV836]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP837]], label [[IF_THEN839:%.*]], label [[IF_END840:%.*]]
|
|
// SIMD-ONLY0: if.then839:
|
|
// SIMD-ONLY0-NEXT: [[TMP521:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP521]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END840]]
|
|
// SIMD-ONLY0: if.end840:
|
|
// SIMD-ONLY0-NEXT: [[TMP522:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP522]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP523:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV841:%.*]] = zext i8 [[TMP523]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP524:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV842:%.*]] = zext i8 [[TMP524]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP843:%.*]] = icmp sgt i32 [[CONV841]], [[CONV842]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP843]], label [[IF_THEN845:%.*]], label [[IF_END846:%.*]]
|
|
// SIMD-ONLY0: if.then845:
|
|
// SIMD-ONLY0-NEXT: [[TMP525:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP525]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END846]]
|
|
// SIMD-ONLY0: if.end846:
|
|
// SIMD-ONLY0-NEXT: [[TMP526:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP526]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP527:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV847:%.*]] = zext i8 [[TMP527]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP528:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV848:%.*]] = zext i8 [[TMP528]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP849:%.*]] = icmp slt i32 [[CONV847]], [[CONV848]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP849]], label [[IF_THEN851:%.*]], label [[IF_END852:%.*]]
|
|
// SIMD-ONLY0: if.then851:
|
|
// SIMD-ONLY0-NEXT: [[TMP529:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP529]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END852]]
|
|
// SIMD-ONLY0: if.end852:
|
|
// SIMD-ONLY0-NEXT: [[TMP530:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP530]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP531:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV853:%.*]] = zext i8 [[TMP531]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP532:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV854:%.*]] = zext i8 [[TMP532]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP855:%.*]] = icmp slt i32 [[CONV853]], [[CONV854]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP855]], label [[IF_THEN857:%.*]], label [[IF_END858:%.*]]
|
|
// SIMD-ONLY0: if.then857:
|
|
// SIMD-ONLY0-NEXT: [[TMP533:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP533]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END858]]
|
|
// SIMD-ONLY0: if.end858:
|
|
// SIMD-ONLY0-NEXT: [[TMP534:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP534]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP535:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV859:%.*]] = zext i8 [[TMP535]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP536:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV860:%.*]] = zext i8 [[TMP536]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP861:%.*]] = icmp eq i32 [[CONV859]], [[CONV860]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP861]], label [[IF_THEN863:%.*]], label [[IF_END864:%.*]]
|
|
// SIMD-ONLY0: if.then863:
|
|
// SIMD-ONLY0-NEXT: [[TMP537:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP537]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END864]]
|
|
// SIMD-ONLY0: if.end864:
|
|
// SIMD-ONLY0-NEXT: [[TMP538:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP538]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP539:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV865:%.*]] = zext i8 [[TMP539]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP540:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV866:%.*]] = zext i8 [[TMP540]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP867:%.*]] = icmp eq i32 [[CONV865]], [[CONV866]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP867]], label [[IF_THEN869:%.*]], label [[IF_END870:%.*]]
|
|
// SIMD-ONLY0: if.then869:
|
|
// SIMD-ONLY0-NEXT: [[TMP541:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP541]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END870]]
|
|
// SIMD-ONLY0: if.end870:
|
|
// SIMD-ONLY0-NEXT: [[TMP542:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV871:%.*]] = zext i8 [[TMP542]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP543:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV872:%.*]] = zext i8 [[TMP543]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP873:%.*]] = icmp sgt i32 [[CONV871]], [[CONV872]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP873]], label [[IF_THEN875:%.*]], label [[IF_END876:%.*]]
|
|
// SIMD-ONLY0: if.then875:
|
|
// SIMD-ONLY0-NEXT: [[TMP544:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP544]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END876]]
|
|
// SIMD-ONLY0: if.end876:
|
|
// SIMD-ONLY0-NEXT: [[TMP545:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP545]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP546:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV877:%.*]] = zext i8 [[TMP546]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP547:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV878:%.*]] = zext i8 [[TMP547]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP879:%.*]] = icmp sgt i32 [[CONV877]], [[CONV878]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP879]], label [[IF_THEN881:%.*]], label [[IF_END882:%.*]]
|
|
// SIMD-ONLY0: if.then881:
|
|
// SIMD-ONLY0-NEXT: [[TMP548:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP548]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END882]]
|
|
// SIMD-ONLY0: if.end882:
|
|
// SIMD-ONLY0-NEXT: [[TMP549:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP549]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP550:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV883:%.*]] = zext i8 [[TMP550]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP551:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV884:%.*]] = zext i8 [[TMP551]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP885:%.*]] = icmp slt i32 [[CONV883]], [[CONV884]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP885]], label [[IF_THEN887:%.*]], label [[IF_END888:%.*]]
|
|
// SIMD-ONLY0: if.then887:
|
|
// SIMD-ONLY0-NEXT: [[TMP552:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP552]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END888]]
|
|
// SIMD-ONLY0: if.end888:
|
|
// SIMD-ONLY0-NEXT: [[TMP553:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP553]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP554:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV889:%.*]] = zext i8 [[TMP554]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP555:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV890:%.*]] = zext i8 [[TMP555]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP891:%.*]] = icmp slt i32 [[CONV889]], [[CONV890]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP891]], label [[IF_THEN893:%.*]], label [[IF_END894:%.*]]
|
|
// SIMD-ONLY0: if.then893:
|
|
// SIMD-ONLY0-NEXT: [[TMP556:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP556]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END894]]
|
|
// SIMD-ONLY0: if.end894:
|
|
// SIMD-ONLY0-NEXT: [[TMP557:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP557]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP558:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV895:%.*]] = zext i8 [[TMP558]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP559:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV896:%.*]] = zext i8 [[TMP559]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP897:%.*]] = icmp eq i32 [[CONV895]], [[CONV896]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP897]], label [[IF_THEN899:%.*]], label [[IF_END900:%.*]]
|
|
// SIMD-ONLY0: if.then899:
|
|
// SIMD-ONLY0-NEXT: [[TMP560:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP560]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END900]]
|
|
// SIMD-ONLY0: if.end900:
|
|
// SIMD-ONLY0-NEXT: [[TMP561:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP561]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP562:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV901:%.*]] = zext i8 [[TMP562]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP563:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV902:%.*]] = zext i8 [[TMP563]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP903:%.*]] = icmp eq i32 [[CONV901]], [[CONV902]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP903]], label [[IF_THEN905:%.*]], label [[IF_END906:%.*]]
|
|
// SIMD-ONLY0: if.then905:
|
|
// SIMD-ONLY0-NEXT: [[TMP564:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP564]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END906]]
|
|
// SIMD-ONLY0: if.end906:
|
|
// SIMD-ONLY0-NEXT: [[TMP565:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP565]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP566:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV907:%.*]] = zext i8 [[TMP566]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP567:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV908:%.*]] = zext i8 [[TMP567]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP909:%.*]] = icmp eq i32 [[CONV907]], [[CONV908]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP909]], label [[IF_THEN911:%.*]], label [[IF_ELSE912:%.*]]
|
|
// SIMD-ONLY0: if.then911:
|
|
// SIMD-ONLY0-NEXT: [[TMP568:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP568]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END913:%.*]]
|
|
// SIMD-ONLY0: if.else912:
|
|
// SIMD-ONLY0-NEXT: [[TMP569:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP569]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END913]]
|
|
// SIMD-ONLY0: if.end913:
|
|
// SIMD-ONLY0-NEXT: [[TMP570:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV914:%.*]] = zext i8 [[TMP570]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP571:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV915:%.*]] = zext i8 [[TMP571]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP916:%.*]] = icmp eq i32 [[CONV914]], [[CONV915]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP916]], label [[IF_THEN918:%.*]], label [[IF_ELSE919:%.*]]
|
|
// SIMD-ONLY0: if.then918:
|
|
// SIMD-ONLY0-NEXT: [[TMP572:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP572]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END920:%.*]]
|
|
// SIMD-ONLY0: if.else919:
|
|
// SIMD-ONLY0-NEXT: [[TMP573:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP573]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END920]]
|
|
// SIMD-ONLY0: if.end920:
|
|
// SIMD-ONLY0-NEXT: [[TMP574:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV921:%.*]] = zext i8 [[TMP574]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP575:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV922:%.*]] = zext i8 [[TMP575]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP923:%.*]] = icmp eq i32 [[CONV921]], [[CONV922]]
|
|
// SIMD-ONLY0-NEXT: [[CONV924:%.*]] = zext i1 [[CMP923]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV925:%.*]] = trunc i32 [[CONV924]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV925]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP576:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL926:%.*]] = icmp ne i8 [[TMP576]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL926]], label [[IF_THEN927:%.*]], label [[IF_END928:%.*]]
|
|
// SIMD-ONLY0: if.then927:
|
|
// SIMD-ONLY0-NEXT: [[TMP577:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP577]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END928]]
|
|
// SIMD-ONLY0: if.end928:
|
|
// SIMD-ONLY0-NEXT: [[TMP578:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV929:%.*]] = zext i8 [[TMP578]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP579:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV930:%.*]] = zext i8 [[TMP579]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP931:%.*]] = icmp eq i32 [[CONV929]], [[CONV930]]
|
|
// SIMD-ONLY0-NEXT: [[CONV932:%.*]] = zext i1 [[CMP931]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV933:%.*]] = trunc i32 [[CONV932]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV933]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP580:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL934:%.*]] = icmp ne i8 [[TMP580]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL934]], label [[IF_THEN935:%.*]], label [[IF_END936:%.*]]
|
|
// SIMD-ONLY0: if.then935:
|
|
// SIMD-ONLY0-NEXT: [[TMP581:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP581]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END936]]
|
|
// SIMD-ONLY0: if.end936:
|
|
// SIMD-ONLY0-NEXT: [[TMP582:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV937:%.*]] = zext i8 [[TMP582]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP583:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV938:%.*]] = zext i8 [[TMP583]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP939:%.*]] = icmp eq i32 [[CONV937]], [[CONV938]]
|
|
// SIMD-ONLY0-NEXT: [[CONV940:%.*]] = zext i1 [[CMP939]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV941:%.*]] = trunc i32 [[CONV940]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV941]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP584:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL942:%.*]] = icmp ne i8 [[TMP584]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL942]], label [[IF_THEN943:%.*]], label [[IF_ELSE944:%.*]]
|
|
// SIMD-ONLY0: if.then943:
|
|
// SIMD-ONLY0-NEXT: [[TMP585:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP585]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END945:%.*]]
|
|
// SIMD-ONLY0: if.else944:
|
|
// SIMD-ONLY0-NEXT: [[TMP586:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP586]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END945]]
|
|
// SIMD-ONLY0: if.end945:
|
|
// SIMD-ONLY0-NEXT: [[TMP587:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV946:%.*]] = zext i8 [[TMP587]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP588:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV947:%.*]] = zext i8 [[TMP588]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP948:%.*]] = icmp eq i32 [[CONV946]], [[CONV947]]
|
|
// SIMD-ONLY0-NEXT: [[CONV949:%.*]] = zext i1 [[CMP948]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV950:%.*]] = trunc i32 [[CONV949]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV950]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP589:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL951:%.*]] = icmp ne i8 [[TMP589]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL951]], label [[IF_THEN952:%.*]], label [[IF_ELSE953:%.*]]
|
|
// SIMD-ONLY0: if.then952:
|
|
// SIMD-ONLY0-NEXT: [[TMP590:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP590]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END954:%.*]]
|
|
// SIMD-ONLY0: if.else953:
|
|
// SIMD-ONLY0-NEXT: [[TMP591:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP591]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END954]]
|
|
// SIMD-ONLY0: if.end954:
|
|
// SIMD-ONLY0-NEXT: [[TMP592:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP592]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP593:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV955:%.*]] = zext i8 [[TMP593]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP594:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV956:%.*]] = zext i8 [[TMP594]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP957:%.*]] = icmp sgt i32 [[CONV955]], [[CONV956]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP957]], label [[IF_THEN959:%.*]], label [[IF_END960:%.*]]
|
|
// SIMD-ONLY0: if.then959:
|
|
// SIMD-ONLY0-NEXT: [[TMP595:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP595]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END960]]
|
|
// SIMD-ONLY0: if.end960:
|
|
// SIMD-ONLY0-NEXT: [[TMP596:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP596]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP597:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV961:%.*]] = zext i8 [[TMP597]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP598:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV962:%.*]] = zext i8 [[TMP598]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP963:%.*]] = icmp sgt i32 [[CONV961]], [[CONV962]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP963]], label [[IF_THEN965:%.*]], label [[IF_END966:%.*]]
|
|
// SIMD-ONLY0: if.then965:
|
|
// SIMD-ONLY0-NEXT: [[TMP599:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP599]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END966]]
|
|
// SIMD-ONLY0: if.end966:
|
|
// SIMD-ONLY0-NEXT: [[TMP600:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP600]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP601:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV967:%.*]] = zext i8 [[TMP601]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP602:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV968:%.*]] = zext i8 [[TMP602]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP969:%.*]] = icmp slt i32 [[CONV967]], [[CONV968]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP969]], label [[IF_THEN971:%.*]], label [[IF_END972:%.*]]
|
|
// SIMD-ONLY0: if.then971:
|
|
// SIMD-ONLY0-NEXT: [[TMP603:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP603]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END972]]
|
|
// SIMD-ONLY0: if.end972:
|
|
// SIMD-ONLY0-NEXT: [[TMP604:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP604]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP605:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV973:%.*]] = zext i8 [[TMP605]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP606:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV974:%.*]] = zext i8 [[TMP606]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP975:%.*]] = icmp slt i32 [[CONV973]], [[CONV974]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP975]], label [[IF_THEN977:%.*]], label [[IF_END978:%.*]]
|
|
// SIMD-ONLY0: if.then977:
|
|
// SIMD-ONLY0-NEXT: [[TMP607:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP607]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END978]]
|
|
// SIMD-ONLY0: if.end978:
|
|
// SIMD-ONLY0-NEXT: [[TMP608:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP608]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP609:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV979:%.*]] = zext i8 [[TMP609]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP610:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV980:%.*]] = zext i8 [[TMP610]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP981:%.*]] = icmp eq i32 [[CONV979]], [[CONV980]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP981]], label [[IF_THEN983:%.*]], label [[IF_END984:%.*]]
|
|
// SIMD-ONLY0: if.then983:
|
|
// SIMD-ONLY0-NEXT: [[TMP611:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP611]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END984]]
|
|
// SIMD-ONLY0: if.end984:
|
|
// SIMD-ONLY0-NEXT: [[TMP612:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP612]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP613:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV985:%.*]] = zext i8 [[TMP613]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP614:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV986:%.*]] = zext i8 [[TMP614]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP987:%.*]] = icmp eq i32 [[CONV985]], [[CONV986]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP987]], label [[IF_THEN989:%.*]], label [[IF_END990:%.*]]
|
|
// SIMD-ONLY0: if.then989:
|
|
// SIMD-ONLY0-NEXT: [[TMP615:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP615]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END990]]
|
|
// SIMD-ONLY0: if.end990:
|
|
// SIMD-ONLY0-NEXT: [[TMP616:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV991:%.*]] = zext i8 [[TMP616]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP617:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV992:%.*]] = zext i8 [[TMP617]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP993:%.*]] = icmp sgt i32 [[CONV991]], [[CONV992]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP993]], label [[IF_THEN995:%.*]], label [[IF_END996:%.*]]
|
|
// SIMD-ONLY0: if.then995:
|
|
// SIMD-ONLY0-NEXT: [[TMP618:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP618]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END996]]
|
|
// SIMD-ONLY0: if.end996:
|
|
// SIMD-ONLY0-NEXT: [[TMP619:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP619]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP620:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV997:%.*]] = zext i8 [[TMP620]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP621:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV998:%.*]] = zext i8 [[TMP621]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP999:%.*]] = icmp sgt i32 [[CONV997]], [[CONV998]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP999]], label [[IF_THEN1001:%.*]], label [[IF_END1002:%.*]]
|
|
// SIMD-ONLY0: if.then1001:
|
|
// SIMD-ONLY0-NEXT: [[TMP622:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP622]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1002]]
|
|
// SIMD-ONLY0: if.end1002:
|
|
// SIMD-ONLY0-NEXT: [[TMP623:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP623]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP624:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1003:%.*]] = zext i8 [[TMP624]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP625:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1004:%.*]] = zext i8 [[TMP625]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1005:%.*]] = icmp slt i32 [[CONV1003]], [[CONV1004]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1005]], label [[IF_THEN1007:%.*]], label [[IF_END1008:%.*]]
|
|
// SIMD-ONLY0: if.then1007:
|
|
// SIMD-ONLY0-NEXT: [[TMP626:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP626]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1008]]
|
|
// SIMD-ONLY0: if.end1008:
|
|
// SIMD-ONLY0-NEXT: [[TMP627:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP627]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP628:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1009:%.*]] = zext i8 [[TMP628]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP629:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1010:%.*]] = zext i8 [[TMP629]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1011:%.*]] = icmp slt i32 [[CONV1009]], [[CONV1010]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1011]], label [[IF_THEN1013:%.*]], label [[IF_END1014:%.*]]
|
|
// SIMD-ONLY0: if.then1013:
|
|
// SIMD-ONLY0-NEXT: [[TMP630:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP630]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1014]]
|
|
// SIMD-ONLY0: if.end1014:
|
|
// SIMD-ONLY0-NEXT: [[TMP631:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP631]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP632:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1015:%.*]] = zext i8 [[TMP632]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP633:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1016:%.*]] = zext i8 [[TMP633]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1017:%.*]] = icmp eq i32 [[CONV1015]], [[CONV1016]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1017]], label [[IF_THEN1019:%.*]], label [[IF_END1020:%.*]]
|
|
// SIMD-ONLY0: if.then1019:
|
|
// SIMD-ONLY0-NEXT: [[TMP634:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP634]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1020]]
|
|
// SIMD-ONLY0: if.end1020:
|
|
// SIMD-ONLY0-NEXT: [[TMP635:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP635]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP636:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1021:%.*]] = zext i8 [[TMP636]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP637:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1022:%.*]] = zext i8 [[TMP637]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1023:%.*]] = icmp eq i32 [[CONV1021]], [[CONV1022]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1023]], label [[IF_THEN1025:%.*]], label [[IF_END1026:%.*]]
|
|
// SIMD-ONLY0: if.then1025:
|
|
// SIMD-ONLY0-NEXT: [[TMP638:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP638]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1026]]
|
|
// SIMD-ONLY0: if.end1026:
|
|
// SIMD-ONLY0-NEXT: [[TMP639:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP639]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP640:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1027:%.*]] = zext i8 [[TMP640]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP641:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1028:%.*]] = zext i8 [[TMP641]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1029:%.*]] = icmp eq i32 [[CONV1027]], [[CONV1028]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1029]], label [[IF_THEN1031:%.*]], label [[IF_ELSE1032:%.*]]
|
|
// SIMD-ONLY0: if.then1031:
|
|
// SIMD-ONLY0-NEXT: [[TMP642:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP642]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1033:%.*]]
|
|
// SIMD-ONLY0: if.else1032:
|
|
// SIMD-ONLY0-NEXT: [[TMP643:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP643]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1033]]
|
|
// SIMD-ONLY0: if.end1033:
|
|
// SIMD-ONLY0-NEXT: [[TMP644:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1034:%.*]] = zext i8 [[TMP644]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP645:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1035:%.*]] = zext i8 [[TMP645]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1036:%.*]] = icmp eq i32 [[CONV1034]], [[CONV1035]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1036]], label [[IF_THEN1038:%.*]], label [[IF_ELSE1039:%.*]]
|
|
// SIMD-ONLY0: if.then1038:
|
|
// SIMD-ONLY0-NEXT: [[TMP646:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP646]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1040:%.*]]
|
|
// SIMD-ONLY0: if.else1039:
|
|
// SIMD-ONLY0-NEXT: [[TMP647:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP647]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1040]]
|
|
// SIMD-ONLY0: if.end1040:
|
|
// SIMD-ONLY0-NEXT: [[TMP648:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1041:%.*]] = zext i8 [[TMP648]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP649:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1042:%.*]] = zext i8 [[TMP649]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1043:%.*]] = icmp eq i32 [[CONV1041]], [[CONV1042]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1044:%.*]] = zext i1 [[CMP1043]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1045:%.*]] = trunc i32 [[CONV1044]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1045]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP650:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1046:%.*]] = icmp ne i8 [[TMP650]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1046]], label [[IF_THEN1047:%.*]], label [[IF_END1048:%.*]]
|
|
// SIMD-ONLY0: if.then1047:
|
|
// SIMD-ONLY0-NEXT: [[TMP651:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP651]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1048]]
|
|
// SIMD-ONLY0: if.end1048:
|
|
// SIMD-ONLY0-NEXT: [[TMP652:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1049:%.*]] = zext i8 [[TMP652]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP653:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1050:%.*]] = zext i8 [[TMP653]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1051:%.*]] = icmp eq i32 [[CONV1049]], [[CONV1050]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1052:%.*]] = zext i1 [[CMP1051]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1053:%.*]] = trunc i32 [[CONV1052]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1053]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP654:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1054:%.*]] = icmp ne i8 [[TMP654]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1054]], label [[IF_THEN1055:%.*]], label [[IF_END1056:%.*]]
|
|
// SIMD-ONLY0: if.then1055:
|
|
// SIMD-ONLY0-NEXT: [[TMP655:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP655]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1056]]
|
|
// SIMD-ONLY0: if.end1056:
|
|
// SIMD-ONLY0-NEXT: [[TMP656:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1057:%.*]] = zext i8 [[TMP656]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP657:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1058:%.*]] = zext i8 [[TMP657]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1059:%.*]] = icmp eq i32 [[CONV1057]], [[CONV1058]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1060:%.*]] = zext i1 [[CMP1059]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1061:%.*]] = trunc i32 [[CONV1060]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1061]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP658:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1062:%.*]] = icmp ne i8 [[TMP658]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1062]], label [[IF_THEN1063:%.*]], label [[IF_ELSE1064:%.*]]
|
|
// SIMD-ONLY0: if.then1063:
|
|
// SIMD-ONLY0-NEXT: [[TMP659:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP659]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1065:%.*]]
|
|
// SIMD-ONLY0: if.else1064:
|
|
// SIMD-ONLY0-NEXT: [[TMP660:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP660]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1065]]
|
|
// SIMD-ONLY0: if.end1065:
|
|
// SIMD-ONLY0-NEXT: [[TMP661:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1066:%.*]] = zext i8 [[TMP661]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP662:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1067:%.*]] = zext i8 [[TMP662]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1068:%.*]] = icmp eq i32 [[CONV1066]], [[CONV1067]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1069:%.*]] = zext i1 [[CMP1068]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1070:%.*]] = trunc i32 [[CONV1069]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1070]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP663:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1071:%.*]] = icmp ne i8 [[TMP663]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1071]], label [[IF_THEN1072:%.*]], label [[IF_ELSE1073:%.*]]
|
|
// SIMD-ONLY0: if.then1072:
|
|
// SIMD-ONLY0-NEXT: [[TMP664:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP664]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1074:%.*]]
|
|
// SIMD-ONLY0: if.else1073:
|
|
// SIMD-ONLY0-NEXT: [[TMP665:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP665]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1074]]
|
|
// SIMD-ONLY0: if.end1074:
|
|
// SIMD-ONLY0-NEXT: [[TMP666:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP666]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP667:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1075:%.*]] = zext i8 [[TMP667]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP668:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1076:%.*]] = zext i8 [[TMP668]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1077:%.*]] = icmp sgt i32 [[CONV1075]], [[CONV1076]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1077]], label [[IF_THEN1079:%.*]], label [[IF_END1080:%.*]]
|
|
// SIMD-ONLY0: if.then1079:
|
|
// SIMD-ONLY0-NEXT: [[TMP669:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP669]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1080]]
|
|
// SIMD-ONLY0: if.end1080:
|
|
// SIMD-ONLY0-NEXT: [[TMP670:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP670]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP671:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1081:%.*]] = zext i8 [[TMP671]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP672:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1082:%.*]] = zext i8 [[TMP672]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1083:%.*]] = icmp sgt i32 [[CONV1081]], [[CONV1082]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1083]], label [[IF_THEN1085:%.*]], label [[IF_END1086:%.*]]
|
|
// SIMD-ONLY0: if.then1085:
|
|
// SIMD-ONLY0-NEXT: [[TMP673:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP673]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1086]]
|
|
// SIMD-ONLY0: if.end1086:
|
|
// SIMD-ONLY0-NEXT: [[TMP674:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP674]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP675:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1087:%.*]] = zext i8 [[TMP675]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP676:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1088:%.*]] = zext i8 [[TMP676]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1089:%.*]] = icmp slt i32 [[CONV1087]], [[CONV1088]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1089]], label [[IF_THEN1091:%.*]], label [[IF_END1092:%.*]]
|
|
// SIMD-ONLY0: if.then1091:
|
|
// SIMD-ONLY0-NEXT: [[TMP677:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP677]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1092]]
|
|
// SIMD-ONLY0: if.end1092:
|
|
// SIMD-ONLY0-NEXT: [[TMP678:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP678]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP679:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1093:%.*]] = zext i8 [[TMP679]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP680:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1094:%.*]] = zext i8 [[TMP680]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1095:%.*]] = icmp slt i32 [[CONV1093]], [[CONV1094]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1095]], label [[IF_THEN1097:%.*]], label [[IF_END1098:%.*]]
|
|
// SIMD-ONLY0: if.then1097:
|
|
// SIMD-ONLY0-NEXT: [[TMP681:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP681]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1098]]
|
|
// SIMD-ONLY0: if.end1098:
|
|
// SIMD-ONLY0-NEXT: [[TMP682:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP682]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP683:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1099:%.*]] = zext i8 [[TMP683]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP684:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1100:%.*]] = zext i8 [[TMP684]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1101:%.*]] = icmp eq i32 [[CONV1099]], [[CONV1100]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1101]], label [[IF_THEN1103:%.*]], label [[IF_END1104:%.*]]
|
|
// SIMD-ONLY0: if.then1103:
|
|
// SIMD-ONLY0-NEXT: [[TMP685:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP685]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1104]]
|
|
// SIMD-ONLY0: if.end1104:
|
|
// SIMD-ONLY0-NEXT: [[TMP686:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP686]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP687:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1105:%.*]] = zext i8 [[TMP687]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP688:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1106:%.*]] = zext i8 [[TMP688]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1107:%.*]] = icmp eq i32 [[CONV1105]], [[CONV1106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1107]], label [[IF_THEN1109:%.*]], label [[IF_END1110:%.*]]
|
|
// SIMD-ONLY0: if.then1109:
|
|
// SIMD-ONLY0-NEXT: [[TMP689:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP689]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1110]]
|
|
// SIMD-ONLY0: if.end1110:
|
|
// SIMD-ONLY0-NEXT: [[TMP690:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1111:%.*]] = zext i8 [[TMP690]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP691:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1112:%.*]] = zext i8 [[TMP691]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1113:%.*]] = icmp sgt i32 [[CONV1111]], [[CONV1112]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1113]], label [[IF_THEN1115:%.*]], label [[IF_END1116:%.*]]
|
|
// SIMD-ONLY0: if.then1115:
|
|
// SIMD-ONLY0-NEXT: [[TMP692:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP692]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1116]]
|
|
// SIMD-ONLY0: if.end1116:
|
|
// SIMD-ONLY0-NEXT: [[TMP693:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP693]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP694:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1117:%.*]] = zext i8 [[TMP694]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP695:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1118:%.*]] = zext i8 [[TMP695]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1119:%.*]] = icmp sgt i32 [[CONV1117]], [[CONV1118]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1119]], label [[IF_THEN1121:%.*]], label [[IF_END1122:%.*]]
|
|
// SIMD-ONLY0: if.then1121:
|
|
// SIMD-ONLY0-NEXT: [[TMP696:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP696]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1122]]
|
|
// SIMD-ONLY0: if.end1122:
|
|
// SIMD-ONLY0-NEXT: [[TMP697:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP697]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP698:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1123:%.*]] = zext i8 [[TMP698]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP699:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1124:%.*]] = zext i8 [[TMP699]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1125:%.*]] = icmp slt i32 [[CONV1123]], [[CONV1124]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1125]], label [[IF_THEN1127:%.*]], label [[IF_END1128:%.*]]
|
|
// SIMD-ONLY0: if.then1127:
|
|
// SIMD-ONLY0-NEXT: [[TMP700:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP700]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1128]]
|
|
// SIMD-ONLY0: if.end1128:
|
|
// SIMD-ONLY0-NEXT: [[TMP701:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP701]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP702:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1129:%.*]] = zext i8 [[TMP702]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP703:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1130:%.*]] = zext i8 [[TMP703]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1131:%.*]] = icmp slt i32 [[CONV1129]], [[CONV1130]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1131]], label [[IF_THEN1133:%.*]], label [[IF_END1134:%.*]]
|
|
// SIMD-ONLY0: if.then1133:
|
|
// SIMD-ONLY0-NEXT: [[TMP704:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP704]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1134]]
|
|
// SIMD-ONLY0: if.end1134:
|
|
// SIMD-ONLY0-NEXT: [[TMP705:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP705]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP706:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1135:%.*]] = zext i8 [[TMP706]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP707:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1136:%.*]] = zext i8 [[TMP707]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1137:%.*]] = icmp eq i32 [[CONV1135]], [[CONV1136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1137]], label [[IF_THEN1139:%.*]], label [[IF_END1140:%.*]]
|
|
// SIMD-ONLY0: if.then1139:
|
|
// SIMD-ONLY0-NEXT: [[TMP708:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP708]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1140]]
|
|
// SIMD-ONLY0: if.end1140:
|
|
// SIMD-ONLY0-NEXT: [[TMP709:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP709]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP710:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1141:%.*]] = zext i8 [[TMP710]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP711:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1142:%.*]] = zext i8 [[TMP711]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1143:%.*]] = icmp eq i32 [[CONV1141]], [[CONV1142]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1143]], label [[IF_THEN1145:%.*]], label [[IF_END1146:%.*]]
|
|
// SIMD-ONLY0: if.then1145:
|
|
// SIMD-ONLY0-NEXT: [[TMP712:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP712]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1146]]
|
|
// SIMD-ONLY0: if.end1146:
|
|
// SIMD-ONLY0-NEXT: [[TMP713:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP713]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP714:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1147:%.*]] = zext i8 [[TMP714]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP715:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1148:%.*]] = zext i8 [[TMP715]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1149:%.*]] = icmp eq i32 [[CONV1147]], [[CONV1148]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1149]], label [[IF_THEN1151:%.*]], label [[IF_ELSE1152:%.*]]
|
|
// SIMD-ONLY0: if.then1151:
|
|
// SIMD-ONLY0-NEXT: [[TMP716:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP716]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1153:%.*]]
|
|
// SIMD-ONLY0: if.else1152:
|
|
// SIMD-ONLY0-NEXT: [[TMP717:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP717]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1153]]
|
|
// SIMD-ONLY0: if.end1153:
|
|
// SIMD-ONLY0-NEXT: [[TMP718:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1154:%.*]] = zext i8 [[TMP718]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP719:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1155:%.*]] = zext i8 [[TMP719]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1156:%.*]] = icmp eq i32 [[CONV1154]], [[CONV1155]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1156]], label [[IF_THEN1158:%.*]], label [[IF_ELSE1159:%.*]]
|
|
// SIMD-ONLY0: if.then1158:
|
|
// SIMD-ONLY0-NEXT: [[TMP720:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP720]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1160:%.*]]
|
|
// SIMD-ONLY0: if.else1159:
|
|
// SIMD-ONLY0-NEXT: [[TMP721:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP721]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1160]]
|
|
// SIMD-ONLY0: if.end1160:
|
|
// SIMD-ONLY0-NEXT: [[TMP722:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1161:%.*]] = zext i8 [[TMP722]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP723:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1162:%.*]] = zext i8 [[TMP723]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1163:%.*]] = icmp eq i32 [[CONV1161]], [[CONV1162]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1164:%.*]] = zext i1 [[CMP1163]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1165:%.*]] = trunc i32 [[CONV1164]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1165]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP724:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1166:%.*]] = icmp ne i8 [[TMP724]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1166]], label [[IF_THEN1167:%.*]], label [[IF_END1168:%.*]]
|
|
// SIMD-ONLY0: if.then1167:
|
|
// SIMD-ONLY0-NEXT: [[TMP725:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP725]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1168]]
|
|
// SIMD-ONLY0: if.end1168:
|
|
// SIMD-ONLY0-NEXT: [[TMP726:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1169:%.*]] = zext i8 [[TMP726]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP727:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1170:%.*]] = zext i8 [[TMP727]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1171:%.*]] = icmp eq i32 [[CONV1169]], [[CONV1170]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1172:%.*]] = zext i1 [[CMP1171]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1173:%.*]] = trunc i32 [[CONV1172]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1173]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP728:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1174:%.*]] = icmp ne i8 [[TMP728]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1174]], label [[IF_THEN1175:%.*]], label [[IF_END1176:%.*]]
|
|
// SIMD-ONLY0: if.then1175:
|
|
// SIMD-ONLY0-NEXT: [[TMP729:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP729]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1176]]
|
|
// SIMD-ONLY0: if.end1176:
|
|
// SIMD-ONLY0-NEXT: [[TMP730:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1177:%.*]] = zext i8 [[TMP730]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP731:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1178:%.*]] = zext i8 [[TMP731]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1179:%.*]] = icmp eq i32 [[CONV1177]], [[CONV1178]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1180:%.*]] = zext i1 [[CMP1179]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1181:%.*]] = trunc i32 [[CONV1180]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1181]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP732:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1182:%.*]] = icmp ne i8 [[TMP732]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1182]], label [[IF_THEN1183:%.*]], label [[IF_ELSE1184:%.*]]
|
|
// SIMD-ONLY0: if.then1183:
|
|
// SIMD-ONLY0-NEXT: [[TMP733:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP733]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1185:%.*]]
|
|
// SIMD-ONLY0: if.else1184:
|
|
// SIMD-ONLY0-NEXT: [[TMP734:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP734]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1185]]
|
|
// SIMD-ONLY0: if.end1185:
|
|
// SIMD-ONLY0-NEXT: [[TMP735:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1186:%.*]] = zext i8 [[TMP735]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP736:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1187:%.*]] = zext i8 [[TMP736]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1188:%.*]] = icmp eq i32 [[CONV1186]], [[CONV1187]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1189:%.*]] = zext i1 [[CMP1188]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1190:%.*]] = trunc i32 [[CONV1189]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1190]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP737:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1191:%.*]] = icmp ne i8 [[TMP737]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1191]], label [[IF_THEN1192:%.*]], label [[IF_ELSE1193:%.*]]
|
|
// SIMD-ONLY0: if.then1192:
|
|
// SIMD-ONLY0-NEXT: [[TMP738:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP738]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1194:%.*]]
|
|
// SIMD-ONLY0: if.else1193:
|
|
// SIMD-ONLY0-NEXT: [[TMP739:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP739]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1194]]
|
|
// SIMD-ONLY0: if.end1194:
|
|
// SIMD-ONLY0-NEXT: [[TMP740:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP740]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP741:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1195:%.*]] = zext i8 [[TMP741]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP742:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1196:%.*]] = zext i8 [[TMP742]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1197:%.*]] = icmp sgt i32 [[CONV1195]], [[CONV1196]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1197]], label [[IF_THEN1199:%.*]], label [[IF_END1200:%.*]]
|
|
// SIMD-ONLY0: if.then1199:
|
|
// SIMD-ONLY0-NEXT: [[TMP743:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP743]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1200]]
|
|
// SIMD-ONLY0: if.end1200:
|
|
// SIMD-ONLY0-NEXT: [[TMP744:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP744]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP745:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1201:%.*]] = zext i8 [[TMP745]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP746:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1202:%.*]] = zext i8 [[TMP746]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1203:%.*]] = icmp sgt i32 [[CONV1201]], [[CONV1202]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1203]], label [[IF_THEN1205:%.*]], label [[IF_END1206:%.*]]
|
|
// SIMD-ONLY0: if.then1205:
|
|
// SIMD-ONLY0-NEXT: [[TMP747:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP747]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1206]]
|
|
// SIMD-ONLY0: if.end1206:
|
|
// SIMD-ONLY0-NEXT: [[TMP748:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP748]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP749:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1207:%.*]] = zext i8 [[TMP749]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP750:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1208:%.*]] = zext i8 [[TMP750]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1209:%.*]] = icmp slt i32 [[CONV1207]], [[CONV1208]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1209]], label [[IF_THEN1211:%.*]], label [[IF_END1212:%.*]]
|
|
// SIMD-ONLY0: if.then1211:
|
|
// SIMD-ONLY0-NEXT: [[TMP751:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP751]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1212]]
|
|
// SIMD-ONLY0: if.end1212:
|
|
// SIMD-ONLY0-NEXT: [[TMP752:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP752]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP753:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1213:%.*]] = zext i8 [[TMP753]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP754:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1214:%.*]] = zext i8 [[TMP754]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1215:%.*]] = icmp slt i32 [[CONV1213]], [[CONV1214]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1215]], label [[IF_THEN1217:%.*]], label [[IF_END1218:%.*]]
|
|
// SIMD-ONLY0: if.then1217:
|
|
// SIMD-ONLY0-NEXT: [[TMP755:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP755]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1218]]
|
|
// SIMD-ONLY0: if.end1218:
|
|
// SIMD-ONLY0-NEXT: [[TMP756:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP756]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP757:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1219:%.*]] = zext i8 [[TMP757]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP758:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1220:%.*]] = zext i8 [[TMP758]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1221:%.*]] = icmp eq i32 [[CONV1219]], [[CONV1220]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1221]], label [[IF_THEN1223:%.*]], label [[IF_END1224:%.*]]
|
|
// SIMD-ONLY0: if.then1223:
|
|
// SIMD-ONLY0-NEXT: [[TMP759:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP759]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1224]]
|
|
// SIMD-ONLY0: if.end1224:
|
|
// SIMD-ONLY0-NEXT: [[TMP760:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP760]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP761:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1225:%.*]] = zext i8 [[TMP761]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP762:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1226:%.*]] = zext i8 [[TMP762]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1227:%.*]] = icmp eq i32 [[CONV1225]], [[CONV1226]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1227]], label [[IF_THEN1229:%.*]], label [[IF_END1230:%.*]]
|
|
// SIMD-ONLY0: if.then1229:
|
|
// SIMD-ONLY0-NEXT: [[TMP763:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP763]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1230]]
|
|
// SIMD-ONLY0: if.end1230:
|
|
// SIMD-ONLY0-NEXT: [[TMP764:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1231:%.*]] = zext i8 [[TMP764]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP765:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1232:%.*]] = zext i8 [[TMP765]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1233:%.*]] = icmp sgt i32 [[CONV1231]], [[CONV1232]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1233]], label [[IF_THEN1235:%.*]], label [[IF_END1236:%.*]]
|
|
// SIMD-ONLY0: if.then1235:
|
|
// SIMD-ONLY0-NEXT: [[TMP766:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP766]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1236]]
|
|
// SIMD-ONLY0: if.end1236:
|
|
// SIMD-ONLY0-NEXT: [[TMP767:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP767]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP768:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1237:%.*]] = zext i8 [[TMP768]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP769:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1238:%.*]] = zext i8 [[TMP769]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1239:%.*]] = icmp sgt i32 [[CONV1237]], [[CONV1238]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1239]], label [[IF_THEN1241:%.*]], label [[IF_END1242:%.*]]
|
|
// SIMD-ONLY0: if.then1241:
|
|
// SIMD-ONLY0-NEXT: [[TMP770:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP770]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1242]]
|
|
// SIMD-ONLY0: if.end1242:
|
|
// SIMD-ONLY0-NEXT: [[TMP771:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP771]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP772:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1243:%.*]] = zext i8 [[TMP772]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP773:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1244:%.*]] = zext i8 [[TMP773]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1245:%.*]] = icmp slt i32 [[CONV1243]], [[CONV1244]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1245]], label [[IF_THEN1247:%.*]], label [[IF_END1248:%.*]]
|
|
// SIMD-ONLY0: if.then1247:
|
|
// SIMD-ONLY0-NEXT: [[TMP774:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP774]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1248]]
|
|
// SIMD-ONLY0: if.end1248:
|
|
// SIMD-ONLY0-NEXT: [[TMP775:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP775]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP776:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1249:%.*]] = zext i8 [[TMP776]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP777:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1250:%.*]] = zext i8 [[TMP777]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1251:%.*]] = icmp slt i32 [[CONV1249]], [[CONV1250]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1251]], label [[IF_THEN1253:%.*]], label [[IF_END1254:%.*]]
|
|
// SIMD-ONLY0: if.then1253:
|
|
// SIMD-ONLY0-NEXT: [[TMP778:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP778]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1254]]
|
|
// SIMD-ONLY0: if.end1254:
|
|
// SIMD-ONLY0-NEXT: [[TMP779:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP779]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP780:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1255:%.*]] = zext i8 [[TMP780]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP781:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1256:%.*]] = zext i8 [[TMP781]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1257:%.*]] = icmp eq i32 [[CONV1255]], [[CONV1256]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1257]], label [[IF_THEN1259:%.*]], label [[IF_END1260:%.*]]
|
|
// SIMD-ONLY0: if.then1259:
|
|
// SIMD-ONLY0-NEXT: [[TMP782:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP782]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1260]]
|
|
// SIMD-ONLY0: if.end1260:
|
|
// SIMD-ONLY0-NEXT: [[TMP783:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP783]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP784:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1261:%.*]] = zext i8 [[TMP784]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP785:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1262:%.*]] = zext i8 [[TMP785]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1263:%.*]] = icmp eq i32 [[CONV1261]], [[CONV1262]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1263]], label [[IF_THEN1265:%.*]], label [[IF_END1266:%.*]]
|
|
// SIMD-ONLY0: if.then1265:
|
|
// SIMD-ONLY0-NEXT: [[TMP786:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP786]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1266]]
|
|
// SIMD-ONLY0: if.end1266:
|
|
// SIMD-ONLY0-NEXT: [[TMP787:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP787]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP788:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1267:%.*]] = zext i8 [[TMP788]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP789:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1268:%.*]] = zext i8 [[TMP789]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1269:%.*]] = icmp eq i32 [[CONV1267]], [[CONV1268]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1269]], label [[IF_THEN1271:%.*]], label [[IF_ELSE1272:%.*]]
|
|
// SIMD-ONLY0: if.then1271:
|
|
// SIMD-ONLY0-NEXT: [[TMP790:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP790]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1273:%.*]]
|
|
// SIMD-ONLY0: if.else1272:
|
|
// SIMD-ONLY0-NEXT: [[TMP791:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP791]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1273]]
|
|
// SIMD-ONLY0: if.end1273:
|
|
// SIMD-ONLY0-NEXT: [[TMP792:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1274:%.*]] = zext i8 [[TMP792]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP793:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1275:%.*]] = zext i8 [[TMP793]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1276:%.*]] = icmp eq i32 [[CONV1274]], [[CONV1275]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1276]], label [[IF_THEN1278:%.*]], label [[IF_ELSE1279:%.*]]
|
|
// SIMD-ONLY0: if.then1278:
|
|
// SIMD-ONLY0-NEXT: [[TMP794:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP794]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1280:%.*]]
|
|
// SIMD-ONLY0: if.else1279:
|
|
// SIMD-ONLY0-NEXT: [[TMP795:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP795]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1280]]
|
|
// SIMD-ONLY0: if.end1280:
|
|
// SIMD-ONLY0-NEXT: [[TMP796:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1281:%.*]] = zext i8 [[TMP796]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP797:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1282:%.*]] = zext i8 [[TMP797]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1283:%.*]] = icmp eq i32 [[CONV1281]], [[CONV1282]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1284:%.*]] = zext i1 [[CMP1283]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1285:%.*]] = trunc i32 [[CONV1284]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1285]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP798:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1286:%.*]] = icmp ne i8 [[TMP798]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1286]], label [[IF_THEN1287:%.*]], label [[IF_END1288:%.*]]
|
|
// SIMD-ONLY0: if.then1287:
|
|
// SIMD-ONLY0-NEXT: [[TMP799:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP799]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1288]]
|
|
// SIMD-ONLY0: if.end1288:
|
|
// SIMD-ONLY0-NEXT: [[TMP800:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1289:%.*]] = zext i8 [[TMP800]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP801:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1290:%.*]] = zext i8 [[TMP801]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1291:%.*]] = icmp eq i32 [[CONV1289]], [[CONV1290]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1292:%.*]] = zext i1 [[CMP1291]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1293:%.*]] = trunc i32 [[CONV1292]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1293]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP802:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1294:%.*]] = icmp ne i8 [[TMP802]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1294]], label [[IF_THEN1295:%.*]], label [[IF_END1296:%.*]]
|
|
// SIMD-ONLY0: if.then1295:
|
|
// SIMD-ONLY0-NEXT: [[TMP803:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP803]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1296]]
|
|
// SIMD-ONLY0: if.end1296:
|
|
// SIMD-ONLY0-NEXT: [[TMP804:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1297:%.*]] = zext i8 [[TMP804]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP805:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1298:%.*]] = zext i8 [[TMP805]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1299:%.*]] = icmp eq i32 [[CONV1297]], [[CONV1298]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1300:%.*]] = zext i1 [[CMP1299]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1301:%.*]] = trunc i32 [[CONV1300]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1301]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP806:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1302:%.*]] = icmp ne i8 [[TMP806]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1302]], label [[IF_THEN1303:%.*]], label [[IF_ELSE1304:%.*]]
|
|
// SIMD-ONLY0: if.then1303:
|
|
// SIMD-ONLY0-NEXT: [[TMP807:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP807]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1305:%.*]]
|
|
// SIMD-ONLY0: if.else1304:
|
|
// SIMD-ONLY0-NEXT: [[TMP808:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP808]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1305]]
|
|
// SIMD-ONLY0: if.end1305:
|
|
// SIMD-ONLY0-NEXT: [[TMP809:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1306:%.*]] = zext i8 [[TMP809]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP810:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1307:%.*]] = zext i8 [[TMP810]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1308:%.*]] = icmp eq i32 [[CONV1306]], [[CONV1307]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1309:%.*]] = zext i1 [[CMP1308]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1310:%.*]] = trunc i32 [[CONV1309]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1310]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP811:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1311:%.*]] = icmp ne i8 [[TMP811]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1311]], label [[IF_THEN1312:%.*]], label [[IF_ELSE1313:%.*]]
|
|
// SIMD-ONLY0: if.then1312:
|
|
// SIMD-ONLY0-NEXT: [[TMP812:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP812]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1314:%.*]]
|
|
// SIMD-ONLY0: if.else1313:
|
|
// SIMD-ONLY0-NEXT: [[TMP813:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP813]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1314]]
|
|
// SIMD-ONLY0: if.end1314:
|
|
// SIMD-ONLY0-NEXT: [[TMP814:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP814]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP815:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1315:%.*]] = zext i8 [[TMP815]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP816:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1316:%.*]] = zext i8 [[TMP816]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1317:%.*]] = icmp sgt i32 [[CONV1315]], [[CONV1316]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1317]], label [[IF_THEN1319:%.*]], label [[IF_END1320:%.*]]
|
|
// SIMD-ONLY0: if.then1319:
|
|
// SIMD-ONLY0-NEXT: [[TMP817:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP817]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1320]]
|
|
// SIMD-ONLY0: if.end1320:
|
|
// SIMD-ONLY0-NEXT: [[TMP818:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP818]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP819:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1321:%.*]] = zext i8 [[TMP819]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP820:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1322:%.*]] = zext i8 [[TMP820]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1323:%.*]] = icmp sgt i32 [[CONV1321]], [[CONV1322]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1323]], label [[IF_THEN1325:%.*]], label [[IF_END1326:%.*]]
|
|
// SIMD-ONLY0: if.then1325:
|
|
// SIMD-ONLY0-NEXT: [[TMP821:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP821]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1326]]
|
|
// SIMD-ONLY0: if.end1326:
|
|
// SIMD-ONLY0-NEXT: [[TMP822:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP822]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP823:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1327:%.*]] = zext i8 [[TMP823]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP824:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1328:%.*]] = zext i8 [[TMP824]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1329:%.*]] = icmp slt i32 [[CONV1327]], [[CONV1328]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1329]], label [[IF_THEN1331:%.*]], label [[IF_END1332:%.*]]
|
|
// SIMD-ONLY0: if.then1331:
|
|
// SIMD-ONLY0-NEXT: [[TMP825:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP825]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1332]]
|
|
// SIMD-ONLY0: if.end1332:
|
|
// SIMD-ONLY0-NEXT: [[TMP826:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP826]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP827:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1333:%.*]] = zext i8 [[TMP827]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP828:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1334:%.*]] = zext i8 [[TMP828]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1335:%.*]] = icmp slt i32 [[CONV1333]], [[CONV1334]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1335]], label [[IF_THEN1337:%.*]], label [[IF_END1338:%.*]]
|
|
// SIMD-ONLY0: if.then1337:
|
|
// SIMD-ONLY0-NEXT: [[TMP829:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP829]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1338]]
|
|
// SIMD-ONLY0: if.end1338:
|
|
// SIMD-ONLY0-NEXT: [[TMP830:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP830]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP831:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1339:%.*]] = zext i8 [[TMP831]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP832:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1340:%.*]] = zext i8 [[TMP832]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1341:%.*]] = icmp eq i32 [[CONV1339]], [[CONV1340]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1341]], label [[IF_THEN1343:%.*]], label [[IF_END1344:%.*]]
|
|
// SIMD-ONLY0: if.then1343:
|
|
// SIMD-ONLY0-NEXT: [[TMP833:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP833]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1344]]
|
|
// SIMD-ONLY0: if.end1344:
|
|
// SIMD-ONLY0-NEXT: [[TMP834:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP834]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP835:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1345:%.*]] = zext i8 [[TMP835]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP836:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1346:%.*]] = zext i8 [[TMP836]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1347:%.*]] = icmp eq i32 [[CONV1345]], [[CONV1346]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1347]], label [[IF_THEN1349:%.*]], label [[IF_END1350:%.*]]
|
|
// SIMD-ONLY0: if.then1349:
|
|
// SIMD-ONLY0-NEXT: [[TMP837:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP837]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1350]]
|
|
// SIMD-ONLY0: if.end1350:
|
|
// SIMD-ONLY0-NEXT: [[TMP838:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1351:%.*]] = zext i8 [[TMP838]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP839:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1352:%.*]] = zext i8 [[TMP839]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1353:%.*]] = icmp sgt i32 [[CONV1351]], [[CONV1352]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1353]], label [[IF_THEN1355:%.*]], label [[IF_END1356:%.*]]
|
|
// SIMD-ONLY0: if.then1355:
|
|
// SIMD-ONLY0-NEXT: [[TMP840:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP840]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1356]]
|
|
// SIMD-ONLY0: if.end1356:
|
|
// SIMD-ONLY0-NEXT: [[TMP841:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP841]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP842:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1357:%.*]] = zext i8 [[TMP842]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP843:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1358:%.*]] = zext i8 [[TMP843]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1359:%.*]] = icmp sgt i32 [[CONV1357]], [[CONV1358]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1359]], label [[IF_THEN1361:%.*]], label [[IF_END1362:%.*]]
|
|
// SIMD-ONLY0: if.then1361:
|
|
// SIMD-ONLY0-NEXT: [[TMP844:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP844]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1362]]
|
|
// SIMD-ONLY0: if.end1362:
|
|
// SIMD-ONLY0-NEXT: [[TMP845:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP845]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP846:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1363:%.*]] = zext i8 [[TMP846]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP847:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1364:%.*]] = zext i8 [[TMP847]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1365:%.*]] = icmp slt i32 [[CONV1363]], [[CONV1364]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1365]], label [[IF_THEN1367:%.*]], label [[IF_END1368:%.*]]
|
|
// SIMD-ONLY0: if.then1367:
|
|
// SIMD-ONLY0-NEXT: [[TMP848:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP848]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1368]]
|
|
// SIMD-ONLY0: if.end1368:
|
|
// SIMD-ONLY0-NEXT: [[TMP849:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP849]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP850:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1369:%.*]] = zext i8 [[TMP850]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP851:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1370:%.*]] = zext i8 [[TMP851]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1371:%.*]] = icmp slt i32 [[CONV1369]], [[CONV1370]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1371]], label [[IF_THEN1373:%.*]], label [[IF_END1374:%.*]]
|
|
// SIMD-ONLY0: if.then1373:
|
|
// SIMD-ONLY0-NEXT: [[TMP852:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP852]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1374]]
|
|
// SIMD-ONLY0: if.end1374:
|
|
// SIMD-ONLY0-NEXT: [[TMP853:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP853]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP854:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1375:%.*]] = zext i8 [[TMP854]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP855:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1376:%.*]] = zext i8 [[TMP855]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1377:%.*]] = icmp eq i32 [[CONV1375]], [[CONV1376]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1377]], label [[IF_THEN1379:%.*]], label [[IF_END1380:%.*]]
|
|
// SIMD-ONLY0: if.then1379:
|
|
// SIMD-ONLY0-NEXT: [[TMP856:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP856]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1380]]
|
|
// SIMD-ONLY0: if.end1380:
|
|
// SIMD-ONLY0-NEXT: [[TMP857:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP857]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP858:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1381:%.*]] = zext i8 [[TMP858]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP859:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1382:%.*]] = zext i8 [[TMP859]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1383:%.*]] = icmp eq i32 [[CONV1381]], [[CONV1382]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1383]], label [[IF_THEN1385:%.*]], label [[IF_END1386:%.*]]
|
|
// SIMD-ONLY0: if.then1385:
|
|
// SIMD-ONLY0-NEXT: [[TMP860:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP860]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1386]]
|
|
// SIMD-ONLY0: if.end1386:
|
|
// SIMD-ONLY0-NEXT: [[TMP861:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP861]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP862:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1387:%.*]] = zext i8 [[TMP862]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP863:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1388:%.*]] = zext i8 [[TMP863]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1389:%.*]] = icmp eq i32 [[CONV1387]], [[CONV1388]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1389]], label [[IF_THEN1391:%.*]], label [[IF_ELSE1392:%.*]]
|
|
// SIMD-ONLY0: if.then1391:
|
|
// SIMD-ONLY0-NEXT: [[TMP864:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP864]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1393:%.*]]
|
|
// SIMD-ONLY0: if.else1392:
|
|
// SIMD-ONLY0-NEXT: [[TMP865:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP865]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1393]]
|
|
// SIMD-ONLY0: if.end1393:
|
|
// SIMD-ONLY0-NEXT: [[TMP866:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1394:%.*]] = zext i8 [[TMP866]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP867:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1395:%.*]] = zext i8 [[TMP867]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1396:%.*]] = icmp eq i32 [[CONV1394]], [[CONV1395]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1396]], label [[IF_THEN1398:%.*]], label [[IF_ELSE1399:%.*]]
|
|
// SIMD-ONLY0: if.then1398:
|
|
// SIMD-ONLY0-NEXT: [[TMP868:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP868]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1400:%.*]]
|
|
// SIMD-ONLY0: if.else1399:
|
|
// SIMD-ONLY0-NEXT: [[TMP869:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP869]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1400]]
|
|
// SIMD-ONLY0: if.end1400:
|
|
// SIMD-ONLY0-NEXT: [[TMP870:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1401:%.*]] = zext i8 [[TMP870]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP871:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1402:%.*]] = zext i8 [[TMP871]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1403:%.*]] = icmp eq i32 [[CONV1401]], [[CONV1402]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1404:%.*]] = zext i1 [[CMP1403]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1405:%.*]] = trunc i32 [[CONV1404]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1405]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP872:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1406:%.*]] = icmp ne i8 [[TMP872]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1406]], label [[IF_THEN1407:%.*]], label [[IF_END1408:%.*]]
|
|
// SIMD-ONLY0: if.then1407:
|
|
// SIMD-ONLY0-NEXT: [[TMP873:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP873]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1408]]
|
|
// SIMD-ONLY0: if.end1408:
|
|
// SIMD-ONLY0-NEXT: [[TMP874:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1409:%.*]] = zext i8 [[TMP874]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP875:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1410:%.*]] = zext i8 [[TMP875]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1411:%.*]] = icmp eq i32 [[CONV1409]], [[CONV1410]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1412:%.*]] = zext i1 [[CMP1411]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1413:%.*]] = trunc i32 [[CONV1412]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1413]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP876:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1414:%.*]] = icmp ne i8 [[TMP876]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1414]], label [[IF_THEN1415:%.*]], label [[IF_END1416:%.*]]
|
|
// SIMD-ONLY0: if.then1415:
|
|
// SIMD-ONLY0-NEXT: [[TMP877:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP877]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1416]]
|
|
// SIMD-ONLY0: if.end1416:
|
|
// SIMD-ONLY0-NEXT: [[TMP878:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1417:%.*]] = zext i8 [[TMP878]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP879:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1418:%.*]] = zext i8 [[TMP879]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1419:%.*]] = icmp eq i32 [[CONV1417]], [[CONV1418]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1420:%.*]] = zext i1 [[CMP1419]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1421:%.*]] = trunc i32 [[CONV1420]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1421]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP880:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1422:%.*]] = icmp ne i8 [[TMP880]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1422]], label [[IF_THEN1423:%.*]], label [[IF_ELSE1424:%.*]]
|
|
// SIMD-ONLY0: if.then1423:
|
|
// SIMD-ONLY0-NEXT: [[TMP881:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP881]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1425:%.*]]
|
|
// SIMD-ONLY0: if.else1424:
|
|
// SIMD-ONLY0-NEXT: [[TMP882:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP882]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1425]]
|
|
// SIMD-ONLY0: if.end1425:
|
|
// SIMD-ONLY0-NEXT: [[TMP883:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1426:%.*]] = zext i8 [[TMP883]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP884:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1427:%.*]] = zext i8 [[TMP884]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1428:%.*]] = icmp eq i32 [[CONV1426]], [[CONV1427]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1429:%.*]] = zext i1 [[CMP1428]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1430:%.*]] = trunc i32 [[CONV1429]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV1430]], ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP885:%.*]] = load i8, ptr [[UCR]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1431:%.*]] = icmp ne i8 [[TMP885]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1431]], label [[IF_THEN1432:%.*]], label [[IF_ELSE1433:%.*]]
|
|
// SIMD-ONLY0: if.then1432:
|
|
// SIMD-ONLY0-NEXT: [[TMP886:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP886]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1434:%.*]]
|
|
// SIMD-ONLY0: if.else1433:
|
|
// SIMD-ONLY0-NEXT: [[TMP887:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP887]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1434]]
|
|
// SIMD-ONLY0: if.end1434:
|
|
// SIMD-ONLY0-NEXT: [[TMP888:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP888]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP889:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1435:%.*]] = sext i16 [[TMP889]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP890:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1436:%.*]] = sext i16 [[TMP890]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1437:%.*]] = icmp sgt i32 [[CONV1435]], [[CONV1436]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1437]], label [[IF_THEN1439:%.*]], label [[IF_END1440:%.*]]
|
|
// SIMD-ONLY0: if.then1439:
|
|
// SIMD-ONLY0-NEXT: [[TMP891:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP891]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1440]]
|
|
// SIMD-ONLY0: if.end1440:
|
|
// SIMD-ONLY0-NEXT: [[TMP892:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP892]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP893:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1441:%.*]] = sext i16 [[TMP893]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP894:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1442:%.*]] = sext i16 [[TMP894]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1443:%.*]] = icmp sgt i32 [[CONV1441]], [[CONV1442]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1443]], label [[IF_THEN1445:%.*]], label [[IF_END1446:%.*]]
|
|
// SIMD-ONLY0: if.then1445:
|
|
// SIMD-ONLY0-NEXT: [[TMP895:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP895]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1446]]
|
|
// SIMD-ONLY0: if.end1446:
|
|
// SIMD-ONLY0-NEXT: [[TMP896:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP896]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP897:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1447:%.*]] = sext i16 [[TMP897]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP898:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1448:%.*]] = sext i16 [[TMP898]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1449:%.*]] = icmp slt i32 [[CONV1447]], [[CONV1448]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1449]], label [[IF_THEN1451:%.*]], label [[IF_END1452:%.*]]
|
|
// SIMD-ONLY0: if.then1451:
|
|
// SIMD-ONLY0-NEXT: [[TMP899:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP899]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1452]]
|
|
// SIMD-ONLY0: if.end1452:
|
|
// SIMD-ONLY0-NEXT: [[TMP900:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP900]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP901:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1453:%.*]] = sext i16 [[TMP901]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP902:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1454:%.*]] = sext i16 [[TMP902]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1455:%.*]] = icmp slt i32 [[CONV1453]], [[CONV1454]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1455]], label [[IF_THEN1457:%.*]], label [[IF_END1458:%.*]]
|
|
// SIMD-ONLY0: if.then1457:
|
|
// SIMD-ONLY0-NEXT: [[TMP903:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP903]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1458]]
|
|
// SIMD-ONLY0: if.end1458:
|
|
// SIMD-ONLY0-NEXT: [[TMP904:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP904]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP905:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1459:%.*]] = sext i16 [[TMP905]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP906:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1460:%.*]] = sext i16 [[TMP906]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1461:%.*]] = icmp eq i32 [[CONV1459]], [[CONV1460]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1461]], label [[IF_THEN1463:%.*]], label [[IF_END1464:%.*]]
|
|
// SIMD-ONLY0: if.then1463:
|
|
// SIMD-ONLY0-NEXT: [[TMP907:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP907]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1464]]
|
|
// SIMD-ONLY0: if.end1464:
|
|
// SIMD-ONLY0-NEXT: [[TMP908:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP908]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP909:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1465:%.*]] = sext i16 [[TMP909]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP910:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1466:%.*]] = sext i16 [[TMP910]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1467:%.*]] = icmp eq i32 [[CONV1465]], [[CONV1466]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1467]], label [[IF_THEN1469:%.*]], label [[IF_END1470:%.*]]
|
|
// SIMD-ONLY0: if.then1469:
|
|
// SIMD-ONLY0-NEXT: [[TMP911:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP911]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1470]]
|
|
// SIMD-ONLY0: if.end1470:
|
|
// SIMD-ONLY0-NEXT: [[TMP912:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1471:%.*]] = sext i16 [[TMP912]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP913:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1472:%.*]] = sext i16 [[TMP913]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1473:%.*]] = icmp sgt i32 [[CONV1471]], [[CONV1472]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1473]], label [[IF_THEN1475:%.*]], label [[IF_END1476:%.*]]
|
|
// SIMD-ONLY0: if.then1475:
|
|
// SIMD-ONLY0-NEXT: [[TMP914:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP914]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1476]]
|
|
// SIMD-ONLY0: if.end1476:
|
|
// SIMD-ONLY0-NEXT: [[TMP915:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP915]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP916:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1477:%.*]] = sext i16 [[TMP916]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP917:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1478:%.*]] = sext i16 [[TMP917]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1479:%.*]] = icmp sgt i32 [[CONV1477]], [[CONV1478]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1479]], label [[IF_THEN1481:%.*]], label [[IF_END1482:%.*]]
|
|
// SIMD-ONLY0: if.then1481:
|
|
// SIMD-ONLY0-NEXT: [[TMP918:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP918]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1482]]
|
|
// SIMD-ONLY0: if.end1482:
|
|
// SIMD-ONLY0-NEXT: [[TMP919:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP919]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP920:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1483:%.*]] = sext i16 [[TMP920]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP921:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1484:%.*]] = sext i16 [[TMP921]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1485:%.*]] = icmp slt i32 [[CONV1483]], [[CONV1484]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1485]], label [[IF_THEN1487:%.*]], label [[IF_END1488:%.*]]
|
|
// SIMD-ONLY0: if.then1487:
|
|
// SIMD-ONLY0-NEXT: [[TMP922:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP922]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1488]]
|
|
// SIMD-ONLY0: if.end1488:
|
|
// SIMD-ONLY0-NEXT: [[TMP923:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP923]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP924:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1489:%.*]] = sext i16 [[TMP924]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP925:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1490:%.*]] = sext i16 [[TMP925]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1491:%.*]] = icmp slt i32 [[CONV1489]], [[CONV1490]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1491]], label [[IF_THEN1493:%.*]], label [[IF_END1494:%.*]]
|
|
// SIMD-ONLY0: if.then1493:
|
|
// SIMD-ONLY0-NEXT: [[TMP926:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP926]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1494]]
|
|
// SIMD-ONLY0: if.end1494:
|
|
// SIMD-ONLY0-NEXT: [[TMP927:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP927]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP928:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1495:%.*]] = sext i16 [[TMP928]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP929:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1496:%.*]] = sext i16 [[TMP929]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1497:%.*]] = icmp eq i32 [[CONV1495]], [[CONV1496]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1497]], label [[IF_THEN1499:%.*]], label [[IF_END1500:%.*]]
|
|
// SIMD-ONLY0: if.then1499:
|
|
// SIMD-ONLY0-NEXT: [[TMP930:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP930]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1500]]
|
|
// SIMD-ONLY0: if.end1500:
|
|
// SIMD-ONLY0-NEXT: [[TMP931:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP931]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP932:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1501:%.*]] = sext i16 [[TMP932]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP933:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1502:%.*]] = sext i16 [[TMP933]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1503:%.*]] = icmp eq i32 [[CONV1501]], [[CONV1502]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1503]], label [[IF_THEN1505:%.*]], label [[IF_END1506:%.*]]
|
|
// SIMD-ONLY0: if.then1505:
|
|
// SIMD-ONLY0-NEXT: [[TMP934:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP934]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1506]]
|
|
// SIMD-ONLY0: if.end1506:
|
|
// SIMD-ONLY0-NEXT: [[TMP935:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP935]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP936:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1507:%.*]] = sext i16 [[TMP936]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP937:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1508:%.*]] = sext i16 [[TMP937]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1509:%.*]] = icmp eq i32 [[CONV1507]], [[CONV1508]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1509]], label [[IF_THEN1511:%.*]], label [[IF_ELSE1512:%.*]]
|
|
// SIMD-ONLY0: if.then1511:
|
|
// SIMD-ONLY0-NEXT: [[TMP938:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP938]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1513:%.*]]
|
|
// SIMD-ONLY0: if.else1512:
|
|
// SIMD-ONLY0-NEXT: [[TMP939:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP939]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1513]]
|
|
// SIMD-ONLY0: if.end1513:
|
|
// SIMD-ONLY0-NEXT: [[TMP940:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1514:%.*]] = sext i16 [[TMP940]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP941:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1515:%.*]] = sext i16 [[TMP941]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1516:%.*]] = icmp eq i32 [[CONV1514]], [[CONV1515]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1516]], label [[IF_THEN1518:%.*]], label [[IF_ELSE1519:%.*]]
|
|
// SIMD-ONLY0: if.then1518:
|
|
// SIMD-ONLY0-NEXT: [[TMP942:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP942]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1520:%.*]]
|
|
// SIMD-ONLY0: if.else1519:
|
|
// SIMD-ONLY0-NEXT: [[TMP943:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP943]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1520]]
|
|
// SIMD-ONLY0: if.end1520:
|
|
// SIMD-ONLY0-NEXT: [[TMP944:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1521:%.*]] = sext i16 [[TMP944]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP945:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1522:%.*]] = sext i16 [[TMP945]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1523:%.*]] = icmp eq i32 [[CONV1521]], [[CONV1522]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1524:%.*]] = zext i1 [[CMP1523]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1525:%.*]] = trunc i32 [[CONV1524]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1525]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP946:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1526:%.*]] = icmp ne i16 [[TMP946]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1526]], label [[IF_THEN1527:%.*]], label [[IF_END1528:%.*]]
|
|
// SIMD-ONLY0: if.then1527:
|
|
// SIMD-ONLY0-NEXT: [[TMP947:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP947]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1528]]
|
|
// SIMD-ONLY0: if.end1528:
|
|
// SIMD-ONLY0-NEXT: [[TMP948:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1529:%.*]] = sext i16 [[TMP948]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP949:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1530:%.*]] = sext i16 [[TMP949]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1531:%.*]] = icmp eq i32 [[CONV1529]], [[CONV1530]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1532:%.*]] = zext i1 [[CMP1531]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1533:%.*]] = trunc i32 [[CONV1532]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1533]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP950:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1534:%.*]] = icmp ne i16 [[TMP950]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1534]], label [[IF_THEN1535:%.*]], label [[IF_END1536:%.*]]
|
|
// SIMD-ONLY0: if.then1535:
|
|
// SIMD-ONLY0-NEXT: [[TMP951:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP951]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1536]]
|
|
// SIMD-ONLY0: if.end1536:
|
|
// SIMD-ONLY0-NEXT: [[TMP952:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1537:%.*]] = sext i16 [[TMP952]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP953:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1538:%.*]] = sext i16 [[TMP953]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1539:%.*]] = icmp eq i32 [[CONV1537]], [[CONV1538]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1540:%.*]] = zext i1 [[CMP1539]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1541:%.*]] = trunc i32 [[CONV1540]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1541]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP954:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1542:%.*]] = icmp ne i16 [[TMP954]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1542]], label [[IF_THEN1543:%.*]], label [[IF_ELSE1544:%.*]]
|
|
// SIMD-ONLY0: if.then1543:
|
|
// SIMD-ONLY0-NEXT: [[TMP955:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP955]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1545:%.*]]
|
|
// SIMD-ONLY0: if.else1544:
|
|
// SIMD-ONLY0-NEXT: [[TMP956:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP956]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1545]]
|
|
// SIMD-ONLY0: if.end1545:
|
|
// SIMD-ONLY0-NEXT: [[TMP957:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1546:%.*]] = sext i16 [[TMP957]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP958:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1547:%.*]] = sext i16 [[TMP958]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1548:%.*]] = icmp eq i32 [[CONV1546]], [[CONV1547]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1549:%.*]] = zext i1 [[CMP1548]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1550:%.*]] = trunc i32 [[CONV1549]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1550]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP959:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1551:%.*]] = icmp ne i16 [[TMP959]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1551]], label [[IF_THEN1552:%.*]], label [[IF_ELSE1553:%.*]]
|
|
// SIMD-ONLY0: if.then1552:
|
|
// SIMD-ONLY0-NEXT: [[TMP960:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP960]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1554:%.*]]
|
|
// SIMD-ONLY0: if.else1553:
|
|
// SIMD-ONLY0-NEXT: [[TMP961:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP961]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1554]]
|
|
// SIMD-ONLY0: if.end1554:
|
|
// SIMD-ONLY0-NEXT: [[TMP962:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP962]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP963:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1555:%.*]] = sext i16 [[TMP963]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP964:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1556:%.*]] = sext i16 [[TMP964]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1557:%.*]] = icmp sgt i32 [[CONV1555]], [[CONV1556]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1557]], label [[IF_THEN1559:%.*]], label [[IF_END1560:%.*]]
|
|
// SIMD-ONLY0: if.then1559:
|
|
// SIMD-ONLY0-NEXT: [[TMP965:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP965]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1560]]
|
|
// SIMD-ONLY0: if.end1560:
|
|
// SIMD-ONLY0-NEXT: [[TMP966:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP966]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP967:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1561:%.*]] = sext i16 [[TMP967]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP968:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1562:%.*]] = sext i16 [[TMP968]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1563:%.*]] = icmp sgt i32 [[CONV1561]], [[CONV1562]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1563]], label [[IF_THEN1565:%.*]], label [[IF_END1566:%.*]]
|
|
// SIMD-ONLY0: if.then1565:
|
|
// SIMD-ONLY0-NEXT: [[TMP969:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP969]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1566]]
|
|
// SIMD-ONLY0: if.end1566:
|
|
// SIMD-ONLY0-NEXT: [[TMP970:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP970]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP971:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1567:%.*]] = sext i16 [[TMP971]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP972:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1568:%.*]] = sext i16 [[TMP972]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1569:%.*]] = icmp slt i32 [[CONV1567]], [[CONV1568]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1569]], label [[IF_THEN1571:%.*]], label [[IF_END1572:%.*]]
|
|
// SIMD-ONLY0: if.then1571:
|
|
// SIMD-ONLY0-NEXT: [[TMP973:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP973]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1572]]
|
|
// SIMD-ONLY0: if.end1572:
|
|
// SIMD-ONLY0-NEXT: [[TMP974:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP974]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP975:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1573:%.*]] = sext i16 [[TMP975]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP976:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1574:%.*]] = sext i16 [[TMP976]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1575:%.*]] = icmp slt i32 [[CONV1573]], [[CONV1574]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1575]], label [[IF_THEN1577:%.*]], label [[IF_END1578:%.*]]
|
|
// SIMD-ONLY0: if.then1577:
|
|
// SIMD-ONLY0-NEXT: [[TMP977:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP977]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1578]]
|
|
// SIMD-ONLY0: if.end1578:
|
|
// SIMD-ONLY0-NEXT: [[TMP978:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP978]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP979:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1579:%.*]] = sext i16 [[TMP979]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP980:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1580:%.*]] = sext i16 [[TMP980]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1581:%.*]] = icmp eq i32 [[CONV1579]], [[CONV1580]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1581]], label [[IF_THEN1583:%.*]], label [[IF_END1584:%.*]]
|
|
// SIMD-ONLY0: if.then1583:
|
|
// SIMD-ONLY0-NEXT: [[TMP981:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP981]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1584]]
|
|
// SIMD-ONLY0: if.end1584:
|
|
// SIMD-ONLY0-NEXT: [[TMP982:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP982]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP983:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1585:%.*]] = sext i16 [[TMP983]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP984:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1586:%.*]] = sext i16 [[TMP984]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1587:%.*]] = icmp eq i32 [[CONV1585]], [[CONV1586]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1587]], label [[IF_THEN1589:%.*]], label [[IF_END1590:%.*]]
|
|
// SIMD-ONLY0: if.then1589:
|
|
// SIMD-ONLY0-NEXT: [[TMP985:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP985]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1590]]
|
|
// SIMD-ONLY0: if.end1590:
|
|
// SIMD-ONLY0-NEXT: [[TMP986:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1591:%.*]] = sext i16 [[TMP986]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP987:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1592:%.*]] = sext i16 [[TMP987]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1593:%.*]] = icmp sgt i32 [[CONV1591]], [[CONV1592]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1593]], label [[IF_THEN1595:%.*]], label [[IF_END1596:%.*]]
|
|
// SIMD-ONLY0: if.then1595:
|
|
// SIMD-ONLY0-NEXT: [[TMP988:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP988]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1596]]
|
|
// SIMD-ONLY0: if.end1596:
|
|
// SIMD-ONLY0-NEXT: [[TMP989:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP989]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP990:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1597:%.*]] = sext i16 [[TMP990]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP991:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1598:%.*]] = sext i16 [[TMP991]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1599:%.*]] = icmp sgt i32 [[CONV1597]], [[CONV1598]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1599]], label [[IF_THEN1601:%.*]], label [[IF_END1602:%.*]]
|
|
// SIMD-ONLY0: if.then1601:
|
|
// SIMD-ONLY0-NEXT: [[TMP992:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP992]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1602]]
|
|
// SIMD-ONLY0: if.end1602:
|
|
// SIMD-ONLY0-NEXT: [[TMP993:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP993]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP994:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1603:%.*]] = sext i16 [[TMP994]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP995:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1604:%.*]] = sext i16 [[TMP995]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1605:%.*]] = icmp slt i32 [[CONV1603]], [[CONV1604]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1605]], label [[IF_THEN1607:%.*]], label [[IF_END1608:%.*]]
|
|
// SIMD-ONLY0: if.then1607:
|
|
// SIMD-ONLY0-NEXT: [[TMP996:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP996]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1608]]
|
|
// SIMD-ONLY0: if.end1608:
|
|
// SIMD-ONLY0-NEXT: [[TMP997:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP997]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP998:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1609:%.*]] = sext i16 [[TMP998]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP999:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1610:%.*]] = sext i16 [[TMP999]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1611:%.*]] = icmp slt i32 [[CONV1609]], [[CONV1610]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1611]], label [[IF_THEN1613:%.*]], label [[IF_END1614:%.*]]
|
|
// SIMD-ONLY0: if.then1613:
|
|
// SIMD-ONLY0-NEXT: [[TMP1000:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1000]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1614]]
|
|
// SIMD-ONLY0: if.end1614:
|
|
// SIMD-ONLY0-NEXT: [[TMP1001:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1001]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1002:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1615:%.*]] = sext i16 [[TMP1002]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1003:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1616:%.*]] = sext i16 [[TMP1003]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1617:%.*]] = icmp eq i32 [[CONV1615]], [[CONV1616]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1617]], label [[IF_THEN1619:%.*]], label [[IF_END1620:%.*]]
|
|
// SIMD-ONLY0: if.then1619:
|
|
// SIMD-ONLY0-NEXT: [[TMP1004:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1004]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1620]]
|
|
// SIMD-ONLY0: if.end1620:
|
|
// SIMD-ONLY0-NEXT: [[TMP1005:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1005]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1006:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1621:%.*]] = sext i16 [[TMP1006]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1007:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1622:%.*]] = sext i16 [[TMP1007]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1623:%.*]] = icmp eq i32 [[CONV1621]], [[CONV1622]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1623]], label [[IF_THEN1625:%.*]], label [[IF_END1626:%.*]]
|
|
// SIMD-ONLY0: if.then1625:
|
|
// SIMD-ONLY0-NEXT: [[TMP1008:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1008]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1626]]
|
|
// SIMD-ONLY0: if.end1626:
|
|
// SIMD-ONLY0-NEXT: [[TMP1009:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1009]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1010:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1627:%.*]] = sext i16 [[TMP1010]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1011:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1628:%.*]] = sext i16 [[TMP1011]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1629:%.*]] = icmp eq i32 [[CONV1627]], [[CONV1628]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1629]], label [[IF_THEN1631:%.*]], label [[IF_ELSE1632:%.*]]
|
|
// SIMD-ONLY0: if.then1631:
|
|
// SIMD-ONLY0-NEXT: [[TMP1012:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1012]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1633:%.*]]
|
|
// SIMD-ONLY0: if.else1632:
|
|
// SIMD-ONLY0-NEXT: [[TMP1013:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1013]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1633]]
|
|
// SIMD-ONLY0: if.end1633:
|
|
// SIMD-ONLY0-NEXT: [[TMP1014:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1634:%.*]] = sext i16 [[TMP1014]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1015:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1635:%.*]] = sext i16 [[TMP1015]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1636:%.*]] = icmp eq i32 [[CONV1634]], [[CONV1635]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1636]], label [[IF_THEN1638:%.*]], label [[IF_ELSE1639:%.*]]
|
|
// SIMD-ONLY0: if.then1638:
|
|
// SIMD-ONLY0-NEXT: [[TMP1016:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1016]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1640:%.*]]
|
|
// SIMD-ONLY0: if.else1639:
|
|
// SIMD-ONLY0-NEXT: [[TMP1017:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1017]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1640]]
|
|
// SIMD-ONLY0: if.end1640:
|
|
// SIMD-ONLY0-NEXT: [[TMP1018:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1641:%.*]] = sext i16 [[TMP1018]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1019:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1642:%.*]] = sext i16 [[TMP1019]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1643:%.*]] = icmp eq i32 [[CONV1641]], [[CONV1642]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1644:%.*]] = zext i1 [[CMP1643]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1645:%.*]] = trunc i32 [[CONV1644]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1645]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1020:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1646:%.*]] = icmp ne i16 [[TMP1020]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1646]], label [[IF_THEN1647:%.*]], label [[IF_END1648:%.*]]
|
|
// SIMD-ONLY0: if.then1647:
|
|
// SIMD-ONLY0-NEXT: [[TMP1021:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1021]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1648]]
|
|
// SIMD-ONLY0: if.end1648:
|
|
// SIMD-ONLY0-NEXT: [[TMP1022:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1649:%.*]] = sext i16 [[TMP1022]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1023:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1650:%.*]] = sext i16 [[TMP1023]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1651:%.*]] = icmp eq i32 [[CONV1649]], [[CONV1650]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1652:%.*]] = zext i1 [[CMP1651]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1653:%.*]] = trunc i32 [[CONV1652]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1653]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1024:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1654:%.*]] = icmp ne i16 [[TMP1024]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1654]], label [[IF_THEN1655:%.*]], label [[IF_END1656:%.*]]
|
|
// SIMD-ONLY0: if.then1655:
|
|
// SIMD-ONLY0-NEXT: [[TMP1025:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1025]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1656]]
|
|
// SIMD-ONLY0: if.end1656:
|
|
// SIMD-ONLY0-NEXT: [[TMP1026:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1657:%.*]] = sext i16 [[TMP1026]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1027:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1658:%.*]] = sext i16 [[TMP1027]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1659:%.*]] = icmp eq i32 [[CONV1657]], [[CONV1658]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1660:%.*]] = zext i1 [[CMP1659]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1661:%.*]] = trunc i32 [[CONV1660]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1661]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1028:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1662:%.*]] = icmp ne i16 [[TMP1028]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1662]], label [[IF_THEN1663:%.*]], label [[IF_ELSE1664:%.*]]
|
|
// SIMD-ONLY0: if.then1663:
|
|
// SIMD-ONLY0-NEXT: [[TMP1029:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1029]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1665:%.*]]
|
|
// SIMD-ONLY0: if.else1664:
|
|
// SIMD-ONLY0-NEXT: [[TMP1030:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1030]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1665]]
|
|
// SIMD-ONLY0: if.end1665:
|
|
// SIMD-ONLY0-NEXT: [[TMP1031:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1666:%.*]] = sext i16 [[TMP1031]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1032:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1667:%.*]] = sext i16 [[TMP1032]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1668:%.*]] = icmp eq i32 [[CONV1666]], [[CONV1667]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1669:%.*]] = zext i1 [[CMP1668]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1670:%.*]] = trunc i32 [[CONV1669]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1670]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1033:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1671:%.*]] = icmp ne i16 [[TMP1033]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1671]], label [[IF_THEN1672:%.*]], label [[IF_ELSE1673:%.*]]
|
|
// SIMD-ONLY0: if.then1672:
|
|
// SIMD-ONLY0-NEXT: [[TMP1034:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1034]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1674:%.*]]
|
|
// SIMD-ONLY0: if.else1673:
|
|
// SIMD-ONLY0-NEXT: [[TMP1035:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1035]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1674]]
|
|
// SIMD-ONLY0: if.end1674:
|
|
// SIMD-ONLY0-NEXT: [[TMP1036:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1036]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1037:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1675:%.*]] = sext i16 [[TMP1037]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1038:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1676:%.*]] = sext i16 [[TMP1038]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1677:%.*]] = icmp sgt i32 [[CONV1675]], [[CONV1676]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1677]], label [[IF_THEN1679:%.*]], label [[IF_END1680:%.*]]
|
|
// SIMD-ONLY0: if.then1679:
|
|
// SIMD-ONLY0-NEXT: [[TMP1039:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1039]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1680]]
|
|
// SIMD-ONLY0: if.end1680:
|
|
// SIMD-ONLY0-NEXT: [[TMP1040:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1040]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1041:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1681:%.*]] = sext i16 [[TMP1041]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1042:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1682:%.*]] = sext i16 [[TMP1042]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1683:%.*]] = icmp sgt i32 [[CONV1681]], [[CONV1682]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1683]], label [[IF_THEN1685:%.*]], label [[IF_END1686:%.*]]
|
|
// SIMD-ONLY0: if.then1685:
|
|
// SIMD-ONLY0-NEXT: [[TMP1043:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1043]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1686]]
|
|
// SIMD-ONLY0: if.end1686:
|
|
// SIMD-ONLY0-NEXT: [[TMP1044:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1044]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1045:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1687:%.*]] = sext i16 [[TMP1045]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1046:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1688:%.*]] = sext i16 [[TMP1046]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1689:%.*]] = icmp slt i32 [[CONV1687]], [[CONV1688]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1689]], label [[IF_THEN1691:%.*]], label [[IF_END1692:%.*]]
|
|
// SIMD-ONLY0: if.then1691:
|
|
// SIMD-ONLY0-NEXT: [[TMP1047:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1047]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1692]]
|
|
// SIMD-ONLY0: if.end1692:
|
|
// SIMD-ONLY0-NEXT: [[TMP1048:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1048]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1049:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1693:%.*]] = sext i16 [[TMP1049]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1050:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1694:%.*]] = sext i16 [[TMP1050]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1695:%.*]] = icmp slt i32 [[CONV1693]], [[CONV1694]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1695]], label [[IF_THEN1697:%.*]], label [[IF_END1698:%.*]]
|
|
// SIMD-ONLY0: if.then1697:
|
|
// SIMD-ONLY0-NEXT: [[TMP1051:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1051]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1698]]
|
|
// SIMD-ONLY0: if.end1698:
|
|
// SIMD-ONLY0-NEXT: [[TMP1052:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1052]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1053:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1699:%.*]] = sext i16 [[TMP1053]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1054:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1700:%.*]] = sext i16 [[TMP1054]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1701:%.*]] = icmp eq i32 [[CONV1699]], [[CONV1700]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1701]], label [[IF_THEN1703:%.*]], label [[IF_END1704:%.*]]
|
|
// SIMD-ONLY0: if.then1703:
|
|
// SIMD-ONLY0-NEXT: [[TMP1055:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1055]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1704]]
|
|
// SIMD-ONLY0: if.end1704:
|
|
// SIMD-ONLY0-NEXT: [[TMP1056:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1056]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1057:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1705:%.*]] = sext i16 [[TMP1057]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1058:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1706:%.*]] = sext i16 [[TMP1058]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1707:%.*]] = icmp eq i32 [[CONV1705]], [[CONV1706]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1707]], label [[IF_THEN1709:%.*]], label [[IF_END1710:%.*]]
|
|
// SIMD-ONLY0: if.then1709:
|
|
// SIMD-ONLY0-NEXT: [[TMP1059:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1059]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1710]]
|
|
// SIMD-ONLY0: if.end1710:
|
|
// SIMD-ONLY0-NEXT: [[TMP1060:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1711:%.*]] = sext i16 [[TMP1060]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1061:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1712:%.*]] = sext i16 [[TMP1061]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1713:%.*]] = icmp sgt i32 [[CONV1711]], [[CONV1712]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1713]], label [[IF_THEN1715:%.*]], label [[IF_END1716:%.*]]
|
|
// SIMD-ONLY0: if.then1715:
|
|
// SIMD-ONLY0-NEXT: [[TMP1062:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1062]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1716]]
|
|
// SIMD-ONLY0: if.end1716:
|
|
// SIMD-ONLY0-NEXT: [[TMP1063:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1063]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1064:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1717:%.*]] = sext i16 [[TMP1064]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1065:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1718:%.*]] = sext i16 [[TMP1065]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1719:%.*]] = icmp sgt i32 [[CONV1717]], [[CONV1718]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1719]], label [[IF_THEN1721:%.*]], label [[IF_END1722:%.*]]
|
|
// SIMD-ONLY0: if.then1721:
|
|
// SIMD-ONLY0-NEXT: [[TMP1066:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1066]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1722]]
|
|
// SIMD-ONLY0: if.end1722:
|
|
// SIMD-ONLY0-NEXT: [[TMP1067:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1067]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1068:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1723:%.*]] = sext i16 [[TMP1068]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1069:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1724:%.*]] = sext i16 [[TMP1069]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1725:%.*]] = icmp slt i32 [[CONV1723]], [[CONV1724]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1725]], label [[IF_THEN1727:%.*]], label [[IF_END1728:%.*]]
|
|
// SIMD-ONLY0: if.then1727:
|
|
// SIMD-ONLY0-NEXT: [[TMP1070:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1070]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1728]]
|
|
// SIMD-ONLY0: if.end1728:
|
|
// SIMD-ONLY0-NEXT: [[TMP1071:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1071]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1072:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1729:%.*]] = sext i16 [[TMP1072]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1073:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1730:%.*]] = sext i16 [[TMP1073]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1731:%.*]] = icmp slt i32 [[CONV1729]], [[CONV1730]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1731]], label [[IF_THEN1733:%.*]], label [[IF_END1734:%.*]]
|
|
// SIMD-ONLY0: if.then1733:
|
|
// SIMD-ONLY0-NEXT: [[TMP1074:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1074]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1734]]
|
|
// SIMD-ONLY0: if.end1734:
|
|
// SIMD-ONLY0-NEXT: [[TMP1075:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1075]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1076:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1735:%.*]] = sext i16 [[TMP1076]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1077:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1736:%.*]] = sext i16 [[TMP1077]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1737:%.*]] = icmp eq i32 [[CONV1735]], [[CONV1736]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1737]], label [[IF_THEN1739:%.*]], label [[IF_END1740:%.*]]
|
|
// SIMD-ONLY0: if.then1739:
|
|
// SIMD-ONLY0-NEXT: [[TMP1078:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1078]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1740]]
|
|
// SIMD-ONLY0: if.end1740:
|
|
// SIMD-ONLY0-NEXT: [[TMP1079:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1079]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1080:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1741:%.*]] = sext i16 [[TMP1080]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1081:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1742:%.*]] = sext i16 [[TMP1081]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1743:%.*]] = icmp eq i32 [[CONV1741]], [[CONV1742]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1743]], label [[IF_THEN1745:%.*]], label [[IF_END1746:%.*]]
|
|
// SIMD-ONLY0: if.then1745:
|
|
// SIMD-ONLY0-NEXT: [[TMP1082:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1082]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1746]]
|
|
// SIMD-ONLY0: if.end1746:
|
|
// SIMD-ONLY0-NEXT: [[TMP1083:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1083]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1084:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1747:%.*]] = sext i16 [[TMP1084]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1085:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1748:%.*]] = sext i16 [[TMP1085]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1749:%.*]] = icmp eq i32 [[CONV1747]], [[CONV1748]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1749]], label [[IF_THEN1751:%.*]], label [[IF_ELSE1752:%.*]]
|
|
// SIMD-ONLY0: if.then1751:
|
|
// SIMD-ONLY0-NEXT: [[TMP1086:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1086]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1753:%.*]]
|
|
// SIMD-ONLY0: if.else1752:
|
|
// SIMD-ONLY0-NEXT: [[TMP1087:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1087]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1753]]
|
|
// SIMD-ONLY0: if.end1753:
|
|
// SIMD-ONLY0-NEXT: [[TMP1088:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1754:%.*]] = sext i16 [[TMP1088]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1089:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1755:%.*]] = sext i16 [[TMP1089]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1756:%.*]] = icmp eq i32 [[CONV1754]], [[CONV1755]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1756]], label [[IF_THEN1758:%.*]], label [[IF_ELSE1759:%.*]]
|
|
// SIMD-ONLY0: if.then1758:
|
|
// SIMD-ONLY0-NEXT: [[TMP1090:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1090]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1760:%.*]]
|
|
// SIMD-ONLY0: if.else1759:
|
|
// SIMD-ONLY0-NEXT: [[TMP1091:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1091]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1760]]
|
|
// SIMD-ONLY0: if.end1760:
|
|
// SIMD-ONLY0-NEXT: [[TMP1092:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1761:%.*]] = sext i16 [[TMP1092]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1093:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1762:%.*]] = sext i16 [[TMP1093]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1763:%.*]] = icmp eq i32 [[CONV1761]], [[CONV1762]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1764:%.*]] = zext i1 [[CMP1763]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1765:%.*]] = trunc i32 [[CONV1764]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1765]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1094:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1766:%.*]] = icmp ne i16 [[TMP1094]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1766]], label [[IF_THEN1767:%.*]], label [[IF_END1768:%.*]]
|
|
// SIMD-ONLY0: if.then1767:
|
|
// SIMD-ONLY0-NEXT: [[TMP1095:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1095]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1768]]
|
|
// SIMD-ONLY0: if.end1768:
|
|
// SIMD-ONLY0-NEXT: [[TMP1096:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1769:%.*]] = sext i16 [[TMP1096]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1097:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1770:%.*]] = sext i16 [[TMP1097]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1771:%.*]] = icmp eq i32 [[CONV1769]], [[CONV1770]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1772:%.*]] = zext i1 [[CMP1771]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1773:%.*]] = trunc i32 [[CONV1772]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1773]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1098:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1774:%.*]] = icmp ne i16 [[TMP1098]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1774]], label [[IF_THEN1775:%.*]], label [[IF_END1776:%.*]]
|
|
// SIMD-ONLY0: if.then1775:
|
|
// SIMD-ONLY0-NEXT: [[TMP1099:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1099]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1776]]
|
|
// SIMD-ONLY0: if.end1776:
|
|
// SIMD-ONLY0-NEXT: [[TMP1100:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1777:%.*]] = sext i16 [[TMP1100]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1101:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1778:%.*]] = sext i16 [[TMP1101]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1779:%.*]] = icmp eq i32 [[CONV1777]], [[CONV1778]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1780:%.*]] = zext i1 [[CMP1779]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1781:%.*]] = trunc i32 [[CONV1780]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1781]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1102:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1782:%.*]] = icmp ne i16 [[TMP1102]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1782]], label [[IF_THEN1783:%.*]], label [[IF_ELSE1784:%.*]]
|
|
// SIMD-ONLY0: if.then1783:
|
|
// SIMD-ONLY0-NEXT: [[TMP1103:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1103]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1785:%.*]]
|
|
// SIMD-ONLY0: if.else1784:
|
|
// SIMD-ONLY0-NEXT: [[TMP1104:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1104]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1785]]
|
|
// SIMD-ONLY0: if.end1785:
|
|
// SIMD-ONLY0-NEXT: [[TMP1105:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1786:%.*]] = sext i16 [[TMP1105]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1106:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1787:%.*]] = sext i16 [[TMP1106]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1788:%.*]] = icmp eq i32 [[CONV1786]], [[CONV1787]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1789:%.*]] = zext i1 [[CMP1788]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1790:%.*]] = trunc i32 [[CONV1789]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1790]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1107:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1791:%.*]] = icmp ne i16 [[TMP1107]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1791]], label [[IF_THEN1792:%.*]], label [[IF_ELSE1793:%.*]]
|
|
// SIMD-ONLY0: if.then1792:
|
|
// SIMD-ONLY0-NEXT: [[TMP1108:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1108]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1794:%.*]]
|
|
// SIMD-ONLY0: if.else1793:
|
|
// SIMD-ONLY0-NEXT: [[TMP1109:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1109]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1794]]
|
|
// SIMD-ONLY0: if.end1794:
|
|
// SIMD-ONLY0-NEXT: [[TMP1110:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1110]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1111:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1795:%.*]] = sext i16 [[TMP1111]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1112:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1796:%.*]] = sext i16 [[TMP1112]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1797:%.*]] = icmp sgt i32 [[CONV1795]], [[CONV1796]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1797]], label [[IF_THEN1799:%.*]], label [[IF_END1800:%.*]]
|
|
// SIMD-ONLY0: if.then1799:
|
|
// SIMD-ONLY0-NEXT: [[TMP1113:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1113]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1800]]
|
|
// SIMD-ONLY0: if.end1800:
|
|
// SIMD-ONLY0-NEXT: [[TMP1114:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1114]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1115:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1801:%.*]] = sext i16 [[TMP1115]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1116:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1802:%.*]] = sext i16 [[TMP1116]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1803:%.*]] = icmp sgt i32 [[CONV1801]], [[CONV1802]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1803]], label [[IF_THEN1805:%.*]], label [[IF_END1806:%.*]]
|
|
// SIMD-ONLY0: if.then1805:
|
|
// SIMD-ONLY0-NEXT: [[TMP1117:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1117]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1806]]
|
|
// SIMD-ONLY0: if.end1806:
|
|
// SIMD-ONLY0-NEXT: [[TMP1118:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1118]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1119:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1807:%.*]] = sext i16 [[TMP1119]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1120:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1808:%.*]] = sext i16 [[TMP1120]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1809:%.*]] = icmp slt i32 [[CONV1807]], [[CONV1808]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1809]], label [[IF_THEN1811:%.*]], label [[IF_END1812:%.*]]
|
|
// SIMD-ONLY0: if.then1811:
|
|
// SIMD-ONLY0-NEXT: [[TMP1121:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1121]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1812]]
|
|
// SIMD-ONLY0: if.end1812:
|
|
// SIMD-ONLY0-NEXT: [[TMP1122:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1122]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1123:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1813:%.*]] = sext i16 [[TMP1123]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1124:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1814:%.*]] = sext i16 [[TMP1124]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1815:%.*]] = icmp slt i32 [[CONV1813]], [[CONV1814]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1815]], label [[IF_THEN1817:%.*]], label [[IF_END1818:%.*]]
|
|
// SIMD-ONLY0: if.then1817:
|
|
// SIMD-ONLY0-NEXT: [[TMP1125:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1125]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1818]]
|
|
// SIMD-ONLY0: if.end1818:
|
|
// SIMD-ONLY0-NEXT: [[TMP1126:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1126]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1127:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1819:%.*]] = sext i16 [[TMP1127]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1128:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1820:%.*]] = sext i16 [[TMP1128]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1821:%.*]] = icmp eq i32 [[CONV1819]], [[CONV1820]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1821]], label [[IF_THEN1823:%.*]], label [[IF_END1824:%.*]]
|
|
// SIMD-ONLY0: if.then1823:
|
|
// SIMD-ONLY0-NEXT: [[TMP1129:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1129]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1824]]
|
|
// SIMD-ONLY0: if.end1824:
|
|
// SIMD-ONLY0-NEXT: [[TMP1130:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1130]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1131:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1825:%.*]] = sext i16 [[TMP1131]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1132:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1826:%.*]] = sext i16 [[TMP1132]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1827:%.*]] = icmp eq i32 [[CONV1825]], [[CONV1826]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1827]], label [[IF_THEN1829:%.*]], label [[IF_END1830:%.*]]
|
|
// SIMD-ONLY0: if.then1829:
|
|
// SIMD-ONLY0-NEXT: [[TMP1133:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1133]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1830]]
|
|
// SIMD-ONLY0: if.end1830:
|
|
// SIMD-ONLY0-NEXT: [[TMP1134:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1831:%.*]] = sext i16 [[TMP1134]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1135:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1832:%.*]] = sext i16 [[TMP1135]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1833:%.*]] = icmp sgt i32 [[CONV1831]], [[CONV1832]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1833]], label [[IF_THEN1835:%.*]], label [[IF_END1836:%.*]]
|
|
// SIMD-ONLY0: if.then1835:
|
|
// SIMD-ONLY0-NEXT: [[TMP1136:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1136]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1836]]
|
|
// SIMD-ONLY0: if.end1836:
|
|
// SIMD-ONLY0-NEXT: [[TMP1137:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1137]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1138:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1837:%.*]] = sext i16 [[TMP1138]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1139:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1838:%.*]] = sext i16 [[TMP1139]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1839:%.*]] = icmp sgt i32 [[CONV1837]], [[CONV1838]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1839]], label [[IF_THEN1841:%.*]], label [[IF_END1842:%.*]]
|
|
// SIMD-ONLY0: if.then1841:
|
|
// SIMD-ONLY0-NEXT: [[TMP1140:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1140]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1842]]
|
|
// SIMD-ONLY0: if.end1842:
|
|
// SIMD-ONLY0-NEXT: [[TMP1141:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1141]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1142:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1843:%.*]] = sext i16 [[TMP1142]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1143:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1844:%.*]] = sext i16 [[TMP1143]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1845:%.*]] = icmp slt i32 [[CONV1843]], [[CONV1844]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1845]], label [[IF_THEN1847:%.*]], label [[IF_END1848:%.*]]
|
|
// SIMD-ONLY0: if.then1847:
|
|
// SIMD-ONLY0-NEXT: [[TMP1144:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1144]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1848]]
|
|
// SIMD-ONLY0: if.end1848:
|
|
// SIMD-ONLY0-NEXT: [[TMP1145:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1145]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1146:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1849:%.*]] = sext i16 [[TMP1146]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1147:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1850:%.*]] = sext i16 [[TMP1147]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1851:%.*]] = icmp slt i32 [[CONV1849]], [[CONV1850]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1851]], label [[IF_THEN1853:%.*]], label [[IF_END1854:%.*]]
|
|
// SIMD-ONLY0: if.then1853:
|
|
// SIMD-ONLY0-NEXT: [[TMP1148:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1148]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1854]]
|
|
// SIMD-ONLY0: if.end1854:
|
|
// SIMD-ONLY0-NEXT: [[TMP1149:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1149]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1150:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1855:%.*]] = sext i16 [[TMP1150]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1151:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1856:%.*]] = sext i16 [[TMP1151]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1857:%.*]] = icmp eq i32 [[CONV1855]], [[CONV1856]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1857]], label [[IF_THEN1859:%.*]], label [[IF_END1860:%.*]]
|
|
// SIMD-ONLY0: if.then1859:
|
|
// SIMD-ONLY0-NEXT: [[TMP1152:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1152]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1860]]
|
|
// SIMD-ONLY0: if.end1860:
|
|
// SIMD-ONLY0-NEXT: [[TMP1153:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1153]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1154:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1861:%.*]] = sext i16 [[TMP1154]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1155:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1862:%.*]] = sext i16 [[TMP1155]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1863:%.*]] = icmp eq i32 [[CONV1861]], [[CONV1862]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1863]], label [[IF_THEN1865:%.*]], label [[IF_END1866:%.*]]
|
|
// SIMD-ONLY0: if.then1865:
|
|
// SIMD-ONLY0-NEXT: [[TMP1156:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1156]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1866]]
|
|
// SIMD-ONLY0: if.end1866:
|
|
// SIMD-ONLY0-NEXT: [[TMP1157:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1157]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1158:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1867:%.*]] = sext i16 [[TMP1158]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1159:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1868:%.*]] = sext i16 [[TMP1159]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1869:%.*]] = icmp eq i32 [[CONV1867]], [[CONV1868]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1869]], label [[IF_THEN1871:%.*]], label [[IF_ELSE1872:%.*]]
|
|
// SIMD-ONLY0: if.then1871:
|
|
// SIMD-ONLY0-NEXT: [[TMP1160:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1160]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1873:%.*]]
|
|
// SIMD-ONLY0: if.else1872:
|
|
// SIMD-ONLY0-NEXT: [[TMP1161:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1161]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1873]]
|
|
// SIMD-ONLY0: if.end1873:
|
|
// SIMD-ONLY0-NEXT: [[TMP1162:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1874:%.*]] = sext i16 [[TMP1162]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1163:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1875:%.*]] = sext i16 [[TMP1163]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1876:%.*]] = icmp eq i32 [[CONV1874]], [[CONV1875]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1876]], label [[IF_THEN1878:%.*]], label [[IF_ELSE1879:%.*]]
|
|
// SIMD-ONLY0: if.then1878:
|
|
// SIMD-ONLY0-NEXT: [[TMP1164:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1164]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1880:%.*]]
|
|
// SIMD-ONLY0: if.else1879:
|
|
// SIMD-ONLY0-NEXT: [[TMP1165:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1165]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1880]]
|
|
// SIMD-ONLY0: if.end1880:
|
|
// SIMD-ONLY0-NEXT: [[TMP1166:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1881:%.*]] = sext i16 [[TMP1166]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1167:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1882:%.*]] = sext i16 [[TMP1167]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1883:%.*]] = icmp eq i32 [[CONV1881]], [[CONV1882]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1884:%.*]] = zext i1 [[CMP1883]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1885:%.*]] = trunc i32 [[CONV1884]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1885]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1168:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1886:%.*]] = icmp ne i16 [[TMP1168]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1886]], label [[IF_THEN1887:%.*]], label [[IF_END1888:%.*]]
|
|
// SIMD-ONLY0: if.then1887:
|
|
// SIMD-ONLY0-NEXT: [[TMP1169:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1169]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1888]]
|
|
// SIMD-ONLY0: if.end1888:
|
|
// SIMD-ONLY0-NEXT: [[TMP1170:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1889:%.*]] = sext i16 [[TMP1170]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1171:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1890:%.*]] = sext i16 [[TMP1171]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1891:%.*]] = icmp eq i32 [[CONV1889]], [[CONV1890]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1892:%.*]] = zext i1 [[CMP1891]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1893:%.*]] = trunc i32 [[CONV1892]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1893]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1172:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1894:%.*]] = icmp ne i16 [[TMP1172]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1894]], label [[IF_THEN1895:%.*]], label [[IF_END1896:%.*]]
|
|
// SIMD-ONLY0: if.then1895:
|
|
// SIMD-ONLY0-NEXT: [[TMP1173:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1173]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1896]]
|
|
// SIMD-ONLY0: if.end1896:
|
|
// SIMD-ONLY0-NEXT: [[TMP1174:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1897:%.*]] = sext i16 [[TMP1174]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1175:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1898:%.*]] = sext i16 [[TMP1175]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1899:%.*]] = icmp eq i32 [[CONV1897]], [[CONV1898]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1900:%.*]] = zext i1 [[CMP1899]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1901:%.*]] = trunc i32 [[CONV1900]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1901]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1176:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1902:%.*]] = icmp ne i16 [[TMP1176]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1902]], label [[IF_THEN1903:%.*]], label [[IF_ELSE1904:%.*]]
|
|
// SIMD-ONLY0: if.then1903:
|
|
// SIMD-ONLY0-NEXT: [[TMP1177:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1177]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1905:%.*]]
|
|
// SIMD-ONLY0: if.else1904:
|
|
// SIMD-ONLY0-NEXT: [[TMP1178:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1178]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1905]]
|
|
// SIMD-ONLY0: if.end1905:
|
|
// SIMD-ONLY0-NEXT: [[TMP1179:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1906:%.*]] = sext i16 [[TMP1179]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1180:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1907:%.*]] = sext i16 [[TMP1180]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1908:%.*]] = icmp eq i32 [[CONV1906]], [[CONV1907]]
|
|
// SIMD-ONLY0-NEXT: [[CONV1909:%.*]] = zext i1 [[CMP1908]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV1910:%.*]] = trunc i32 [[CONV1909]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV1910]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1181:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL1911:%.*]] = icmp ne i16 [[TMP1181]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL1911]], label [[IF_THEN1912:%.*]], label [[IF_ELSE1913:%.*]]
|
|
// SIMD-ONLY0: if.then1912:
|
|
// SIMD-ONLY0-NEXT: [[TMP1182:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1182]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1914:%.*]]
|
|
// SIMD-ONLY0: if.else1913:
|
|
// SIMD-ONLY0-NEXT: [[TMP1183:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1183]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1914]]
|
|
// SIMD-ONLY0: if.end1914:
|
|
// SIMD-ONLY0-NEXT: [[TMP1184:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1184]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1185:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1915:%.*]] = sext i16 [[TMP1185]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1186:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1916:%.*]] = sext i16 [[TMP1186]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1917:%.*]] = icmp sgt i32 [[CONV1915]], [[CONV1916]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1917]], label [[IF_THEN1919:%.*]], label [[IF_END1920:%.*]]
|
|
// SIMD-ONLY0: if.then1919:
|
|
// SIMD-ONLY0-NEXT: [[TMP1187:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1187]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1920]]
|
|
// SIMD-ONLY0: if.end1920:
|
|
// SIMD-ONLY0-NEXT: [[TMP1188:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1188]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1189:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1921:%.*]] = sext i16 [[TMP1189]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1190:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1922:%.*]] = sext i16 [[TMP1190]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1923:%.*]] = icmp sgt i32 [[CONV1921]], [[CONV1922]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1923]], label [[IF_THEN1925:%.*]], label [[IF_END1926:%.*]]
|
|
// SIMD-ONLY0: if.then1925:
|
|
// SIMD-ONLY0-NEXT: [[TMP1191:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1191]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1926]]
|
|
// SIMD-ONLY0: if.end1926:
|
|
// SIMD-ONLY0-NEXT: [[TMP1192:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1192]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1193:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1927:%.*]] = sext i16 [[TMP1193]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1194:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1928:%.*]] = sext i16 [[TMP1194]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1929:%.*]] = icmp slt i32 [[CONV1927]], [[CONV1928]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1929]], label [[IF_THEN1931:%.*]], label [[IF_END1932:%.*]]
|
|
// SIMD-ONLY0: if.then1931:
|
|
// SIMD-ONLY0-NEXT: [[TMP1195:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1195]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1932]]
|
|
// SIMD-ONLY0: if.end1932:
|
|
// SIMD-ONLY0-NEXT: [[TMP1196:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1196]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1197:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1933:%.*]] = sext i16 [[TMP1197]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1198:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1934:%.*]] = sext i16 [[TMP1198]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1935:%.*]] = icmp slt i32 [[CONV1933]], [[CONV1934]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1935]], label [[IF_THEN1937:%.*]], label [[IF_END1938:%.*]]
|
|
// SIMD-ONLY0: if.then1937:
|
|
// SIMD-ONLY0-NEXT: [[TMP1199:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1199]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1938]]
|
|
// SIMD-ONLY0: if.end1938:
|
|
// SIMD-ONLY0-NEXT: [[TMP1200:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1200]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1201:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1939:%.*]] = sext i16 [[TMP1201]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1202:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1940:%.*]] = sext i16 [[TMP1202]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1941:%.*]] = icmp eq i32 [[CONV1939]], [[CONV1940]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1941]], label [[IF_THEN1943:%.*]], label [[IF_END1944:%.*]]
|
|
// SIMD-ONLY0: if.then1943:
|
|
// SIMD-ONLY0-NEXT: [[TMP1203:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1203]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1944]]
|
|
// SIMD-ONLY0: if.end1944:
|
|
// SIMD-ONLY0-NEXT: [[TMP1204:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1204]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1205:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1945:%.*]] = sext i16 [[TMP1205]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1206:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1946:%.*]] = sext i16 [[TMP1206]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1947:%.*]] = icmp eq i32 [[CONV1945]], [[CONV1946]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1947]], label [[IF_THEN1949:%.*]], label [[IF_END1950:%.*]]
|
|
// SIMD-ONLY0: if.then1949:
|
|
// SIMD-ONLY0-NEXT: [[TMP1207:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1207]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1950]]
|
|
// SIMD-ONLY0: if.end1950:
|
|
// SIMD-ONLY0-NEXT: [[TMP1208:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1951:%.*]] = sext i16 [[TMP1208]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1209:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1952:%.*]] = sext i16 [[TMP1209]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1953:%.*]] = icmp sgt i32 [[CONV1951]], [[CONV1952]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1953]], label [[IF_THEN1955:%.*]], label [[IF_END1956:%.*]]
|
|
// SIMD-ONLY0: if.then1955:
|
|
// SIMD-ONLY0-NEXT: [[TMP1210:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1210]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1956]]
|
|
// SIMD-ONLY0: if.end1956:
|
|
// SIMD-ONLY0-NEXT: [[TMP1211:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1211]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1212:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1957:%.*]] = sext i16 [[TMP1212]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1213:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1958:%.*]] = sext i16 [[TMP1213]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1959:%.*]] = icmp sgt i32 [[CONV1957]], [[CONV1958]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1959]], label [[IF_THEN1961:%.*]], label [[IF_END1962:%.*]]
|
|
// SIMD-ONLY0: if.then1961:
|
|
// SIMD-ONLY0-NEXT: [[TMP1214:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1214]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1962]]
|
|
// SIMD-ONLY0: if.end1962:
|
|
// SIMD-ONLY0-NEXT: [[TMP1215:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1215]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1216:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1963:%.*]] = sext i16 [[TMP1216]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1217:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1964:%.*]] = sext i16 [[TMP1217]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1965:%.*]] = icmp slt i32 [[CONV1963]], [[CONV1964]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1965]], label [[IF_THEN1967:%.*]], label [[IF_END1968:%.*]]
|
|
// SIMD-ONLY0: if.then1967:
|
|
// SIMD-ONLY0-NEXT: [[TMP1218:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1218]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1968]]
|
|
// SIMD-ONLY0: if.end1968:
|
|
// SIMD-ONLY0-NEXT: [[TMP1219:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1219]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1220:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1969:%.*]] = sext i16 [[TMP1220]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1221:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1970:%.*]] = sext i16 [[TMP1221]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1971:%.*]] = icmp slt i32 [[CONV1969]], [[CONV1970]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1971]], label [[IF_THEN1973:%.*]], label [[IF_END1974:%.*]]
|
|
// SIMD-ONLY0: if.then1973:
|
|
// SIMD-ONLY0-NEXT: [[TMP1222:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1222]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1974]]
|
|
// SIMD-ONLY0: if.end1974:
|
|
// SIMD-ONLY0-NEXT: [[TMP1223:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1223]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1224:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1975:%.*]] = sext i16 [[TMP1224]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1225:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1976:%.*]] = sext i16 [[TMP1225]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1977:%.*]] = icmp eq i32 [[CONV1975]], [[CONV1976]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1977]], label [[IF_THEN1979:%.*]], label [[IF_END1980:%.*]]
|
|
// SIMD-ONLY0: if.then1979:
|
|
// SIMD-ONLY0-NEXT: [[TMP1226:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1226]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1980]]
|
|
// SIMD-ONLY0: if.end1980:
|
|
// SIMD-ONLY0-NEXT: [[TMP1227:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1227]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1228:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1981:%.*]] = sext i16 [[TMP1228]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1229:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1982:%.*]] = sext i16 [[TMP1229]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1983:%.*]] = icmp eq i32 [[CONV1981]], [[CONV1982]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1983]], label [[IF_THEN1985:%.*]], label [[IF_END1986:%.*]]
|
|
// SIMD-ONLY0: if.then1985:
|
|
// SIMD-ONLY0-NEXT: [[TMP1230:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1230]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1986]]
|
|
// SIMD-ONLY0: if.end1986:
|
|
// SIMD-ONLY0-NEXT: [[TMP1231:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1231]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1232:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1987:%.*]] = sext i16 [[TMP1232]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1233:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1988:%.*]] = sext i16 [[TMP1233]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1989:%.*]] = icmp eq i32 [[CONV1987]], [[CONV1988]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1989]], label [[IF_THEN1991:%.*]], label [[IF_ELSE1992:%.*]]
|
|
// SIMD-ONLY0: if.then1991:
|
|
// SIMD-ONLY0-NEXT: [[TMP1234:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1234]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1993:%.*]]
|
|
// SIMD-ONLY0: if.else1992:
|
|
// SIMD-ONLY0-NEXT: [[TMP1235:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1235]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END1993]]
|
|
// SIMD-ONLY0: if.end1993:
|
|
// SIMD-ONLY0-NEXT: [[TMP1236:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1994:%.*]] = sext i16 [[TMP1236]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1237:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1995:%.*]] = sext i16 [[TMP1237]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP1996:%.*]] = icmp eq i32 [[CONV1994]], [[CONV1995]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1996]], label [[IF_THEN1998:%.*]], label [[IF_ELSE1999:%.*]]
|
|
// SIMD-ONLY0: if.then1998:
|
|
// SIMD-ONLY0-NEXT: [[TMP1238:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1238]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2000:%.*]]
|
|
// SIMD-ONLY0: if.else1999:
|
|
// SIMD-ONLY0-NEXT: [[TMP1239:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1239]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2000]]
|
|
// SIMD-ONLY0: if.end2000:
|
|
// SIMD-ONLY0-NEXT: [[TMP1240:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2001:%.*]] = sext i16 [[TMP1240]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1241:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2002:%.*]] = sext i16 [[TMP1241]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2003:%.*]] = icmp eq i32 [[CONV2001]], [[CONV2002]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2004:%.*]] = zext i1 [[CMP2003]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2005:%.*]] = trunc i32 [[CONV2004]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2005]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1242:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2006:%.*]] = icmp ne i16 [[TMP1242]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2006]], label [[IF_THEN2007:%.*]], label [[IF_END2008:%.*]]
|
|
// SIMD-ONLY0: if.then2007:
|
|
// SIMD-ONLY0-NEXT: [[TMP1243:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1243]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2008]]
|
|
// SIMD-ONLY0: if.end2008:
|
|
// SIMD-ONLY0-NEXT: [[TMP1244:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2009:%.*]] = sext i16 [[TMP1244]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1245:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2010:%.*]] = sext i16 [[TMP1245]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2011:%.*]] = icmp eq i32 [[CONV2009]], [[CONV2010]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2012:%.*]] = zext i1 [[CMP2011]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2013:%.*]] = trunc i32 [[CONV2012]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2013]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1246:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2014:%.*]] = icmp ne i16 [[TMP1246]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2014]], label [[IF_THEN2015:%.*]], label [[IF_END2016:%.*]]
|
|
// SIMD-ONLY0: if.then2015:
|
|
// SIMD-ONLY0-NEXT: [[TMP1247:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1247]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2016]]
|
|
// SIMD-ONLY0: if.end2016:
|
|
// SIMD-ONLY0-NEXT: [[TMP1248:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2017:%.*]] = sext i16 [[TMP1248]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1249:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2018:%.*]] = sext i16 [[TMP1249]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2019:%.*]] = icmp eq i32 [[CONV2017]], [[CONV2018]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2020:%.*]] = zext i1 [[CMP2019]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2021:%.*]] = trunc i32 [[CONV2020]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2021]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1250:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2022:%.*]] = icmp ne i16 [[TMP1250]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2022]], label [[IF_THEN2023:%.*]], label [[IF_ELSE2024:%.*]]
|
|
// SIMD-ONLY0: if.then2023:
|
|
// SIMD-ONLY0-NEXT: [[TMP1251:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1251]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2025:%.*]]
|
|
// SIMD-ONLY0: if.else2024:
|
|
// SIMD-ONLY0-NEXT: [[TMP1252:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1252]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2025]]
|
|
// SIMD-ONLY0: if.end2025:
|
|
// SIMD-ONLY0-NEXT: [[TMP1253:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2026:%.*]] = sext i16 [[TMP1253]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1254:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2027:%.*]] = sext i16 [[TMP1254]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2028:%.*]] = icmp eq i32 [[CONV2026]], [[CONV2027]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2029:%.*]] = zext i1 [[CMP2028]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2030:%.*]] = trunc i32 [[CONV2029]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2030]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1255:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2031:%.*]] = icmp ne i16 [[TMP1255]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2031]], label [[IF_THEN2032:%.*]], label [[IF_ELSE2033:%.*]]
|
|
// SIMD-ONLY0: if.then2032:
|
|
// SIMD-ONLY0-NEXT: [[TMP1256:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1256]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2034:%.*]]
|
|
// SIMD-ONLY0: if.else2033:
|
|
// SIMD-ONLY0-NEXT: [[TMP1257:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1257]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2034]]
|
|
// SIMD-ONLY0: if.end2034:
|
|
// SIMD-ONLY0-NEXT: [[TMP1258:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1258]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1259:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2035:%.*]] = sext i16 [[TMP1259]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1260:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2036:%.*]] = sext i16 [[TMP1260]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2037:%.*]] = icmp sgt i32 [[CONV2035]], [[CONV2036]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2037]], label [[IF_THEN2039:%.*]], label [[IF_END2040:%.*]]
|
|
// SIMD-ONLY0: if.then2039:
|
|
// SIMD-ONLY0-NEXT: [[TMP1261:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1261]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2040]]
|
|
// SIMD-ONLY0: if.end2040:
|
|
// SIMD-ONLY0-NEXT: [[TMP1262:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1262]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1263:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2041:%.*]] = sext i16 [[TMP1263]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1264:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2042:%.*]] = sext i16 [[TMP1264]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2043:%.*]] = icmp sgt i32 [[CONV2041]], [[CONV2042]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2043]], label [[IF_THEN2045:%.*]], label [[IF_END2046:%.*]]
|
|
// SIMD-ONLY0: if.then2045:
|
|
// SIMD-ONLY0-NEXT: [[TMP1265:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1265]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2046]]
|
|
// SIMD-ONLY0: if.end2046:
|
|
// SIMD-ONLY0-NEXT: [[TMP1266:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1266]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1267:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2047:%.*]] = sext i16 [[TMP1267]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1268:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2048:%.*]] = sext i16 [[TMP1268]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2049:%.*]] = icmp slt i32 [[CONV2047]], [[CONV2048]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2049]], label [[IF_THEN2051:%.*]], label [[IF_END2052:%.*]]
|
|
// SIMD-ONLY0: if.then2051:
|
|
// SIMD-ONLY0-NEXT: [[TMP1269:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1269]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2052]]
|
|
// SIMD-ONLY0: if.end2052:
|
|
// SIMD-ONLY0-NEXT: [[TMP1270:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1270]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1271:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2053:%.*]] = sext i16 [[TMP1271]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1272:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2054:%.*]] = sext i16 [[TMP1272]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2055:%.*]] = icmp slt i32 [[CONV2053]], [[CONV2054]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2055]], label [[IF_THEN2057:%.*]], label [[IF_END2058:%.*]]
|
|
// SIMD-ONLY0: if.then2057:
|
|
// SIMD-ONLY0-NEXT: [[TMP1273:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1273]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2058]]
|
|
// SIMD-ONLY0: if.end2058:
|
|
// SIMD-ONLY0-NEXT: [[TMP1274:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1274]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1275:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2059:%.*]] = sext i16 [[TMP1275]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1276:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2060:%.*]] = sext i16 [[TMP1276]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2061:%.*]] = icmp eq i32 [[CONV2059]], [[CONV2060]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2061]], label [[IF_THEN2063:%.*]], label [[IF_END2064:%.*]]
|
|
// SIMD-ONLY0: if.then2063:
|
|
// SIMD-ONLY0-NEXT: [[TMP1277:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1277]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2064]]
|
|
// SIMD-ONLY0: if.end2064:
|
|
// SIMD-ONLY0-NEXT: [[TMP1278:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1278]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1279:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2065:%.*]] = sext i16 [[TMP1279]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1280:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2066:%.*]] = sext i16 [[TMP1280]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2067:%.*]] = icmp eq i32 [[CONV2065]], [[CONV2066]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2067]], label [[IF_THEN2069:%.*]], label [[IF_END2070:%.*]]
|
|
// SIMD-ONLY0: if.then2069:
|
|
// SIMD-ONLY0-NEXT: [[TMP1281:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1281]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2070]]
|
|
// SIMD-ONLY0: if.end2070:
|
|
// SIMD-ONLY0-NEXT: [[TMP1282:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2071:%.*]] = sext i16 [[TMP1282]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1283:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2072:%.*]] = sext i16 [[TMP1283]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2073:%.*]] = icmp sgt i32 [[CONV2071]], [[CONV2072]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2073]], label [[IF_THEN2075:%.*]], label [[IF_END2076:%.*]]
|
|
// SIMD-ONLY0: if.then2075:
|
|
// SIMD-ONLY0-NEXT: [[TMP1284:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1284]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2076]]
|
|
// SIMD-ONLY0: if.end2076:
|
|
// SIMD-ONLY0-NEXT: [[TMP1285:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1285]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1286:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2077:%.*]] = sext i16 [[TMP1286]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1287:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2078:%.*]] = sext i16 [[TMP1287]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2079:%.*]] = icmp sgt i32 [[CONV2077]], [[CONV2078]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2079]], label [[IF_THEN2081:%.*]], label [[IF_END2082:%.*]]
|
|
// SIMD-ONLY0: if.then2081:
|
|
// SIMD-ONLY0-NEXT: [[TMP1288:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1288]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2082]]
|
|
// SIMD-ONLY0: if.end2082:
|
|
// SIMD-ONLY0-NEXT: [[TMP1289:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1289]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1290:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2083:%.*]] = sext i16 [[TMP1290]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1291:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2084:%.*]] = sext i16 [[TMP1291]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2085:%.*]] = icmp slt i32 [[CONV2083]], [[CONV2084]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2085]], label [[IF_THEN2087:%.*]], label [[IF_END2088:%.*]]
|
|
// SIMD-ONLY0: if.then2087:
|
|
// SIMD-ONLY0-NEXT: [[TMP1292:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1292]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2088]]
|
|
// SIMD-ONLY0: if.end2088:
|
|
// SIMD-ONLY0-NEXT: [[TMP1293:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1293]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1294:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2089:%.*]] = sext i16 [[TMP1294]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1295:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2090:%.*]] = sext i16 [[TMP1295]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2091:%.*]] = icmp slt i32 [[CONV2089]], [[CONV2090]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2091]], label [[IF_THEN2093:%.*]], label [[IF_END2094:%.*]]
|
|
// SIMD-ONLY0: if.then2093:
|
|
// SIMD-ONLY0-NEXT: [[TMP1296:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1296]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2094]]
|
|
// SIMD-ONLY0: if.end2094:
|
|
// SIMD-ONLY0-NEXT: [[TMP1297:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1297]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1298:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2095:%.*]] = sext i16 [[TMP1298]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1299:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2096:%.*]] = sext i16 [[TMP1299]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2097:%.*]] = icmp eq i32 [[CONV2095]], [[CONV2096]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2097]], label [[IF_THEN2099:%.*]], label [[IF_END2100:%.*]]
|
|
// SIMD-ONLY0: if.then2099:
|
|
// SIMD-ONLY0-NEXT: [[TMP1300:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1300]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2100]]
|
|
// SIMD-ONLY0: if.end2100:
|
|
// SIMD-ONLY0-NEXT: [[TMP1301:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1301]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1302:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2101:%.*]] = sext i16 [[TMP1302]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1303:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2102:%.*]] = sext i16 [[TMP1303]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2103:%.*]] = icmp eq i32 [[CONV2101]], [[CONV2102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2103]], label [[IF_THEN2105:%.*]], label [[IF_END2106:%.*]]
|
|
// SIMD-ONLY0: if.then2105:
|
|
// SIMD-ONLY0-NEXT: [[TMP1304:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1304]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2106]]
|
|
// SIMD-ONLY0: if.end2106:
|
|
// SIMD-ONLY0-NEXT: [[TMP1305:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1305]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1306:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2107:%.*]] = sext i16 [[TMP1306]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1307:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2108:%.*]] = sext i16 [[TMP1307]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2109:%.*]] = icmp eq i32 [[CONV2107]], [[CONV2108]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2109]], label [[IF_THEN2111:%.*]], label [[IF_ELSE2112:%.*]]
|
|
// SIMD-ONLY0: if.then2111:
|
|
// SIMD-ONLY0-NEXT: [[TMP1308:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1308]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2113:%.*]]
|
|
// SIMD-ONLY0: if.else2112:
|
|
// SIMD-ONLY0-NEXT: [[TMP1309:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1309]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2113]]
|
|
// SIMD-ONLY0: if.end2113:
|
|
// SIMD-ONLY0-NEXT: [[TMP1310:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2114:%.*]] = sext i16 [[TMP1310]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1311:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2115:%.*]] = sext i16 [[TMP1311]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2116:%.*]] = icmp eq i32 [[CONV2114]], [[CONV2115]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2116]], label [[IF_THEN2118:%.*]], label [[IF_ELSE2119:%.*]]
|
|
// SIMD-ONLY0: if.then2118:
|
|
// SIMD-ONLY0-NEXT: [[TMP1312:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1312]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2120:%.*]]
|
|
// SIMD-ONLY0: if.else2119:
|
|
// SIMD-ONLY0-NEXT: [[TMP1313:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1313]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2120]]
|
|
// SIMD-ONLY0: if.end2120:
|
|
// SIMD-ONLY0-NEXT: [[TMP1314:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2121:%.*]] = sext i16 [[TMP1314]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1315:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2122:%.*]] = sext i16 [[TMP1315]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2123:%.*]] = icmp eq i32 [[CONV2121]], [[CONV2122]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2124:%.*]] = zext i1 [[CMP2123]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2125:%.*]] = trunc i32 [[CONV2124]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2125]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1316:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2126:%.*]] = icmp ne i16 [[TMP1316]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2126]], label [[IF_THEN2127:%.*]], label [[IF_END2128:%.*]]
|
|
// SIMD-ONLY0: if.then2127:
|
|
// SIMD-ONLY0-NEXT: [[TMP1317:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1317]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2128]]
|
|
// SIMD-ONLY0: if.end2128:
|
|
// SIMD-ONLY0-NEXT: [[TMP1318:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2129:%.*]] = sext i16 [[TMP1318]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1319:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2130:%.*]] = sext i16 [[TMP1319]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2131:%.*]] = icmp eq i32 [[CONV2129]], [[CONV2130]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2132:%.*]] = zext i1 [[CMP2131]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2133:%.*]] = trunc i32 [[CONV2132]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2133]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1320:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2134:%.*]] = icmp ne i16 [[TMP1320]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2134]], label [[IF_THEN2135:%.*]], label [[IF_END2136:%.*]]
|
|
// SIMD-ONLY0: if.then2135:
|
|
// SIMD-ONLY0-NEXT: [[TMP1321:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1321]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2136]]
|
|
// SIMD-ONLY0: if.end2136:
|
|
// SIMD-ONLY0-NEXT: [[TMP1322:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2137:%.*]] = sext i16 [[TMP1322]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1323:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2138:%.*]] = sext i16 [[TMP1323]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2139:%.*]] = icmp eq i32 [[CONV2137]], [[CONV2138]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2140:%.*]] = zext i1 [[CMP2139]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2141:%.*]] = trunc i32 [[CONV2140]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2141]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1324:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2142:%.*]] = icmp ne i16 [[TMP1324]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2142]], label [[IF_THEN2143:%.*]], label [[IF_ELSE2144:%.*]]
|
|
// SIMD-ONLY0: if.then2143:
|
|
// SIMD-ONLY0-NEXT: [[TMP1325:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1325]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2145:%.*]]
|
|
// SIMD-ONLY0: if.else2144:
|
|
// SIMD-ONLY0-NEXT: [[TMP1326:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1326]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2145]]
|
|
// SIMD-ONLY0: if.end2145:
|
|
// SIMD-ONLY0-NEXT: [[TMP1327:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2146:%.*]] = sext i16 [[TMP1327]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1328:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2147:%.*]] = sext i16 [[TMP1328]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2148:%.*]] = icmp eq i32 [[CONV2146]], [[CONV2147]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2149:%.*]] = zext i1 [[CMP2148]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2150:%.*]] = trunc i32 [[CONV2149]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2150]], ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1329:%.*]] = load i16, ptr [[SR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2151:%.*]] = icmp ne i16 [[TMP1329]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2151]], label [[IF_THEN2152:%.*]], label [[IF_ELSE2153:%.*]]
|
|
// SIMD-ONLY0: if.then2152:
|
|
// SIMD-ONLY0-NEXT: [[TMP1330:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1330]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2154:%.*]]
|
|
// SIMD-ONLY0: if.else2153:
|
|
// SIMD-ONLY0-NEXT: [[TMP1331:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1331]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2154]]
|
|
// SIMD-ONLY0: if.end2154:
|
|
// SIMD-ONLY0-NEXT: [[TMP1332:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1332]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1333:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2155:%.*]] = zext i16 [[TMP1333]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1334:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2156:%.*]] = zext i16 [[TMP1334]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2157:%.*]] = icmp sgt i32 [[CONV2155]], [[CONV2156]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2157]], label [[IF_THEN2159:%.*]], label [[IF_END2160:%.*]]
|
|
// SIMD-ONLY0: if.then2159:
|
|
// SIMD-ONLY0-NEXT: [[TMP1335:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1335]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2160]]
|
|
// SIMD-ONLY0: if.end2160:
|
|
// SIMD-ONLY0-NEXT: [[TMP1336:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1336]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1337:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2161:%.*]] = zext i16 [[TMP1337]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1338:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2162:%.*]] = zext i16 [[TMP1338]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2163:%.*]] = icmp sgt i32 [[CONV2161]], [[CONV2162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2163]], label [[IF_THEN2165:%.*]], label [[IF_END2166:%.*]]
|
|
// SIMD-ONLY0: if.then2165:
|
|
// SIMD-ONLY0-NEXT: [[TMP1339:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1339]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2166]]
|
|
// SIMD-ONLY0: if.end2166:
|
|
// SIMD-ONLY0-NEXT: [[TMP1340:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1340]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1341:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2167:%.*]] = zext i16 [[TMP1341]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1342:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2168:%.*]] = zext i16 [[TMP1342]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2169:%.*]] = icmp slt i32 [[CONV2167]], [[CONV2168]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2169]], label [[IF_THEN2171:%.*]], label [[IF_END2172:%.*]]
|
|
// SIMD-ONLY0: if.then2171:
|
|
// SIMD-ONLY0-NEXT: [[TMP1343:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1343]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2172]]
|
|
// SIMD-ONLY0: if.end2172:
|
|
// SIMD-ONLY0-NEXT: [[TMP1344:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1344]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1345:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2173:%.*]] = zext i16 [[TMP1345]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1346:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2174:%.*]] = zext i16 [[TMP1346]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2175:%.*]] = icmp slt i32 [[CONV2173]], [[CONV2174]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2175]], label [[IF_THEN2177:%.*]], label [[IF_END2178:%.*]]
|
|
// SIMD-ONLY0: if.then2177:
|
|
// SIMD-ONLY0-NEXT: [[TMP1347:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1347]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2178]]
|
|
// SIMD-ONLY0: if.end2178:
|
|
// SIMD-ONLY0-NEXT: [[TMP1348:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1348]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1349:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2179:%.*]] = zext i16 [[TMP1349]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1350:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2180:%.*]] = zext i16 [[TMP1350]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2181:%.*]] = icmp eq i32 [[CONV2179]], [[CONV2180]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2181]], label [[IF_THEN2183:%.*]], label [[IF_END2184:%.*]]
|
|
// SIMD-ONLY0: if.then2183:
|
|
// SIMD-ONLY0-NEXT: [[TMP1351:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1351]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2184]]
|
|
// SIMD-ONLY0: if.end2184:
|
|
// SIMD-ONLY0-NEXT: [[TMP1352:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1352]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1353:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2185:%.*]] = zext i16 [[TMP1353]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1354:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2186:%.*]] = zext i16 [[TMP1354]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2187:%.*]] = icmp eq i32 [[CONV2185]], [[CONV2186]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2187]], label [[IF_THEN2189:%.*]], label [[IF_END2190:%.*]]
|
|
// SIMD-ONLY0: if.then2189:
|
|
// SIMD-ONLY0-NEXT: [[TMP1355:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1355]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2190]]
|
|
// SIMD-ONLY0: if.end2190:
|
|
// SIMD-ONLY0-NEXT: [[TMP1356:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2191:%.*]] = zext i16 [[TMP1356]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1357:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2192:%.*]] = zext i16 [[TMP1357]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2193:%.*]] = icmp sgt i32 [[CONV2191]], [[CONV2192]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2193]], label [[IF_THEN2195:%.*]], label [[IF_END2196:%.*]]
|
|
// SIMD-ONLY0: if.then2195:
|
|
// SIMD-ONLY0-NEXT: [[TMP1358:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1358]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2196]]
|
|
// SIMD-ONLY0: if.end2196:
|
|
// SIMD-ONLY0-NEXT: [[TMP1359:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1359]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1360:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2197:%.*]] = zext i16 [[TMP1360]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1361:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2198:%.*]] = zext i16 [[TMP1361]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2199:%.*]] = icmp sgt i32 [[CONV2197]], [[CONV2198]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2199]], label [[IF_THEN2201:%.*]], label [[IF_END2202:%.*]]
|
|
// SIMD-ONLY0: if.then2201:
|
|
// SIMD-ONLY0-NEXT: [[TMP1362:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1362]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2202]]
|
|
// SIMD-ONLY0: if.end2202:
|
|
// SIMD-ONLY0-NEXT: [[TMP1363:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1363]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1364:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2203:%.*]] = zext i16 [[TMP1364]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1365:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2204:%.*]] = zext i16 [[TMP1365]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2205:%.*]] = icmp slt i32 [[CONV2203]], [[CONV2204]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2205]], label [[IF_THEN2207:%.*]], label [[IF_END2208:%.*]]
|
|
// SIMD-ONLY0: if.then2207:
|
|
// SIMD-ONLY0-NEXT: [[TMP1366:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1366]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2208]]
|
|
// SIMD-ONLY0: if.end2208:
|
|
// SIMD-ONLY0-NEXT: [[TMP1367:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1367]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1368:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2209:%.*]] = zext i16 [[TMP1368]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1369:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2210:%.*]] = zext i16 [[TMP1369]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2211:%.*]] = icmp slt i32 [[CONV2209]], [[CONV2210]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2211]], label [[IF_THEN2213:%.*]], label [[IF_END2214:%.*]]
|
|
// SIMD-ONLY0: if.then2213:
|
|
// SIMD-ONLY0-NEXT: [[TMP1370:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1370]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2214]]
|
|
// SIMD-ONLY0: if.end2214:
|
|
// SIMD-ONLY0-NEXT: [[TMP1371:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1371]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1372:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2215:%.*]] = zext i16 [[TMP1372]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1373:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2216:%.*]] = zext i16 [[TMP1373]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2217:%.*]] = icmp eq i32 [[CONV2215]], [[CONV2216]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2217]], label [[IF_THEN2219:%.*]], label [[IF_END2220:%.*]]
|
|
// SIMD-ONLY0: if.then2219:
|
|
// SIMD-ONLY0-NEXT: [[TMP1374:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1374]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2220]]
|
|
// SIMD-ONLY0: if.end2220:
|
|
// SIMD-ONLY0-NEXT: [[TMP1375:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1375]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1376:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2221:%.*]] = zext i16 [[TMP1376]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1377:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2222:%.*]] = zext i16 [[TMP1377]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2223:%.*]] = icmp eq i32 [[CONV2221]], [[CONV2222]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2223]], label [[IF_THEN2225:%.*]], label [[IF_END2226:%.*]]
|
|
// SIMD-ONLY0: if.then2225:
|
|
// SIMD-ONLY0-NEXT: [[TMP1378:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1378]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2226]]
|
|
// SIMD-ONLY0: if.end2226:
|
|
// SIMD-ONLY0-NEXT: [[TMP1379:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1379]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1380:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2227:%.*]] = zext i16 [[TMP1380]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1381:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2228:%.*]] = zext i16 [[TMP1381]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2229:%.*]] = icmp eq i32 [[CONV2227]], [[CONV2228]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2229]], label [[IF_THEN2231:%.*]], label [[IF_ELSE2232:%.*]]
|
|
// SIMD-ONLY0: if.then2231:
|
|
// SIMD-ONLY0-NEXT: [[TMP1382:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1382]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2233:%.*]]
|
|
// SIMD-ONLY0: if.else2232:
|
|
// SIMD-ONLY0-NEXT: [[TMP1383:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1383]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2233]]
|
|
// SIMD-ONLY0: if.end2233:
|
|
// SIMD-ONLY0-NEXT: [[TMP1384:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2234:%.*]] = zext i16 [[TMP1384]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1385:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2235:%.*]] = zext i16 [[TMP1385]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2236:%.*]] = icmp eq i32 [[CONV2234]], [[CONV2235]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2236]], label [[IF_THEN2238:%.*]], label [[IF_ELSE2239:%.*]]
|
|
// SIMD-ONLY0: if.then2238:
|
|
// SIMD-ONLY0-NEXT: [[TMP1386:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1386]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2240:%.*]]
|
|
// SIMD-ONLY0: if.else2239:
|
|
// SIMD-ONLY0-NEXT: [[TMP1387:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1387]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2240]]
|
|
// SIMD-ONLY0: if.end2240:
|
|
// SIMD-ONLY0-NEXT: [[TMP1388:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2241:%.*]] = zext i16 [[TMP1388]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1389:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2242:%.*]] = zext i16 [[TMP1389]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2243:%.*]] = icmp eq i32 [[CONV2241]], [[CONV2242]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2244:%.*]] = zext i1 [[CMP2243]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2245:%.*]] = trunc i32 [[CONV2244]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2245]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1390:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2246:%.*]] = icmp ne i16 [[TMP1390]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2246]], label [[IF_THEN2247:%.*]], label [[IF_END2248:%.*]]
|
|
// SIMD-ONLY0: if.then2247:
|
|
// SIMD-ONLY0-NEXT: [[TMP1391:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1391]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2248]]
|
|
// SIMD-ONLY0: if.end2248:
|
|
// SIMD-ONLY0-NEXT: [[TMP1392:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2249:%.*]] = zext i16 [[TMP1392]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1393:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2250:%.*]] = zext i16 [[TMP1393]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2251:%.*]] = icmp eq i32 [[CONV2249]], [[CONV2250]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2252:%.*]] = zext i1 [[CMP2251]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2253:%.*]] = trunc i32 [[CONV2252]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2253]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1394:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2254:%.*]] = icmp ne i16 [[TMP1394]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2254]], label [[IF_THEN2255:%.*]], label [[IF_END2256:%.*]]
|
|
// SIMD-ONLY0: if.then2255:
|
|
// SIMD-ONLY0-NEXT: [[TMP1395:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1395]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2256]]
|
|
// SIMD-ONLY0: if.end2256:
|
|
// SIMD-ONLY0-NEXT: [[TMP1396:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2257:%.*]] = zext i16 [[TMP1396]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1397:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2258:%.*]] = zext i16 [[TMP1397]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2259:%.*]] = icmp eq i32 [[CONV2257]], [[CONV2258]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2260:%.*]] = zext i1 [[CMP2259]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2261:%.*]] = trunc i32 [[CONV2260]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2261]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1398:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2262:%.*]] = icmp ne i16 [[TMP1398]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2262]], label [[IF_THEN2263:%.*]], label [[IF_ELSE2264:%.*]]
|
|
// SIMD-ONLY0: if.then2263:
|
|
// SIMD-ONLY0-NEXT: [[TMP1399:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1399]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2265:%.*]]
|
|
// SIMD-ONLY0: if.else2264:
|
|
// SIMD-ONLY0-NEXT: [[TMP1400:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1400]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2265]]
|
|
// SIMD-ONLY0: if.end2265:
|
|
// SIMD-ONLY0-NEXT: [[TMP1401:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2266:%.*]] = zext i16 [[TMP1401]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1402:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2267:%.*]] = zext i16 [[TMP1402]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2268:%.*]] = icmp eq i32 [[CONV2266]], [[CONV2267]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2269:%.*]] = zext i1 [[CMP2268]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2270:%.*]] = trunc i32 [[CONV2269]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2270]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1403:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2271:%.*]] = icmp ne i16 [[TMP1403]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2271]], label [[IF_THEN2272:%.*]], label [[IF_ELSE2273:%.*]]
|
|
// SIMD-ONLY0: if.then2272:
|
|
// SIMD-ONLY0-NEXT: [[TMP1404:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1404]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2274:%.*]]
|
|
// SIMD-ONLY0: if.else2273:
|
|
// SIMD-ONLY0-NEXT: [[TMP1405:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1405]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2274]]
|
|
// SIMD-ONLY0: if.end2274:
|
|
// SIMD-ONLY0-NEXT: [[TMP1406:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1406]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1407:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2275:%.*]] = zext i16 [[TMP1407]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1408:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2276:%.*]] = zext i16 [[TMP1408]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2277:%.*]] = icmp sgt i32 [[CONV2275]], [[CONV2276]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2277]], label [[IF_THEN2279:%.*]], label [[IF_END2280:%.*]]
|
|
// SIMD-ONLY0: if.then2279:
|
|
// SIMD-ONLY0-NEXT: [[TMP1409:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1409]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2280]]
|
|
// SIMD-ONLY0: if.end2280:
|
|
// SIMD-ONLY0-NEXT: [[TMP1410:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1410]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1411:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2281:%.*]] = zext i16 [[TMP1411]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1412:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2282:%.*]] = zext i16 [[TMP1412]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2283:%.*]] = icmp sgt i32 [[CONV2281]], [[CONV2282]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2283]], label [[IF_THEN2285:%.*]], label [[IF_END2286:%.*]]
|
|
// SIMD-ONLY0: if.then2285:
|
|
// SIMD-ONLY0-NEXT: [[TMP1413:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1413]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2286]]
|
|
// SIMD-ONLY0: if.end2286:
|
|
// SIMD-ONLY0-NEXT: [[TMP1414:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1414]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1415:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2287:%.*]] = zext i16 [[TMP1415]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1416:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2288:%.*]] = zext i16 [[TMP1416]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2289:%.*]] = icmp slt i32 [[CONV2287]], [[CONV2288]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2289]], label [[IF_THEN2291:%.*]], label [[IF_END2292:%.*]]
|
|
// SIMD-ONLY0: if.then2291:
|
|
// SIMD-ONLY0-NEXT: [[TMP1417:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1417]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2292]]
|
|
// SIMD-ONLY0: if.end2292:
|
|
// SIMD-ONLY0-NEXT: [[TMP1418:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1418]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1419:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2293:%.*]] = zext i16 [[TMP1419]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1420:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2294:%.*]] = zext i16 [[TMP1420]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2295:%.*]] = icmp slt i32 [[CONV2293]], [[CONV2294]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2295]], label [[IF_THEN2297:%.*]], label [[IF_END2298:%.*]]
|
|
// SIMD-ONLY0: if.then2297:
|
|
// SIMD-ONLY0-NEXT: [[TMP1421:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1421]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2298]]
|
|
// SIMD-ONLY0: if.end2298:
|
|
// SIMD-ONLY0-NEXT: [[TMP1422:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1422]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1423:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2299:%.*]] = zext i16 [[TMP1423]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1424:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2300:%.*]] = zext i16 [[TMP1424]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2301:%.*]] = icmp eq i32 [[CONV2299]], [[CONV2300]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2301]], label [[IF_THEN2303:%.*]], label [[IF_END2304:%.*]]
|
|
// SIMD-ONLY0: if.then2303:
|
|
// SIMD-ONLY0-NEXT: [[TMP1425:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1425]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2304]]
|
|
// SIMD-ONLY0: if.end2304:
|
|
// SIMD-ONLY0-NEXT: [[TMP1426:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1426]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1427:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2305:%.*]] = zext i16 [[TMP1427]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1428:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2306:%.*]] = zext i16 [[TMP1428]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2307:%.*]] = icmp eq i32 [[CONV2305]], [[CONV2306]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2307]], label [[IF_THEN2309:%.*]], label [[IF_END2310:%.*]]
|
|
// SIMD-ONLY0: if.then2309:
|
|
// SIMD-ONLY0-NEXT: [[TMP1429:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1429]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2310]]
|
|
// SIMD-ONLY0: if.end2310:
|
|
// SIMD-ONLY0-NEXT: [[TMP1430:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2311:%.*]] = zext i16 [[TMP1430]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1431:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2312:%.*]] = zext i16 [[TMP1431]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2313:%.*]] = icmp sgt i32 [[CONV2311]], [[CONV2312]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2313]], label [[IF_THEN2315:%.*]], label [[IF_END2316:%.*]]
|
|
// SIMD-ONLY0: if.then2315:
|
|
// SIMD-ONLY0-NEXT: [[TMP1432:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1432]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2316]]
|
|
// SIMD-ONLY0: if.end2316:
|
|
// SIMD-ONLY0-NEXT: [[TMP1433:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1433]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1434:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2317:%.*]] = zext i16 [[TMP1434]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1435:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2318:%.*]] = zext i16 [[TMP1435]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2319:%.*]] = icmp sgt i32 [[CONV2317]], [[CONV2318]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2319]], label [[IF_THEN2321:%.*]], label [[IF_END2322:%.*]]
|
|
// SIMD-ONLY0: if.then2321:
|
|
// SIMD-ONLY0-NEXT: [[TMP1436:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1436]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2322]]
|
|
// SIMD-ONLY0: if.end2322:
|
|
// SIMD-ONLY0-NEXT: [[TMP1437:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1437]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1438:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2323:%.*]] = zext i16 [[TMP1438]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1439:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2324:%.*]] = zext i16 [[TMP1439]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2325:%.*]] = icmp slt i32 [[CONV2323]], [[CONV2324]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2325]], label [[IF_THEN2327:%.*]], label [[IF_END2328:%.*]]
|
|
// SIMD-ONLY0: if.then2327:
|
|
// SIMD-ONLY0-NEXT: [[TMP1440:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1440]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2328]]
|
|
// SIMD-ONLY0: if.end2328:
|
|
// SIMD-ONLY0-NEXT: [[TMP1441:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1441]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1442:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2329:%.*]] = zext i16 [[TMP1442]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1443:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2330:%.*]] = zext i16 [[TMP1443]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2331:%.*]] = icmp slt i32 [[CONV2329]], [[CONV2330]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2331]], label [[IF_THEN2333:%.*]], label [[IF_END2334:%.*]]
|
|
// SIMD-ONLY0: if.then2333:
|
|
// SIMD-ONLY0-NEXT: [[TMP1444:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1444]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2334]]
|
|
// SIMD-ONLY0: if.end2334:
|
|
// SIMD-ONLY0-NEXT: [[TMP1445:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1445]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1446:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2335:%.*]] = zext i16 [[TMP1446]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1447:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2336:%.*]] = zext i16 [[TMP1447]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2337:%.*]] = icmp eq i32 [[CONV2335]], [[CONV2336]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2337]], label [[IF_THEN2339:%.*]], label [[IF_END2340:%.*]]
|
|
// SIMD-ONLY0: if.then2339:
|
|
// SIMD-ONLY0-NEXT: [[TMP1448:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1448]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2340]]
|
|
// SIMD-ONLY0: if.end2340:
|
|
// SIMD-ONLY0-NEXT: [[TMP1449:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1449]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1450:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2341:%.*]] = zext i16 [[TMP1450]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1451:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2342:%.*]] = zext i16 [[TMP1451]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2343:%.*]] = icmp eq i32 [[CONV2341]], [[CONV2342]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2343]], label [[IF_THEN2345:%.*]], label [[IF_END2346:%.*]]
|
|
// SIMD-ONLY0: if.then2345:
|
|
// SIMD-ONLY0-NEXT: [[TMP1452:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1452]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2346]]
|
|
// SIMD-ONLY0: if.end2346:
|
|
// SIMD-ONLY0-NEXT: [[TMP1453:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1453]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1454:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2347:%.*]] = zext i16 [[TMP1454]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1455:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2348:%.*]] = zext i16 [[TMP1455]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2349:%.*]] = icmp eq i32 [[CONV2347]], [[CONV2348]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2349]], label [[IF_THEN2351:%.*]], label [[IF_ELSE2352:%.*]]
|
|
// SIMD-ONLY0: if.then2351:
|
|
// SIMD-ONLY0-NEXT: [[TMP1456:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1456]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2353:%.*]]
|
|
// SIMD-ONLY0: if.else2352:
|
|
// SIMD-ONLY0-NEXT: [[TMP1457:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1457]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2353]]
|
|
// SIMD-ONLY0: if.end2353:
|
|
// SIMD-ONLY0-NEXT: [[TMP1458:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2354:%.*]] = zext i16 [[TMP1458]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1459:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2355:%.*]] = zext i16 [[TMP1459]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2356:%.*]] = icmp eq i32 [[CONV2354]], [[CONV2355]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2356]], label [[IF_THEN2358:%.*]], label [[IF_ELSE2359:%.*]]
|
|
// SIMD-ONLY0: if.then2358:
|
|
// SIMD-ONLY0-NEXT: [[TMP1460:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1460]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2360:%.*]]
|
|
// SIMD-ONLY0: if.else2359:
|
|
// SIMD-ONLY0-NEXT: [[TMP1461:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1461]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2360]]
|
|
// SIMD-ONLY0: if.end2360:
|
|
// SIMD-ONLY0-NEXT: [[TMP1462:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2361:%.*]] = zext i16 [[TMP1462]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1463:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2362:%.*]] = zext i16 [[TMP1463]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2363:%.*]] = icmp eq i32 [[CONV2361]], [[CONV2362]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2364:%.*]] = zext i1 [[CMP2363]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2365:%.*]] = trunc i32 [[CONV2364]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2365]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1464:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2366:%.*]] = icmp ne i16 [[TMP1464]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2366]], label [[IF_THEN2367:%.*]], label [[IF_END2368:%.*]]
|
|
// SIMD-ONLY0: if.then2367:
|
|
// SIMD-ONLY0-NEXT: [[TMP1465:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1465]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2368]]
|
|
// SIMD-ONLY0: if.end2368:
|
|
// SIMD-ONLY0-NEXT: [[TMP1466:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2369:%.*]] = zext i16 [[TMP1466]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1467:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2370:%.*]] = zext i16 [[TMP1467]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2371:%.*]] = icmp eq i32 [[CONV2369]], [[CONV2370]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2372:%.*]] = zext i1 [[CMP2371]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2373:%.*]] = trunc i32 [[CONV2372]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2373]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1468:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2374:%.*]] = icmp ne i16 [[TMP1468]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2374]], label [[IF_THEN2375:%.*]], label [[IF_END2376:%.*]]
|
|
// SIMD-ONLY0: if.then2375:
|
|
// SIMD-ONLY0-NEXT: [[TMP1469:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1469]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2376]]
|
|
// SIMD-ONLY0: if.end2376:
|
|
// SIMD-ONLY0-NEXT: [[TMP1470:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2377:%.*]] = zext i16 [[TMP1470]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1471:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2378:%.*]] = zext i16 [[TMP1471]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2379:%.*]] = icmp eq i32 [[CONV2377]], [[CONV2378]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2380:%.*]] = zext i1 [[CMP2379]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2381:%.*]] = trunc i32 [[CONV2380]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2381]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1472:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2382:%.*]] = icmp ne i16 [[TMP1472]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2382]], label [[IF_THEN2383:%.*]], label [[IF_ELSE2384:%.*]]
|
|
// SIMD-ONLY0: if.then2383:
|
|
// SIMD-ONLY0-NEXT: [[TMP1473:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1473]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2385:%.*]]
|
|
// SIMD-ONLY0: if.else2384:
|
|
// SIMD-ONLY0-NEXT: [[TMP1474:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1474]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2385]]
|
|
// SIMD-ONLY0: if.end2385:
|
|
// SIMD-ONLY0-NEXT: [[TMP1475:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2386:%.*]] = zext i16 [[TMP1475]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1476:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2387:%.*]] = zext i16 [[TMP1476]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2388:%.*]] = icmp eq i32 [[CONV2386]], [[CONV2387]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2389:%.*]] = zext i1 [[CMP2388]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2390:%.*]] = trunc i32 [[CONV2389]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2390]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1477:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2391:%.*]] = icmp ne i16 [[TMP1477]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2391]], label [[IF_THEN2392:%.*]], label [[IF_ELSE2393:%.*]]
|
|
// SIMD-ONLY0: if.then2392:
|
|
// SIMD-ONLY0-NEXT: [[TMP1478:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1478]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2394:%.*]]
|
|
// SIMD-ONLY0: if.else2393:
|
|
// SIMD-ONLY0-NEXT: [[TMP1479:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1479]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2394]]
|
|
// SIMD-ONLY0: if.end2394:
|
|
// SIMD-ONLY0-NEXT: [[TMP1480:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1480]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1481:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2395:%.*]] = zext i16 [[TMP1481]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1482:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2396:%.*]] = zext i16 [[TMP1482]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2397:%.*]] = icmp sgt i32 [[CONV2395]], [[CONV2396]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2397]], label [[IF_THEN2399:%.*]], label [[IF_END2400:%.*]]
|
|
// SIMD-ONLY0: if.then2399:
|
|
// SIMD-ONLY0-NEXT: [[TMP1483:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1483]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2400]]
|
|
// SIMD-ONLY0: if.end2400:
|
|
// SIMD-ONLY0-NEXT: [[TMP1484:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1484]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1485:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2401:%.*]] = zext i16 [[TMP1485]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1486:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2402:%.*]] = zext i16 [[TMP1486]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2403:%.*]] = icmp sgt i32 [[CONV2401]], [[CONV2402]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2403]], label [[IF_THEN2405:%.*]], label [[IF_END2406:%.*]]
|
|
// SIMD-ONLY0: if.then2405:
|
|
// SIMD-ONLY0-NEXT: [[TMP1487:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1487]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2406]]
|
|
// SIMD-ONLY0: if.end2406:
|
|
// SIMD-ONLY0-NEXT: [[TMP1488:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1488]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1489:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2407:%.*]] = zext i16 [[TMP1489]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1490:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2408:%.*]] = zext i16 [[TMP1490]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2409:%.*]] = icmp slt i32 [[CONV2407]], [[CONV2408]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2409]], label [[IF_THEN2411:%.*]], label [[IF_END2412:%.*]]
|
|
// SIMD-ONLY0: if.then2411:
|
|
// SIMD-ONLY0-NEXT: [[TMP1491:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1491]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2412]]
|
|
// SIMD-ONLY0: if.end2412:
|
|
// SIMD-ONLY0-NEXT: [[TMP1492:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1492]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1493:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2413:%.*]] = zext i16 [[TMP1493]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1494:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2414:%.*]] = zext i16 [[TMP1494]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2415:%.*]] = icmp slt i32 [[CONV2413]], [[CONV2414]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2415]], label [[IF_THEN2417:%.*]], label [[IF_END2418:%.*]]
|
|
// SIMD-ONLY0: if.then2417:
|
|
// SIMD-ONLY0-NEXT: [[TMP1495:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1495]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2418]]
|
|
// SIMD-ONLY0: if.end2418:
|
|
// SIMD-ONLY0-NEXT: [[TMP1496:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1496]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1497:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2419:%.*]] = zext i16 [[TMP1497]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1498:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2420:%.*]] = zext i16 [[TMP1498]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2421:%.*]] = icmp eq i32 [[CONV2419]], [[CONV2420]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2421]], label [[IF_THEN2423:%.*]], label [[IF_END2424:%.*]]
|
|
// SIMD-ONLY0: if.then2423:
|
|
// SIMD-ONLY0-NEXT: [[TMP1499:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1499]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2424]]
|
|
// SIMD-ONLY0: if.end2424:
|
|
// SIMD-ONLY0-NEXT: [[TMP1500:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1500]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1501:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2425:%.*]] = zext i16 [[TMP1501]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1502:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2426:%.*]] = zext i16 [[TMP1502]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2427:%.*]] = icmp eq i32 [[CONV2425]], [[CONV2426]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2427]], label [[IF_THEN2429:%.*]], label [[IF_END2430:%.*]]
|
|
// SIMD-ONLY0: if.then2429:
|
|
// SIMD-ONLY0-NEXT: [[TMP1503:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1503]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2430]]
|
|
// SIMD-ONLY0: if.end2430:
|
|
// SIMD-ONLY0-NEXT: [[TMP1504:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2431:%.*]] = zext i16 [[TMP1504]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1505:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2432:%.*]] = zext i16 [[TMP1505]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2433:%.*]] = icmp sgt i32 [[CONV2431]], [[CONV2432]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2433]], label [[IF_THEN2435:%.*]], label [[IF_END2436:%.*]]
|
|
// SIMD-ONLY0: if.then2435:
|
|
// SIMD-ONLY0-NEXT: [[TMP1506:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1506]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2436]]
|
|
// SIMD-ONLY0: if.end2436:
|
|
// SIMD-ONLY0-NEXT: [[TMP1507:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1507]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1508:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2437:%.*]] = zext i16 [[TMP1508]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1509:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2438:%.*]] = zext i16 [[TMP1509]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2439:%.*]] = icmp sgt i32 [[CONV2437]], [[CONV2438]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2439]], label [[IF_THEN2441:%.*]], label [[IF_END2442:%.*]]
|
|
// SIMD-ONLY0: if.then2441:
|
|
// SIMD-ONLY0-NEXT: [[TMP1510:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1510]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2442]]
|
|
// SIMD-ONLY0: if.end2442:
|
|
// SIMD-ONLY0-NEXT: [[TMP1511:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1511]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1512:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2443:%.*]] = zext i16 [[TMP1512]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1513:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2444:%.*]] = zext i16 [[TMP1513]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2445:%.*]] = icmp slt i32 [[CONV2443]], [[CONV2444]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2445]], label [[IF_THEN2447:%.*]], label [[IF_END2448:%.*]]
|
|
// SIMD-ONLY0: if.then2447:
|
|
// SIMD-ONLY0-NEXT: [[TMP1514:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1514]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2448]]
|
|
// SIMD-ONLY0: if.end2448:
|
|
// SIMD-ONLY0-NEXT: [[TMP1515:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1515]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1516:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2449:%.*]] = zext i16 [[TMP1516]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1517:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2450:%.*]] = zext i16 [[TMP1517]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2451:%.*]] = icmp slt i32 [[CONV2449]], [[CONV2450]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2451]], label [[IF_THEN2453:%.*]], label [[IF_END2454:%.*]]
|
|
// SIMD-ONLY0: if.then2453:
|
|
// SIMD-ONLY0-NEXT: [[TMP1518:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1518]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2454]]
|
|
// SIMD-ONLY0: if.end2454:
|
|
// SIMD-ONLY0-NEXT: [[TMP1519:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1519]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1520:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2455:%.*]] = zext i16 [[TMP1520]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1521:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2456:%.*]] = zext i16 [[TMP1521]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2457:%.*]] = icmp eq i32 [[CONV2455]], [[CONV2456]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2457]], label [[IF_THEN2459:%.*]], label [[IF_END2460:%.*]]
|
|
// SIMD-ONLY0: if.then2459:
|
|
// SIMD-ONLY0-NEXT: [[TMP1522:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1522]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2460]]
|
|
// SIMD-ONLY0: if.end2460:
|
|
// SIMD-ONLY0-NEXT: [[TMP1523:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1523]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1524:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2461:%.*]] = zext i16 [[TMP1524]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1525:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2462:%.*]] = zext i16 [[TMP1525]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2463:%.*]] = icmp eq i32 [[CONV2461]], [[CONV2462]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2463]], label [[IF_THEN2465:%.*]], label [[IF_END2466:%.*]]
|
|
// SIMD-ONLY0: if.then2465:
|
|
// SIMD-ONLY0-NEXT: [[TMP1526:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1526]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2466]]
|
|
// SIMD-ONLY0: if.end2466:
|
|
// SIMD-ONLY0-NEXT: [[TMP1527:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1527]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1528:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2467:%.*]] = zext i16 [[TMP1528]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1529:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2468:%.*]] = zext i16 [[TMP1529]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2469:%.*]] = icmp eq i32 [[CONV2467]], [[CONV2468]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2469]], label [[IF_THEN2471:%.*]], label [[IF_ELSE2472:%.*]]
|
|
// SIMD-ONLY0: if.then2471:
|
|
// SIMD-ONLY0-NEXT: [[TMP1530:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1530]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2473:%.*]]
|
|
// SIMD-ONLY0: if.else2472:
|
|
// SIMD-ONLY0-NEXT: [[TMP1531:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1531]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2473]]
|
|
// SIMD-ONLY0: if.end2473:
|
|
// SIMD-ONLY0-NEXT: [[TMP1532:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2474:%.*]] = zext i16 [[TMP1532]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1533:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2475:%.*]] = zext i16 [[TMP1533]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2476:%.*]] = icmp eq i32 [[CONV2474]], [[CONV2475]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2476]], label [[IF_THEN2478:%.*]], label [[IF_ELSE2479:%.*]]
|
|
// SIMD-ONLY0: if.then2478:
|
|
// SIMD-ONLY0-NEXT: [[TMP1534:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1534]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2480:%.*]]
|
|
// SIMD-ONLY0: if.else2479:
|
|
// SIMD-ONLY0-NEXT: [[TMP1535:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1535]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2480]]
|
|
// SIMD-ONLY0: if.end2480:
|
|
// SIMD-ONLY0-NEXT: [[TMP1536:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2481:%.*]] = zext i16 [[TMP1536]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1537:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2482:%.*]] = zext i16 [[TMP1537]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2483:%.*]] = icmp eq i32 [[CONV2481]], [[CONV2482]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2484:%.*]] = zext i1 [[CMP2483]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2485:%.*]] = trunc i32 [[CONV2484]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2485]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1538:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2486:%.*]] = icmp ne i16 [[TMP1538]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2486]], label [[IF_THEN2487:%.*]], label [[IF_END2488:%.*]]
|
|
// SIMD-ONLY0: if.then2487:
|
|
// SIMD-ONLY0-NEXT: [[TMP1539:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1539]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2488]]
|
|
// SIMD-ONLY0: if.end2488:
|
|
// SIMD-ONLY0-NEXT: [[TMP1540:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2489:%.*]] = zext i16 [[TMP1540]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1541:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2490:%.*]] = zext i16 [[TMP1541]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2491:%.*]] = icmp eq i32 [[CONV2489]], [[CONV2490]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2492:%.*]] = zext i1 [[CMP2491]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2493:%.*]] = trunc i32 [[CONV2492]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2493]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1542:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2494:%.*]] = icmp ne i16 [[TMP1542]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2494]], label [[IF_THEN2495:%.*]], label [[IF_END2496:%.*]]
|
|
// SIMD-ONLY0: if.then2495:
|
|
// SIMD-ONLY0-NEXT: [[TMP1543:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1543]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2496]]
|
|
// SIMD-ONLY0: if.end2496:
|
|
// SIMD-ONLY0-NEXT: [[TMP1544:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2497:%.*]] = zext i16 [[TMP1544]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1545:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2498:%.*]] = zext i16 [[TMP1545]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2499:%.*]] = icmp eq i32 [[CONV2497]], [[CONV2498]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2500:%.*]] = zext i1 [[CMP2499]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2501:%.*]] = trunc i32 [[CONV2500]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2501]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1546:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2502:%.*]] = icmp ne i16 [[TMP1546]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2502]], label [[IF_THEN2503:%.*]], label [[IF_ELSE2504:%.*]]
|
|
// SIMD-ONLY0: if.then2503:
|
|
// SIMD-ONLY0-NEXT: [[TMP1547:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1547]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2505:%.*]]
|
|
// SIMD-ONLY0: if.else2504:
|
|
// SIMD-ONLY0-NEXT: [[TMP1548:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1548]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2505]]
|
|
// SIMD-ONLY0: if.end2505:
|
|
// SIMD-ONLY0-NEXT: [[TMP1549:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2506:%.*]] = zext i16 [[TMP1549]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1550:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2507:%.*]] = zext i16 [[TMP1550]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2508:%.*]] = icmp eq i32 [[CONV2506]], [[CONV2507]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2509:%.*]] = zext i1 [[CMP2508]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2510:%.*]] = trunc i32 [[CONV2509]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2510]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1551:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2511:%.*]] = icmp ne i16 [[TMP1551]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2511]], label [[IF_THEN2512:%.*]], label [[IF_ELSE2513:%.*]]
|
|
// SIMD-ONLY0: if.then2512:
|
|
// SIMD-ONLY0-NEXT: [[TMP1552:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1552]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2514:%.*]]
|
|
// SIMD-ONLY0: if.else2513:
|
|
// SIMD-ONLY0-NEXT: [[TMP1553:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1553]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2514]]
|
|
// SIMD-ONLY0: if.end2514:
|
|
// SIMD-ONLY0-NEXT: [[TMP1554:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1554]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1555:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2515:%.*]] = zext i16 [[TMP1555]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1556:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2516:%.*]] = zext i16 [[TMP1556]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2517:%.*]] = icmp sgt i32 [[CONV2515]], [[CONV2516]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2517]], label [[IF_THEN2519:%.*]], label [[IF_END2520:%.*]]
|
|
// SIMD-ONLY0: if.then2519:
|
|
// SIMD-ONLY0-NEXT: [[TMP1557:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1557]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2520]]
|
|
// SIMD-ONLY0: if.end2520:
|
|
// SIMD-ONLY0-NEXT: [[TMP1558:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1558]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1559:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2521:%.*]] = zext i16 [[TMP1559]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1560:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2522:%.*]] = zext i16 [[TMP1560]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2523:%.*]] = icmp sgt i32 [[CONV2521]], [[CONV2522]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2523]], label [[IF_THEN2525:%.*]], label [[IF_END2526:%.*]]
|
|
// SIMD-ONLY0: if.then2525:
|
|
// SIMD-ONLY0-NEXT: [[TMP1561:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1561]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2526]]
|
|
// SIMD-ONLY0: if.end2526:
|
|
// SIMD-ONLY0-NEXT: [[TMP1562:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1562]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1563:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2527:%.*]] = zext i16 [[TMP1563]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1564:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2528:%.*]] = zext i16 [[TMP1564]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2529:%.*]] = icmp slt i32 [[CONV2527]], [[CONV2528]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2529]], label [[IF_THEN2531:%.*]], label [[IF_END2532:%.*]]
|
|
// SIMD-ONLY0: if.then2531:
|
|
// SIMD-ONLY0-NEXT: [[TMP1565:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1565]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2532]]
|
|
// SIMD-ONLY0: if.end2532:
|
|
// SIMD-ONLY0-NEXT: [[TMP1566:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1566]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1567:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2533:%.*]] = zext i16 [[TMP1567]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1568:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2534:%.*]] = zext i16 [[TMP1568]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2535:%.*]] = icmp slt i32 [[CONV2533]], [[CONV2534]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2535]], label [[IF_THEN2537:%.*]], label [[IF_END2538:%.*]]
|
|
// SIMD-ONLY0: if.then2537:
|
|
// SIMD-ONLY0-NEXT: [[TMP1569:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1569]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2538]]
|
|
// SIMD-ONLY0: if.end2538:
|
|
// SIMD-ONLY0-NEXT: [[TMP1570:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1570]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1571:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2539:%.*]] = zext i16 [[TMP1571]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1572:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2540:%.*]] = zext i16 [[TMP1572]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2541:%.*]] = icmp eq i32 [[CONV2539]], [[CONV2540]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2541]], label [[IF_THEN2543:%.*]], label [[IF_END2544:%.*]]
|
|
// SIMD-ONLY0: if.then2543:
|
|
// SIMD-ONLY0-NEXT: [[TMP1573:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1573]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2544]]
|
|
// SIMD-ONLY0: if.end2544:
|
|
// SIMD-ONLY0-NEXT: [[TMP1574:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1574]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1575:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2545:%.*]] = zext i16 [[TMP1575]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1576:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2546:%.*]] = zext i16 [[TMP1576]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2547:%.*]] = icmp eq i32 [[CONV2545]], [[CONV2546]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2547]], label [[IF_THEN2549:%.*]], label [[IF_END2550:%.*]]
|
|
// SIMD-ONLY0: if.then2549:
|
|
// SIMD-ONLY0-NEXT: [[TMP1577:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1577]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2550]]
|
|
// SIMD-ONLY0: if.end2550:
|
|
// SIMD-ONLY0-NEXT: [[TMP1578:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2551:%.*]] = zext i16 [[TMP1578]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1579:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2552:%.*]] = zext i16 [[TMP1579]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2553:%.*]] = icmp sgt i32 [[CONV2551]], [[CONV2552]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2553]], label [[IF_THEN2555:%.*]], label [[IF_END2556:%.*]]
|
|
// SIMD-ONLY0: if.then2555:
|
|
// SIMD-ONLY0-NEXT: [[TMP1580:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1580]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2556]]
|
|
// SIMD-ONLY0: if.end2556:
|
|
// SIMD-ONLY0-NEXT: [[TMP1581:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1581]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1582:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2557:%.*]] = zext i16 [[TMP1582]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1583:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2558:%.*]] = zext i16 [[TMP1583]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2559:%.*]] = icmp sgt i32 [[CONV2557]], [[CONV2558]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2559]], label [[IF_THEN2561:%.*]], label [[IF_END2562:%.*]]
|
|
// SIMD-ONLY0: if.then2561:
|
|
// SIMD-ONLY0-NEXT: [[TMP1584:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1584]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2562]]
|
|
// SIMD-ONLY0: if.end2562:
|
|
// SIMD-ONLY0-NEXT: [[TMP1585:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1585]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1586:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2563:%.*]] = zext i16 [[TMP1586]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1587:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2564:%.*]] = zext i16 [[TMP1587]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2565:%.*]] = icmp slt i32 [[CONV2563]], [[CONV2564]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2565]], label [[IF_THEN2567:%.*]], label [[IF_END2568:%.*]]
|
|
// SIMD-ONLY0: if.then2567:
|
|
// SIMD-ONLY0-NEXT: [[TMP1588:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1588]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2568]]
|
|
// SIMD-ONLY0: if.end2568:
|
|
// SIMD-ONLY0-NEXT: [[TMP1589:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1589]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1590:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2569:%.*]] = zext i16 [[TMP1590]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1591:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2570:%.*]] = zext i16 [[TMP1591]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2571:%.*]] = icmp slt i32 [[CONV2569]], [[CONV2570]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2571]], label [[IF_THEN2573:%.*]], label [[IF_END2574:%.*]]
|
|
// SIMD-ONLY0: if.then2573:
|
|
// SIMD-ONLY0-NEXT: [[TMP1592:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1592]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2574]]
|
|
// SIMD-ONLY0: if.end2574:
|
|
// SIMD-ONLY0-NEXT: [[TMP1593:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1593]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1594:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2575:%.*]] = zext i16 [[TMP1594]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1595:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2576:%.*]] = zext i16 [[TMP1595]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2577:%.*]] = icmp eq i32 [[CONV2575]], [[CONV2576]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2577]], label [[IF_THEN2579:%.*]], label [[IF_END2580:%.*]]
|
|
// SIMD-ONLY0: if.then2579:
|
|
// SIMD-ONLY0-NEXT: [[TMP1596:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1596]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2580]]
|
|
// SIMD-ONLY0: if.end2580:
|
|
// SIMD-ONLY0-NEXT: [[TMP1597:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1597]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1598:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2581:%.*]] = zext i16 [[TMP1598]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1599:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2582:%.*]] = zext i16 [[TMP1599]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2583:%.*]] = icmp eq i32 [[CONV2581]], [[CONV2582]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2583]], label [[IF_THEN2585:%.*]], label [[IF_END2586:%.*]]
|
|
// SIMD-ONLY0: if.then2585:
|
|
// SIMD-ONLY0-NEXT: [[TMP1600:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1600]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2586]]
|
|
// SIMD-ONLY0: if.end2586:
|
|
// SIMD-ONLY0-NEXT: [[TMP1601:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1601]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1602:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2587:%.*]] = zext i16 [[TMP1602]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1603:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2588:%.*]] = zext i16 [[TMP1603]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2589:%.*]] = icmp eq i32 [[CONV2587]], [[CONV2588]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2589]], label [[IF_THEN2591:%.*]], label [[IF_ELSE2592:%.*]]
|
|
// SIMD-ONLY0: if.then2591:
|
|
// SIMD-ONLY0-NEXT: [[TMP1604:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1604]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2593:%.*]]
|
|
// SIMD-ONLY0: if.else2592:
|
|
// SIMD-ONLY0-NEXT: [[TMP1605:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1605]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2593]]
|
|
// SIMD-ONLY0: if.end2593:
|
|
// SIMD-ONLY0-NEXT: [[TMP1606:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2594:%.*]] = zext i16 [[TMP1606]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1607:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2595:%.*]] = zext i16 [[TMP1607]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2596:%.*]] = icmp eq i32 [[CONV2594]], [[CONV2595]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2596]], label [[IF_THEN2598:%.*]], label [[IF_ELSE2599:%.*]]
|
|
// SIMD-ONLY0: if.then2598:
|
|
// SIMD-ONLY0-NEXT: [[TMP1608:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1608]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2600:%.*]]
|
|
// SIMD-ONLY0: if.else2599:
|
|
// SIMD-ONLY0-NEXT: [[TMP1609:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1609]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2600]]
|
|
// SIMD-ONLY0: if.end2600:
|
|
// SIMD-ONLY0-NEXT: [[TMP1610:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2601:%.*]] = zext i16 [[TMP1610]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1611:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2602:%.*]] = zext i16 [[TMP1611]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2603:%.*]] = icmp eq i32 [[CONV2601]], [[CONV2602]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2604:%.*]] = zext i1 [[CMP2603]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2605:%.*]] = trunc i32 [[CONV2604]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2605]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1612:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2606:%.*]] = icmp ne i16 [[TMP1612]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2606]], label [[IF_THEN2607:%.*]], label [[IF_END2608:%.*]]
|
|
// SIMD-ONLY0: if.then2607:
|
|
// SIMD-ONLY0-NEXT: [[TMP1613:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1613]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2608]]
|
|
// SIMD-ONLY0: if.end2608:
|
|
// SIMD-ONLY0-NEXT: [[TMP1614:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2609:%.*]] = zext i16 [[TMP1614]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1615:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2610:%.*]] = zext i16 [[TMP1615]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2611:%.*]] = icmp eq i32 [[CONV2609]], [[CONV2610]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2612:%.*]] = zext i1 [[CMP2611]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2613:%.*]] = trunc i32 [[CONV2612]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2613]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1616:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2614:%.*]] = icmp ne i16 [[TMP1616]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2614]], label [[IF_THEN2615:%.*]], label [[IF_END2616:%.*]]
|
|
// SIMD-ONLY0: if.then2615:
|
|
// SIMD-ONLY0-NEXT: [[TMP1617:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1617]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2616]]
|
|
// SIMD-ONLY0: if.end2616:
|
|
// SIMD-ONLY0-NEXT: [[TMP1618:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2617:%.*]] = zext i16 [[TMP1618]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1619:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2618:%.*]] = zext i16 [[TMP1619]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2619:%.*]] = icmp eq i32 [[CONV2617]], [[CONV2618]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2620:%.*]] = zext i1 [[CMP2619]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2621:%.*]] = trunc i32 [[CONV2620]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2621]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1620:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2622:%.*]] = icmp ne i16 [[TMP1620]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2622]], label [[IF_THEN2623:%.*]], label [[IF_ELSE2624:%.*]]
|
|
// SIMD-ONLY0: if.then2623:
|
|
// SIMD-ONLY0-NEXT: [[TMP1621:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1621]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2625:%.*]]
|
|
// SIMD-ONLY0: if.else2624:
|
|
// SIMD-ONLY0-NEXT: [[TMP1622:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1622]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2625]]
|
|
// SIMD-ONLY0: if.end2625:
|
|
// SIMD-ONLY0-NEXT: [[TMP1623:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2626:%.*]] = zext i16 [[TMP1623]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1624:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2627:%.*]] = zext i16 [[TMP1624]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2628:%.*]] = icmp eq i32 [[CONV2626]], [[CONV2627]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2629:%.*]] = zext i1 [[CMP2628]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2630:%.*]] = trunc i32 [[CONV2629]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2630]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1625:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2631:%.*]] = icmp ne i16 [[TMP1625]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2631]], label [[IF_THEN2632:%.*]], label [[IF_ELSE2633:%.*]]
|
|
// SIMD-ONLY0: if.then2632:
|
|
// SIMD-ONLY0-NEXT: [[TMP1626:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1626]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2634:%.*]]
|
|
// SIMD-ONLY0: if.else2633:
|
|
// SIMD-ONLY0-NEXT: [[TMP1627:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1627]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2634]]
|
|
// SIMD-ONLY0: if.end2634:
|
|
// SIMD-ONLY0-NEXT: [[TMP1628:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1628]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1629:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2635:%.*]] = zext i16 [[TMP1629]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1630:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2636:%.*]] = zext i16 [[TMP1630]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2637:%.*]] = icmp sgt i32 [[CONV2635]], [[CONV2636]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2637]], label [[IF_THEN2639:%.*]], label [[IF_END2640:%.*]]
|
|
// SIMD-ONLY0: if.then2639:
|
|
// SIMD-ONLY0-NEXT: [[TMP1631:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1631]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2640]]
|
|
// SIMD-ONLY0: if.end2640:
|
|
// SIMD-ONLY0-NEXT: [[TMP1632:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1632]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1633:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2641:%.*]] = zext i16 [[TMP1633]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1634:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2642:%.*]] = zext i16 [[TMP1634]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2643:%.*]] = icmp sgt i32 [[CONV2641]], [[CONV2642]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2643]], label [[IF_THEN2645:%.*]], label [[IF_END2646:%.*]]
|
|
// SIMD-ONLY0: if.then2645:
|
|
// SIMD-ONLY0-NEXT: [[TMP1635:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1635]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2646]]
|
|
// SIMD-ONLY0: if.end2646:
|
|
// SIMD-ONLY0-NEXT: [[TMP1636:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1636]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1637:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2647:%.*]] = zext i16 [[TMP1637]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1638:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2648:%.*]] = zext i16 [[TMP1638]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2649:%.*]] = icmp slt i32 [[CONV2647]], [[CONV2648]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2649]], label [[IF_THEN2651:%.*]], label [[IF_END2652:%.*]]
|
|
// SIMD-ONLY0: if.then2651:
|
|
// SIMD-ONLY0-NEXT: [[TMP1639:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1639]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2652]]
|
|
// SIMD-ONLY0: if.end2652:
|
|
// SIMD-ONLY0-NEXT: [[TMP1640:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1640]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1641:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2653:%.*]] = zext i16 [[TMP1641]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1642:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2654:%.*]] = zext i16 [[TMP1642]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2655:%.*]] = icmp slt i32 [[CONV2653]], [[CONV2654]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2655]], label [[IF_THEN2657:%.*]], label [[IF_END2658:%.*]]
|
|
// SIMD-ONLY0: if.then2657:
|
|
// SIMD-ONLY0-NEXT: [[TMP1643:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1643]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2658]]
|
|
// SIMD-ONLY0: if.end2658:
|
|
// SIMD-ONLY0-NEXT: [[TMP1644:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1644]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1645:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2659:%.*]] = zext i16 [[TMP1645]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1646:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2660:%.*]] = zext i16 [[TMP1646]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2661:%.*]] = icmp eq i32 [[CONV2659]], [[CONV2660]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2661]], label [[IF_THEN2663:%.*]], label [[IF_END2664:%.*]]
|
|
// SIMD-ONLY0: if.then2663:
|
|
// SIMD-ONLY0-NEXT: [[TMP1647:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1647]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2664]]
|
|
// SIMD-ONLY0: if.end2664:
|
|
// SIMD-ONLY0-NEXT: [[TMP1648:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1648]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1649:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2665:%.*]] = zext i16 [[TMP1649]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1650:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2666:%.*]] = zext i16 [[TMP1650]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2667:%.*]] = icmp eq i32 [[CONV2665]], [[CONV2666]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2667]], label [[IF_THEN2669:%.*]], label [[IF_END2670:%.*]]
|
|
// SIMD-ONLY0: if.then2669:
|
|
// SIMD-ONLY0-NEXT: [[TMP1651:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1651]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2670]]
|
|
// SIMD-ONLY0: if.end2670:
|
|
// SIMD-ONLY0-NEXT: [[TMP1652:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2671:%.*]] = zext i16 [[TMP1652]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1653:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2672:%.*]] = zext i16 [[TMP1653]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2673:%.*]] = icmp sgt i32 [[CONV2671]], [[CONV2672]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2673]], label [[IF_THEN2675:%.*]], label [[IF_END2676:%.*]]
|
|
// SIMD-ONLY0: if.then2675:
|
|
// SIMD-ONLY0-NEXT: [[TMP1654:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1654]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2676]]
|
|
// SIMD-ONLY0: if.end2676:
|
|
// SIMD-ONLY0-NEXT: [[TMP1655:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1655]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1656:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2677:%.*]] = zext i16 [[TMP1656]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1657:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2678:%.*]] = zext i16 [[TMP1657]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2679:%.*]] = icmp sgt i32 [[CONV2677]], [[CONV2678]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2679]], label [[IF_THEN2681:%.*]], label [[IF_END2682:%.*]]
|
|
// SIMD-ONLY0: if.then2681:
|
|
// SIMD-ONLY0-NEXT: [[TMP1658:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1658]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2682]]
|
|
// SIMD-ONLY0: if.end2682:
|
|
// SIMD-ONLY0-NEXT: [[TMP1659:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1659]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1660:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2683:%.*]] = zext i16 [[TMP1660]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1661:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2684:%.*]] = zext i16 [[TMP1661]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2685:%.*]] = icmp slt i32 [[CONV2683]], [[CONV2684]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2685]], label [[IF_THEN2687:%.*]], label [[IF_END2688:%.*]]
|
|
// SIMD-ONLY0: if.then2687:
|
|
// SIMD-ONLY0-NEXT: [[TMP1662:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1662]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2688]]
|
|
// SIMD-ONLY0: if.end2688:
|
|
// SIMD-ONLY0-NEXT: [[TMP1663:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1663]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1664:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2689:%.*]] = zext i16 [[TMP1664]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1665:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2690:%.*]] = zext i16 [[TMP1665]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2691:%.*]] = icmp slt i32 [[CONV2689]], [[CONV2690]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2691]], label [[IF_THEN2693:%.*]], label [[IF_END2694:%.*]]
|
|
// SIMD-ONLY0: if.then2693:
|
|
// SIMD-ONLY0-NEXT: [[TMP1666:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1666]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2694]]
|
|
// SIMD-ONLY0: if.end2694:
|
|
// SIMD-ONLY0-NEXT: [[TMP1667:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1667]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1668:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2695:%.*]] = zext i16 [[TMP1668]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1669:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2696:%.*]] = zext i16 [[TMP1669]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2697:%.*]] = icmp eq i32 [[CONV2695]], [[CONV2696]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2697]], label [[IF_THEN2699:%.*]], label [[IF_END2700:%.*]]
|
|
// SIMD-ONLY0: if.then2699:
|
|
// SIMD-ONLY0-NEXT: [[TMP1670:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1670]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2700]]
|
|
// SIMD-ONLY0: if.end2700:
|
|
// SIMD-ONLY0-NEXT: [[TMP1671:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1671]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1672:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2701:%.*]] = zext i16 [[TMP1672]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1673:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2702:%.*]] = zext i16 [[TMP1673]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2703:%.*]] = icmp eq i32 [[CONV2701]], [[CONV2702]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2703]], label [[IF_THEN2705:%.*]], label [[IF_END2706:%.*]]
|
|
// SIMD-ONLY0: if.then2705:
|
|
// SIMD-ONLY0-NEXT: [[TMP1674:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1674]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2706]]
|
|
// SIMD-ONLY0: if.end2706:
|
|
// SIMD-ONLY0-NEXT: [[TMP1675:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1675]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1676:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2707:%.*]] = zext i16 [[TMP1676]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1677:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2708:%.*]] = zext i16 [[TMP1677]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2709:%.*]] = icmp eq i32 [[CONV2707]], [[CONV2708]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2709]], label [[IF_THEN2711:%.*]], label [[IF_ELSE2712:%.*]]
|
|
// SIMD-ONLY0: if.then2711:
|
|
// SIMD-ONLY0-NEXT: [[TMP1678:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1678]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2713:%.*]]
|
|
// SIMD-ONLY0: if.else2712:
|
|
// SIMD-ONLY0-NEXT: [[TMP1679:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1679]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2713]]
|
|
// SIMD-ONLY0: if.end2713:
|
|
// SIMD-ONLY0-NEXT: [[TMP1680:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2714:%.*]] = zext i16 [[TMP1680]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1681:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2715:%.*]] = zext i16 [[TMP1681]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2716:%.*]] = icmp eq i32 [[CONV2714]], [[CONV2715]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2716]], label [[IF_THEN2718:%.*]], label [[IF_ELSE2719:%.*]]
|
|
// SIMD-ONLY0: if.then2718:
|
|
// SIMD-ONLY0-NEXT: [[TMP1682:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1682]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2720:%.*]]
|
|
// SIMD-ONLY0: if.else2719:
|
|
// SIMD-ONLY0-NEXT: [[TMP1683:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1683]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2720]]
|
|
// SIMD-ONLY0: if.end2720:
|
|
// SIMD-ONLY0-NEXT: [[TMP1684:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2721:%.*]] = zext i16 [[TMP1684]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1685:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2722:%.*]] = zext i16 [[TMP1685]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2723:%.*]] = icmp eq i32 [[CONV2721]], [[CONV2722]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2724:%.*]] = zext i1 [[CMP2723]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2725:%.*]] = trunc i32 [[CONV2724]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2725]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1686:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2726:%.*]] = icmp ne i16 [[TMP1686]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2726]], label [[IF_THEN2727:%.*]], label [[IF_END2728:%.*]]
|
|
// SIMD-ONLY0: if.then2727:
|
|
// SIMD-ONLY0-NEXT: [[TMP1687:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1687]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2728]]
|
|
// SIMD-ONLY0: if.end2728:
|
|
// SIMD-ONLY0-NEXT: [[TMP1688:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2729:%.*]] = zext i16 [[TMP1688]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1689:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2730:%.*]] = zext i16 [[TMP1689]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2731:%.*]] = icmp eq i32 [[CONV2729]], [[CONV2730]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2732:%.*]] = zext i1 [[CMP2731]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2733:%.*]] = trunc i32 [[CONV2732]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2733]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1690:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2734:%.*]] = icmp ne i16 [[TMP1690]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2734]], label [[IF_THEN2735:%.*]], label [[IF_END2736:%.*]]
|
|
// SIMD-ONLY0: if.then2735:
|
|
// SIMD-ONLY0-NEXT: [[TMP1691:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1691]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2736]]
|
|
// SIMD-ONLY0: if.end2736:
|
|
// SIMD-ONLY0-NEXT: [[TMP1692:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2737:%.*]] = zext i16 [[TMP1692]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1693:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2738:%.*]] = zext i16 [[TMP1693]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2739:%.*]] = icmp eq i32 [[CONV2737]], [[CONV2738]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2740:%.*]] = zext i1 [[CMP2739]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2741:%.*]] = trunc i32 [[CONV2740]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2741]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1694:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2742:%.*]] = icmp ne i16 [[TMP1694]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2742]], label [[IF_THEN2743:%.*]], label [[IF_ELSE2744:%.*]]
|
|
// SIMD-ONLY0: if.then2743:
|
|
// SIMD-ONLY0-NEXT: [[TMP1695:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1695]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2745:%.*]]
|
|
// SIMD-ONLY0: if.else2744:
|
|
// SIMD-ONLY0-NEXT: [[TMP1696:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1696]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2745]]
|
|
// SIMD-ONLY0: if.end2745:
|
|
// SIMD-ONLY0-NEXT: [[TMP1697:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2746:%.*]] = zext i16 [[TMP1697]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1698:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2747:%.*]] = zext i16 [[TMP1698]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2748:%.*]] = icmp eq i32 [[CONV2746]], [[CONV2747]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2749:%.*]] = zext i1 [[CMP2748]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2750:%.*]] = trunc i32 [[CONV2749]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2750]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1699:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2751:%.*]] = icmp ne i16 [[TMP1699]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2751]], label [[IF_THEN2752:%.*]], label [[IF_ELSE2753:%.*]]
|
|
// SIMD-ONLY0: if.then2752:
|
|
// SIMD-ONLY0-NEXT: [[TMP1700:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1700]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2754:%.*]]
|
|
// SIMD-ONLY0: if.else2753:
|
|
// SIMD-ONLY0-NEXT: [[TMP1701:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1701]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2754]]
|
|
// SIMD-ONLY0: if.end2754:
|
|
// SIMD-ONLY0-NEXT: [[TMP1702:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1702]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1703:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2755:%.*]] = zext i16 [[TMP1703]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1704:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2756:%.*]] = zext i16 [[TMP1704]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2757:%.*]] = icmp sgt i32 [[CONV2755]], [[CONV2756]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2757]], label [[IF_THEN2759:%.*]], label [[IF_END2760:%.*]]
|
|
// SIMD-ONLY0: if.then2759:
|
|
// SIMD-ONLY0-NEXT: [[TMP1705:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1705]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2760]]
|
|
// SIMD-ONLY0: if.end2760:
|
|
// SIMD-ONLY0-NEXT: [[TMP1706:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1706]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1707:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2761:%.*]] = zext i16 [[TMP1707]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1708:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2762:%.*]] = zext i16 [[TMP1708]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2763:%.*]] = icmp sgt i32 [[CONV2761]], [[CONV2762]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2763]], label [[IF_THEN2765:%.*]], label [[IF_END2766:%.*]]
|
|
// SIMD-ONLY0: if.then2765:
|
|
// SIMD-ONLY0-NEXT: [[TMP1709:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1709]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2766]]
|
|
// SIMD-ONLY0: if.end2766:
|
|
// SIMD-ONLY0-NEXT: [[TMP1710:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1710]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1711:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2767:%.*]] = zext i16 [[TMP1711]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1712:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2768:%.*]] = zext i16 [[TMP1712]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2769:%.*]] = icmp slt i32 [[CONV2767]], [[CONV2768]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2769]], label [[IF_THEN2771:%.*]], label [[IF_END2772:%.*]]
|
|
// SIMD-ONLY0: if.then2771:
|
|
// SIMD-ONLY0-NEXT: [[TMP1713:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1713]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2772]]
|
|
// SIMD-ONLY0: if.end2772:
|
|
// SIMD-ONLY0-NEXT: [[TMP1714:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1714]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1715:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2773:%.*]] = zext i16 [[TMP1715]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1716:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2774:%.*]] = zext i16 [[TMP1716]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2775:%.*]] = icmp slt i32 [[CONV2773]], [[CONV2774]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2775]], label [[IF_THEN2777:%.*]], label [[IF_END2778:%.*]]
|
|
// SIMD-ONLY0: if.then2777:
|
|
// SIMD-ONLY0-NEXT: [[TMP1717:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1717]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2778]]
|
|
// SIMD-ONLY0: if.end2778:
|
|
// SIMD-ONLY0-NEXT: [[TMP1718:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1718]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1719:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2779:%.*]] = zext i16 [[TMP1719]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1720:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2780:%.*]] = zext i16 [[TMP1720]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2781:%.*]] = icmp eq i32 [[CONV2779]], [[CONV2780]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2781]], label [[IF_THEN2783:%.*]], label [[IF_END2784:%.*]]
|
|
// SIMD-ONLY0: if.then2783:
|
|
// SIMD-ONLY0-NEXT: [[TMP1721:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1721]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2784]]
|
|
// SIMD-ONLY0: if.end2784:
|
|
// SIMD-ONLY0-NEXT: [[TMP1722:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1722]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1723:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2785:%.*]] = zext i16 [[TMP1723]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1724:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2786:%.*]] = zext i16 [[TMP1724]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2787:%.*]] = icmp eq i32 [[CONV2785]], [[CONV2786]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2787]], label [[IF_THEN2789:%.*]], label [[IF_END2790:%.*]]
|
|
// SIMD-ONLY0: if.then2789:
|
|
// SIMD-ONLY0-NEXT: [[TMP1725:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1725]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2790]]
|
|
// SIMD-ONLY0: if.end2790:
|
|
// SIMD-ONLY0-NEXT: [[TMP1726:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2791:%.*]] = zext i16 [[TMP1726]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1727:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2792:%.*]] = zext i16 [[TMP1727]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2793:%.*]] = icmp sgt i32 [[CONV2791]], [[CONV2792]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2793]], label [[IF_THEN2795:%.*]], label [[IF_END2796:%.*]]
|
|
// SIMD-ONLY0: if.then2795:
|
|
// SIMD-ONLY0-NEXT: [[TMP1728:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1728]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2796]]
|
|
// SIMD-ONLY0: if.end2796:
|
|
// SIMD-ONLY0-NEXT: [[TMP1729:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1729]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1730:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2797:%.*]] = zext i16 [[TMP1730]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1731:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2798:%.*]] = zext i16 [[TMP1731]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2799:%.*]] = icmp sgt i32 [[CONV2797]], [[CONV2798]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2799]], label [[IF_THEN2801:%.*]], label [[IF_END2802:%.*]]
|
|
// SIMD-ONLY0: if.then2801:
|
|
// SIMD-ONLY0-NEXT: [[TMP1732:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1732]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2802]]
|
|
// SIMD-ONLY0: if.end2802:
|
|
// SIMD-ONLY0-NEXT: [[TMP1733:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1733]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1734:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2803:%.*]] = zext i16 [[TMP1734]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1735:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2804:%.*]] = zext i16 [[TMP1735]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2805:%.*]] = icmp slt i32 [[CONV2803]], [[CONV2804]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2805]], label [[IF_THEN2807:%.*]], label [[IF_END2808:%.*]]
|
|
// SIMD-ONLY0: if.then2807:
|
|
// SIMD-ONLY0-NEXT: [[TMP1736:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1736]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2808]]
|
|
// SIMD-ONLY0: if.end2808:
|
|
// SIMD-ONLY0-NEXT: [[TMP1737:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1737]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1738:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2809:%.*]] = zext i16 [[TMP1738]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1739:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2810:%.*]] = zext i16 [[TMP1739]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2811:%.*]] = icmp slt i32 [[CONV2809]], [[CONV2810]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2811]], label [[IF_THEN2813:%.*]], label [[IF_END2814:%.*]]
|
|
// SIMD-ONLY0: if.then2813:
|
|
// SIMD-ONLY0-NEXT: [[TMP1740:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1740]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2814]]
|
|
// SIMD-ONLY0: if.end2814:
|
|
// SIMD-ONLY0-NEXT: [[TMP1741:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1741]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1742:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2815:%.*]] = zext i16 [[TMP1742]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1743:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2816:%.*]] = zext i16 [[TMP1743]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2817:%.*]] = icmp eq i32 [[CONV2815]], [[CONV2816]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2817]], label [[IF_THEN2819:%.*]], label [[IF_END2820:%.*]]
|
|
// SIMD-ONLY0: if.then2819:
|
|
// SIMD-ONLY0-NEXT: [[TMP1744:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1744]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2820]]
|
|
// SIMD-ONLY0: if.end2820:
|
|
// SIMD-ONLY0-NEXT: [[TMP1745:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1745]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1746:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2821:%.*]] = zext i16 [[TMP1746]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1747:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2822:%.*]] = zext i16 [[TMP1747]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2823:%.*]] = icmp eq i32 [[CONV2821]], [[CONV2822]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2823]], label [[IF_THEN2825:%.*]], label [[IF_END2826:%.*]]
|
|
// SIMD-ONLY0: if.then2825:
|
|
// SIMD-ONLY0-NEXT: [[TMP1748:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1748]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2826]]
|
|
// SIMD-ONLY0: if.end2826:
|
|
// SIMD-ONLY0-NEXT: [[TMP1749:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1749]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1750:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2827:%.*]] = zext i16 [[TMP1750]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1751:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2828:%.*]] = zext i16 [[TMP1751]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2829:%.*]] = icmp eq i32 [[CONV2827]], [[CONV2828]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2829]], label [[IF_THEN2831:%.*]], label [[IF_ELSE2832:%.*]]
|
|
// SIMD-ONLY0: if.then2831:
|
|
// SIMD-ONLY0-NEXT: [[TMP1752:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1752]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2833:%.*]]
|
|
// SIMD-ONLY0: if.else2832:
|
|
// SIMD-ONLY0-NEXT: [[TMP1753:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1753]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2833]]
|
|
// SIMD-ONLY0: if.end2833:
|
|
// SIMD-ONLY0-NEXT: [[TMP1754:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2834:%.*]] = zext i16 [[TMP1754]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1755:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2835:%.*]] = zext i16 [[TMP1755]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2836:%.*]] = icmp eq i32 [[CONV2834]], [[CONV2835]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2836]], label [[IF_THEN2838:%.*]], label [[IF_ELSE2839:%.*]]
|
|
// SIMD-ONLY0: if.then2838:
|
|
// SIMD-ONLY0-NEXT: [[TMP1756:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1756]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2840:%.*]]
|
|
// SIMD-ONLY0: if.else2839:
|
|
// SIMD-ONLY0-NEXT: [[TMP1757:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1757]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2840]]
|
|
// SIMD-ONLY0: if.end2840:
|
|
// SIMD-ONLY0-NEXT: [[TMP1758:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2841:%.*]] = zext i16 [[TMP1758]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1759:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2842:%.*]] = zext i16 [[TMP1759]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2843:%.*]] = icmp eq i32 [[CONV2841]], [[CONV2842]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2844:%.*]] = zext i1 [[CMP2843]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2845:%.*]] = trunc i32 [[CONV2844]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2845]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1760:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2846:%.*]] = icmp ne i16 [[TMP1760]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2846]], label [[IF_THEN2847:%.*]], label [[IF_END2848:%.*]]
|
|
// SIMD-ONLY0: if.then2847:
|
|
// SIMD-ONLY0-NEXT: [[TMP1761:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1761]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2848]]
|
|
// SIMD-ONLY0: if.end2848:
|
|
// SIMD-ONLY0-NEXT: [[TMP1762:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2849:%.*]] = zext i16 [[TMP1762]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1763:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2850:%.*]] = zext i16 [[TMP1763]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2851:%.*]] = icmp eq i32 [[CONV2849]], [[CONV2850]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2852:%.*]] = zext i1 [[CMP2851]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2853:%.*]] = trunc i32 [[CONV2852]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2853]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1764:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2854:%.*]] = icmp ne i16 [[TMP1764]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2854]], label [[IF_THEN2855:%.*]], label [[IF_END2856:%.*]]
|
|
// SIMD-ONLY0: if.then2855:
|
|
// SIMD-ONLY0-NEXT: [[TMP1765:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1765]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2856]]
|
|
// SIMD-ONLY0: if.end2856:
|
|
// SIMD-ONLY0-NEXT: [[TMP1766:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2857:%.*]] = zext i16 [[TMP1766]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1767:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2858:%.*]] = zext i16 [[TMP1767]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2859:%.*]] = icmp eq i32 [[CONV2857]], [[CONV2858]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2860:%.*]] = zext i1 [[CMP2859]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2861:%.*]] = trunc i32 [[CONV2860]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2861]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1768:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2862:%.*]] = icmp ne i16 [[TMP1768]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2862]], label [[IF_THEN2863:%.*]], label [[IF_ELSE2864:%.*]]
|
|
// SIMD-ONLY0: if.then2863:
|
|
// SIMD-ONLY0-NEXT: [[TMP1769:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1769]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2865:%.*]]
|
|
// SIMD-ONLY0: if.else2864:
|
|
// SIMD-ONLY0-NEXT: [[TMP1770:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1770]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2865]]
|
|
// SIMD-ONLY0: if.end2865:
|
|
// SIMD-ONLY0-NEXT: [[TMP1771:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2866:%.*]] = zext i16 [[TMP1771]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP1772:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV2867:%.*]] = zext i16 [[TMP1772]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP2868:%.*]] = icmp eq i32 [[CONV2866]], [[CONV2867]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2869:%.*]] = zext i1 [[CMP2868]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV2870:%.*]] = trunc i32 [[CONV2869]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV2870]], ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1773:%.*]] = load i16, ptr [[USR]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2871:%.*]] = icmp ne i16 [[TMP1773]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2871]], label [[IF_THEN2872:%.*]], label [[IF_ELSE2873:%.*]]
|
|
// SIMD-ONLY0: if.then2872:
|
|
// SIMD-ONLY0-NEXT: [[TMP1774:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1774]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2874:%.*]]
|
|
// SIMD-ONLY0: if.else2873:
|
|
// SIMD-ONLY0-NEXT: [[TMP1775:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP1775]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2874]]
|
|
// SIMD-ONLY0: if.end2874:
|
|
// SIMD-ONLY0-NEXT: [[TMP1776:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1776]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1777:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1778:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2875:%.*]] = icmp sgt i32 [[TMP1777]], [[TMP1778]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2875]], label [[IF_THEN2877:%.*]], label [[IF_END2878:%.*]]
|
|
// SIMD-ONLY0: if.then2877:
|
|
// SIMD-ONLY0-NEXT: [[TMP1779:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1779]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2878]]
|
|
// SIMD-ONLY0: if.end2878:
|
|
// SIMD-ONLY0-NEXT: [[TMP1780:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1780]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1781:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1782:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2879:%.*]] = icmp sgt i32 [[TMP1781]], [[TMP1782]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2879]], label [[IF_THEN2881:%.*]], label [[IF_END2882:%.*]]
|
|
// SIMD-ONLY0: if.then2881:
|
|
// SIMD-ONLY0-NEXT: [[TMP1783:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1783]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2882]]
|
|
// SIMD-ONLY0: if.end2882:
|
|
// SIMD-ONLY0-NEXT: [[TMP1784:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1784]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1785:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1786:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2883:%.*]] = icmp slt i32 [[TMP1785]], [[TMP1786]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2883]], label [[IF_THEN2885:%.*]], label [[IF_END2886:%.*]]
|
|
// SIMD-ONLY0: if.then2885:
|
|
// SIMD-ONLY0-NEXT: [[TMP1787:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1787]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2886]]
|
|
// SIMD-ONLY0: if.end2886:
|
|
// SIMD-ONLY0-NEXT: [[TMP1788:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1788]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1789:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1790:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2887:%.*]] = icmp slt i32 [[TMP1789]], [[TMP1790]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2887]], label [[IF_THEN2889:%.*]], label [[IF_END2890:%.*]]
|
|
// SIMD-ONLY0: if.then2889:
|
|
// SIMD-ONLY0-NEXT: [[TMP1791:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1791]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2890]]
|
|
// SIMD-ONLY0: if.end2890:
|
|
// SIMD-ONLY0-NEXT: [[TMP1792:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1792]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1793:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1794:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2891:%.*]] = icmp eq i32 [[TMP1793]], [[TMP1794]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2891]], label [[IF_THEN2893:%.*]], label [[IF_END2894:%.*]]
|
|
// SIMD-ONLY0: if.then2893:
|
|
// SIMD-ONLY0-NEXT: [[TMP1795:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1795]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2894]]
|
|
// SIMD-ONLY0: if.end2894:
|
|
// SIMD-ONLY0-NEXT: [[TMP1796:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1796]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1797:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1798:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2895:%.*]] = icmp eq i32 [[TMP1797]], [[TMP1798]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2895]], label [[IF_THEN2897:%.*]], label [[IF_END2898:%.*]]
|
|
// SIMD-ONLY0: if.then2897:
|
|
// SIMD-ONLY0-NEXT: [[TMP1799:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1799]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2898]]
|
|
// SIMD-ONLY0: if.end2898:
|
|
// SIMD-ONLY0-NEXT: [[TMP1800:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1801:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2899:%.*]] = icmp sgt i32 [[TMP1800]], [[TMP1801]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2899]], label [[IF_THEN2901:%.*]], label [[IF_END2902:%.*]]
|
|
// SIMD-ONLY0: if.then2901:
|
|
// SIMD-ONLY0-NEXT: [[TMP1802:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1802]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2902]]
|
|
// SIMD-ONLY0: if.end2902:
|
|
// SIMD-ONLY0-NEXT: [[TMP1803:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1803]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1804:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1805:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2903:%.*]] = icmp sgt i32 [[TMP1804]], [[TMP1805]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2903]], label [[IF_THEN2905:%.*]], label [[IF_END2906:%.*]]
|
|
// SIMD-ONLY0: if.then2905:
|
|
// SIMD-ONLY0-NEXT: [[TMP1806:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1806]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2906]]
|
|
// SIMD-ONLY0: if.end2906:
|
|
// SIMD-ONLY0-NEXT: [[TMP1807:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1807]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1808:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1809:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2907:%.*]] = icmp slt i32 [[TMP1808]], [[TMP1809]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2907]], label [[IF_THEN2909:%.*]], label [[IF_END2910:%.*]]
|
|
// SIMD-ONLY0: if.then2909:
|
|
// SIMD-ONLY0-NEXT: [[TMP1810:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1810]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2910]]
|
|
// SIMD-ONLY0: if.end2910:
|
|
// SIMD-ONLY0-NEXT: [[TMP1811:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1811]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1812:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1813:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2911:%.*]] = icmp slt i32 [[TMP1812]], [[TMP1813]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2911]], label [[IF_THEN2913:%.*]], label [[IF_END2914:%.*]]
|
|
// SIMD-ONLY0: if.then2913:
|
|
// SIMD-ONLY0-NEXT: [[TMP1814:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1814]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2914]]
|
|
// SIMD-ONLY0: if.end2914:
|
|
// SIMD-ONLY0-NEXT: [[TMP1815:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1815]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1816:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1817:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2915:%.*]] = icmp eq i32 [[TMP1816]], [[TMP1817]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2915]], label [[IF_THEN2917:%.*]], label [[IF_END2918:%.*]]
|
|
// SIMD-ONLY0: if.then2917:
|
|
// SIMD-ONLY0-NEXT: [[TMP1818:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1818]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2918]]
|
|
// SIMD-ONLY0: if.end2918:
|
|
// SIMD-ONLY0-NEXT: [[TMP1819:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1819]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1820:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1821:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2919:%.*]] = icmp eq i32 [[TMP1820]], [[TMP1821]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2919]], label [[IF_THEN2921:%.*]], label [[IF_END2922:%.*]]
|
|
// SIMD-ONLY0: if.then2921:
|
|
// SIMD-ONLY0-NEXT: [[TMP1822:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1822]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2922]]
|
|
// SIMD-ONLY0: if.end2922:
|
|
// SIMD-ONLY0-NEXT: [[TMP1823:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1823]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1824:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1825:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2923:%.*]] = icmp eq i32 [[TMP1824]], [[TMP1825]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2923]], label [[IF_THEN2925:%.*]], label [[IF_ELSE2926:%.*]]
|
|
// SIMD-ONLY0: if.then2925:
|
|
// SIMD-ONLY0-NEXT: [[TMP1826:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1826]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2927:%.*]]
|
|
// SIMD-ONLY0: if.else2926:
|
|
// SIMD-ONLY0-NEXT: [[TMP1827:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1827]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2927]]
|
|
// SIMD-ONLY0: if.end2927:
|
|
// SIMD-ONLY0-NEXT: [[TMP1828:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1829:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2928:%.*]] = icmp eq i32 [[TMP1828]], [[TMP1829]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2928]], label [[IF_THEN2930:%.*]], label [[IF_ELSE2931:%.*]]
|
|
// SIMD-ONLY0: if.then2930:
|
|
// SIMD-ONLY0-NEXT: [[TMP1830:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1830]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2932:%.*]]
|
|
// SIMD-ONLY0: if.else2931:
|
|
// SIMD-ONLY0-NEXT: [[TMP1831:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1831]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2932]]
|
|
// SIMD-ONLY0: if.end2932:
|
|
// SIMD-ONLY0-NEXT: [[TMP1832:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1833:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2933:%.*]] = icmp eq i32 [[TMP1832]], [[TMP1833]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2934:%.*]] = zext i1 [[CMP2933]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV2934]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1834:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2935:%.*]] = icmp ne i32 [[TMP1834]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2935]], label [[IF_THEN2936:%.*]], label [[IF_END2937:%.*]]
|
|
// SIMD-ONLY0: if.then2936:
|
|
// SIMD-ONLY0-NEXT: [[TMP1835:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1835]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2937]]
|
|
// SIMD-ONLY0: if.end2937:
|
|
// SIMD-ONLY0-NEXT: [[TMP1836:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1837:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2938:%.*]] = icmp eq i32 [[TMP1836]], [[TMP1837]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2939:%.*]] = zext i1 [[CMP2938]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV2939]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1838:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2940:%.*]] = icmp ne i32 [[TMP1838]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2940]], label [[IF_THEN2941:%.*]], label [[IF_END2942:%.*]]
|
|
// SIMD-ONLY0: if.then2941:
|
|
// SIMD-ONLY0-NEXT: [[TMP1839:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1839]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2942]]
|
|
// SIMD-ONLY0: if.end2942:
|
|
// SIMD-ONLY0-NEXT: [[TMP1840:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1841:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2943:%.*]] = icmp eq i32 [[TMP1840]], [[TMP1841]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2944:%.*]] = zext i1 [[CMP2943]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV2944]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1842:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2945:%.*]] = icmp ne i32 [[TMP1842]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2945]], label [[IF_THEN2946:%.*]], label [[IF_ELSE2947:%.*]]
|
|
// SIMD-ONLY0: if.then2946:
|
|
// SIMD-ONLY0-NEXT: [[TMP1843:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1843]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2948:%.*]]
|
|
// SIMD-ONLY0: if.else2947:
|
|
// SIMD-ONLY0-NEXT: [[TMP1844:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1844]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2948]]
|
|
// SIMD-ONLY0: if.end2948:
|
|
// SIMD-ONLY0-NEXT: [[TMP1845:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1846:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2949:%.*]] = icmp eq i32 [[TMP1845]], [[TMP1846]]
|
|
// SIMD-ONLY0-NEXT: [[CONV2950:%.*]] = zext i1 [[CMP2949]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV2950]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1847:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL2951:%.*]] = icmp ne i32 [[TMP1847]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL2951]], label [[IF_THEN2952:%.*]], label [[IF_ELSE2953:%.*]]
|
|
// SIMD-ONLY0: if.then2952:
|
|
// SIMD-ONLY0-NEXT: [[TMP1848:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1848]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2954:%.*]]
|
|
// SIMD-ONLY0: if.else2953:
|
|
// SIMD-ONLY0-NEXT: [[TMP1849:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1849]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2954]]
|
|
// SIMD-ONLY0: if.end2954:
|
|
// SIMD-ONLY0-NEXT: [[TMP1850:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1850]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1851:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1852:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2955:%.*]] = icmp sgt i32 [[TMP1851]], [[TMP1852]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2955]], label [[IF_THEN2957:%.*]], label [[IF_END2958:%.*]]
|
|
// SIMD-ONLY0: if.then2957:
|
|
// SIMD-ONLY0-NEXT: [[TMP1853:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1853]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2958]]
|
|
// SIMD-ONLY0: if.end2958:
|
|
// SIMD-ONLY0-NEXT: [[TMP1854:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1854]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1855:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1856:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2959:%.*]] = icmp sgt i32 [[TMP1855]], [[TMP1856]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2959]], label [[IF_THEN2961:%.*]], label [[IF_END2962:%.*]]
|
|
// SIMD-ONLY0: if.then2961:
|
|
// SIMD-ONLY0-NEXT: [[TMP1857:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1857]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2962]]
|
|
// SIMD-ONLY0: if.end2962:
|
|
// SIMD-ONLY0-NEXT: [[TMP1858:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1858]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1859:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1860:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2963:%.*]] = icmp slt i32 [[TMP1859]], [[TMP1860]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2963]], label [[IF_THEN2965:%.*]], label [[IF_END2966:%.*]]
|
|
// SIMD-ONLY0: if.then2965:
|
|
// SIMD-ONLY0-NEXT: [[TMP1861:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1861]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2966]]
|
|
// SIMD-ONLY0: if.end2966:
|
|
// SIMD-ONLY0-NEXT: [[TMP1862:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1862]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1863:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1864:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2967:%.*]] = icmp slt i32 [[TMP1863]], [[TMP1864]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2967]], label [[IF_THEN2969:%.*]], label [[IF_END2970:%.*]]
|
|
// SIMD-ONLY0: if.then2969:
|
|
// SIMD-ONLY0-NEXT: [[TMP1865:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1865]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2970]]
|
|
// SIMD-ONLY0: if.end2970:
|
|
// SIMD-ONLY0-NEXT: [[TMP1866:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1866]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1867:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1868:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2971:%.*]] = icmp eq i32 [[TMP1867]], [[TMP1868]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2971]], label [[IF_THEN2973:%.*]], label [[IF_END2974:%.*]]
|
|
// SIMD-ONLY0: if.then2973:
|
|
// SIMD-ONLY0-NEXT: [[TMP1869:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1869]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2974]]
|
|
// SIMD-ONLY0: if.end2974:
|
|
// SIMD-ONLY0-NEXT: [[TMP1870:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1870]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1871:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1872:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2975:%.*]] = icmp eq i32 [[TMP1871]], [[TMP1872]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2975]], label [[IF_THEN2977:%.*]], label [[IF_END2978:%.*]]
|
|
// SIMD-ONLY0: if.then2977:
|
|
// SIMD-ONLY0-NEXT: [[TMP1873:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1873]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2978]]
|
|
// SIMD-ONLY0: if.end2978:
|
|
// SIMD-ONLY0-NEXT: [[TMP1874:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1875:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2979:%.*]] = icmp sgt i32 [[TMP1874]], [[TMP1875]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2979]], label [[IF_THEN2981:%.*]], label [[IF_END2982:%.*]]
|
|
// SIMD-ONLY0: if.then2981:
|
|
// SIMD-ONLY0-NEXT: [[TMP1876:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1876]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2982]]
|
|
// SIMD-ONLY0: if.end2982:
|
|
// SIMD-ONLY0-NEXT: [[TMP1877:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1877]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1878:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1879:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2983:%.*]] = icmp sgt i32 [[TMP1878]], [[TMP1879]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2983]], label [[IF_THEN2985:%.*]], label [[IF_END2986:%.*]]
|
|
// SIMD-ONLY0: if.then2985:
|
|
// SIMD-ONLY0-NEXT: [[TMP1880:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1880]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2986]]
|
|
// SIMD-ONLY0: if.end2986:
|
|
// SIMD-ONLY0-NEXT: [[TMP1881:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1881]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1882:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1883:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2987:%.*]] = icmp slt i32 [[TMP1882]], [[TMP1883]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2987]], label [[IF_THEN2989:%.*]], label [[IF_END2990:%.*]]
|
|
// SIMD-ONLY0: if.then2989:
|
|
// SIMD-ONLY0-NEXT: [[TMP1884:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1884]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2990]]
|
|
// SIMD-ONLY0: if.end2990:
|
|
// SIMD-ONLY0-NEXT: [[TMP1885:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1885]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1886:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1887:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2991:%.*]] = icmp slt i32 [[TMP1886]], [[TMP1887]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2991]], label [[IF_THEN2993:%.*]], label [[IF_END2994:%.*]]
|
|
// SIMD-ONLY0: if.then2993:
|
|
// SIMD-ONLY0-NEXT: [[TMP1888:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1888]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2994]]
|
|
// SIMD-ONLY0: if.end2994:
|
|
// SIMD-ONLY0-NEXT: [[TMP1889:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1889]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1890:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1891:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2995:%.*]] = icmp eq i32 [[TMP1890]], [[TMP1891]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2995]], label [[IF_THEN2997:%.*]], label [[IF_END2998:%.*]]
|
|
// SIMD-ONLY0: if.then2997:
|
|
// SIMD-ONLY0-NEXT: [[TMP1892:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1892]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END2998]]
|
|
// SIMD-ONLY0: if.end2998:
|
|
// SIMD-ONLY0-NEXT: [[TMP1893:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1893]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1894:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1895:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP2999:%.*]] = icmp eq i32 [[TMP1894]], [[TMP1895]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP2999]], label [[IF_THEN3001:%.*]], label [[IF_END3002:%.*]]
|
|
// SIMD-ONLY0: if.then3001:
|
|
// SIMD-ONLY0-NEXT: [[TMP1896:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1896]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3002]]
|
|
// SIMD-ONLY0: if.end3002:
|
|
// SIMD-ONLY0-NEXT: [[TMP1897:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1897]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1898:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1899:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3003:%.*]] = icmp eq i32 [[TMP1898]], [[TMP1899]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3003]], label [[IF_THEN3005:%.*]], label [[IF_ELSE3006:%.*]]
|
|
// SIMD-ONLY0: if.then3005:
|
|
// SIMD-ONLY0-NEXT: [[TMP1900:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1900]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3007:%.*]]
|
|
// SIMD-ONLY0: if.else3006:
|
|
// SIMD-ONLY0-NEXT: [[TMP1901:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1901]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3007]]
|
|
// SIMD-ONLY0: if.end3007:
|
|
// SIMD-ONLY0-NEXT: [[TMP1902:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1903:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3008:%.*]] = icmp eq i32 [[TMP1902]], [[TMP1903]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3008]], label [[IF_THEN3010:%.*]], label [[IF_ELSE3011:%.*]]
|
|
// SIMD-ONLY0: if.then3010:
|
|
// SIMD-ONLY0-NEXT: [[TMP1904:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1904]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3012:%.*]]
|
|
// SIMD-ONLY0: if.else3011:
|
|
// SIMD-ONLY0-NEXT: [[TMP1905:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1905]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3012]]
|
|
// SIMD-ONLY0: if.end3012:
|
|
// SIMD-ONLY0-NEXT: [[TMP1906:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1907:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3013:%.*]] = icmp eq i32 [[TMP1906]], [[TMP1907]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3014:%.*]] = zext i1 [[CMP3013]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3014]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1908:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3015:%.*]] = icmp ne i32 [[TMP1908]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3015]], label [[IF_THEN3016:%.*]], label [[IF_END3017:%.*]]
|
|
// SIMD-ONLY0: if.then3016:
|
|
// SIMD-ONLY0-NEXT: [[TMP1909:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1909]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3017]]
|
|
// SIMD-ONLY0: if.end3017:
|
|
// SIMD-ONLY0-NEXT: [[TMP1910:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1911:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3018:%.*]] = icmp eq i32 [[TMP1910]], [[TMP1911]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3019:%.*]] = zext i1 [[CMP3018]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3019]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1912:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3020:%.*]] = icmp ne i32 [[TMP1912]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3020]], label [[IF_THEN3021:%.*]], label [[IF_END3022:%.*]]
|
|
// SIMD-ONLY0: if.then3021:
|
|
// SIMD-ONLY0-NEXT: [[TMP1913:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1913]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3022]]
|
|
// SIMD-ONLY0: if.end3022:
|
|
// SIMD-ONLY0-NEXT: [[TMP1914:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1915:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3023:%.*]] = icmp eq i32 [[TMP1914]], [[TMP1915]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3024:%.*]] = zext i1 [[CMP3023]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3024]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1916:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3025:%.*]] = icmp ne i32 [[TMP1916]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3025]], label [[IF_THEN3026:%.*]], label [[IF_ELSE3027:%.*]]
|
|
// SIMD-ONLY0: if.then3026:
|
|
// SIMD-ONLY0-NEXT: [[TMP1917:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1917]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3028:%.*]]
|
|
// SIMD-ONLY0: if.else3027:
|
|
// SIMD-ONLY0-NEXT: [[TMP1918:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1918]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3028]]
|
|
// SIMD-ONLY0: if.end3028:
|
|
// SIMD-ONLY0-NEXT: [[TMP1919:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1920:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3029:%.*]] = icmp eq i32 [[TMP1919]], [[TMP1920]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3030:%.*]] = zext i1 [[CMP3029]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3030]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1921:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3031:%.*]] = icmp ne i32 [[TMP1921]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3031]], label [[IF_THEN3032:%.*]], label [[IF_ELSE3033:%.*]]
|
|
// SIMD-ONLY0: if.then3032:
|
|
// SIMD-ONLY0-NEXT: [[TMP1922:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1922]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3034:%.*]]
|
|
// SIMD-ONLY0: if.else3033:
|
|
// SIMD-ONLY0-NEXT: [[TMP1923:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1923]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3034]]
|
|
// SIMD-ONLY0: if.end3034:
|
|
// SIMD-ONLY0-NEXT: [[TMP1924:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1924]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1925:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1926:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3035:%.*]] = icmp sgt i32 [[TMP1925]], [[TMP1926]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3035]], label [[IF_THEN3037:%.*]], label [[IF_END3038:%.*]]
|
|
// SIMD-ONLY0: if.then3037:
|
|
// SIMD-ONLY0-NEXT: [[TMP1927:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1927]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3038]]
|
|
// SIMD-ONLY0: if.end3038:
|
|
// SIMD-ONLY0-NEXT: [[TMP1928:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1928]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1929:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1930:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3039:%.*]] = icmp sgt i32 [[TMP1929]], [[TMP1930]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3039]], label [[IF_THEN3041:%.*]], label [[IF_END3042:%.*]]
|
|
// SIMD-ONLY0: if.then3041:
|
|
// SIMD-ONLY0-NEXT: [[TMP1931:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1931]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3042]]
|
|
// SIMD-ONLY0: if.end3042:
|
|
// SIMD-ONLY0-NEXT: [[TMP1932:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1932]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1933:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1934:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3043:%.*]] = icmp slt i32 [[TMP1933]], [[TMP1934]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3043]], label [[IF_THEN3045:%.*]], label [[IF_END3046:%.*]]
|
|
// SIMD-ONLY0: if.then3045:
|
|
// SIMD-ONLY0-NEXT: [[TMP1935:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1935]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3046]]
|
|
// SIMD-ONLY0: if.end3046:
|
|
// SIMD-ONLY0-NEXT: [[TMP1936:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1936]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1937:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1938:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3047:%.*]] = icmp slt i32 [[TMP1937]], [[TMP1938]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3047]], label [[IF_THEN3049:%.*]], label [[IF_END3050:%.*]]
|
|
// SIMD-ONLY0: if.then3049:
|
|
// SIMD-ONLY0-NEXT: [[TMP1939:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1939]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3050]]
|
|
// SIMD-ONLY0: if.end3050:
|
|
// SIMD-ONLY0-NEXT: [[TMP1940:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1940]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1941:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1942:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3051:%.*]] = icmp eq i32 [[TMP1941]], [[TMP1942]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3051]], label [[IF_THEN3053:%.*]], label [[IF_END3054:%.*]]
|
|
// SIMD-ONLY0: if.then3053:
|
|
// SIMD-ONLY0-NEXT: [[TMP1943:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1943]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3054]]
|
|
// SIMD-ONLY0: if.end3054:
|
|
// SIMD-ONLY0-NEXT: [[TMP1944:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1944]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1945:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1946:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3055:%.*]] = icmp eq i32 [[TMP1945]], [[TMP1946]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3055]], label [[IF_THEN3057:%.*]], label [[IF_END3058:%.*]]
|
|
// SIMD-ONLY0: if.then3057:
|
|
// SIMD-ONLY0-NEXT: [[TMP1947:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1947]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3058]]
|
|
// SIMD-ONLY0: if.end3058:
|
|
// SIMD-ONLY0-NEXT: [[TMP1948:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1949:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3059:%.*]] = icmp sgt i32 [[TMP1948]], [[TMP1949]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3059]], label [[IF_THEN3061:%.*]], label [[IF_END3062:%.*]]
|
|
// SIMD-ONLY0: if.then3061:
|
|
// SIMD-ONLY0-NEXT: [[TMP1950:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1950]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3062]]
|
|
// SIMD-ONLY0: if.end3062:
|
|
// SIMD-ONLY0-NEXT: [[TMP1951:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1951]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1952:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1953:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3063:%.*]] = icmp sgt i32 [[TMP1952]], [[TMP1953]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3063]], label [[IF_THEN3065:%.*]], label [[IF_END3066:%.*]]
|
|
// SIMD-ONLY0: if.then3065:
|
|
// SIMD-ONLY0-NEXT: [[TMP1954:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1954]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3066]]
|
|
// SIMD-ONLY0: if.end3066:
|
|
// SIMD-ONLY0-NEXT: [[TMP1955:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1955]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1956:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1957:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3067:%.*]] = icmp slt i32 [[TMP1956]], [[TMP1957]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3067]], label [[IF_THEN3069:%.*]], label [[IF_END3070:%.*]]
|
|
// SIMD-ONLY0: if.then3069:
|
|
// SIMD-ONLY0-NEXT: [[TMP1958:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1958]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3070]]
|
|
// SIMD-ONLY0: if.end3070:
|
|
// SIMD-ONLY0-NEXT: [[TMP1959:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1959]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1960:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1961:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3071:%.*]] = icmp slt i32 [[TMP1960]], [[TMP1961]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3071]], label [[IF_THEN3073:%.*]], label [[IF_END3074:%.*]]
|
|
// SIMD-ONLY0: if.then3073:
|
|
// SIMD-ONLY0-NEXT: [[TMP1962:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1962]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3074]]
|
|
// SIMD-ONLY0: if.end3074:
|
|
// SIMD-ONLY0-NEXT: [[TMP1963:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1963]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1964:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1965:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3075:%.*]] = icmp eq i32 [[TMP1964]], [[TMP1965]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3075]], label [[IF_THEN3077:%.*]], label [[IF_END3078:%.*]]
|
|
// SIMD-ONLY0: if.then3077:
|
|
// SIMD-ONLY0-NEXT: [[TMP1966:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1966]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3078]]
|
|
// SIMD-ONLY0: if.end3078:
|
|
// SIMD-ONLY0-NEXT: [[TMP1967:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1967]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1968:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1969:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3079:%.*]] = icmp eq i32 [[TMP1968]], [[TMP1969]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3079]], label [[IF_THEN3081:%.*]], label [[IF_END3082:%.*]]
|
|
// SIMD-ONLY0: if.then3081:
|
|
// SIMD-ONLY0-NEXT: [[TMP1970:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1970]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3082]]
|
|
// SIMD-ONLY0: if.end3082:
|
|
// SIMD-ONLY0-NEXT: [[TMP1971:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1971]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1972:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1973:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3083:%.*]] = icmp eq i32 [[TMP1972]], [[TMP1973]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3083]], label [[IF_THEN3085:%.*]], label [[IF_ELSE3086:%.*]]
|
|
// SIMD-ONLY0: if.then3085:
|
|
// SIMD-ONLY0-NEXT: [[TMP1974:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1974]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3087:%.*]]
|
|
// SIMD-ONLY0: if.else3086:
|
|
// SIMD-ONLY0-NEXT: [[TMP1975:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1975]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3087]]
|
|
// SIMD-ONLY0: if.end3087:
|
|
// SIMD-ONLY0-NEXT: [[TMP1976:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1977:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3088:%.*]] = icmp eq i32 [[TMP1976]], [[TMP1977]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3088]], label [[IF_THEN3090:%.*]], label [[IF_ELSE3091:%.*]]
|
|
// SIMD-ONLY0: if.then3090:
|
|
// SIMD-ONLY0-NEXT: [[TMP1978:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1978]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3092:%.*]]
|
|
// SIMD-ONLY0: if.else3091:
|
|
// SIMD-ONLY0-NEXT: [[TMP1979:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1979]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3092]]
|
|
// SIMD-ONLY0: if.end3092:
|
|
// SIMD-ONLY0-NEXT: [[TMP1980:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1981:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3093:%.*]] = icmp eq i32 [[TMP1980]], [[TMP1981]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3094:%.*]] = zext i1 [[CMP3093]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3094]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1982:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3095:%.*]] = icmp ne i32 [[TMP1982]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3095]], label [[IF_THEN3096:%.*]], label [[IF_END3097:%.*]]
|
|
// SIMD-ONLY0: if.then3096:
|
|
// SIMD-ONLY0-NEXT: [[TMP1983:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1983]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3097]]
|
|
// SIMD-ONLY0: if.end3097:
|
|
// SIMD-ONLY0-NEXT: [[TMP1984:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1985:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3098:%.*]] = icmp eq i32 [[TMP1984]], [[TMP1985]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3099:%.*]] = zext i1 [[CMP3098]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3099]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1986:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3100:%.*]] = icmp ne i32 [[TMP1986]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3100]], label [[IF_THEN3101:%.*]], label [[IF_END3102:%.*]]
|
|
// SIMD-ONLY0: if.then3101:
|
|
// SIMD-ONLY0-NEXT: [[TMP1987:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1987]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3102]]
|
|
// SIMD-ONLY0: if.end3102:
|
|
// SIMD-ONLY0-NEXT: [[TMP1988:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1989:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3103:%.*]] = icmp eq i32 [[TMP1988]], [[TMP1989]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3104:%.*]] = zext i1 [[CMP3103]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3104]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1990:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3105:%.*]] = icmp ne i32 [[TMP1990]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3105]], label [[IF_THEN3106:%.*]], label [[IF_ELSE3107:%.*]]
|
|
// SIMD-ONLY0: if.then3106:
|
|
// SIMD-ONLY0-NEXT: [[TMP1991:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1991]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3108:%.*]]
|
|
// SIMD-ONLY0: if.else3107:
|
|
// SIMD-ONLY0-NEXT: [[TMP1992:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1992]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3108]]
|
|
// SIMD-ONLY0: if.end3108:
|
|
// SIMD-ONLY0-NEXT: [[TMP1993:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1994:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3109:%.*]] = icmp eq i32 [[TMP1993]], [[TMP1994]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3110:%.*]] = zext i1 [[CMP3109]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3110]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1995:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3111:%.*]] = icmp ne i32 [[TMP1995]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3111]], label [[IF_THEN3112:%.*]], label [[IF_ELSE3113:%.*]]
|
|
// SIMD-ONLY0: if.then3112:
|
|
// SIMD-ONLY0-NEXT: [[TMP1996:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1996]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3114:%.*]]
|
|
// SIMD-ONLY0: if.else3113:
|
|
// SIMD-ONLY0-NEXT: [[TMP1997:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1997]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3114]]
|
|
// SIMD-ONLY0: if.end3114:
|
|
// SIMD-ONLY0-NEXT: [[TMP1998:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP1998]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1999:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2000:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3115:%.*]] = icmp sgt i32 [[TMP1999]], [[TMP2000]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3115]], label [[IF_THEN3117:%.*]], label [[IF_END3118:%.*]]
|
|
// SIMD-ONLY0: if.then3117:
|
|
// SIMD-ONLY0-NEXT: [[TMP2001:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2001]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3118]]
|
|
// SIMD-ONLY0: if.end3118:
|
|
// SIMD-ONLY0-NEXT: [[TMP2002:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2002]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2003:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2004:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3119:%.*]] = icmp sgt i32 [[TMP2003]], [[TMP2004]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3119]], label [[IF_THEN3121:%.*]], label [[IF_END3122:%.*]]
|
|
// SIMD-ONLY0: if.then3121:
|
|
// SIMD-ONLY0-NEXT: [[TMP2005:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2005]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3122]]
|
|
// SIMD-ONLY0: if.end3122:
|
|
// SIMD-ONLY0-NEXT: [[TMP2006:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2006]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2007:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2008:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3123:%.*]] = icmp slt i32 [[TMP2007]], [[TMP2008]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3123]], label [[IF_THEN3125:%.*]], label [[IF_END3126:%.*]]
|
|
// SIMD-ONLY0: if.then3125:
|
|
// SIMD-ONLY0-NEXT: [[TMP2009:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2009]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3126]]
|
|
// SIMD-ONLY0: if.end3126:
|
|
// SIMD-ONLY0-NEXT: [[TMP2010:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2010]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2011:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2012:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3127:%.*]] = icmp slt i32 [[TMP2011]], [[TMP2012]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3127]], label [[IF_THEN3129:%.*]], label [[IF_END3130:%.*]]
|
|
// SIMD-ONLY0: if.then3129:
|
|
// SIMD-ONLY0-NEXT: [[TMP2013:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2013]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3130]]
|
|
// SIMD-ONLY0: if.end3130:
|
|
// SIMD-ONLY0-NEXT: [[TMP2014:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2014]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2015:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2016:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3131:%.*]] = icmp eq i32 [[TMP2015]], [[TMP2016]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3131]], label [[IF_THEN3133:%.*]], label [[IF_END3134:%.*]]
|
|
// SIMD-ONLY0: if.then3133:
|
|
// SIMD-ONLY0-NEXT: [[TMP2017:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2017]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3134]]
|
|
// SIMD-ONLY0: if.end3134:
|
|
// SIMD-ONLY0-NEXT: [[TMP2018:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2018]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2019:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2020:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3135:%.*]] = icmp eq i32 [[TMP2019]], [[TMP2020]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3135]], label [[IF_THEN3137:%.*]], label [[IF_END3138:%.*]]
|
|
// SIMD-ONLY0: if.then3137:
|
|
// SIMD-ONLY0-NEXT: [[TMP2021:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2021]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3138]]
|
|
// SIMD-ONLY0: if.end3138:
|
|
// SIMD-ONLY0-NEXT: [[TMP2022:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2023:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3139:%.*]] = icmp sgt i32 [[TMP2022]], [[TMP2023]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3139]], label [[IF_THEN3141:%.*]], label [[IF_END3142:%.*]]
|
|
// SIMD-ONLY0: if.then3141:
|
|
// SIMD-ONLY0-NEXT: [[TMP2024:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2024]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3142]]
|
|
// SIMD-ONLY0: if.end3142:
|
|
// SIMD-ONLY0-NEXT: [[TMP2025:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2025]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2026:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2027:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3143:%.*]] = icmp sgt i32 [[TMP2026]], [[TMP2027]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3143]], label [[IF_THEN3145:%.*]], label [[IF_END3146:%.*]]
|
|
// SIMD-ONLY0: if.then3145:
|
|
// SIMD-ONLY0-NEXT: [[TMP2028:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2028]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3146]]
|
|
// SIMD-ONLY0: if.end3146:
|
|
// SIMD-ONLY0-NEXT: [[TMP2029:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2029]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2030:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2031:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3147:%.*]] = icmp slt i32 [[TMP2030]], [[TMP2031]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3147]], label [[IF_THEN3149:%.*]], label [[IF_END3150:%.*]]
|
|
// SIMD-ONLY0: if.then3149:
|
|
// SIMD-ONLY0-NEXT: [[TMP2032:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2032]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3150]]
|
|
// SIMD-ONLY0: if.end3150:
|
|
// SIMD-ONLY0-NEXT: [[TMP2033:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2033]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2034:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2035:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3151:%.*]] = icmp slt i32 [[TMP2034]], [[TMP2035]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3151]], label [[IF_THEN3153:%.*]], label [[IF_END3154:%.*]]
|
|
// SIMD-ONLY0: if.then3153:
|
|
// SIMD-ONLY0-NEXT: [[TMP2036:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2036]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3154]]
|
|
// SIMD-ONLY0: if.end3154:
|
|
// SIMD-ONLY0-NEXT: [[TMP2037:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2037]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2038:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2039:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3155:%.*]] = icmp eq i32 [[TMP2038]], [[TMP2039]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3155]], label [[IF_THEN3157:%.*]], label [[IF_END3158:%.*]]
|
|
// SIMD-ONLY0: if.then3157:
|
|
// SIMD-ONLY0-NEXT: [[TMP2040:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2040]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3158]]
|
|
// SIMD-ONLY0: if.end3158:
|
|
// SIMD-ONLY0-NEXT: [[TMP2041:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2041]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2042:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2043:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3159:%.*]] = icmp eq i32 [[TMP2042]], [[TMP2043]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3159]], label [[IF_THEN3161:%.*]], label [[IF_END3162:%.*]]
|
|
// SIMD-ONLY0: if.then3161:
|
|
// SIMD-ONLY0-NEXT: [[TMP2044:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2044]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3162]]
|
|
// SIMD-ONLY0: if.end3162:
|
|
// SIMD-ONLY0-NEXT: [[TMP2045:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2045]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2046:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2047:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3163:%.*]] = icmp eq i32 [[TMP2046]], [[TMP2047]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3163]], label [[IF_THEN3165:%.*]], label [[IF_ELSE3166:%.*]]
|
|
// SIMD-ONLY0: if.then3165:
|
|
// SIMD-ONLY0-NEXT: [[TMP2048:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2048]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3167:%.*]]
|
|
// SIMD-ONLY0: if.else3166:
|
|
// SIMD-ONLY0-NEXT: [[TMP2049:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2049]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3167]]
|
|
// SIMD-ONLY0: if.end3167:
|
|
// SIMD-ONLY0-NEXT: [[TMP2050:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2051:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3168:%.*]] = icmp eq i32 [[TMP2050]], [[TMP2051]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3168]], label [[IF_THEN3170:%.*]], label [[IF_ELSE3171:%.*]]
|
|
// SIMD-ONLY0: if.then3170:
|
|
// SIMD-ONLY0-NEXT: [[TMP2052:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2052]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3172:%.*]]
|
|
// SIMD-ONLY0: if.else3171:
|
|
// SIMD-ONLY0-NEXT: [[TMP2053:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2053]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3172]]
|
|
// SIMD-ONLY0: if.end3172:
|
|
// SIMD-ONLY0-NEXT: [[TMP2054:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2055:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3173:%.*]] = icmp eq i32 [[TMP2054]], [[TMP2055]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3174:%.*]] = zext i1 [[CMP3173]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3174]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2056:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3175:%.*]] = icmp ne i32 [[TMP2056]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3175]], label [[IF_THEN3176:%.*]], label [[IF_END3177:%.*]]
|
|
// SIMD-ONLY0: if.then3176:
|
|
// SIMD-ONLY0-NEXT: [[TMP2057:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2057]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3177]]
|
|
// SIMD-ONLY0: if.end3177:
|
|
// SIMD-ONLY0-NEXT: [[TMP2058:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2059:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3178:%.*]] = icmp eq i32 [[TMP2058]], [[TMP2059]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3179:%.*]] = zext i1 [[CMP3178]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3179]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2060:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3180:%.*]] = icmp ne i32 [[TMP2060]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3180]], label [[IF_THEN3181:%.*]], label [[IF_END3182:%.*]]
|
|
// SIMD-ONLY0: if.then3181:
|
|
// SIMD-ONLY0-NEXT: [[TMP2061:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2061]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3182]]
|
|
// SIMD-ONLY0: if.end3182:
|
|
// SIMD-ONLY0-NEXT: [[TMP2062:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2063:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3183:%.*]] = icmp eq i32 [[TMP2062]], [[TMP2063]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3184:%.*]] = zext i1 [[CMP3183]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3184]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2064:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3185:%.*]] = icmp ne i32 [[TMP2064]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3185]], label [[IF_THEN3186:%.*]], label [[IF_ELSE3187:%.*]]
|
|
// SIMD-ONLY0: if.then3186:
|
|
// SIMD-ONLY0-NEXT: [[TMP2065:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2065]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3188:%.*]]
|
|
// SIMD-ONLY0: if.else3187:
|
|
// SIMD-ONLY0-NEXT: [[TMP2066:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2066]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3188]]
|
|
// SIMD-ONLY0: if.end3188:
|
|
// SIMD-ONLY0-NEXT: [[TMP2067:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2068:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3189:%.*]] = icmp eq i32 [[TMP2067]], [[TMP2068]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3190:%.*]] = zext i1 [[CMP3189]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3190]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2069:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3191:%.*]] = icmp ne i32 [[TMP2069]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3191]], label [[IF_THEN3192:%.*]], label [[IF_ELSE3193:%.*]]
|
|
// SIMD-ONLY0: if.then3192:
|
|
// SIMD-ONLY0-NEXT: [[TMP2070:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2070]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3194:%.*]]
|
|
// SIMD-ONLY0: if.else3193:
|
|
// SIMD-ONLY0-NEXT: [[TMP2071:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2071]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3194]]
|
|
// SIMD-ONLY0: if.end3194:
|
|
// SIMD-ONLY0-NEXT: [[TMP2072:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2072]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2073:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2074:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3195:%.*]] = icmp sgt i32 [[TMP2073]], [[TMP2074]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3195]], label [[IF_THEN3197:%.*]], label [[IF_END3198:%.*]]
|
|
// SIMD-ONLY0: if.then3197:
|
|
// SIMD-ONLY0-NEXT: [[TMP2075:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2075]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3198]]
|
|
// SIMD-ONLY0: if.end3198:
|
|
// SIMD-ONLY0-NEXT: [[TMP2076:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2076]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2077:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2078:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3199:%.*]] = icmp sgt i32 [[TMP2077]], [[TMP2078]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3199]], label [[IF_THEN3201:%.*]], label [[IF_END3202:%.*]]
|
|
// SIMD-ONLY0: if.then3201:
|
|
// SIMD-ONLY0-NEXT: [[TMP2079:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2079]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3202]]
|
|
// SIMD-ONLY0: if.end3202:
|
|
// SIMD-ONLY0-NEXT: [[TMP2080:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2080]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2081:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2082:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3203:%.*]] = icmp slt i32 [[TMP2081]], [[TMP2082]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3203]], label [[IF_THEN3205:%.*]], label [[IF_END3206:%.*]]
|
|
// SIMD-ONLY0: if.then3205:
|
|
// SIMD-ONLY0-NEXT: [[TMP2083:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2083]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3206]]
|
|
// SIMD-ONLY0: if.end3206:
|
|
// SIMD-ONLY0-NEXT: [[TMP2084:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2084]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2085:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2086:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3207:%.*]] = icmp slt i32 [[TMP2085]], [[TMP2086]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3207]], label [[IF_THEN3209:%.*]], label [[IF_END3210:%.*]]
|
|
// SIMD-ONLY0: if.then3209:
|
|
// SIMD-ONLY0-NEXT: [[TMP2087:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2087]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3210]]
|
|
// SIMD-ONLY0: if.end3210:
|
|
// SIMD-ONLY0-NEXT: [[TMP2088:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2088]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2089:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2090:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3211:%.*]] = icmp eq i32 [[TMP2089]], [[TMP2090]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3211]], label [[IF_THEN3213:%.*]], label [[IF_END3214:%.*]]
|
|
// SIMD-ONLY0: if.then3213:
|
|
// SIMD-ONLY0-NEXT: [[TMP2091:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2091]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3214]]
|
|
// SIMD-ONLY0: if.end3214:
|
|
// SIMD-ONLY0-NEXT: [[TMP2092:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2092]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2093:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2094:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3215:%.*]] = icmp eq i32 [[TMP2093]], [[TMP2094]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3215]], label [[IF_THEN3217:%.*]], label [[IF_END3218:%.*]]
|
|
// SIMD-ONLY0: if.then3217:
|
|
// SIMD-ONLY0-NEXT: [[TMP2095:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2095]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3218]]
|
|
// SIMD-ONLY0: if.end3218:
|
|
// SIMD-ONLY0-NEXT: [[TMP2096:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2097:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3219:%.*]] = icmp sgt i32 [[TMP2096]], [[TMP2097]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3219]], label [[IF_THEN3221:%.*]], label [[IF_END3222:%.*]]
|
|
// SIMD-ONLY0: if.then3221:
|
|
// SIMD-ONLY0-NEXT: [[TMP2098:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2098]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3222]]
|
|
// SIMD-ONLY0: if.end3222:
|
|
// SIMD-ONLY0-NEXT: [[TMP2099:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2099]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2100:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2101:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3223:%.*]] = icmp sgt i32 [[TMP2100]], [[TMP2101]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3223]], label [[IF_THEN3225:%.*]], label [[IF_END3226:%.*]]
|
|
// SIMD-ONLY0: if.then3225:
|
|
// SIMD-ONLY0-NEXT: [[TMP2102:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2102]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3226]]
|
|
// SIMD-ONLY0: if.end3226:
|
|
// SIMD-ONLY0-NEXT: [[TMP2103:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2103]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2104:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2105:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3227:%.*]] = icmp slt i32 [[TMP2104]], [[TMP2105]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3227]], label [[IF_THEN3229:%.*]], label [[IF_END3230:%.*]]
|
|
// SIMD-ONLY0: if.then3229:
|
|
// SIMD-ONLY0-NEXT: [[TMP2106:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2106]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3230]]
|
|
// SIMD-ONLY0: if.end3230:
|
|
// SIMD-ONLY0-NEXT: [[TMP2107:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2107]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2108:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2109:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3231:%.*]] = icmp slt i32 [[TMP2108]], [[TMP2109]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3231]], label [[IF_THEN3233:%.*]], label [[IF_END3234:%.*]]
|
|
// SIMD-ONLY0: if.then3233:
|
|
// SIMD-ONLY0-NEXT: [[TMP2110:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2110]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3234]]
|
|
// SIMD-ONLY0: if.end3234:
|
|
// SIMD-ONLY0-NEXT: [[TMP2111:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2111]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2112:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2113:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3235:%.*]] = icmp eq i32 [[TMP2112]], [[TMP2113]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3235]], label [[IF_THEN3237:%.*]], label [[IF_END3238:%.*]]
|
|
// SIMD-ONLY0: if.then3237:
|
|
// SIMD-ONLY0-NEXT: [[TMP2114:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2114]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3238]]
|
|
// SIMD-ONLY0: if.end3238:
|
|
// SIMD-ONLY0-NEXT: [[TMP2115:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2115]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2116:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2117:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3239:%.*]] = icmp eq i32 [[TMP2116]], [[TMP2117]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3239]], label [[IF_THEN3241:%.*]], label [[IF_END3242:%.*]]
|
|
// SIMD-ONLY0: if.then3241:
|
|
// SIMD-ONLY0-NEXT: [[TMP2118:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2118]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3242]]
|
|
// SIMD-ONLY0: if.end3242:
|
|
// SIMD-ONLY0-NEXT: [[TMP2119:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2119]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2120:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2121:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3243:%.*]] = icmp eq i32 [[TMP2120]], [[TMP2121]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3243]], label [[IF_THEN3245:%.*]], label [[IF_ELSE3246:%.*]]
|
|
// SIMD-ONLY0: if.then3245:
|
|
// SIMD-ONLY0-NEXT: [[TMP2122:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2122]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3247:%.*]]
|
|
// SIMD-ONLY0: if.else3246:
|
|
// SIMD-ONLY0-NEXT: [[TMP2123:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2123]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3247]]
|
|
// SIMD-ONLY0: if.end3247:
|
|
// SIMD-ONLY0-NEXT: [[TMP2124:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2125:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3248:%.*]] = icmp eq i32 [[TMP2124]], [[TMP2125]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3248]], label [[IF_THEN3250:%.*]], label [[IF_ELSE3251:%.*]]
|
|
// SIMD-ONLY0: if.then3250:
|
|
// SIMD-ONLY0-NEXT: [[TMP2126:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2126]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3252:%.*]]
|
|
// SIMD-ONLY0: if.else3251:
|
|
// SIMD-ONLY0-NEXT: [[TMP2127:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2127]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3252]]
|
|
// SIMD-ONLY0: if.end3252:
|
|
// SIMD-ONLY0-NEXT: [[TMP2128:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2129:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3253:%.*]] = icmp eq i32 [[TMP2128]], [[TMP2129]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3254:%.*]] = zext i1 [[CMP3253]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3254]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2130:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3255:%.*]] = icmp ne i32 [[TMP2130]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3255]], label [[IF_THEN3256:%.*]], label [[IF_END3257:%.*]]
|
|
// SIMD-ONLY0: if.then3256:
|
|
// SIMD-ONLY0-NEXT: [[TMP2131:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2131]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3257]]
|
|
// SIMD-ONLY0: if.end3257:
|
|
// SIMD-ONLY0-NEXT: [[TMP2132:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2133:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3258:%.*]] = icmp eq i32 [[TMP2132]], [[TMP2133]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3259:%.*]] = zext i1 [[CMP3258]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3259]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2134:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3260:%.*]] = icmp ne i32 [[TMP2134]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3260]], label [[IF_THEN3261:%.*]], label [[IF_END3262:%.*]]
|
|
// SIMD-ONLY0: if.then3261:
|
|
// SIMD-ONLY0-NEXT: [[TMP2135:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2135]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3262]]
|
|
// SIMD-ONLY0: if.end3262:
|
|
// SIMD-ONLY0-NEXT: [[TMP2136:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2137:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3263:%.*]] = icmp eq i32 [[TMP2136]], [[TMP2137]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3264:%.*]] = zext i1 [[CMP3263]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3264]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2138:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3265:%.*]] = icmp ne i32 [[TMP2138]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3265]], label [[IF_THEN3266:%.*]], label [[IF_ELSE3267:%.*]]
|
|
// SIMD-ONLY0: if.then3266:
|
|
// SIMD-ONLY0-NEXT: [[TMP2139:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2139]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3268:%.*]]
|
|
// SIMD-ONLY0: if.else3267:
|
|
// SIMD-ONLY0-NEXT: [[TMP2140:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2140]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3268]]
|
|
// SIMD-ONLY0: if.end3268:
|
|
// SIMD-ONLY0-NEXT: [[TMP2141:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2142:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3269:%.*]] = icmp eq i32 [[TMP2141]], [[TMP2142]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3270:%.*]] = zext i1 [[CMP3269]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3270]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2143:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3271:%.*]] = icmp ne i32 [[TMP2143]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3271]], label [[IF_THEN3272:%.*]], label [[IF_ELSE3273:%.*]]
|
|
// SIMD-ONLY0: if.then3272:
|
|
// SIMD-ONLY0-NEXT: [[TMP2144:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2144]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3274:%.*]]
|
|
// SIMD-ONLY0: if.else3273:
|
|
// SIMD-ONLY0-NEXT: [[TMP2145:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2145]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3274]]
|
|
// SIMD-ONLY0: if.end3274:
|
|
// SIMD-ONLY0-NEXT: [[TMP2146:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2146]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2147:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2148:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3275:%.*]] = icmp sgt i32 [[TMP2147]], [[TMP2148]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3275]], label [[IF_THEN3277:%.*]], label [[IF_END3278:%.*]]
|
|
// SIMD-ONLY0: if.then3277:
|
|
// SIMD-ONLY0-NEXT: [[TMP2149:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2149]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3278]]
|
|
// SIMD-ONLY0: if.end3278:
|
|
// SIMD-ONLY0-NEXT: [[TMP2150:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2150]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2151:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2152:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3279:%.*]] = icmp sgt i32 [[TMP2151]], [[TMP2152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3279]], label [[IF_THEN3281:%.*]], label [[IF_END3282:%.*]]
|
|
// SIMD-ONLY0: if.then3281:
|
|
// SIMD-ONLY0-NEXT: [[TMP2153:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2153]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3282]]
|
|
// SIMD-ONLY0: if.end3282:
|
|
// SIMD-ONLY0-NEXT: [[TMP2154:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2154]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2155:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2156:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3283:%.*]] = icmp slt i32 [[TMP2155]], [[TMP2156]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3283]], label [[IF_THEN3285:%.*]], label [[IF_END3286:%.*]]
|
|
// SIMD-ONLY0: if.then3285:
|
|
// SIMD-ONLY0-NEXT: [[TMP2157:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2157]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3286]]
|
|
// SIMD-ONLY0: if.end3286:
|
|
// SIMD-ONLY0-NEXT: [[TMP2158:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2158]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2159:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2160:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3287:%.*]] = icmp slt i32 [[TMP2159]], [[TMP2160]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3287]], label [[IF_THEN3289:%.*]], label [[IF_END3290:%.*]]
|
|
// SIMD-ONLY0: if.then3289:
|
|
// SIMD-ONLY0-NEXT: [[TMP2161:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2161]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3290]]
|
|
// SIMD-ONLY0: if.end3290:
|
|
// SIMD-ONLY0-NEXT: [[TMP2162:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2162]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2163:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2164:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3291:%.*]] = icmp eq i32 [[TMP2163]], [[TMP2164]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3291]], label [[IF_THEN3293:%.*]], label [[IF_END3294:%.*]]
|
|
// SIMD-ONLY0: if.then3293:
|
|
// SIMD-ONLY0-NEXT: [[TMP2165:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2165]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3294]]
|
|
// SIMD-ONLY0: if.end3294:
|
|
// SIMD-ONLY0-NEXT: [[TMP2166:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2166]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2167:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2168:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3295:%.*]] = icmp eq i32 [[TMP2167]], [[TMP2168]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3295]], label [[IF_THEN3297:%.*]], label [[IF_END3298:%.*]]
|
|
// SIMD-ONLY0: if.then3297:
|
|
// SIMD-ONLY0-NEXT: [[TMP2169:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2169]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3298]]
|
|
// SIMD-ONLY0: if.end3298:
|
|
// SIMD-ONLY0-NEXT: [[TMP2170:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2171:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3299:%.*]] = icmp sgt i32 [[TMP2170]], [[TMP2171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3299]], label [[IF_THEN3301:%.*]], label [[IF_END3302:%.*]]
|
|
// SIMD-ONLY0: if.then3301:
|
|
// SIMD-ONLY0-NEXT: [[TMP2172:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2172]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3302]]
|
|
// SIMD-ONLY0: if.end3302:
|
|
// SIMD-ONLY0-NEXT: [[TMP2173:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2173]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2174:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2175:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3303:%.*]] = icmp sgt i32 [[TMP2174]], [[TMP2175]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3303]], label [[IF_THEN3305:%.*]], label [[IF_END3306:%.*]]
|
|
// SIMD-ONLY0: if.then3305:
|
|
// SIMD-ONLY0-NEXT: [[TMP2176:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2176]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3306]]
|
|
// SIMD-ONLY0: if.end3306:
|
|
// SIMD-ONLY0-NEXT: [[TMP2177:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2177]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2178:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2179:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3307:%.*]] = icmp slt i32 [[TMP2178]], [[TMP2179]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3307]], label [[IF_THEN3309:%.*]], label [[IF_END3310:%.*]]
|
|
// SIMD-ONLY0: if.then3309:
|
|
// SIMD-ONLY0-NEXT: [[TMP2180:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2180]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3310]]
|
|
// SIMD-ONLY0: if.end3310:
|
|
// SIMD-ONLY0-NEXT: [[TMP2181:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2181]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2182:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2183:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3311:%.*]] = icmp slt i32 [[TMP2182]], [[TMP2183]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3311]], label [[IF_THEN3313:%.*]], label [[IF_END3314:%.*]]
|
|
// SIMD-ONLY0: if.then3313:
|
|
// SIMD-ONLY0-NEXT: [[TMP2184:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2184]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3314]]
|
|
// SIMD-ONLY0: if.end3314:
|
|
// SIMD-ONLY0-NEXT: [[TMP2185:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2185]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2186:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2187:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3315:%.*]] = icmp eq i32 [[TMP2186]], [[TMP2187]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3315]], label [[IF_THEN3317:%.*]], label [[IF_END3318:%.*]]
|
|
// SIMD-ONLY0: if.then3317:
|
|
// SIMD-ONLY0-NEXT: [[TMP2188:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2188]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3318]]
|
|
// SIMD-ONLY0: if.end3318:
|
|
// SIMD-ONLY0-NEXT: [[TMP2189:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2189]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2190:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2191:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3319:%.*]] = icmp eq i32 [[TMP2190]], [[TMP2191]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3319]], label [[IF_THEN3321:%.*]], label [[IF_END3322:%.*]]
|
|
// SIMD-ONLY0: if.then3321:
|
|
// SIMD-ONLY0-NEXT: [[TMP2192:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2192]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3322]]
|
|
// SIMD-ONLY0: if.end3322:
|
|
// SIMD-ONLY0-NEXT: [[TMP2193:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2193]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2194:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2195:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3323:%.*]] = icmp eq i32 [[TMP2194]], [[TMP2195]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3323]], label [[IF_THEN3325:%.*]], label [[IF_ELSE3326:%.*]]
|
|
// SIMD-ONLY0: if.then3325:
|
|
// SIMD-ONLY0-NEXT: [[TMP2196:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2196]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3327:%.*]]
|
|
// SIMD-ONLY0: if.else3326:
|
|
// SIMD-ONLY0-NEXT: [[TMP2197:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2197]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3327]]
|
|
// SIMD-ONLY0: if.end3327:
|
|
// SIMD-ONLY0-NEXT: [[TMP2198:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2199:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3328:%.*]] = icmp eq i32 [[TMP2198]], [[TMP2199]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3328]], label [[IF_THEN3330:%.*]], label [[IF_ELSE3331:%.*]]
|
|
// SIMD-ONLY0: if.then3330:
|
|
// SIMD-ONLY0-NEXT: [[TMP2200:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2200]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3332:%.*]]
|
|
// SIMD-ONLY0: if.else3331:
|
|
// SIMD-ONLY0-NEXT: [[TMP2201:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2201]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3332]]
|
|
// SIMD-ONLY0: if.end3332:
|
|
// SIMD-ONLY0-NEXT: [[TMP2202:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2203:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3333:%.*]] = icmp eq i32 [[TMP2202]], [[TMP2203]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3334:%.*]] = zext i1 [[CMP3333]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3334]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2204:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3335:%.*]] = icmp ne i32 [[TMP2204]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3335]], label [[IF_THEN3336:%.*]], label [[IF_END3337:%.*]]
|
|
// SIMD-ONLY0: if.then3336:
|
|
// SIMD-ONLY0-NEXT: [[TMP2205:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2205]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3337]]
|
|
// SIMD-ONLY0: if.end3337:
|
|
// SIMD-ONLY0-NEXT: [[TMP2206:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2207:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3338:%.*]] = icmp eq i32 [[TMP2206]], [[TMP2207]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3339:%.*]] = zext i1 [[CMP3338]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3339]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2208:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3340:%.*]] = icmp ne i32 [[TMP2208]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3340]], label [[IF_THEN3341:%.*]], label [[IF_END3342:%.*]]
|
|
// SIMD-ONLY0: if.then3341:
|
|
// SIMD-ONLY0-NEXT: [[TMP2209:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2209]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3342]]
|
|
// SIMD-ONLY0: if.end3342:
|
|
// SIMD-ONLY0-NEXT: [[TMP2210:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2211:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3343:%.*]] = icmp eq i32 [[TMP2210]], [[TMP2211]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3344:%.*]] = zext i1 [[CMP3343]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3344]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2212:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3345:%.*]] = icmp ne i32 [[TMP2212]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3345]], label [[IF_THEN3346:%.*]], label [[IF_ELSE3347:%.*]]
|
|
// SIMD-ONLY0: if.then3346:
|
|
// SIMD-ONLY0-NEXT: [[TMP2213:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2213]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3348:%.*]]
|
|
// SIMD-ONLY0: if.else3347:
|
|
// SIMD-ONLY0-NEXT: [[TMP2214:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2214]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3348]]
|
|
// SIMD-ONLY0: if.end3348:
|
|
// SIMD-ONLY0-NEXT: [[TMP2215:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2216:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3349:%.*]] = icmp eq i32 [[TMP2215]], [[TMP2216]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3350:%.*]] = zext i1 [[CMP3349]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3350]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2217:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3351:%.*]] = icmp ne i32 [[TMP2217]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3351]], label [[IF_THEN3352:%.*]], label [[IF_ELSE3353:%.*]]
|
|
// SIMD-ONLY0: if.then3352:
|
|
// SIMD-ONLY0-NEXT: [[TMP2218:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2218]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3354:%.*]]
|
|
// SIMD-ONLY0: if.else3353:
|
|
// SIMD-ONLY0-NEXT: [[TMP2219:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2219]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3354]]
|
|
// SIMD-ONLY0: if.end3354:
|
|
// SIMD-ONLY0-NEXT: [[TMP2220:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2220]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2221:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2222:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3355:%.*]] = icmp ugt i32 [[TMP2221]], [[TMP2222]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3355]], label [[IF_THEN3357:%.*]], label [[IF_END3358:%.*]]
|
|
// SIMD-ONLY0: if.then3357:
|
|
// SIMD-ONLY0-NEXT: [[TMP2223:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2223]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3358]]
|
|
// SIMD-ONLY0: if.end3358:
|
|
// SIMD-ONLY0-NEXT: [[TMP2224:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2224]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2225:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2226:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3359:%.*]] = icmp ugt i32 [[TMP2225]], [[TMP2226]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3359]], label [[IF_THEN3361:%.*]], label [[IF_END3362:%.*]]
|
|
// SIMD-ONLY0: if.then3361:
|
|
// SIMD-ONLY0-NEXT: [[TMP2227:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2227]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3362]]
|
|
// SIMD-ONLY0: if.end3362:
|
|
// SIMD-ONLY0-NEXT: [[TMP2228:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2228]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2229:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2230:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3363:%.*]] = icmp ult i32 [[TMP2229]], [[TMP2230]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3363]], label [[IF_THEN3365:%.*]], label [[IF_END3366:%.*]]
|
|
// SIMD-ONLY0: if.then3365:
|
|
// SIMD-ONLY0-NEXT: [[TMP2231:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2231]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3366]]
|
|
// SIMD-ONLY0: if.end3366:
|
|
// SIMD-ONLY0-NEXT: [[TMP2232:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2232]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2233:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2234:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3367:%.*]] = icmp ult i32 [[TMP2233]], [[TMP2234]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3367]], label [[IF_THEN3369:%.*]], label [[IF_END3370:%.*]]
|
|
// SIMD-ONLY0: if.then3369:
|
|
// SIMD-ONLY0-NEXT: [[TMP2235:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2235]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3370]]
|
|
// SIMD-ONLY0: if.end3370:
|
|
// SIMD-ONLY0-NEXT: [[TMP2236:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2236]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2237:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2238:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3371:%.*]] = icmp eq i32 [[TMP2237]], [[TMP2238]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3371]], label [[IF_THEN3373:%.*]], label [[IF_END3374:%.*]]
|
|
// SIMD-ONLY0: if.then3373:
|
|
// SIMD-ONLY0-NEXT: [[TMP2239:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2239]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3374]]
|
|
// SIMD-ONLY0: if.end3374:
|
|
// SIMD-ONLY0-NEXT: [[TMP2240:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2240]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2241:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2242:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3375:%.*]] = icmp eq i32 [[TMP2241]], [[TMP2242]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3375]], label [[IF_THEN3377:%.*]], label [[IF_END3378:%.*]]
|
|
// SIMD-ONLY0: if.then3377:
|
|
// SIMD-ONLY0-NEXT: [[TMP2243:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2243]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3378]]
|
|
// SIMD-ONLY0: if.end3378:
|
|
// SIMD-ONLY0-NEXT: [[TMP2244:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2245:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3379:%.*]] = icmp ugt i32 [[TMP2244]], [[TMP2245]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3379]], label [[IF_THEN3381:%.*]], label [[IF_END3382:%.*]]
|
|
// SIMD-ONLY0: if.then3381:
|
|
// SIMD-ONLY0-NEXT: [[TMP2246:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2246]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3382]]
|
|
// SIMD-ONLY0: if.end3382:
|
|
// SIMD-ONLY0-NEXT: [[TMP2247:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2247]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2248:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2249:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3383:%.*]] = icmp ugt i32 [[TMP2248]], [[TMP2249]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3383]], label [[IF_THEN3385:%.*]], label [[IF_END3386:%.*]]
|
|
// SIMD-ONLY0: if.then3385:
|
|
// SIMD-ONLY0-NEXT: [[TMP2250:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2250]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3386]]
|
|
// SIMD-ONLY0: if.end3386:
|
|
// SIMD-ONLY0-NEXT: [[TMP2251:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2251]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2252:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2253:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3387:%.*]] = icmp ult i32 [[TMP2252]], [[TMP2253]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3387]], label [[IF_THEN3389:%.*]], label [[IF_END3390:%.*]]
|
|
// SIMD-ONLY0: if.then3389:
|
|
// SIMD-ONLY0-NEXT: [[TMP2254:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2254]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3390]]
|
|
// SIMD-ONLY0: if.end3390:
|
|
// SIMD-ONLY0-NEXT: [[TMP2255:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2255]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2256:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2257:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3391:%.*]] = icmp ult i32 [[TMP2256]], [[TMP2257]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3391]], label [[IF_THEN3393:%.*]], label [[IF_END3394:%.*]]
|
|
// SIMD-ONLY0: if.then3393:
|
|
// SIMD-ONLY0-NEXT: [[TMP2258:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2258]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3394]]
|
|
// SIMD-ONLY0: if.end3394:
|
|
// SIMD-ONLY0-NEXT: [[TMP2259:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2259]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2260:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2261:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3395:%.*]] = icmp eq i32 [[TMP2260]], [[TMP2261]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3395]], label [[IF_THEN3397:%.*]], label [[IF_END3398:%.*]]
|
|
// SIMD-ONLY0: if.then3397:
|
|
// SIMD-ONLY0-NEXT: [[TMP2262:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2262]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3398]]
|
|
// SIMD-ONLY0: if.end3398:
|
|
// SIMD-ONLY0-NEXT: [[TMP2263:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2263]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2264:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2265:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3399:%.*]] = icmp eq i32 [[TMP2264]], [[TMP2265]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3399]], label [[IF_THEN3401:%.*]], label [[IF_END3402:%.*]]
|
|
// SIMD-ONLY0: if.then3401:
|
|
// SIMD-ONLY0-NEXT: [[TMP2266:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2266]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3402]]
|
|
// SIMD-ONLY0: if.end3402:
|
|
// SIMD-ONLY0-NEXT: [[TMP2267:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2267]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2268:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2269:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3403:%.*]] = icmp eq i32 [[TMP2268]], [[TMP2269]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3403]], label [[IF_THEN3405:%.*]], label [[IF_ELSE3406:%.*]]
|
|
// SIMD-ONLY0: if.then3405:
|
|
// SIMD-ONLY0-NEXT: [[TMP2270:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2270]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3407:%.*]]
|
|
// SIMD-ONLY0: if.else3406:
|
|
// SIMD-ONLY0-NEXT: [[TMP2271:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2271]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3407]]
|
|
// SIMD-ONLY0: if.end3407:
|
|
// SIMD-ONLY0-NEXT: [[TMP2272:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2273:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3408:%.*]] = icmp eq i32 [[TMP2272]], [[TMP2273]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3408]], label [[IF_THEN3410:%.*]], label [[IF_ELSE3411:%.*]]
|
|
// SIMD-ONLY0: if.then3410:
|
|
// SIMD-ONLY0-NEXT: [[TMP2274:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2274]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3412:%.*]]
|
|
// SIMD-ONLY0: if.else3411:
|
|
// SIMD-ONLY0-NEXT: [[TMP2275:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2275]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3412]]
|
|
// SIMD-ONLY0: if.end3412:
|
|
// SIMD-ONLY0-NEXT: [[TMP2276:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2277:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3413:%.*]] = icmp eq i32 [[TMP2276]], [[TMP2277]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3414:%.*]] = zext i1 [[CMP3413]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3414]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2278:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3415:%.*]] = icmp ne i32 [[TMP2278]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3415]], label [[IF_THEN3416:%.*]], label [[IF_END3417:%.*]]
|
|
// SIMD-ONLY0: if.then3416:
|
|
// SIMD-ONLY0-NEXT: [[TMP2279:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2279]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3417]]
|
|
// SIMD-ONLY0: if.end3417:
|
|
// SIMD-ONLY0-NEXT: [[TMP2280:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2281:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3418:%.*]] = icmp eq i32 [[TMP2280]], [[TMP2281]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3419:%.*]] = zext i1 [[CMP3418]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3419]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2282:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3420:%.*]] = icmp ne i32 [[TMP2282]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3420]], label [[IF_THEN3421:%.*]], label [[IF_END3422:%.*]]
|
|
// SIMD-ONLY0: if.then3421:
|
|
// SIMD-ONLY0-NEXT: [[TMP2283:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2283]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3422]]
|
|
// SIMD-ONLY0: if.end3422:
|
|
// SIMD-ONLY0-NEXT: [[TMP2284:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2285:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3423:%.*]] = icmp eq i32 [[TMP2284]], [[TMP2285]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3424:%.*]] = zext i1 [[CMP3423]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3424]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2286:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3425:%.*]] = icmp ne i32 [[TMP2286]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3425]], label [[IF_THEN3426:%.*]], label [[IF_ELSE3427:%.*]]
|
|
// SIMD-ONLY0: if.then3426:
|
|
// SIMD-ONLY0-NEXT: [[TMP2287:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2287]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3428:%.*]]
|
|
// SIMD-ONLY0: if.else3427:
|
|
// SIMD-ONLY0-NEXT: [[TMP2288:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2288]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3428]]
|
|
// SIMD-ONLY0: if.end3428:
|
|
// SIMD-ONLY0-NEXT: [[TMP2289:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2290:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3429:%.*]] = icmp eq i32 [[TMP2289]], [[TMP2290]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3430:%.*]] = zext i1 [[CMP3429]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3430]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2291:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3431:%.*]] = icmp ne i32 [[TMP2291]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3431]], label [[IF_THEN3432:%.*]], label [[IF_ELSE3433:%.*]]
|
|
// SIMD-ONLY0: if.then3432:
|
|
// SIMD-ONLY0-NEXT: [[TMP2292:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2292]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3434:%.*]]
|
|
// SIMD-ONLY0: if.else3433:
|
|
// SIMD-ONLY0-NEXT: [[TMP2293:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2293]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3434]]
|
|
// SIMD-ONLY0: if.end3434:
|
|
// SIMD-ONLY0-NEXT: [[TMP2294:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2294]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2295:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2296:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3435:%.*]] = icmp ugt i32 [[TMP2295]], [[TMP2296]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3435]], label [[IF_THEN3437:%.*]], label [[IF_END3438:%.*]]
|
|
// SIMD-ONLY0: if.then3437:
|
|
// SIMD-ONLY0-NEXT: [[TMP2297:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2297]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3438]]
|
|
// SIMD-ONLY0: if.end3438:
|
|
// SIMD-ONLY0-NEXT: [[TMP2298:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2298]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2299:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2300:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3439:%.*]] = icmp ugt i32 [[TMP2299]], [[TMP2300]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3439]], label [[IF_THEN3441:%.*]], label [[IF_END3442:%.*]]
|
|
// SIMD-ONLY0: if.then3441:
|
|
// SIMD-ONLY0-NEXT: [[TMP2301:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2301]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3442]]
|
|
// SIMD-ONLY0: if.end3442:
|
|
// SIMD-ONLY0-NEXT: [[TMP2302:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2302]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2303:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2304:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3443:%.*]] = icmp ult i32 [[TMP2303]], [[TMP2304]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3443]], label [[IF_THEN3445:%.*]], label [[IF_END3446:%.*]]
|
|
// SIMD-ONLY0: if.then3445:
|
|
// SIMD-ONLY0-NEXT: [[TMP2305:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2305]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3446]]
|
|
// SIMD-ONLY0: if.end3446:
|
|
// SIMD-ONLY0-NEXT: [[TMP2306:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2306]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2307:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2308:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3447:%.*]] = icmp ult i32 [[TMP2307]], [[TMP2308]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3447]], label [[IF_THEN3449:%.*]], label [[IF_END3450:%.*]]
|
|
// SIMD-ONLY0: if.then3449:
|
|
// SIMD-ONLY0-NEXT: [[TMP2309:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2309]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3450]]
|
|
// SIMD-ONLY0: if.end3450:
|
|
// SIMD-ONLY0-NEXT: [[TMP2310:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2310]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2311:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2312:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3451:%.*]] = icmp eq i32 [[TMP2311]], [[TMP2312]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3451]], label [[IF_THEN3453:%.*]], label [[IF_END3454:%.*]]
|
|
// SIMD-ONLY0: if.then3453:
|
|
// SIMD-ONLY0-NEXT: [[TMP2313:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2313]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3454]]
|
|
// SIMD-ONLY0: if.end3454:
|
|
// SIMD-ONLY0-NEXT: [[TMP2314:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2314]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2315:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2316:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3455:%.*]] = icmp eq i32 [[TMP2315]], [[TMP2316]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3455]], label [[IF_THEN3457:%.*]], label [[IF_END3458:%.*]]
|
|
// SIMD-ONLY0: if.then3457:
|
|
// SIMD-ONLY0-NEXT: [[TMP2317:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2317]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3458]]
|
|
// SIMD-ONLY0: if.end3458:
|
|
// SIMD-ONLY0-NEXT: [[TMP2318:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2319:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3459:%.*]] = icmp ugt i32 [[TMP2318]], [[TMP2319]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3459]], label [[IF_THEN3461:%.*]], label [[IF_END3462:%.*]]
|
|
// SIMD-ONLY0: if.then3461:
|
|
// SIMD-ONLY0-NEXT: [[TMP2320:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2320]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3462]]
|
|
// SIMD-ONLY0: if.end3462:
|
|
// SIMD-ONLY0-NEXT: [[TMP2321:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2321]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2322:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2323:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3463:%.*]] = icmp ugt i32 [[TMP2322]], [[TMP2323]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3463]], label [[IF_THEN3465:%.*]], label [[IF_END3466:%.*]]
|
|
// SIMD-ONLY0: if.then3465:
|
|
// SIMD-ONLY0-NEXT: [[TMP2324:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2324]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3466]]
|
|
// SIMD-ONLY0: if.end3466:
|
|
// SIMD-ONLY0-NEXT: [[TMP2325:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2325]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2326:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2327:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3467:%.*]] = icmp ult i32 [[TMP2326]], [[TMP2327]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3467]], label [[IF_THEN3469:%.*]], label [[IF_END3470:%.*]]
|
|
// SIMD-ONLY0: if.then3469:
|
|
// SIMD-ONLY0-NEXT: [[TMP2328:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2328]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3470]]
|
|
// SIMD-ONLY0: if.end3470:
|
|
// SIMD-ONLY0-NEXT: [[TMP2329:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2329]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2330:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2331:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3471:%.*]] = icmp ult i32 [[TMP2330]], [[TMP2331]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3471]], label [[IF_THEN3473:%.*]], label [[IF_END3474:%.*]]
|
|
// SIMD-ONLY0: if.then3473:
|
|
// SIMD-ONLY0-NEXT: [[TMP2332:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2332]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3474]]
|
|
// SIMD-ONLY0: if.end3474:
|
|
// SIMD-ONLY0-NEXT: [[TMP2333:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2333]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2334:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2335:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3475:%.*]] = icmp eq i32 [[TMP2334]], [[TMP2335]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3475]], label [[IF_THEN3477:%.*]], label [[IF_END3478:%.*]]
|
|
// SIMD-ONLY0: if.then3477:
|
|
// SIMD-ONLY0-NEXT: [[TMP2336:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2336]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3478]]
|
|
// SIMD-ONLY0: if.end3478:
|
|
// SIMD-ONLY0-NEXT: [[TMP2337:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2337]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2338:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2339:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3479:%.*]] = icmp eq i32 [[TMP2338]], [[TMP2339]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3479]], label [[IF_THEN3481:%.*]], label [[IF_END3482:%.*]]
|
|
// SIMD-ONLY0: if.then3481:
|
|
// SIMD-ONLY0-NEXT: [[TMP2340:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2340]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3482]]
|
|
// SIMD-ONLY0: if.end3482:
|
|
// SIMD-ONLY0-NEXT: [[TMP2341:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2341]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2342:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2343:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3483:%.*]] = icmp eq i32 [[TMP2342]], [[TMP2343]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3483]], label [[IF_THEN3485:%.*]], label [[IF_ELSE3486:%.*]]
|
|
// SIMD-ONLY0: if.then3485:
|
|
// SIMD-ONLY0-NEXT: [[TMP2344:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2344]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3487:%.*]]
|
|
// SIMD-ONLY0: if.else3486:
|
|
// SIMD-ONLY0-NEXT: [[TMP2345:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2345]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3487]]
|
|
// SIMD-ONLY0: if.end3487:
|
|
// SIMD-ONLY0-NEXT: [[TMP2346:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2347:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3488:%.*]] = icmp eq i32 [[TMP2346]], [[TMP2347]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3488]], label [[IF_THEN3490:%.*]], label [[IF_ELSE3491:%.*]]
|
|
// SIMD-ONLY0: if.then3490:
|
|
// SIMD-ONLY0-NEXT: [[TMP2348:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2348]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3492:%.*]]
|
|
// SIMD-ONLY0: if.else3491:
|
|
// SIMD-ONLY0-NEXT: [[TMP2349:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2349]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3492]]
|
|
// SIMD-ONLY0: if.end3492:
|
|
// SIMD-ONLY0-NEXT: [[TMP2350:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2351:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3493:%.*]] = icmp eq i32 [[TMP2350]], [[TMP2351]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3494:%.*]] = zext i1 [[CMP3493]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3494]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2352:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3495:%.*]] = icmp ne i32 [[TMP2352]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3495]], label [[IF_THEN3496:%.*]], label [[IF_END3497:%.*]]
|
|
// SIMD-ONLY0: if.then3496:
|
|
// SIMD-ONLY0-NEXT: [[TMP2353:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2353]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3497]]
|
|
// SIMD-ONLY0: if.end3497:
|
|
// SIMD-ONLY0-NEXT: [[TMP2354:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2355:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3498:%.*]] = icmp eq i32 [[TMP2354]], [[TMP2355]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3499:%.*]] = zext i1 [[CMP3498]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3499]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2356:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3500:%.*]] = icmp ne i32 [[TMP2356]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3500]], label [[IF_THEN3501:%.*]], label [[IF_END3502:%.*]]
|
|
// SIMD-ONLY0: if.then3501:
|
|
// SIMD-ONLY0-NEXT: [[TMP2357:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2357]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3502]]
|
|
// SIMD-ONLY0: if.end3502:
|
|
// SIMD-ONLY0-NEXT: [[TMP2358:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2359:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3503:%.*]] = icmp eq i32 [[TMP2358]], [[TMP2359]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3504:%.*]] = zext i1 [[CMP3503]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3504]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2360:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3505:%.*]] = icmp ne i32 [[TMP2360]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3505]], label [[IF_THEN3506:%.*]], label [[IF_ELSE3507:%.*]]
|
|
// SIMD-ONLY0: if.then3506:
|
|
// SIMD-ONLY0-NEXT: [[TMP2361:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2361]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3508:%.*]]
|
|
// SIMD-ONLY0: if.else3507:
|
|
// SIMD-ONLY0-NEXT: [[TMP2362:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2362]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3508]]
|
|
// SIMD-ONLY0: if.end3508:
|
|
// SIMD-ONLY0-NEXT: [[TMP2363:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2364:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3509:%.*]] = icmp eq i32 [[TMP2363]], [[TMP2364]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3510:%.*]] = zext i1 [[CMP3509]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3510]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2365:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3511:%.*]] = icmp ne i32 [[TMP2365]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3511]], label [[IF_THEN3512:%.*]], label [[IF_ELSE3513:%.*]]
|
|
// SIMD-ONLY0: if.then3512:
|
|
// SIMD-ONLY0-NEXT: [[TMP2366:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2366]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3514:%.*]]
|
|
// SIMD-ONLY0: if.else3513:
|
|
// SIMD-ONLY0-NEXT: [[TMP2367:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2367]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3514]]
|
|
// SIMD-ONLY0: if.end3514:
|
|
// SIMD-ONLY0-NEXT: [[TMP2368:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2368]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2369:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2370:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3515:%.*]] = icmp ugt i32 [[TMP2369]], [[TMP2370]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3515]], label [[IF_THEN3517:%.*]], label [[IF_END3518:%.*]]
|
|
// SIMD-ONLY0: if.then3517:
|
|
// SIMD-ONLY0-NEXT: [[TMP2371:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2371]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3518]]
|
|
// SIMD-ONLY0: if.end3518:
|
|
// SIMD-ONLY0-NEXT: [[TMP2372:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2372]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2373:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2374:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3519:%.*]] = icmp ugt i32 [[TMP2373]], [[TMP2374]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3519]], label [[IF_THEN3521:%.*]], label [[IF_END3522:%.*]]
|
|
// SIMD-ONLY0: if.then3521:
|
|
// SIMD-ONLY0-NEXT: [[TMP2375:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2375]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3522]]
|
|
// SIMD-ONLY0: if.end3522:
|
|
// SIMD-ONLY0-NEXT: [[TMP2376:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2376]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2377:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2378:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3523:%.*]] = icmp ult i32 [[TMP2377]], [[TMP2378]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3523]], label [[IF_THEN3525:%.*]], label [[IF_END3526:%.*]]
|
|
// SIMD-ONLY0: if.then3525:
|
|
// SIMD-ONLY0-NEXT: [[TMP2379:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2379]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3526]]
|
|
// SIMD-ONLY0: if.end3526:
|
|
// SIMD-ONLY0-NEXT: [[TMP2380:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2380]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2381:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2382:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3527:%.*]] = icmp ult i32 [[TMP2381]], [[TMP2382]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3527]], label [[IF_THEN3529:%.*]], label [[IF_END3530:%.*]]
|
|
// SIMD-ONLY0: if.then3529:
|
|
// SIMD-ONLY0-NEXT: [[TMP2383:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2383]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3530]]
|
|
// SIMD-ONLY0: if.end3530:
|
|
// SIMD-ONLY0-NEXT: [[TMP2384:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2384]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2385:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2386:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3531:%.*]] = icmp eq i32 [[TMP2385]], [[TMP2386]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3531]], label [[IF_THEN3533:%.*]], label [[IF_END3534:%.*]]
|
|
// SIMD-ONLY0: if.then3533:
|
|
// SIMD-ONLY0-NEXT: [[TMP2387:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2387]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3534]]
|
|
// SIMD-ONLY0: if.end3534:
|
|
// SIMD-ONLY0-NEXT: [[TMP2388:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2388]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2389:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2390:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3535:%.*]] = icmp eq i32 [[TMP2389]], [[TMP2390]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3535]], label [[IF_THEN3537:%.*]], label [[IF_END3538:%.*]]
|
|
// SIMD-ONLY0: if.then3537:
|
|
// SIMD-ONLY0-NEXT: [[TMP2391:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2391]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3538]]
|
|
// SIMD-ONLY0: if.end3538:
|
|
// SIMD-ONLY0-NEXT: [[TMP2392:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2393:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3539:%.*]] = icmp ugt i32 [[TMP2392]], [[TMP2393]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3539]], label [[IF_THEN3541:%.*]], label [[IF_END3542:%.*]]
|
|
// SIMD-ONLY0: if.then3541:
|
|
// SIMD-ONLY0-NEXT: [[TMP2394:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2394]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3542]]
|
|
// SIMD-ONLY0: if.end3542:
|
|
// SIMD-ONLY0-NEXT: [[TMP2395:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2395]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2396:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2397:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3543:%.*]] = icmp ugt i32 [[TMP2396]], [[TMP2397]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3543]], label [[IF_THEN3545:%.*]], label [[IF_END3546:%.*]]
|
|
// SIMD-ONLY0: if.then3545:
|
|
// SIMD-ONLY0-NEXT: [[TMP2398:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2398]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3546]]
|
|
// SIMD-ONLY0: if.end3546:
|
|
// SIMD-ONLY0-NEXT: [[TMP2399:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2399]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2400:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2401:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3547:%.*]] = icmp ult i32 [[TMP2400]], [[TMP2401]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3547]], label [[IF_THEN3549:%.*]], label [[IF_END3550:%.*]]
|
|
// SIMD-ONLY0: if.then3549:
|
|
// SIMD-ONLY0-NEXT: [[TMP2402:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2402]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3550]]
|
|
// SIMD-ONLY0: if.end3550:
|
|
// SIMD-ONLY0-NEXT: [[TMP2403:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2403]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2404:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2405:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3551:%.*]] = icmp ult i32 [[TMP2404]], [[TMP2405]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3551]], label [[IF_THEN3553:%.*]], label [[IF_END3554:%.*]]
|
|
// SIMD-ONLY0: if.then3553:
|
|
// SIMD-ONLY0-NEXT: [[TMP2406:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2406]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3554]]
|
|
// SIMD-ONLY0: if.end3554:
|
|
// SIMD-ONLY0-NEXT: [[TMP2407:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2407]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2408:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2409:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3555:%.*]] = icmp eq i32 [[TMP2408]], [[TMP2409]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3555]], label [[IF_THEN3557:%.*]], label [[IF_END3558:%.*]]
|
|
// SIMD-ONLY0: if.then3557:
|
|
// SIMD-ONLY0-NEXT: [[TMP2410:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2410]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3558]]
|
|
// SIMD-ONLY0: if.end3558:
|
|
// SIMD-ONLY0-NEXT: [[TMP2411:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2411]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2412:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2413:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3559:%.*]] = icmp eq i32 [[TMP2412]], [[TMP2413]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3559]], label [[IF_THEN3561:%.*]], label [[IF_END3562:%.*]]
|
|
// SIMD-ONLY0: if.then3561:
|
|
// SIMD-ONLY0-NEXT: [[TMP2414:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2414]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3562]]
|
|
// SIMD-ONLY0: if.end3562:
|
|
// SIMD-ONLY0-NEXT: [[TMP2415:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2415]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2416:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2417:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3563:%.*]] = icmp eq i32 [[TMP2416]], [[TMP2417]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3563]], label [[IF_THEN3565:%.*]], label [[IF_ELSE3566:%.*]]
|
|
// SIMD-ONLY0: if.then3565:
|
|
// SIMD-ONLY0-NEXT: [[TMP2418:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2418]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3567:%.*]]
|
|
// SIMD-ONLY0: if.else3566:
|
|
// SIMD-ONLY0-NEXT: [[TMP2419:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2419]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3567]]
|
|
// SIMD-ONLY0: if.end3567:
|
|
// SIMD-ONLY0-NEXT: [[TMP2420:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2421:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3568:%.*]] = icmp eq i32 [[TMP2420]], [[TMP2421]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3568]], label [[IF_THEN3570:%.*]], label [[IF_ELSE3571:%.*]]
|
|
// SIMD-ONLY0: if.then3570:
|
|
// SIMD-ONLY0-NEXT: [[TMP2422:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2422]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3572:%.*]]
|
|
// SIMD-ONLY0: if.else3571:
|
|
// SIMD-ONLY0-NEXT: [[TMP2423:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2423]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3572]]
|
|
// SIMD-ONLY0: if.end3572:
|
|
// SIMD-ONLY0-NEXT: [[TMP2424:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2425:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3573:%.*]] = icmp eq i32 [[TMP2424]], [[TMP2425]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3574:%.*]] = zext i1 [[CMP3573]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3574]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2426:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3575:%.*]] = icmp ne i32 [[TMP2426]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3575]], label [[IF_THEN3576:%.*]], label [[IF_END3577:%.*]]
|
|
// SIMD-ONLY0: if.then3576:
|
|
// SIMD-ONLY0-NEXT: [[TMP2427:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2427]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3577]]
|
|
// SIMD-ONLY0: if.end3577:
|
|
// SIMD-ONLY0-NEXT: [[TMP2428:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2429:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3578:%.*]] = icmp eq i32 [[TMP2428]], [[TMP2429]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3579:%.*]] = zext i1 [[CMP3578]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3579]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2430:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3580:%.*]] = icmp ne i32 [[TMP2430]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3580]], label [[IF_THEN3581:%.*]], label [[IF_END3582:%.*]]
|
|
// SIMD-ONLY0: if.then3581:
|
|
// SIMD-ONLY0-NEXT: [[TMP2431:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2431]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3582]]
|
|
// SIMD-ONLY0: if.end3582:
|
|
// SIMD-ONLY0-NEXT: [[TMP2432:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2433:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3583:%.*]] = icmp eq i32 [[TMP2432]], [[TMP2433]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3584:%.*]] = zext i1 [[CMP3583]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3584]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2434:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3585:%.*]] = icmp ne i32 [[TMP2434]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3585]], label [[IF_THEN3586:%.*]], label [[IF_ELSE3587:%.*]]
|
|
// SIMD-ONLY0: if.then3586:
|
|
// SIMD-ONLY0-NEXT: [[TMP2435:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2435]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3588:%.*]]
|
|
// SIMD-ONLY0: if.else3587:
|
|
// SIMD-ONLY0-NEXT: [[TMP2436:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2436]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3588]]
|
|
// SIMD-ONLY0: if.end3588:
|
|
// SIMD-ONLY0-NEXT: [[TMP2437:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2438:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3589:%.*]] = icmp eq i32 [[TMP2437]], [[TMP2438]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3590:%.*]] = zext i1 [[CMP3589]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3590]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2439:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3591:%.*]] = icmp ne i32 [[TMP2439]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3591]], label [[IF_THEN3592:%.*]], label [[IF_ELSE3593:%.*]]
|
|
// SIMD-ONLY0: if.then3592:
|
|
// SIMD-ONLY0-NEXT: [[TMP2440:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2440]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3594:%.*]]
|
|
// SIMD-ONLY0: if.else3593:
|
|
// SIMD-ONLY0-NEXT: [[TMP2441:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2441]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3594]]
|
|
// SIMD-ONLY0: if.end3594:
|
|
// SIMD-ONLY0-NEXT: [[TMP2442:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2442]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2443:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2444:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3595:%.*]] = icmp ugt i32 [[TMP2443]], [[TMP2444]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3595]], label [[IF_THEN3597:%.*]], label [[IF_END3598:%.*]]
|
|
// SIMD-ONLY0: if.then3597:
|
|
// SIMD-ONLY0-NEXT: [[TMP2445:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2445]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3598]]
|
|
// SIMD-ONLY0: if.end3598:
|
|
// SIMD-ONLY0-NEXT: [[TMP2446:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2446]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2447:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2448:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3599:%.*]] = icmp ugt i32 [[TMP2447]], [[TMP2448]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3599]], label [[IF_THEN3601:%.*]], label [[IF_END3602:%.*]]
|
|
// SIMD-ONLY0: if.then3601:
|
|
// SIMD-ONLY0-NEXT: [[TMP2449:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2449]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3602]]
|
|
// SIMD-ONLY0: if.end3602:
|
|
// SIMD-ONLY0-NEXT: [[TMP2450:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2450]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2451:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2452:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3603:%.*]] = icmp ult i32 [[TMP2451]], [[TMP2452]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3603]], label [[IF_THEN3605:%.*]], label [[IF_END3606:%.*]]
|
|
// SIMD-ONLY0: if.then3605:
|
|
// SIMD-ONLY0-NEXT: [[TMP2453:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2453]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3606]]
|
|
// SIMD-ONLY0: if.end3606:
|
|
// SIMD-ONLY0-NEXT: [[TMP2454:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2454]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2455:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2456:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3607:%.*]] = icmp ult i32 [[TMP2455]], [[TMP2456]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3607]], label [[IF_THEN3609:%.*]], label [[IF_END3610:%.*]]
|
|
// SIMD-ONLY0: if.then3609:
|
|
// SIMD-ONLY0-NEXT: [[TMP2457:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2457]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3610]]
|
|
// SIMD-ONLY0: if.end3610:
|
|
// SIMD-ONLY0-NEXT: [[TMP2458:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2458]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2459:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2460:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3611:%.*]] = icmp eq i32 [[TMP2459]], [[TMP2460]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3611]], label [[IF_THEN3613:%.*]], label [[IF_END3614:%.*]]
|
|
// SIMD-ONLY0: if.then3613:
|
|
// SIMD-ONLY0-NEXT: [[TMP2461:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2461]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3614]]
|
|
// SIMD-ONLY0: if.end3614:
|
|
// SIMD-ONLY0-NEXT: [[TMP2462:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2462]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2463:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2464:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3615:%.*]] = icmp eq i32 [[TMP2463]], [[TMP2464]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3615]], label [[IF_THEN3617:%.*]], label [[IF_END3618:%.*]]
|
|
// SIMD-ONLY0: if.then3617:
|
|
// SIMD-ONLY0-NEXT: [[TMP2465:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2465]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3618]]
|
|
// SIMD-ONLY0: if.end3618:
|
|
// SIMD-ONLY0-NEXT: [[TMP2466:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2467:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3619:%.*]] = icmp ugt i32 [[TMP2466]], [[TMP2467]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3619]], label [[IF_THEN3621:%.*]], label [[IF_END3622:%.*]]
|
|
// SIMD-ONLY0: if.then3621:
|
|
// SIMD-ONLY0-NEXT: [[TMP2468:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2468]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3622]]
|
|
// SIMD-ONLY0: if.end3622:
|
|
// SIMD-ONLY0-NEXT: [[TMP2469:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2469]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2470:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2471:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3623:%.*]] = icmp ugt i32 [[TMP2470]], [[TMP2471]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3623]], label [[IF_THEN3625:%.*]], label [[IF_END3626:%.*]]
|
|
// SIMD-ONLY0: if.then3625:
|
|
// SIMD-ONLY0-NEXT: [[TMP2472:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2472]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3626]]
|
|
// SIMD-ONLY0: if.end3626:
|
|
// SIMD-ONLY0-NEXT: [[TMP2473:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2473]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2474:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2475:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3627:%.*]] = icmp ult i32 [[TMP2474]], [[TMP2475]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3627]], label [[IF_THEN3629:%.*]], label [[IF_END3630:%.*]]
|
|
// SIMD-ONLY0: if.then3629:
|
|
// SIMD-ONLY0-NEXT: [[TMP2476:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2476]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3630]]
|
|
// SIMD-ONLY0: if.end3630:
|
|
// SIMD-ONLY0-NEXT: [[TMP2477:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2477]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2478:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2479:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3631:%.*]] = icmp ult i32 [[TMP2478]], [[TMP2479]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3631]], label [[IF_THEN3633:%.*]], label [[IF_END3634:%.*]]
|
|
// SIMD-ONLY0: if.then3633:
|
|
// SIMD-ONLY0-NEXT: [[TMP2480:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2480]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3634]]
|
|
// SIMD-ONLY0: if.end3634:
|
|
// SIMD-ONLY0-NEXT: [[TMP2481:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2481]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2482:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2483:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3635:%.*]] = icmp eq i32 [[TMP2482]], [[TMP2483]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3635]], label [[IF_THEN3637:%.*]], label [[IF_END3638:%.*]]
|
|
// SIMD-ONLY0: if.then3637:
|
|
// SIMD-ONLY0-NEXT: [[TMP2484:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2484]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3638]]
|
|
// SIMD-ONLY0: if.end3638:
|
|
// SIMD-ONLY0-NEXT: [[TMP2485:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2485]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2486:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2487:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3639:%.*]] = icmp eq i32 [[TMP2486]], [[TMP2487]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3639]], label [[IF_THEN3641:%.*]], label [[IF_END3642:%.*]]
|
|
// SIMD-ONLY0: if.then3641:
|
|
// SIMD-ONLY0-NEXT: [[TMP2488:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2488]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3642]]
|
|
// SIMD-ONLY0: if.end3642:
|
|
// SIMD-ONLY0-NEXT: [[TMP2489:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2489]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2490:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2491:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3643:%.*]] = icmp eq i32 [[TMP2490]], [[TMP2491]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3643]], label [[IF_THEN3645:%.*]], label [[IF_ELSE3646:%.*]]
|
|
// SIMD-ONLY0: if.then3645:
|
|
// SIMD-ONLY0-NEXT: [[TMP2492:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2492]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3647:%.*]]
|
|
// SIMD-ONLY0: if.else3646:
|
|
// SIMD-ONLY0-NEXT: [[TMP2493:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2493]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3647]]
|
|
// SIMD-ONLY0: if.end3647:
|
|
// SIMD-ONLY0-NEXT: [[TMP2494:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2495:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3648:%.*]] = icmp eq i32 [[TMP2494]], [[TMP2495]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3648]], label [[IF_THEN3650:%.*]], label [[IF_ELSE3651:%.*]]
|
|
// SIMD-ONLY0: if.then3650:
|
|
// SIMD-ONLY0-NEXT: [[TMP2496:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2496]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3652:%.*]]
|
|
// SIMD-ONLY0: if.else3651:
|
|
// SIMD-ONLY0-NEXT: [[TMP2497:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2497]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3652]]
|
|
// SIMD-ONLY0: if.end3652:
|
|
// SIMD-ONLY0-NEXT: [[TMP2498:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2499:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3653:%.*]] = icmp eq i32 [[TMP2498]], [[TMP2499]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3654:%.*]] = zext i1 [[CMP3653]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3654]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2500:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3655:%.*]] = icmp ne i32 [[TMP2500]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3655]], label [[IF_THEN3656:%.*]], label [[IF_END3657:%.*]]
|
|
// SIMD-ONLY0: if.then3656:
|
|
// SIMD-ONLY0-NEXT: [[TMP2501:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2501]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3657]]
|
|
// SIMD-ONLY0: if.end3657:
|
|
// SIMD-ONLY0-NEXT: [[TMP2502:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2503:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3658:%.*]] = icmp eq i32 [[TMP2502]], [[TMP2503]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3659:%.*]] = zext i1 [[CMP3658]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3659]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2504:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3660:%.*]] = icmp ne i32 [[TMP2504]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3660]], label [[IF_THEN3661:%.*]], label [[IF_END3662:%.*]]
|
|
// SIMD-ONLY0: if.then3661:
|
|
// SIMD-ONLY0-NEXT: [[TMP2505:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2505]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3662]]
|
|
// SIMD-ONLY0: if.end3662:
|
|
// SIMD-ONLY0-NEXT: [[TMP2506:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2507:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3663:%.*]] = icmp eq i32 [[TMP2506]], [[TMP2507]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3664:%.*]] = zext i1 [[CMP3663]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3664]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2508:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3665:%.*]] = icmp ne i32 [[TMP2508]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3665]], label [[IF_THEN3666:%.*]], label [[IF_ELSE3667:%.*]]
|
|
// SIMD-ONLY0: if.then3666:
|
|
// SIMD-ONLY0-NEXT: [[TMP2509:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2509]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3668:%.*]]
|
|
// SIMD-ONLY0: if.else3667:
|
|
// SIMD-ONLY0-NEXT: [[TMP2510:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2510]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3668]]
|
|
// SIMD-ONLY0: if.end3668:
|
|
// SIMD-ONLY0-NEXT: [[TMP2511:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2512:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3669:%.*]] = icmp eq i32 [[TMP2511]], [[TMP2512]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3670:%.*]] = zext i1 [[CMP3669]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3670]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2513:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3671:%.*]] = icmp ne i32 [[TMP2513]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3671]], label [[IF_THEN3672:%.*]], label [[IF_ELSE3673:%.*]]
|
|
// SIMD-ONLY0: if.then3672:
|
|
// SIMD-ONLY0-NEXT: [[TMP2514:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2514]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3674:%.*]]
|
|
// SIMD-ONLY0: if.else3673:
|
|
// SIMD-ONLY0-NEXT: [[TMP2515:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2515]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3674]]
|
|
// SIMD-ONLY0: if.end3674:
|
|
// SIMD-ONLY0-NEXT: [[TMP2516:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2516]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2517:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2518:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3675:%.*]] = icmp ugt i32 [[TMP2517]], [[TMP2518]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3675]], label [[IF_THEN3677:%.*]], label [[IF_END3678:%.*]]
|
|
// SIMD-ONLY0: if.then3677:
|
|
// SIMD-ONLY0-NEXT: [[TMP2519:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2519]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3678]]
|
|
// SIMD-ONLY0: if.end3678:
|
|
// SIMD-ONLY0-NEXT: [[TMP2520:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2520]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2521:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2522:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3679:%.*]] = icmp ugt i32 [[TMP2521]], [[TMP2522]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3679]], label [[IF_THEN3681:%.*]], label [[IF_END3682:%.*]]
|
|
// SIMD-ONLY0: if.then3681:
|
|
// SIMD-ONLY0-NEXT: [[TMP2523:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2523]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3682]]
|
|
// SIMD-ONLY0: if.end3682:
|
|
// SIMD-ONLY0-NEXT: [[TMP2524:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2524]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2525:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2526:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3683:%.*]] = icmp ult i32 [[TMP2525]], [[TMP2526]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3683]], label [[IF_THEN3685:%.*]], label [[IF_END3686:%.*]]
|
|
// SIMD-ONLY0: if.then3685:
|
|
// SIMD-ONLY0-NEXT: [[TMP2527:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2527]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3686]]
|
|
// SIMD-ONLY0: if.end3686:
|
|
// SIMD-ONLY0-NEXT: [[TMP2528:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2528]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2529:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2530:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3687:%.*]] = icmp ult i32 [[TMP2529]], [[TMP2530]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3687]], label [[IF_THEN3689:%.*]], label [[IF_END3690:%.*]]
|
|
// SIMD-ONLY0: if.then3689:
|
|
// SIMD-ONLY0-NEXT: [[TMP2531:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2531]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3690]]
|
|
// SIMD-ONLY0: if.end3690:
|
|
// SIMD-ONLY0-NEXT: [[TMP2532:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2532]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2533:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2534:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3691:%.*]] = icmp eq i32 [[TMP2533]], [[TMP2534]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3691]], label [[IF_THEN3693:%.*]], label [[IF_END3694:%.*]]
|
|
// SIMD-ONLY0: if.then3693:
|
|
// SIMD-ONLY0-NEXT: [[TMP2535:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2535]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3694]]
|
|
// SIMD-ONLY0: if.end3694:
|
|
// SIMD-ONLY0-NEXT: [[TMP2536:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2536]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2537:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2538:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3695:%.*]] = icmp eq i32 [[TMP2537]], [[TMP2538]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3695]], label [[IF_THEN3697:%.*]], label [[IF_END3698:%.*]]
|
|
// SIMD-ONLY0: if.then3697:
|
|
// SIMD-ONLY0-NEXT: [[TMP2539:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2539]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3698]]
|
|
// SIMD-ONLY0: if.end3698:
|
|
// SIMD-ONLY0-NEXT: [[TMP2540:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2541:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3699:%.*]] = icmp ugt i32 [[TMP2540]], [[TMP2541]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3699]], label [[IF_THEN3701:%.*]], label [[IF_END3702:%.*]]
|
|
// SIMD-ONLY0: if.then3701:
|
|
// SIMD-ONLY0-NEXT: [[TMP2542:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2542]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3702]]
|
|
// SIMD-ONLY0: if.end3702:
|
|
// SIMD-ONLY0-NEXT: [[TMP2543:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2543]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2544:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2545:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3703:%.*]] = icmp ugt i32 [[TMP2544]], [[TMP2545]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3703]], label [[IF_THEN3705:%.*]], label [[IF_END3706:%.*]]
|
|
// SIMD-ONLY0: if.then3705:
|
|
// SIMD-ONLY0-NEXT: [[TMP2546:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2546]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3706]]
|
|
// SIMD-ONLY0: if.end3706:
|
|
// SIMD-ONLY0-NEXT: [[TMP2547:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2547]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2548:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2549:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3707:%.*]] = icmp ult i32 [[TMP2548]], [[TMP2549]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3707]], label [[IF_THEN3709:%.*]], label [[IF_END3710:%.*]]
|
|
// SIMD-ONLY0: if.then3709:
|
|
// SIMD-ONLY0-NEXT: [[TMP2550:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2550]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3710]]
|
|
// SIMD-ONLY0: if.end3710:
|
|
// SIMD-ONLY0-NEXT: [[TMP2551:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2551]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2552:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2553:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3711:%.*]] = icmp ult i32 [[TMP2552]], [[TMP2553]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3711]], label [[IF_THEN3713:%.*]], label [[IF_END3714:%.*]]
|
|
// SIMD-ONLY0: if.then3713:
|
|
// SIMD-ONLY0-NEXT: [[TMP2554:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2554]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3714]]
|
|
// SIMD-ONLY0: if.end3714:
|
|
// SIMD-ONLY0-NEXT: [[TMP2555:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2555]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2556:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2557:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3715:%.*]] = icmp eq i32 [[TMP2556]], [[TMP2557]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3715]], label [[IF_THEN3717:%.*]], label [[IF_END3718:%.*]]
|
|
// SIMD-ONLY0: if.then3717:
|
|
// SIMD-ONLY0-NEXT: [[TMP2558:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2558]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3718]]
|
|
// SIMD-ONLY0: if.end3718:
|
|
// SIMD-ONLY0-NEXT: [[TMP2559:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2559]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2560:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2561:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3719:%.*]] = icmp eq i32 [[TMP2560]], [[TMP2561]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3719]], label [[IF_THEN3721:%.*]], label [[IF_END3722:%.*]]
|
|
// SIMD-ONLY0: if.then3721:
|
|
// SIMD-ONLY0-NEXT: [[TMP2562:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2562]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3722]]
|
|
// SIMD-ONLY0: if.end3722:
|
|
// SIMD-ONLY0-NEXT: [[TMP2563:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2563]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2564:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2565:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3723:%.*]] = icmp eq i32 [[TMP2564]], [[TMP2565]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3723]], label [[IF_THEN3725:%.*]], label [[IF_ELSE3726:%.*]]
|
|
// SIMD-ONLY0: if.then3725:
|
|
// SIMD-ONLY0-NEXT: [[TMP2566:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2566]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3727:%.*]]
|
|
// SIMD-ONLY0: if.else3726:
|
|
// SIMD-ONLY0-NEXT: [[TMP2567:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2567]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3727]]
|
|
// SIMD-ONLY0: if.end3727:
|
|
// SIMD-ONLY0-NEXT: [[TMP2568:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2569:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3728:%.*]] = icmp eq i32 [[TMP2568]], [[TMP2569]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3728]], label [[IF_THEN3730:%.*]], label [[IF_ELSE3731:%.*]]
|
|
// SIMD-ONLY0: if.then3730:
|
|
// SIMD-ONLY0-NEXT: [[TMP2570:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2570]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3732:%.*]]
|
|
// SIMD-ONLY0: if.else3731:
|
|
// SIMD-ONLY0-NEXT: [[TMP2571:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2571]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3732]]
|
|
// SIMD-ONLY0: if.end3732:
|
|
// SIMD-ONLY0-NEXT: [[TMP2572:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2573:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3733:%.*]] = icmp eq i32 [[TMP2572]], [[TMP2573]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3734:%.*]] = zext i1 [[CMP3733]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3734]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2574:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3735:%.*]] = icmp ne i32 [[TMP2574]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3735]], label [[IF_THEN3736:%.*]], label [[IF_END3737:%.*]]
|
|
// SIMD-ONLY0: if.then3736:
|
|
// SIMD-ONLY0-NEXT: [[TMP2575:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2575]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3737]]
|
|
// SIMD-ONLY0: if.end3737:
|
|
// SIMD-ONLY0-NEXT: [[TMP2576:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2577:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3738:%.*]] = icmp eq i32 [[TMP2576]], [[TMP2577]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3739:%.*]] = zext i1 [[CMP3738]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3739]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2578:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3740:%.*]] = icmp ne i32 [[TMP2578]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3740]], label [[IF_THEN3741:%.*]], label [[IF_END3742:%.*]]
|
|
// SIMD-ONLY0: if.then3741:
|
|
// SIMD-ONLY0-NEXT: [[TMP2579:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2579]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3742]]
|
|
// SIMD-ONLY0: if.end3742:
|
|
// SIMD-ONLY0-NEXT: [[TMP2580:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2581:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3743:%.*]] = icmp eq i32 [[TMP2580]], [[TMP2581]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3744:%.*]] = zext i1 [[CMP3743]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3744]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2582:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3745:%.*]] = icmp ne i32 [[TMP2582]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3745]], label [[IF_THEN3746:%.*]], label [[IF_ELSE3747:%.*]]
|
|
// SIMD-ONLY0: if.then3746:
|
|
// SIMD-ONLY0-NEXT: [[TMP2583:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2583]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3748:%.*]]
|
|
// SIMD-ONLY0: if.else3747:
|
|
// SIMD-ONLY0-NEXT: [[TMP2584:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2584]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3748]]
|
|
// SIMD-ONLY0: if.end3748:
|
|
// SIMD-ONLY0-NEXT: [[TMP2585:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2586:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3749:%.*]] = icmp eq i32 [[TMP2585]], [[TMP2586]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3750:%.*]] = zext i1 [[CMP3749]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3750]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2587:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3751:%.*]] = icmp ne i32 [[TMP2587]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3751]], label [[IF_THEN3752:%.*]], label [[IF_ELSE3753:%.*]]
|
|
// SIMD-ONLY0: if.then3752:
|
|
// SIMD-ONLY0-NEXT: [[TMP2588:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2588]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3754:%.*]]
|
|
// SIMD-ONLY0: if.else3753:
|
|
// SIMD-ONLY0-NEXT: [[TMP2589:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2589]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3754]]
|
|
// SIMD-ONLY0: if.end3754:
|
|
// SIMD-ONLY0-NEXT: [[TMP2590:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2590]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2591:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2592:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3755:%.*]] = icmp ugt i32 [[TMP2591]], [[TMP2592]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3755]], label [[IF_THEN3757:%.*]], label [[IF_END3758:%.*]]
|
|
// SIMD-ONLY0: if.then3757:
|
|
// SIMD-ONLY0-NEXT: [[TMP2593:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2593]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3758]]
|
|
// SIMD-ONLY0: if.end3758:
|
|
// SIMD-ONLY0-NEXT: [[TMP2594:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2594]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2595:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2596:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3759:%.*]] = icmp ugt i32 [[TMP2595]], [[TMP2596]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3759]], label [[IF_THEN3761:%.*]], label [[IF_END3762:%.*]]
|
|
// SIMD-ONLY0: if.then3761:
|
|
// SIMD-ONLY0-NEXT: [[TMP2597:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2597]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3762]]
|
|
// SIMD-ONLY0: if.end3762:
|
|
// SIMD-ONLY0-NEXT: [[TMP2598:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2598]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2599:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2600:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3763:%.*]] = icmp ult i32 [[TMP2599]], [[TMP2600]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3763]], label [[IF_THEN3765:%.*]], label [[IF_END3766:%.*]]
|
|
// SIMD-ONLY0: if.then3765:
|
|
// SIMD-ONLY0-NEXT: [[TMP2601:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2601]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3766]]
|
|
// SIMD-ONLY0: if.end3766:
|
|
// SIMD-ONLY0-NEXT: [[TMP2602:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2602]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2603:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2604:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3767:%.*]] = icmp ult i32 [[TMP2603]], [[TMP2604]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3767]], label [[IF_THEN3769:%.*]], label [[IF_END3770:%.*]]
|
|
// SIMD-ONLY0: if.then3769:
|
|
// SIMD-ONLY0-NEXT: [[TMP2605:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2605]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3770]]
|
|
// SIMD-ONLY0: if.end3770:
|
|
// SIMD-ONLY0-NEXT: [[TMP2606:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2606]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2607:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2608:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3771:%.*]] = icmp eq i32 [[TMP2607]], [[TMP2608]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3771]], label [[IF_THEN3773:%.*]], label [[IF_END3774:%.*]]
|
|
// SIMD-ONLY0: if.then3773:
|
|
// SIMD-ONLY0-NEXT: [[TMP2609:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2609]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3774]]
|
|
// SIMD-ONLY0: if.end3774:
|
|
// SIMD-ONLY0-NEXT: [[TMP2610:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2610]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2611:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2612:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3775:%.*]] = icmp eq i32 [[TMP2611]], [[TMP2612]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3775]], label [[IF_THEN3777:%.*]], label [[IF_END3778:%.*]]
|
|
// SIMD-ONLY0: if.then3777:
|
|
// SIMD-ONLY0-NEXT: [[TMP2613:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2613]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3778]]
|
|
// SIMD-ONLY0: if.end3778:
|
|
// SIMD-ONLY0-NEXT: [[TMP2614:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2615:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3779:%.*]] = icmp ugt i32 [[TMP2614]], [[TMP2615]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3779]], label [[IF_THEN3781:%.*]], label [[IF_END3782:%.*]]
|
|
// SIMD-ONLY0: if.then3781:
|
|
// SIMD-ONLY0-NEXT: [[TMP2616:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2616]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3782]]
|
|
// SIMD-ONLY0: if.end3782:
|
|
// SIMD-ONLY0-NEXT: [[TMP2617:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2617]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2618:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2619:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3783:%.*]] = icmp ugt i32 [[TMP2618]], [[TMP2619]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3783]], label [[IF_THEN3785:%.*]], label [[IF_END3786:%.*]]
|
|
// SIMD-ONLY0: if.then3785:
|
|
// SIMD-ONLY0-NEXT: [[TMP2620:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2620]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3786]]
|
|
// SIMD-ONLY0: if.end3786:
|
|
// SIMD-ONLY0-NEXT: [[TMP2621:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2621]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2622:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2623:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3787:%.*]] = icmp ult i32 [[TMP2622]], [[TMP2623]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3787]], label [[IF_THEN3789:%.*]], label [[IF_END3790:%.*]]
|
|
// SIMD-ONLY0: if.then3789:
|
|
// SIMD-ONLY0-NEXT: [[TMP2624:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2624]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3790]]
|
|
// SIMD-ONLY0: if.end3790:
|
|
// SIMD-ONLY0-NEXT: [[TMP2625:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2625]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2626:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2627:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3791:%.*]] = icmp ult i32 [[TMP2626]], [[TMP2627]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3791]], label [[IF_THEN3793:%.*]], label [[IF_END3794:%.*]]
|
|
// SIMD-ONLY0: if.then3793:
|
|
// SIMD-ONLY0-NEXT: [[TMP2628:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2628]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3794]]
|
|
// SIMD-ONLY0: if.end3794:
|
|
// SIMD-ONLY0-NEXT: [[TMP2629:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2629]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2630:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2631:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3795:%.*]] = icmp eq i32 [[TMP2630]], [[TMP2631]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3795]], label [[IF_THEN3797:%.*]], label [[IF_END3798:%.*]]
|
|
// SIMD-ONLY0: if.then3797:
|
|
// SIMD-ONLY0-NEXT: [[TMP2632:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2632]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3798]]
|
|
// SIMD-ONLY0: if.end3798:
|
|
// SIMD-ONLY0-NEXT: [[TMP2633:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2633]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2634:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2635:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3799:%.*]] = icmp eq i32 [[TMP2634]], [[TMP2635]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3799]], label [[IF_THEN3801:%.*]], label [[IF_END3802:%.*]]
|
|
// SIMD-ONLY0: if.then3801:
|
|
// SIMD-ONLY0-NEXT: [[TMP2636:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2636]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3802]]
|
|
// SIMD-ONLY0: if.end3802:
|
|
// SIMD-ONLY0-NEXT: [[TMP2637:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2637]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2638:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2639:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3803:%.*]] = icmp eq i32 [[TMP2638]], [[TMP2639]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3803]], label [[IF_THEN3805:%.*]], label [[IF_ELSE3806:%.*]]
|
|
// SIMD-ONLY0: if.then3805:
|
|
// SIMD-ONLY0-NEXT: [[TMP2640:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2640]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3807:%.*]]
|
|
// SIMD-ONLY0: if.else3806:
|
|
// SIMD-ONLY0-NEXT: [[TMP2641:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2641]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3807]]
|
|
// SIMD-ONLY0: if.end3807:
|
|
// SIMD-ONLY0-NEXT: [[TMP2642:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2643:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3808:%.*]] = icmp eq i32 [[TMP2642]], [[TMP2643]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3808]], label [[IF_THEN3810:%.*]], label [[IF_ELSE3811:%.*]]
|
|
// SIMD-ONLY0: if.then3810:
|
|
// SIMD-ONLY0-NEXT: [[TMP2644:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2644]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3812:%.*]]
|
|
// SIMD-ONLY0: if.else3811:
|
|
// SIMD-ONLY0-NEXT: [[TMP2645:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2645]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3812]]
|
|
// SIMD-ONLY0: if.end3812:
|
|
// SIMD-ONLY0-NEXT: [[TMP2646:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2647:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3813:%.*]] = icmp eq i32 [[TMP2646]], [[TMP2647]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3814:%.*]] = zext i1 [[CMP3813]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3814]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2648:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3815:%.*]] = icmp ne i32 [[TMP2648]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3815]], label [[IF_THEN3816:%.*]], label [[IF_END3817:%.*]]
|
|
// SIMD-ONLY0: if.then3816:
|
|
// SIMD-ONLY0-NEXT: [[TMP2649:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2649]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3817]]
|
|
// SIMD-ONLY0: if.end3817:
|
|
// SIMD-ONLY0-NEXT: [[TMP2650:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2651:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3818:%.*]] = icmp eq i32 [[TMP2650]], [[TMP2651]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3819:%.*]] = zext i1 [[CMP3818]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3819]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2652:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3820:%.*]] = icmp ne i32 [[TMP2652]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3820]], label [[IF_THEN3821:%.*]], label [[IF_END3822:%.*]]
|
|
// SIMD-ONLY0: if.then3821:
|
|
// SIMD-ONLY0-NEXT: [[TMP2653:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2653]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3822]]
|
|
// SIMD-ONLY0: if.end3822:
|
|
// SIMD-ONLY0-NEXT: [[TMP2654:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2655:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3823:%.*]] = icmp eq i32 [[TMP2654]], [[TMP2655]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3824:%.*]] = zext i1 [[CMP3823]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3824]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2656:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3825:%.*]] = icmp ne i32 [[TMP2656]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3825]], label [[IF_THEN3826:%.*]], label [[IF_ELSE3827:%.*]]
|
|
// SIMD-ONLY0: if.then3826:
|
|
// SIMD-ONLY0-NEXT: [[TMP2657:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2657]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3828:%.*]]
|
|
// SIMD-ONLY0: if.else3827:
|
|
// SIMD-ONLY0-NEXT: [[TMP2658:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2658]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3828]]
|
|
// SIMD-ONLY0: if.end3828:
|
|
// SIMD-ONLY0-NEXT: [[TMP2659:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2660:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP3829:%.*]] = icmp eq i32 [[TMP2659]], [[TMP2660]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3830:%.*]] = zext i1 [[CMP3829]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV3830]], ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2661:%.*]] = load i32, ptr [[UIR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3831:%.*]] = icmp ne i32 [[TMP2661]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3831]], label [[IF_THEN3832:%.*]], label [[IF_ELSE3833:%.*]]
|
|
// SIMD-ONLY0: if.then3832:
|
|
// SIMD-ONLY0-NEXT: [[TMP2662:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2662]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3834:%.*]]
|
|
// SIMD-ONLY0: if.else3833:
|
|
// SIMD-ONLY0-NEXT: [[TMP2663:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP2663]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3834]]
|
|
// SIMD-ONLY0: if.end3834:
|
|
// SIMD-ONLY0-NEXT: [[TMP2664:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2664]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2665:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2666:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3835:%.*]] = icmp sgt i64 [[TMP2665]], [[TMP2666]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3835]], label [[IF_THEN3837:%.*]], label [[IF_END3838:%.*]]
|
|
// SIMD-ONLY0: if.then3837:
|
|
// SIMD-ONLY0-NEXT: [[TMP2667:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2667]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3838]]
|
|
// SIMD-ONLY0: if.end3838:
|
|
// SIMD-ONLY0-NEXT: [[TMP2668:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2668]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2669:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2670:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3839:%.*]] = icmp sgt i64 [[TMP2669]], [[TMP2670]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3839]], label [[IF_THEN3841:%.*]], label [[IF_END3842:%.*]]
|
|
// SIMD-ONLY0: if.then3841:
|
|
// SIMD-ONLY0-NEXT: [[TMP2671:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2671]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3842]]
|
|
// SIMD-ONLY0: if.end3842:
|
|
// SIMD-ONLY0-NEXT: [[TMP2672:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2672]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2673:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2674:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3843:%.*]] = icmp slt i64 [[TMP2673]], [[TMP2674]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3843]], label [[IF_THEN3845:%.*]], label [[IF_END3846:%.*]]
|
|
// SIMD-ONLY0: if.then3845:
|
|
// SIMD-ONLY0-NEXT: [[TMP2675:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2675]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3846]]
|
|
// SIMD-ONLY0: if.end3846:
|
|
// SIMD-ONLY0-NEXT: [[TMP2676:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2676]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2677:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2678:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3847:%.*]] = icmp slt i64 [[TMP2677]], [[TMP2678]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3847]], label [[IF_THEN3849:%.*]], label [[IF_END3850:%.*]]
|
|
// SIMD-ONLY0: if.then3849:
|
|
// SIMD-ONLY0-NEXT: [[TMP2679:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2679]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3850]]
|
|
// SIMD-ONLY0: if.end3850:
|
|
// SIMD-ONLY0-NEXT: [[TMP2680:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2680]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2681:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2682:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3851:%.*]] = icmp eq i64 [[TMP2681]], [[TMP2682]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3851]], label [[IF_THEN3853:%.*]], label [[IF_END3854:%.*]]
|
|
// SIMD-ONLY0: if.then3853:
|
|
// SIMD-ONLY0-NEXT: [[TMP2683:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2683]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3854]]
|
|
// SIMD-ONLY0: if.end3854:
|
|
// SIMD-ONLY0-NEXT: [[TMP2684:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2684]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2685:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2686:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3855:%.*]] = icmp eq i64 [[TMP2685]], [[TMP2686]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3855]], label [[IF_THEN3857:%.*]], label [[IF_END3858:%.*]]
|
|
// SIMD-ONLY0: if.then3857:
|
|
// SIMD-ONLY0-NEXT: [[TMP2687:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2687]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3858]]
|
|
// SIMD-ONLY0: if.end3858:
|
|
// SIMD-ONLY0-NEXT: [[TMP2688:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2689:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3859:%.*]] = icmp sgt i64 [[TMP2688]], [[TMP2689]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3859]], label [[IF_THEN3861:%.*]], label [[IF_END3862:%.*]]
|
|
// SIMD-ONLY0: if.then3861:
|
|
// SIMD-ONLY0-NEXT: [[TMP2690:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2690]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3862]]
|
|
// SIMD-ONLY0: if.end3862:
|
|
// SIMD-ONLY0-NEXT: [[TMP2691:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2691]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2692:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2693:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3863:%.*]] = icmp sgt i64 [[TMP2692]], [[TMP2693]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3863]], label [[IF_THEN3865:%.*]], label [[IF_END3866:%.*]]
|
|
// SIMD-ONLY0: if.then3865:
|
|
// SIMD-ONLY0-NEXT: [[TMP2694:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2694]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3866]]
|
|
// SIMD-ONLY0: if.end3866:
|
|
// SIMD-ONLY0-NEXT: [[TMP2695:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2695]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2696:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2697:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3867:%.*]] = icmp slt i64 [[TMP2696]], [[TMP2697]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3867]], label [[IF_THEN3869:%.*]], label [[IF_END3870:%.*]]
|
|
// SIMD-ONLY0: if.then3869:
|
|
// SIMD-ONLY0-NEXT: [[TMP2698:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2698]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3870]]
|
|
// SIMD-ONLY0: if.end3870:
|
|
// SIMD-ONLY0-NEXT: [[TMP2699:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2699]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2700:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2701:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3871:%.*]] = icmp slt i64 [[TMP2700]], [[TMP2701]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3871]], label [[IF_THEN3873:%.*]], label [[IF_END3874:%.*]]
|
|
// SIMD-ONLY0: if.then3873:
|
|
// SIMD-ONLY0-NEXT: [[TMP2702:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2702]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3874]]
|
|
// SIMD-ONLY0: if.end3874:
|
|
// SIMD-ONLY0-NEXT: [[TMP2703:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2703]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2704:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2705:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3875:%.*]] = icmp eq i64 [[TMP2704]], [[TMP2705]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3875]], label [[IF_THEN3877:%.*]], label [[IF_END3878:%.*]]
|
|
// SIMD-ONLY0: if.then3877:
|
|
// SIMD-ONLY0-NEXT: [[TMP2706:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2706]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3878]]
|
|
// SIMD-ONLY0: if.end3878:
|
|
// SIMD-ONLY0-NEXT: [[TMP2707:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2707]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2708:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2709:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3879:%.*]] = icmp eq i64 [[TMP2708]], [[TMP2709]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3879]], label [[IF_THEN3881:%.*]], label [[IF_END3882:%.*]]
|
|
// SIMD-ONLY0: if.then3881:
|
|
// SIMD-ONLY0-NEXT: [[TMP2710:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2710]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3882]]
|
|
// SIMD-ONLY0: if.end3882:
|
|
// SIMD-ONLY0-NEXT: [[TMP2711:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2711]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2712:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2713:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3883:%.*]] = icmp eq i64 [[TMP2712]], [[TMP2713]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3883]], label [[IF_THEN3885:%.*]], label [[IF_ELSE3886:%.*]]
|
|
// SIMD-ONLY0: if.then3885:
|
|
// SIMD-ONLY0-NEXT: [[TMP2714:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2714]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3887:%.*]]
|
|
// SIMD-ONLY0: if.else3886:
|
|
// SIMD-ONLY0-NEXT: [[TMP2715:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2715]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3887]]
|
|
// SIMD-ONLY0: if.end3887:
|
|
// SIMD-ONLY0-NEXT: [[TMP2716:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2717:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3888:%.*]] = icmp eq i64 [[TMP2716]], [[TMP2717]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3888]], label [[IF_THEN3890:%.*]], label [[IF_ELSE3891:%.*]]
|
|
// SIMD-ONLY0: if.then3890:
|
|
// SIMD-ONLY0-NEXT: [[TMP2718:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2718]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3892:%.*]]
|
|
// SIMD-ONLY0: if.else3891:
|
|
// SIMD-ONLY0-NEXT: [[TMP2719:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2719]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3892]]
|
|
// SIMD-ONLY0: if.end3892:
|
|
// SIMD-ONLY0-NEXT: [[TMP2720:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2721:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3893:%.*]] = icmp eq i64 [[TMP2720]], [[TMP2721]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3894:%.*]] = zext i1 [[CMP3893]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV3895:%.*]] = sext i32 [[CONV3894]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV3895]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2722:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3896:%.*]] = icmp ne i64 [[TMP2722]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3896]], label [[IF_THEN3897:%.*]], label [[IF_END3898:%.*]]
|
|
// SIMD-ONLY0: if.then3897:
|
|
// SIMD-ONLY0-NEXT: [[TMP2723:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2723]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3898]]
|
|
// SIMD-ONLY0: if.end3898:
|
|
// SIMD-ONLY0-NEXT: [[TMP2724:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2725:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3899:%.*]] = icmp eq i64 [[TMP2724]], [[TMP2725]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3900:%.*]] = zext i1 [[CMP3899]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV3901:%.*]] = sext i32 [[CONV3900]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV3901]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2726:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3902:%.*]] = icmp ne i64 [[TMP2726]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3902]], label [[IF_THEN3903:%.*]], label [[IF_END3904:%.*]]
|
|
// SIMD-ONLY0: if.then3903:
|
|
// SIMD-ONLY0-NEXT: [[TMP2727:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2727]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3904]]
|
|
// SIMD-ONLY0: if.end3904:
|
|
// SIMD-ONLY0-NEXT: [[TMP2728:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2729:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3905:%.*]] = icmp eq i64 [[TMP2728]], [[TMP2729]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3906:%.*]] = zext i1 [[CMP3905]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV3907:%.*]] = sext i32 [[CONV3906]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV3907]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2730:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3908:%.*]] = icmp ne i64 [[TMP2730]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3908]], label [[IF_THEN3909:%.*]], label [[IF_ELSE3910:%.*]]
|
|
// SIMD-ONLY0: if.then3909:
|
|
// SIMD-ONLY0-NEXT: [[TMP2731:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2731]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3911:%.*]]
|
|
// SIMD-ONLY0: if.else3910:
|
|
// SIMD-ONLY0-NEXT: [[TMP2732:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2732]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3911]]
|
|
// SIMD-ONLY0: if.end3911:
|
|
// SIMD-ONLY0-NEXT: [[TMP2733:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2734:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3912:%.*]] = icmp eq i64 [[TMP2733]], [[TMP2734]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3913:%.*]] = zext i1 [[CMP3912]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV3914:%.*]] = sext i32 [[CONV3913]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV3914]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2735:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3915:%.*]] = icmp ne i64 [[TMP2735]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3915]], label [[IF_THEN3916:%.*]], label [[IF_ELSE3917:%.*]]
|
|
// SIMD-ONLY0: if.then3916:
|
|
// SIMD-ONLY0-NEXT: [[TMP2736:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2736]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3918:%.*]]
|
|
// SIMD-ONLY0: if.else3917:
|
|
// SIMD-ONLY0-NEXT: [[TMP2737:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2737]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3918]]
|
|
// SIMD-ONLY0: if.end3918:
|
|
// SIMD-ONLY0-NEXT: [[TMP2738:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2738]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2739:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2740:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3919:%.*]] = icmp sgt i64 [[TMP2739]], [[TMP2740]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3919]], label [[IF_THEN3921:%.*]], label [[IF_END3922:%.*]]
|
|
// SIMD-ONLY0: if.then3921:
|
|
// SIMD-ONLY0-NEXT: [[TMP2741:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2741]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3922]]
|
|
// SIMD-ONLY0: if.end3922:
|
|
// SIMD-ONLY0-NEXT: [[TMP2742:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2742]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2743:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2744:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3923:%.*]] = icmp sgt i64 [[TMP2743]], [[TMP2744]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3923]], label [[IF_THEN3925:%.*]], label [[IF_END3926:%.*]]
|
|
// SIMD-ONLY0: if.then3925:
|
|
// SIMD-ONLY0-NEXT: [[TMP2745:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2745]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3926]]
|
|
// SIMD-ONLY0: if.end3926:
|
|
// SIMD-ONLY0-NEXT: [[TMP2746:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2746]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2747:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2748:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3927:%.*]] = icmp slt i64 [[TMP2747]], [[TMP2748]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3927]], label [[IF_THEN3929:%.*]], label [[IF_END3930:%.*]]
|
|
// SIMD-ONLY0: if.then3929:
|
|
// SIMD-ONLY0-NEXT: [[TMP2749:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2749]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3930]]
|
|
// SIMD-ONLY0: if.end3930:
|
|
// SIMD-ONLY0-NEXT: [[TMP2750:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2750]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2751:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2752:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3931:%.*]] = icmp slt i64 [[TMP2751]], [[TMP2752]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3931]], label [[IF_THEN3933:%.*]], label [[IF_END3934:%.*]]
|
|
// SIMD-ONLY0: if.then3933:
|
|
// SIMD-ONLY0-NEXT: [[TMP2753:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2753]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3934]]
|
|
// SIMD-ONLY0: if.end3934:
|
|
// SIMD-ONLY0-NEXT: [[TMP2754:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2754]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2755:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2756:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3935:%.*]] = icmp eq i64 [[TMP2755]], [[TMP2756]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3935]], label [[IF_THEN3937:%.*]], label [[IF_END3938:%.*]]
|
|
// SIMD-ONLY0: if.then3937:
|
|
// SIMD-ONLY0-NEXT: [[TMP2757:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2757]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3938]]
|
|
// SIMD-ONLY0: if.end3938:
|
|
// SIMD-ONLY0-NEXT: [[TMP2758:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2758]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2759:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2760:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3939:%.*]] = icmp eq i64 [[TMP2759]], [[TMP2760]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3939]], label [[IF_THEN3941:%.*]], label [[IF_END3942:%.*]]
|
|
// SIMD-ONLY0: if.then3941:
|
|
// SIMD-ONLY0-NEXT: [[TMP2761:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2761]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3942]]
|
|
// SIMD-ONLY0: if.end3942:
|
|
// SIMD-ONLY0-NEXT: [[TMP2762:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2763:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3943:%.*]] = icmp sgt i64 [[TMP2762]], [[TMP2763]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3943]], label [[IF_THEN3945:%.*]], label [[IF_END3946:%.*]]
|
|
// SIMD-ONLY0: if.then3945:
|
|
// SIMD-ONLY0-NEXT: [[TMP2764:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2764]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3946]]
|
|
// SIMD-ONLY0: if.end3946:
|
|
// SIMD-ONLY0-NEXT: [[TMP2765:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2765]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2766:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2767:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3947:%.*]] = icmp sgt i64 [[TMP2766]], [[TMP2767]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3947]], label [[IF_THEN3949:%.*]], label [[IF_END3950:%.*]]
|
|
// SIMD-ONLY0: if.then3949:
|
|
// SIMD-ONLY0-NEXT: [[TMP2768:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2768]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3950]]
|
|
// SIMD-ONLY0: if.end3950:
|
|
// SIMD-ONLY0-NEXT: [[TMP2769:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2769]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2770:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2771:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3951:%.*]] = icmp slt i64 [[TMP2770]], [[TMP2771]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3951]], label [[IF_THEN3953:%.*]], label [[IF_END3954:%.*]]
|
|
// SIMD-ONLY0: if.then3953:
|
|
// SIMD-ONLY0-NEXT: [[TMP2772:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2772]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3954]]
|
|
// SIMD-ONLY0: if.end3954:
|
|
// SIMD-ONLY0-NEXT: [[TMP2773:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2773]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2774:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2775:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3955:%.*]] = icmp slt i64 [[TMP2774]], [[TMP2775]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3955]], label [[IF_THEN3957:%.*]], label [[IF_END3958:%.*]]
|
|
// SIMD-ONLY0: if.then3957:
|
|
// SIMD-ONLY0-NEXT: [[TMP2776:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2776]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3958]]
|
|
// SIMD-ONLY0: if.end3958:
|
|
// SIMD-ONLY0-NEXT: [[TMP2777:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2777]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2778:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2779:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3959:%.*]] = icmp eq i64 [[TMP2778]], [[TMP2779]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3959]], label [[IF_THEN3961:%.*]], label [[IF_END3962:%.*]]
|
|
// SIMD-ONLY0: if.then3961:
|
|
// SIMD-ONLY0-NEXT: [[TMP2780:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2780]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3962]]
|
|
// SIMD-ONLY0: if.end3962:
|
|
// SIMD-ONLY0-NEXT: [[TMP2781:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2781]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2782:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2783:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3963:%.*]] = icmp eq i64 [[TMP2782]], [[TMP2783]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3963]], label [[IF_THEN3965:%.*]], label [[IF_END3966:%.*]]
|
|
// SIMD-ONLY0: if.then3965:
|
|
// SIMD-ONLY0-NEXT: [[TMP2784:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2784]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3966]]
|
|
// SIMD-ONLY0: if.end3966:
|
|
// SIMD-ONLY0-NEXT: [[TMP2785:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2785]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2786:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2787:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3967:%.*]] = icmp eq i64 [[TMP2786]], [[TMP2787]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3967]], label [[IF_THEN3969:%.*]], label [[IF_ELSE3970:%.*]]
|
|
// SIMD-ONLY0: if.then3969:
|
|
// SIMD-ONLY0-NEXT: [[TMP2788:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2788]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3971:%.*]]
|
|
// SIMD-ONLY0: if.else3970:
|
|
// SIMD-ONLY0-NEXT: [[TMP2789:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2789]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3971]]
|
|
// SIMD-ONLY0: if.end3971:
|
|
// SIMD-ONLY0-NEXT: [[TMP2790:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2791:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3972:%.*]] = icmp eq i64 [[TMP2790]], [[TMP2791]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP3972]], label [[IF_THEN3974:%.*]], label [[IF_ELSE3975:%.*]]
|
|
// SIMD-ONLY0: if.then3974:
|
|
// SIMD-ONLY0-NEXT: [[TMP2792:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2792]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3976:%.*]]
|
|
// SIMD-ONLY0: if.else3975:
|
|
// SIMD-ONLY0-NEXT: [[TMP2793:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2793]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3976]]
|
|
// SIMD-ONLY0: if.end3976:
|
|
// SIMD-ONLY0-NEXT: [[TMP2794:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2795:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3977:%.*]] = icmp eq i64 [[TMP2794]], [[TMP2795]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3978:%.*]] = zext i1 [[CMP3977]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV3979:%.*]] = sext i32 [[CONV3978]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV3979]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2796:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3980:%.*]] = icmp ne i64 [[TMP2796]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3980]], label [[IF_THEN3981:%.*]], label [[IF_END3982:%.*]]
|
|
// SIMD-ONLY0: if.then3981:
|
|
// SIMD-ONLY0-NEXT: [[TMP2797:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2797]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3982]]
|
|
// SIMD-ONLY0: if.end3982:
|
|
// SIMD-ONLY0-NEXT: [[TMP2798:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2799:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3983:%.*]] = icmp eq i64 [[TMP2798]], [[TMP2799]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3984:%.*]] = zext i1 [[CMP3983]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV3985:%.*]] = sext i32 [[CONV3984]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV3985]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2800:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3986:%.*]] = icmp ne i64 [[TMP2800]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3986]], label [[IF_THEN3987:%.*]], label [[IF_END3988:%.*]]
|
|
// SIMD-ONLY0: if.then3987:
|
|
// SIMD-ONLY0-NEXT: [[TMP2801:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2801]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3988]]
|
|
// SIMD-ONLY0: if.end3988:
|
|
// SIMD-ONLY0-NEXT: [[TMP2802:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2803:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3989:%.*]] = icmp eq i64 [[TMP2802]], [[TMP2803]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3990:%.*]] = zext i1 [[CMP3989]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV3991:%.*]] = sext i32 [[CONV3990]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV3991]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2804:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3992:%.*]] = icmp ne i64 [[TMP2804]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3992]], label [[IF_THEN3993:%.*]], label [[IF_ELSE3994:%.*]]
|
|
// SIMD-ONLY0: if.then3993:
|
|
// SIMD-ONLY0-NEXT: [[TMP2805:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2805]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3995:%.*]]
|
|
// SIMD-ONLY0: if.else3994:
|
|
// SIMD-ONLY0-NEXT: [[TMP2806:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2806]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END3995]]
|
|
// SIMD-ONLY0: if.end3995:
|
|
// SIMD-ONLY0-NEXT: [[TMP2807:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2808:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP3996:%.*]] = icmp eq i64 [[TMP2807]], [[TMP2808]]
|
|
// SIMD-ONLY0-NEXT: [[CONV3997:%.*]] = zext i1 [[CMP3996]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV3998:%.*]] = sext i32 [[CONV3997]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV3998]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2809:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL3999:%.*]] = icmp ne i64 [[TMP2809]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL3999]], label [[IF_THEN4000:%.*]], label [[IF_ELSE4001:%.*]]
|
|
// SIMD-ONLY0: if.then4000:
|
|
// SIMD-ONLY0-NEXT: [[TMP2810:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2810]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4002:%.*]]
|
|
// SIMD-ONLY0: if.else4001:
|
|
// SIMD-ONLY0-NEXT: [[TMP2811:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2811]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4002]]
|
|
// SIMD-ONLY0: if.end4002:
|
|
// SIMD-ONLY0-NEXT: [[TMP2812:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2812]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2813:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2814:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4003:%.*]] = icmp sgt i64 [[TMP2813]], [[TMP2814]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4003]], label [[IF_THEN4005:%.*]], label [[IF_END4006:%.*]]
|
|
// SIMD-ONLY0: if.then4005:
|
|
// SIMD-ONLY0-NEXT: [[TMP2815:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2815]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4006]]
|
|
// SIMD-ONLY0: if.end4006:
|
|
// SIMD-ONLY0-NEXT: [[TMP2816:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2816]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2817:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2818:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4007:%.*]] = icmp sgt i64 [[TMP2817]], [[TMP2818]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4007]], label [[IF_THEN4009:%.*]], label [[IF_END4010:%.*]]
|
|
// SIMD-ONLY0: if.then4009:
|
|
// SIMD-ONLY0-NEXT: [[TMP2819:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2819]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4010]]
|
|
// SIMD-ONLY0: if.end4010:
|
|
// SIMD-ONLY0-NEXT: [[TMP2820:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2820]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2821:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2822:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4011:%.*]] = icmp slt i64 [[TMP2821]], [[TMP2822]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4011]], label [[IF_THEN4013:%.*]], label [[IF_END4014:%.*]]
|
|
// SIMD-ONLY0: if.then4013:
|
|
// SIMD-ONLY0-NEXT: [[TMP2823:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2823]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4014]]
|
|
// SIMD-ONLY0: if.end4014:
|
|
// SIMD-ONLY0-NEXT: [[TMP2824:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2824]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2825:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2826:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4015:%.*]] = icmp slt i64 [[TMP2825]], [[TMP2826]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4015]], label [[IF_THEN4017:%.*]], label [[IF_END4018:%.*]]
|
|
// SIMD-ONLY0: if.then4017:
|
|
// SIMD-ONLY0-NEXT: [[TMP2827:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2827]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4018]]
|
|
// SIMD-ONLY0: if.end4018:
|
|
// SIMD-ONLY0-NEXT: [[TMP2828:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2828]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2829:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2830:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4019:%.*]] = icmp eq i64 [[TMP2829]], [[TMP2830]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4019]], label [[IF_THEN4021:%.*]], label [[IF_END4022:%.*]]
|
|
// SIMD-ONLY0: if.then4021:
|
|
// SIMD-ONLY0-NEXT: [[TMP2831:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2831]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4022]]
|
|
// SIMD-ONLY0: if.end4022:
|
|
// SIMD-ONLY0-NEXT: [[TMP2832:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2832]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2833:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2834:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4023:%.*]] = icmp eq i64 [[TMP2833]], [[TMP2834]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4023]], label [[IF_THEN4025:%.*]], label [[IF_END4026:%.*]]
|
|
// SIMD-ONLY0: if.then4025:
|
|
// SIMD-ONLY0-NEXT: [[TMP2835:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2835]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4026]]
|
|
// SIMD-ONLY0: if.end4026:
|
|
// SIMD-ONLY0-NEXT: [[TMP2836:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2837:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4027:%.*]] = icmp sgt i64 [[TMP2836]], [[TMP2837]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4027]], label [[IF_THEN4029:%.*]], label [[IF_END4030:%.*]]
|
|
// SIMD-ONLY0: if.then4029:
|
|
// SIMD-ONLY0-NEXT: [[TMP2838:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2838]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4030]]
|
|
// SIMD-ONLY0: if.end4030:
|
|
// SIMD-ONLY0-NEXT: [[TMP2839:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2839]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2840:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2841:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4031:%.*]] = icmp sgt i64 [[TMP2840]], [[TMP2841]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4031]], label [[IF_THEN4033:%.*]], label [[IF_END4034:%.*]]
|
|
// SIMD-ONLY0: if.then4033:
|
|
// SIMD-ONLY0-NEXT: [[TMP2842:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2842]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4034]]
|
|
// SIMD-ONLY0: if.end4034:
|
|
// SIMD-ONLY0-NEXT: [[TMP2843:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2843]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2844:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2845:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4035:%.*]] = icmp slt i64 [[TMP2844]], [[TMP2845]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4035]], label [[IF_THEN4037:%.*]], label [[IF_END4038:%.*]]
|
|
// SIMD-ONLY0: if.then4037:
|
|
// SIMD-ONLY0-NEXT: [[TMP2846:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2846]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4038]]
|
|
// SIMD-ONLY0: if.end4038:
|
|
// SIMD-ONLY0-NEXT: [[TMP2847:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2847]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2848:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2849:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4039:%.*]] = icmp slt i64 [[TMP2848]], [[TMP2849]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4039]], label [[IF_THEN4041:%.*]], label [[IF_END4042:%.*]]
|
|
// SIMD-ONLY0: if.then4041:
|
|
// SIMD-ONLY0-NEXT: [[TMP2850:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2850]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4042]]
|
|
// SIMD-ONLY0: if.end4042:
|
|
// SIMD-ONLY0-NEXT: [[TMP2851:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2851]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2852:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2853:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4043:%.*]] = icmp eq i64 [[TMP2852]], [[TMP2853]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4043]], label [[IF_THEN4045:%.*]], label [[IF_END4046:%.*]]
|
|
// SIMD-ONLY0: if.then4045:
|
|
// SIMD-ONLY0-NEXT: [[TMP2854:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2854]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4046]]
|
|
// SIMD-ONLY0: if.end4046:
|
|
// SIMD-ONLY0-NEXT: [[TMP2855:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2855]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2856:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2857:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4047:%.*]] = icmp eq i64 [[TMP2856]], [[TMP2857]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4047]], label [[IF_THEN4049:%.*]], label [[IF_END4050:%.*]]
|
|
// SIMD-ONLY0: if.then4049:
|
|
// SIMD-ONLY0-NEXT: [[TMP2858:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2858]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4050]]
|
|
// SIMD-ONLY0: if.end4050:
|
|
// SIMD-ONLY0-NEXT: [[TMP2859:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2859]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2860:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2861:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4051:%.*]] = icmp eq i64 [[TMP2860]], [[TMP2861]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4051]], label [[IF_THEN4053:%.*]], label [[IF_ELSE4054:%.*]]
|
|
// SIMD-ONLY0: if.then4053:
|
|
// SIMD-ONLY0-NEXT: [[TMP2862:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2862]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4055:%.*]]
|
|
// SIMD-ONLY0: if.else4054:
|
|
// SIMD-ONLY0-NEXT: [[TMP2863:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2863]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4055]]
|
|
// SIMD-ONLY0: if.end4055:
|
|
// SIMD-ONLY0-NEXT: [[TMP2864:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2865:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4056:%.*]] = icmp eq i64 [[TMP2864]], [[TMP2865]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4056]], label [[IF_THEN4058:%.*]], label [[IF_ELSE4059:%.*]]
|
|
// SIMD-ONLY0: if.then4058:
|
|
// SIMD-ONLY0-NEXT: [[TMP2866:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2866]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4060:%.*]]
|
|
// SIMD-ONLY0: if.else4059:
|
|
// SIMD-ONLY0-NEXT: [[TMP2867:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2867]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4060]]
|
|
// SIMD-ONLY0: if.end4060:
|
|
// SIMD-ONLY0-NEXT: [[TMP2868:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2869:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4061:%.*]] = icmp eq i64 [[TMP2868]], [[TMP2869]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4062:%.*]] = zext i1 [[CMP4061]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4063:%.*]] = sext i32 [[CONV4062]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4063]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2870:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4064:%.*]] = icmp ne i64 [[TMP2870]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4064]], label [[IF_THEN4065:%.*]], label [[IF_END4066:%.*]]
|
|
// SIMD-ONLY0: if.then4065:
|
|
// SIMD-ONLY0-NEXT: [[TMP2871:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2871]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4066]]
|
|
// SIMD-ONLY0: if.end4066:
|
|
// SIMD-ONLY0-NEXT: [[TMP2872:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2873:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4067:%.*]] = icmp eq i64 [[TMP2872]], [[TMP2873]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4068:%.*]] = zext i1 [[CMP4067]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4069:%.*]] = sext i32 [[CONV4068]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4069]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2874:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4070:%.*]] = icmp ne i64 [[TMP2874]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4070]], label [[IF_THEN4071:%.*]], label [[IF_END4072:%.*]]
|
|
// SIMD-ONLY0: if.then4071:
|
|
// SIMD-ONLY0-NEXT: [[TMP2875:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2875]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4072]]
|
|
// SIMD-ONLY0: if.end4072:
|
|
// SIMD-ONLY0-NEXT: [[TMP2876:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2877:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4073:%.*]] = icmp eq i64 [[TMP2876]], [[TMP2877]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4074:%.*]] = zext i1 [[CMP4073]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4075:%.*]] = sext i32 [[CONV4074]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4075]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2878:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4076:%.*]] = icmp ne i64 [[TMP2878]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4076]], label [[IF_THEN4077:%.*]], label [[IF_ELSE4078:%.*]]
|
|
// SIMD-ONLY0: if.then4077:
|
|
// SIMD-ONLY0-NEXT: [[TMP2879:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2879]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4079:%.*]]
|
|
// SIMD-ONLY0: if.else4078:
|
|
// SIMD-ONLY0-NEXT: [[TMP2880:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2880]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4079]]
|
|
// SIMD-ONLY0: if.end4079:
|
|
// SIMD-ONLY0-NEXT: [[TMP2881:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2882:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4080:%.*]] = icmp eq i64 [[TMP2881]], [[TMP2882]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4081:%.*]] = zext i1 [[CMP4080]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4082:%.*]] = sext i32 [[CONV4081]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4082]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2883:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4083:%.*]] = icmp ne i64 [[TMP2883]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4083]], label [[IF_THEN4084:%.*]], label [[IF_ELSE4085:%.*]]
|
|
// SIMD-ONLY0: if.then4084:
|
|
// SIMD-ONLY0-NEXT: [[TMP2884:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2884]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4086:%.*]]
|
|
// SIMD-ONLY0: if.else4085:
|
|
// SIMD-ONLY0-NEXT: [[TMP2885:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2885]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4086]]
|
|
// SIMD-ONLY0: if.end4086:
|
|
// SIMD-ONLY0-NEXT: [[TMP2886:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2886]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2887:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2888:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4087:%.*]] = icmp sgt i64 [[TMP2887]], [[TMP2888]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4087]], label [[IF_THEN4089:%.*]], label [[IF_END4090:%.*]]
|
|
// SIMD-ONLY0: if.then4089:
|
|
// SIMD-ONLY0-NEXT: [[TMP2889:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2889]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4090]]
|
|
// SIMD-ONLY0: if.end4090:
|
|
// SIMD-ONLY0-NEXT: [[TMP2890:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2890]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2891:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2892:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4091:%.*]] = icmp sgt i64 [[TMP2891]], [[TMP2892]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4091]], label [[IF_THEN4093:%.*]], label [[IF_END4094:%.*]]
|
|
// SIMD-ONLY0: if.then4093:
|
|
// SIMD-ONLY0-NEXT: [[TMP2893:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2893]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4094]]
|
|
// SIMD-ONLY0: if.end4094:
|
|
// SIMD-ONLY0-NEXT: [[TMP2894:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2894]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2895:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2896:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4095:%.*]] = icmp slt i64 [[TMP2895]], [[TMP2896]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4095]], label [[IF_THEN4097:%.*]], label [[IF_END4098:%.*]]
|
|
// SIMD-ONLY0: if.then4097:
|
|
// SIMD-ONLY0-NEXT: [[TMP2897:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2897]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4098]]
|
|
// SIMD-ONLY0: if.end4098:
|
|
// SIMD-ONLY0-NEXT: [[TMP2898:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2898]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2899:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2900:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4099:%.*]] = icmp slt i64 [[TMP2899]], [[TMP2900]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4099]], label [[IF_THEN4101:%.*]], label [[IF_END4102:%.*]]
|
|
// SIMD-ONLY0: if.then4101:
|
|
// SIMD-ONLY0-NEXT: [[TMP2901:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2901]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4102]]
|
|
// SIMD-ONLY0: if.end4102:
|
|
// SIMD-ONLY0-NEXT: [[TMP2902:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2902]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2903:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2904:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4103:%.*]] = icmp eq i64 [[TMP2903]], [[TMP2904]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4103]], label [[IF_THEN4105:%.*]], label [[IF_END4106:%.*]]
|
|
// SIMD-ONLY0: if.then4105:
|
|
// SIMD-ONLY0-NEXT: [[TMP2905:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2905]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4106]]
|
|
// SIMD-ONLY0: if.end4106:
|
|
// SIMD-ONLY0-NEXT: [[TMP2906:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2906]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2907:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2908:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4107:%.*]] = icmp eq i64 [[TMP2907]], [[TMP2908]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4107]], label [[IF_THEN4109:%.*]], label [[IF_END4110:%.*]]
|
|
// SIMD-ONLY0: if.then4109:
|
|
// SIMD-ONLY0-NEXT: [[TMP2909:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2909]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4110]]
|
|
// SIMD-ONLY0: if.end4110:
|
|
// SIMD-ONLY0-NEXT: [[TMP2910:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2911:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4111:%.*]] = icmp sgt i64 [[TMP2910]], [[TMP2911]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4111]], label [[IF_THEN4113:%.*]], label [[IF_END4114:%.*]]
|
|
// SIMD-ONLY0: if.then4113:
|
|
// SIMD-ONLY0-NEXT: [[TMP2912:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2912]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4114]]
|
|
// SIMD-ONLY0: if.end4114:
|
|
// SIMD-ONLY0-NEXT: [[TMP2913:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2913]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2914:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2915:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4115:%.*]] = icmp sgt i64 [[TMP2914]], [[TMP2915]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4115]], label [[IF_THEN4117:%.*]], label [[IF_END4118:%.*]]
|
|
// SIMD-ONLY0: if.then4117:
|
|
// SIMD-ONLY0-NEXT: [[TMP2916:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2916]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4118]]
|
|
// SIMD-ONLY0: if.end4118:
|
|
// SIMD-ONLY0-NEXT: [[TMP2917:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2917]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2918:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2919:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4119:%.*]] = icmp slt i64 [[TMP2918]], [[TMP2919]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4119]], label [[IF_THEN4121:%.*]], label [[IF_END4122:%.*]]
|
|
// SIMD-ONLY0: if.then4121:
|
|
// SIMD-ONLY0-NEXT: [[TMP2920:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2920]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4122]]
|
|
// SIMD-ONLY0: if.end4122:
|
|
// SIMD-ONLY0-NEXT: [[TMP2921:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2921]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2922:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2923:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4123:%.*]] = icmp slt i64 [[TMP2922]], [[TMP2923]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4123]], label [[IF_THEN4125:%.*]], label [[IF_END4126:%.*]]
|
|
// SIMD-ONLY0: if.then4125:
|
|
// SIMD-ONLY0-NEXT: [[TMP2924:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2924]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4126]]
|
|
// SIMD-ONLY0: if.end4126:
|
|
// SIMD-ONLY0-NEXT: [[TMP2925:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2925]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2926:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2927:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4127:%.*]] = icmp eq i64 [[TMP2926]], [[TMP2927]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4127]], label [[IF_THEN4129:%.*]], label [[IF_END4130:%.*]]
|
|
// SIMD-ONLY0: if.then4129:
|
|
// SIMD-ONLY0-NEXT: [[TMP2928:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2928]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4130]]
|
|
// SIMD-ONLY0: if.end4130:
|
|
// SIMD-ONLY0-NEXT: [[TMP2929:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2929]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2930:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2931:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4131:%.*]] = icmp eq i64 [[TMP2930]], [[TMP2931]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4131]], label [[IF_THEN4133:%.*]], label [[IF_END4134:%.*]]
|
|
// SIMD-ONLY0: if.then4133:
|
|
// SIMD-ONLY0-NEXT: [[TMP2932:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2932]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4134]]
|
|
// SIMD-ONLY0: if.end4134:
|
|
// SIMD-ONLY0-NEXT: [[TMP2933:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2933]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2934:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2935:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4135:%.*]] = icmp eq i64 [[TMP2934]], [[TMP2935]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4135]], label [[IF_THEN4137:%.*]], label [[IF_ELSE4138:%.*]]
|
|
// SIMD-ONLY0: if.then4137:
|
|
// SIMD-ONLY0-NEXT: [[TMP2936:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2936]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4139:%.*]]
|
|
// SIMD-ONLY0: if.else4138:
|
|
// SIMD-ONLY0-NEXT: [[TMP2937:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2937]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4139]]
|
|
// SIMD-ONLY0: if.end4139:
|
|
// SIMD-ONLY0-NEXT: [[TMP2938:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2939:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4140:%.*]] = icmp eq i64 [[TMP2938]], [[TMP2939]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4140]], label [[IF_THEN4142:%.*]], label [[IF_ELSE4143:%.*]]
|
|
// SIMD-ONLY0: if.then4142:
|
|
// SIMD-ONLY0-NEXT: [[TMP2940:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2940]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4144:%.*]]
|
|
// SIMD-ONLY0: if.else4143:
|
|
// SIMD-ONLY0-NEXT: [[TMP2941:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2941]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4144]]
|
|
// SIMD-ONLY0: if.end4144:
|
|
// SIMD-ONLY0-NEXT: [[TMP2942:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2943:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4145:%.*]] = icmp eq i64 [[TMP2942]], [[TMP2943]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4146:%.*]] = zext i1 [[CMP4145]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4147:%.*]] = sext i32 [[CONV4146]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4147]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2944:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4148:%.*]] = icmp ne i64 [[TMP2944]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4148]], label [[IF_THEN4149:%.*]], label [[IF_END4150:%.*]]
|
|
// SIMD-ONLY0: if.then4149:
|
|
// SIMD-ONLY0-NEXT: [[TMP2945:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2945]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4150]]
|
|
// SIMD-ONLY0: if.end4150:
|
|
// SIMD-ONLY0-NEXT: [[TMP2946:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2947:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4151:%.*]] = icmp eq i64 [[TMP2946]], [[TMP2947]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4152:%.*]] = zext i1 [[CMP4151]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4153:%.*]] = sext i32 [[CONV4152]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4153]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2948:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4154:%.*]] = icmp ne i64 [[TMP2948]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4154]], label [[IF_THEN4155:%.*]], label [[IF_END4156:%.*]]
|
|
// SIMD-ONLY0: if.then4155:
|
|
// SIMD-ONLY0-NEXT: [[TMP2949:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2949]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4156]]
|
|
// SIMD-ONLY0: if.end4156:
|
|
// SIMD-ONLY0-NEXT: [[TMP2950:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2951:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4157:%.*]] = icmp eq i64 [[TMP2950]], [[TMP2951]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4158:%.*]] = zext i1 [[CMP4157]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4159:%.*]] = sext i32 [[CONV4158]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4159]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2952:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4160:%.*]] = icmp ne i64 [[TMP2952]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4160]], label [[IF_THEN4161:%.*]], label [[IF_ELSE4162:%.*]]
|
|
// SIMD-ONLY0: if.then4161:
|
|
// SIMD-ONLY0-NEXT: [[TMP2953:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2953]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4163:%.*]]
|
|
// SIMD-ONLY0: if.else4162:
|
|
// SIMD-ONLY0-NEXT: [[TMP2954:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2954]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4163]]
|
|
// SIMD-ONLY0: if.end4163:
|
|
// SIMD-ONLY0-NEXT: [[TMP2955:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2956:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4164:%.*]] = icmp eq i64 [[TMP2955]], [[TMP2956]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4165:%.*]] = zext i1 [[CMP4164]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4166:%.*]] = sext i32 [[CONV4165]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4166]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2957:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4167:%.*]] = icmp ne i64 [[TMP2957]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4167]], label [[IF_THEN4168:%.*]], label [[IF_ELSE4169:%.*]]
|
|
// SIMD-ONLY0: if.then4168:
|
|
// SIMD-ONLY0-NEXT: [[TMP2958:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2958]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4170:%.*]]
|
|
// SIMD-ONLY0: if.else4169:
|
|
// SIMD-ONLY0-NEXT: [[TMP2959:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2959]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4170]]
|
|
// SIMD-ONLY0: if.end4170:
|
|
// SIMD-ONLY0-NEXT: [[TMP2960:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2960]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2961:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2962:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4171:%.*]] = icmp sgt i64 [[TMP2961]], [[TMP2962]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4171]], label [[IF_THEN4173:%.*]], label [[IF_END4174:%.*]]
|
|
// SIMD-ONLY0: if.then4173:
|
|
// SIMD-ONLY0-NEXT: [[TMP2963:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2963]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4174]]
|
|
// SIMD-ONLY0: if.end4174:
|
|
// SIMD-ONLY0-NEXT: [[TMP2964:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2964]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2965:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2966:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4175:%.*]] = icmp sgt i64 [[TMP2965]], [[TMP2966]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4175]], label [[IF_THEN4177:%.*]], label [[IF_END4178:%.*]]
|
|
// SIMD-ONLY0: if.then4177:
|
|
// SIMD-ONLY0-NEXT: [[TMP2967:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2967]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4178]]
|
|
// SIMD-ONLY0: if.end4178:
|
|
// SIMD-ONLY0-NEXT: [[TMP2968:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2968]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2969:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2970:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4179:%.*]] = icmp slt i64 [[TMP2969]], [[TMP2970]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4179]], label [[IF_THEN4181:%.*]], label [[IF_END4182:%.*]]
|
|
// SIMD-ONLY0: if.then4181:
|
|
// SIMD-ONLY0-NEXT: [[TMP2971:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2971]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4182]]
|
|
// SIMD-ONLY0: if.end4182:
|
|
// SIMD-ONLY0-NEXT: [[TMP2972:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2972]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2973:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2974:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4183:%.*]] = icmp slt i64 [[TMP2973]], [[TMP2974]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4183]], label [[IF_THEN4185:%.*]], label [[IF_END4186:%.*]]
|
|
// SIMD-ONLY0: if.then4185:
|
|
// SIMD-ONLY0-NEXT: [[TMP2975:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2975]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4186]]
|
|
// SIMD-ONLY0: if.end4186:
|
|
// SIMD-ONLY0-NEXT: [[TMP2976:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2976]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2977:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2978:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4187:%.*]] = icmp eq i64 [[TMP2977]], [[TMP2978]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4187]], label [[IF_THEN4189:%.*]], label [[IF_END4190:%.*]]
|
|
// SIMD-ONLY0: if.then4189:
|
|
// SIMD-ONLY0-NEXT: [[TMP2979:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2979]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4190]]
|
|
// SIMD-ONLY0: if.end4190:
|
|
// SIMD-ONLY0-NEXT: [[TMP2980:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2980]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2981:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2982:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4191:%.*]] = icmp eq i64 [[TMP2981]], [[TMP2982]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4191]], label [[IF_THEN4193:%.*]], label [[IF_END4194:%.*]]
|
|
// SIMD-ONLY0: if.then4193:
|
|
// SIMD-ONLY0-NEXT: [[TMP2983:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2983]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4194]]
|
|
// SIMD-ONLY0: if.end4194:
|
|
// SIMD-ONLY0-NEXT: [[TMP2984:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2985:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4195:%.*]] = icmp sgt i64 [[TMP2984]], [[TMP2985]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4195]], label [[IF_THEN4197:%.*]], label [[IF_END4198:%.*]]
|
|
// SIMD-ONLY0: if.then4197:
|
|
// SIMD-ONLY0-NEXT: [[TMP2986:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2986]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4198]]
|
|
// SIMD-ONLY0: if.end4198:
|
|
// SIMD-ONLY0-NEXT: [[TMP2987:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2987]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2988:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2989:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4199:%.*]] = icmp sgt i64 [[TMP2988]], [[TMP2989]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4199]], label [[IF_THEN4201:%.*]], label [[IF_END4202:%.*]]
|
|
// SIMD-ONLY0: if.then4201:
|
|
// SIMD-ONLY0-NEXT: [[TMP2990:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2990]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4202]]
|
|
// SIMD-ONLY0: if.end4202:
|
|
// SIMD-ONLY0-NEXT: [[TMP2991:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2991]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2992:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2993:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4203:%.*]] = icmp slt i64 [[TMP2992]], [[TMP2993]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4203]], label [[IF_THEN4205:%.*]], label [[IF_END4206:%.*]]
|
|
// SIMD-ONLY0: if.then4205:
|
|
// SIMD-ONLY0-NEXT: [[TMP2994:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2994]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4206]]
|
|
// SIMD-ONLY0: if.end4206:
|
|
// SIMD-ONLY0-NEXT: [[TMP2995:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2995]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2996:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2997:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4207:%.*]] = icmp slt i64 [[TMP2996]], [[TMP2997]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4207]], label [[IF_THEN4209:%.*]], label [[IF_END4210:%.*]]
|
|
// SIMD-ONLY0: if.then4209:
|
|
// SIMD-ONLY0-NEXT: [[TMP2998:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2998]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4210]]
|
|
// SIMD-ONLY0: if.end4210:
|
|
// SIMD-ONLY0-NEXT: [[TMP2999:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP2999]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3000:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3001:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4211:%.*]] = icmp eq i64 [[TMP3000]], [[TMP3001]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4211]], label [[IF_THEN4213:%.*]], label [[IF_END4214:%.*]]
|
|
// SIMD-ONLY0: if.then4213:
|
|
// SIMD-ONLY0-NEXT: [[TMP3002:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3002]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4214]]
|
|
// SIMD-ONLY0: if.end4214:
|
|
// SIMD-ONLY0-NEXT: [[TMP3003:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3003]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3004:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3005:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4215:%.*]] = icmp eq i64 [[TMP3004]], [[TMP3005]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4215]], label [[IF_THEN4217:%.*]], label [[IF_END4218:%.*]]
|
|
// SIMD-ONLY0: if.then4217:
|
|
// SIMD-ONLY0-NEXT: [[TMP3006:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3006]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4218]]
|
|
// SIMD-ONLY0: if.end4218:
|
|
// SIMD-ONLY0-NEXT: [[TMP3007:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3007]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3008:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3009:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4219:%.*]] = icmp eq i64 [[TMP3008]], [[TMP3009]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4219]], label [[IF_THEN4221:%.*]], label [[IF_ELSE4222:%.*]]
|
|
// SIMD-ONLY0: if.then4221:
|
|
// SIMD-ONLY0-NEXT: [[TMP3010:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3010]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4223:%.*]]
|
|
// SIMD-ONLY0: if.else4222:
|
|
// SIMD-ONLY0-NEXT: [[TMP3011:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3011]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4223]]
|
|
// SIMD-ONLY0: if.end4223:
|
|
// SIMD-ONLY0-NEXT: [[TMP3012:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3013:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4224:%.*]] = icmp eq i64 [[TMP3012]], [[TMP3013]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4224]], label [[IF_THEN4226:%.*]], label [[IF_ELSE4227:%.*]]
|
|
// SIMD-ONLY0: if.then4226:
|
|
// SIMD-ONLY0-NEXT: [[TMP3014:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3014]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4228:%.*]]
|
|
// SIMD-ONLY0: if.else4227:
|
|
// SIMD-ONLY0-NEXT: [[TMP3015:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3015]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4228]]
|
|
// SIMD-ONLY0: if.end4228:
|
|
// SIMD-ONLY0-NEXT: [[TMP3016:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3017:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4229:%.*]] = icmp eq i64 [[TMP3016]], [[TMP3017]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4230:%.*]] = zext i1 [[CMP4229]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4231:%.*]] = sext i32 [[CONV4230]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4231]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3018:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4232:%.*]] = icmp ne i64 [[TMP3018]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4232]], label [[IF_THEN4233:%.*]], label [[IF_END4234:%.*]]
|
|
// SIMD-ONLY0: if.then4233:
|
|
// SIMD-ONLY0-NEXT: [[TMP3019:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3019]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4234]]
|
|
// SIMD-ONLY0: if.end4234:
|
|
// SIMD-ONLY0-NEXT: [[TMP3020:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3021:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4235:%.*]] = icmp eq i64 [[TMP3020]], [[TMP3021]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4236:%.*]] = zext i1 [[CMP4235]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4237:%.*]] = sext i32 [[CONV4236]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4237]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3022:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4238:%.*]] = icmp ne i64 [[TMP3022]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4238]], label [[IF_THEN4239:%.*]], label [[IF_END4240:%.*]]
|
|
// SIMD-ONLY0: if.then4239:
|
|
// SIMD-ONLY0-NEXT: [[TMP3023:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3023]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4240]]
|
|
// SIMD-ONLY0: if.end4240:
|
|
// SIMD-ONLY0-NEXT: [[TMP3024:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3025:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4241:%.*]] = icmp eq i64 [[TMP3024]], [[TMP3025]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4242:%.*]] = zext i1 [[CMP4241]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4243:%.*]] = sext i32 [[CONV4242]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4243]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3026:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4244:%.*]] = icmp ne i64 [[TMP3026]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4244]], label [[IF_THEN4245:%.*]], label [[IF_ELSE4246:%.*]]
|
|
// SIMD-ONLY0: if.then4245:
|
|
// SIMD-ONLY0-NEXT: [[TMP3027:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3027]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4247:%.*]]
|
|
// SIMD-ONLY0: if.else4246:
|
|
// SIMD-ONLY0-NEXT: [[TMP3028:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3028]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4247]]
|
|
// SIMD-ONLY0: if.end4247:
|
|
// SIMD-ONLY0-NEXT: [[TMP3029:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3030:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4248:%.*]] = icmp eq i64 [[TMP3029]], [[TMP3030]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4249:%.*]] = zext i1 [[CMP4248]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4250:%.*]] = sext i32 [[CONV4249]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4250]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3031:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4251:%.*]] = icmp ne i64 [[TMP3031]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4251]], label [[IF_THEN4252:%.*]], label [[IF_ELSE4253:%.*]]
|
|
// SIMD-ONLY0: if.then4252:
|
|
// SIMD-ONLY0-NEXT: [[TMP3032:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3032]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4254:%.*]]
|
|
// SIMD-ONLY0: if.else4253:
|
|
// SIMD-ONLY0-NEXT: [[TMP3033:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3033]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4254]]
|
|
// SIMD-ONLY0: if.end4254:
|
|
// SIMD-ONLY0-NEXT: [[TMP3034:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3034]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3035:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3036:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4255:%.*]] = icmp sgt i64 [[TMP3035]], [[TMP3036]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4255]], label [[IF_THEN4257:%.*]], label [[IF_END4258:%.*]]
|
|
// SIMD-ONLY0: if.then4257:
|
|
// SIMD-ONLY0-NEXT: [[TMP3037:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3037]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4258]]
|
|
// SIMD-ONLY0: if.end4258:
|
|
// SIMD-ONLY0-NEXT: [[TMP3038:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3038]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3039:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3040:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4259:%.*]] = icmp sgt i64 [[TMP3039]], [[TMP3040]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4259]], label [[IF_THEN4261:%.*]], label [[IF_END4262:%.*]]
|
|
// SIMD-ONLY0: if.then4261:
|
|
// SIMD-ONLY0-NEXT: [[TMP3041:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3041]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4262]]
|
|
// SIMD-ONLY0: if.end4262:
|
|
// SIMD-ONLY0-NEXT: [[TMP3042:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3042]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3043:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3044:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4263:%.*]] = icmp slt i64 [[TMP3043]], [[TMP3044]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4263]], label [[IF_THEN4265:%.*]], label [[IF_END4266:%.*]]
|
|
// SIMD-ONLY0: if.then4265:
|
|
// SIMD-ONLY0-NEXT: [[TMP3045:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3045]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4266]]
|
|
// SIMD-ONLY0: if.end4266:
|
|
// SIMD-ONLY0-NEXT: [[TMP3046:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3046]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3047:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3048:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4267:%.*]] = icmp slt i64 [[TMP3047]], [[TMP3048]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4267]], label [[IF_THEN4269:%.*]], label [[IF_END4270:%.*]]
|
|
// SIMD-ONLY0: if.then4269:
|
|
// SIMD-ONLY0-NEXT: [[TMP3049:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3049]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4270]]
|
|
// SIMD-ONLY0: if.end4270:
|
|
// SIMD-ONLY0-NEXT: [[TMP3050:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3050]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3051:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3052:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4271:%.*]] = icmp eq i64 [[TMP3051]], [[TMP3052]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4271]], label [[IF_THEN4273:%.*]], label [[IF_END4274:%.*]]
|
|
// SIMD-ONLY0: if.then4273:
|
|
// SIMD-ONLY0-NEXT: [[TMP3053:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3053]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4274]]
|
|
// SIMD-ONLY0: if.end4274:
|
|
// SIMD-ONLY0-NEXT: [[TMP3054:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3054]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3055:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3056:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4275:%.*]] = icmp eq i64 [[TMP3055]], [[TMP3056]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4275]], label [[IF_THEN4277:%.*]], label [[IF_END4278:%.*]]
|
|
// SIMD-ONLY0: if.then4277:
|
|
// SIMD-ONLY0-NEXT: [[TMP3057:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3057]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4278]]
|
|
// SIMD-ONLY0: if.end4278:
|
|
// SIMD-ONLY0-NEXT: [[TMP3058:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3059:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4279:%.*]] = icmp sgt i64 [[TMP3058]], [[TMP3059]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4279]], label [[IF_THEN4281:%.*]], label [[IF_END4282:%.*]]
|
|
// SIMD-ONLY0: if.then4281:
|
|
// SIMD-ONLY0-NEXT: [[TMP3060:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3060]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4282]]
|
|
// SIMD-ONLY0: if.end4282:
|
|
// SIMD-ONLY0-NEXT: [[TMP3061:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3061]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3062:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3063:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4283:%.*]] = icmp sgt i64 [[TMP3062]], [[TMP3063]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4283]], label [[IF_THEN4285:%.*]], label [[IF_END4286:%.*]]
|
|
// SIMD-ONLY0: if.then4285:
|
|
// SIMD-ONLY0-NEXT: [[TMP3064:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3064]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4286]]
|
|
// SIMD-ONLY0: if.end4286:
|
|
// SIMD-ONLY0-NEXT: [[TMP3065:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3065]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3066:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3067:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4287:%.*]] = icmp slt i64 [[TMP3066]], [[TMP3067]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4287]], label [[IF_THEN4289:%.*]], label [[IF_END4290:%.*]]
|
|
// SIMD-ONLY0: if.then4289:
|
|
// SIMD-ONLY0-NEXT: [[TMP3068:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3068]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4290]]
|
|
// SIMD-ONLY0: if.end4290:
|
|
// SIMD-ONLY0-NEXT: [[TMP3069:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3069]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3070:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3071:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4291:%.*]] = icmp slt i64 [[TMP3070]], [[TMP3071]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4291]], label [[IF_THEN4293:%.*]], label [[IF_END4294:%.*]]
|
|
// SIMD-ONLY0: if.then4293:
|
|
// SIMD-ONLY0-NEXT: [[TMP3072:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3072]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4294]]
|
|
// SIMD-ONLY0: if.end4294:
|
|
// SIMD-ONLY0-NEXT: [[TMP3073:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3073]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3074:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3075:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4295:%.*]] = icmp eq i64 [[TMP3074]], [[TMP3075]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4295]], label [[IF_THEN4297:%.*]], label [[IF_END4298:%.*]]
|
|
// SIMD-ONLY0: if.then4297:
|
|
// SIMD-ONLY0-NEXT: [[TMP3076:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3076]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4298]]
|
|
// SIMD-ONLY0: if.end4298:
|
|
// SIMD-ONLY0-NEXT: [[TMP3077:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3077]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3078:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3079:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4299:%.*]] = icmp eq i64 [[TMP3078]], [[TMP3079]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4299]], label [[IF_THEN4301:%.*]], label [[IF_END4302:%.*]]
|
|
// SIMD-ONLY0: if.then4301:
|
|
// SIMD-ONLY0-NEXT: [[TMP3080:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3080]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4302]]
|
|
// SIMD-ONLY0: if.end4302:
|
|
// SIMD-ONLY0-NEXT: [[TMP3081:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3081]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3082:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3083:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4303:%.*]] = icmp eq i64 [[TMP3082]], [[TMP3083]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4303]], label [[IF_THEN4305:%.*]], label [[IF_ELSE4306:%.*]]
|
|
// SIMD-ONLY0: if.then4305:
|
|
// SIMD-ONLY0-NEXT: [[TMP3084:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3084]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4307:%.*]]
|
|
// SIMD-ONLY0: if.else4306:
|
|
// SIMD-ONLY0-NEXT: [[TMP3085:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3085]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4307]]
|
|
// SIMD-ONLY0: if.end4307:
|
|
// SIMD-ONLY0-NEXT: [[TMP3086:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3087:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4308:%.*]] = icmp eq i64 [[TMP3086]], [[TMP3087]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4308]], label [[IF_THEN4310:%.*]], label [[IF_ELSE4311:%.*]]
|
|
// SIMD-ONLY0: if.then4310:
|
|
// SIMD-ONLY0-NEXT: [[TMP3088:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3088]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4312:%.*]]
|
|
// SIMD-ONLY0: if.else4311:
|
|
// SIMD-ONLY0-NEXT: [[TMP3089:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3089]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4312]]
|
|
// SIMD-ONLY0: if.end4312:
|
|
// SIMD-ONLY0-NEXT: [[TMP3090:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3091:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4313:%.*]] = icmp eq i64 [[TMP3090]], [[TMP3091]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4314:%.*]] = zext i1 [[CMP4313]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4315:%.*]] = sext i32 [[CONV4314]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4315]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3092:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4316:%.*]] = icmp ne i64 [[TMP3092]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4316]], label [[IF_THEN4317:%.*]], label [[IF_END4318:%.*]]
|
|
// SIMD-ONLY0: if.then4317:
|
|
// SIMD-ONLY0-NEXT: [[TMP3093:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3093]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4318]]
|
|
// SIMD-ONLY0: if.end4318:
|
|
// SIMD-ONLY0-NEXT: [[TMP3094:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3095:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4319:%.*]] = icmp eq i64 [[TMP3094]], [[TMP3095]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4320:%.*]] = zext i1 [[CMP4319]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4321:%.*]] = sext i32 [[CONV4320]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4321]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3096:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4322:%.*]] = icmp ne i64 [[TMP3096]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4322]], label [[IF_THEN4323:%.*]], label [[IF_END4324:%.*]]
|
|
// SIMD-ONLY0: if.then4323:
|
|
// SIMD-ONLY0-NEXT: [[TMP3097:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3097]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4324]]
|
|
// SIMD-ONLY0: if.end4324:
|
|
// SIMD-ONLY0-NEXT: [[TMP3098:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3099:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4325:%.*]] = icmp eq i64 [[TMP3098]], [[TMP3099]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4326:%.*]] = zext i1 [[CMP4325]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4327:%.*]] = sext i32 [[CONV4326]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4327]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3100:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4328:%.*]] = icmp ne i64 [[TMP3100]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4328]], label [[IF_THEN4329:%.*]], label [[IF_ELSE4330:%.*]]
|
|
// SIMD-ONLY0: if.then4329:
|
|
// SIMD-ONLY0-NEXT: [[TMP3101:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3101]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4331:%.*]]
|
|
// SIMD-ONLY0: if.else4330:
|
|
// SIMD-ONLY0-NEXT: [[TMP3102:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3102]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4331]]
|
|
// SIMD-ONLY0: if.end4331:
|
|
// SIMD-ONLY0-NEXT: [[TMP3103:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3104:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4332:%.*]] = icmp eq i64 [[TMP3103]], [[TMP3104]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4333:%.*]] = zext i1 [[CMP4332]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4334:%.*]] = sext i32 [[CONV4333]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4334]], ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3105:%.*]] = load i64, ptr [[LR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4335:%.*]] = icmp ne i64 [[TMP3105]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4335]], label [[IF_THEN4336:%.*]], label [[IF_ELSE4337:%.*]]
|
|
// SIMD-ONLY0: if.then4336:
|
|
// SIMD-ONLY0-NEXT: [[TMP3106:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3106]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4338:%.*]]
|
|
// SIMD-ONLY0: if.else4337:
|
|
// SIMD-ONLY0-NEXT: [[TMP3107:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3107]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4338]]
|
|
// SIMD-ONLY0: if.end4338:
|
|
// SIMD-ONLY0-NEXT: [[TMP3108:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3108]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3109:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3110:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4339:%.*]] = icmp ugt i64 [[TMP3109]], [[TMP3110]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4339]], label [[IF_THEN4341:%.*]], label [[IF_END4342:%.*]]
|
|
// SIMD-ONLY0: if.then4341:
|
|
// SIMD-ONLY0-NEXT: [[TMP3111:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3111]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4342]]
|
|
// SIMD-ONLY0: if.end4342:
|
|
// SIMD-ONLY0-NEXT: [[TMP3112:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3112]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3113:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3114:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4343:%.*]] = icmp ugt i64 [[TMP3113]], [[TMP3114]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4343]], label [[IF_THEN4345:%.*]], label [[IF_END4346:%.*]]
|
|
// SIMD-ONLY0: if.then4345:
|
|
// SIMD-ONLY0-NEXT: [[TMP3115:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3115]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4346]]
|
|
// SIMD-ONLY0: if.end4346:
|
|
// SIMD-ONLY0-NEXT: [[TMP3116:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3116]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3117:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3118:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4347:%.*]] = icmp ult i64 [[TMP3117]], [[TMP3118]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4347]], label [[IF_THEN4349:%.*]], label [[IF_END4350:%.*]]
|
|
// SIMD-ONLY0: if.then4349:
|
|
// SIMD-ONLY0-NEXT: [[TMP3119:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3119]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4350]]
|
|
// SIMD-ONLY0: if.end4350:
|
|
// SIMD-ONLY0-NEXT: [[TMP3120:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3120]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3121:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3122:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4351:%.*]] = icmp ult i64 [[TMP3121]], [[TMP3122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4351]], label [[IF_THEN4353:%.*]], label [[IF_END4354:%.*]]
|
|
// SIMD-ONLY0: if.then4353:
|
|
// SIMD-ONLY0-NEXT: [[TMP3123:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3123]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4354]]
|
|
// SIMD-ONLY0: if.end4354:
|
|
// SIMD-ONLY0-NEXT: [[TMP3124:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3124]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3125:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3126:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4355:%.*]] = icmp eq i64 [[TMP3125]], [[TMP3126]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4355]], label [[IF_THEN4357:%.*]], label [[IF_END4358:%.*]]
|
|
// SIMD-ONLY0: if.then4357:
|
|
// SIMD-ONLY0-NEXT: [[TMP3127:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3127]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4358]]
|
|
// SIMD-ONLY0: if.end4358:
|
|
// SIMD-ONLY0-NEXT: [[TMP3128:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3128]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3129:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3130:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4359:%.*]] = icmp eq i64 [[TMP3129]], [[TMP3130]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4359]], label [[IF_THEN4361:%.*]], label [[IF_END4362:%.*]]
|
|
// SIMD-ONLY0: if.then4361:
|
|
// SIMD-ONLY0-NEXT: [[TMP3131:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3131]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4362]]
|
|
// SIMD-ONLY0: if.end4362:
|
|
// SIMD-ONLY0-NEXT: [[TMP3132:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3133:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4363:%.*]] = icmp ugt i64 [[TMP3132]], [[TMP3133]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4363]], label [[IF_THEN4365:%.*]], label [[IF_END4366:%.*]]
|
|
// SIMD-ONLY0: if.then4365:
|
|
// SIMD-ONLY0-NEXT: [[TMP3134:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3134]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4366]]
|
|
// SIMD-ONLY0: if.end4366:
|
|
// SIMD-ONLY0-NEXT: [[TMP3135:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3135]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3136:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3137:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4367:%.*]] = icmp ugt i64 [[TMP3136]], [[TMP3137]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4367]], label [[IF_THEN4369:%.*]], label [[IF_END4370:%.*]]
|
|
// SIMD-ONLY0: if.then4369:
|
|
// SIMD-ONLY0-NEXT: [[TMP3138:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3138]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4370]]
|
|
// SIMD-ONLY0: if.end4370:
|
|
// SIMD-ONLY0-NEXT: [[TMP3139:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3139]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3140:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3141:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4371:%.*]] = icmp ult i64 [[TMP3140]], [[TMP3141]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4371]], label [[IF_THEN4373:%.*]], label [[IF_END4374:%.*]]
|
|
// SIMD-ONLY0: if.then4373:
|
|
// SIMD-ONLY0-NEXT: [[TMP3142:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3142]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4374]]
|
|
// SIMD-ONLY0: if.end4374:
|
|
// SIMD-ONLY0-NEXT: [[TMP3143:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3143]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3144:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3145:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4375:%.*]] = icmp ult i64 [[TMP3144]], [[TMP3145]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4375]], label [[IF_THEN4377:%.*]], label [[IF_END4378:%.*]]
|
|
// SIMD-ONLY0: if.then4377:
|
|
// SIMD-ONLY0-NEXT: [[TMP3146:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3146]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4378]]
|
|
// SIMD-ONLY0: if.end4378:
|
|
// SIMD-ONLY0-NEXT: [[TMP3147:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3147]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3148:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3149:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4379:%.*]] = icmp eq i64 [[TMP3148]], [[TMP3149]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4379]], label [[IF_THEN4381:%.*]], label [[IF_END4382:%.*]]
|
|
// SIMD-ONLY0: if.then4381:
|
|
// SIMD-ONLY0-NEXT: [[TMP3150:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3150]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4382]]
|
|
// SIMD-ONLY0: if.end4382:
|
|
// SIMD-ONLY0-NEXT: [[TMP3151:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3151]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3152:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3153:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4383:%.*]] = icmp eq i64 [[TMP3152]], [[TMP3153]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4383]], label [[IF_THEN4385:%.*]], label [[IF_END4386:%.*]]
|
|
// SIMD-ONLY0: if.then4385:
|
|
// SIMD-ONLY0-NEXT: [[TMP3154:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3154]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4386]]
|
|
// SIMD-ONLY0: if.end4386:
|
|
// SIMD-ONLY0-NEXT: [[TMP3155:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3155]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3156:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3157:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4387:%.*]] = icmp eq i64 [[TMP3156]], [[TMP3157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4387]], label [[IF_THEN4389:%.*]], label [[IF_ELSE4390:%.*]]
|
|
// SIMD-ONLY0: if.then4389:
|
|
// SIMD-ONLY0-NEXT: [[TMP3158:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3158]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4391:%.*]]
|
|
// SIMD-ONLY0: if.else4390:
|
|
// SIMD-ONLY0-NEXT: [[TMP3159:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3159]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4391]]
|
|
// SIMD-ONLY0: if.end4391:
|
|
// SIMD-ONLY0-NEXT: [[TMP3160:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3161:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4392:%.*]] = icmp eq i64 [[TMP3160]], [[TMP3161]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4392]], label [[IF_THEN4394:%.*]], label [[IF_ELSE4395:%.*]]
|
|
// SIMD-ONLY0: if.then4394:
|
|
// SIMD-ONLY0-NEXT: [[TMP3162:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3162]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4396:%.*]]
|
|
// SIMD-ONLY0: if.else4395:
|
|
// SIMD-ONLY0-NEXT: [[TMP3163:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3163]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4396]]
|
|
// SIMD-ONLY0: if.end4396:
|
|
// SIMD-ONLY0-NEXT: [[TMP3164:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3165:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4397:%.*]] = icmp eq i64 [[TMP3164]], [[TMP3165]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4398:%.*]] = zext i1 [[CMP4397]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4399:%.*]] = sext i32 [[CONV4398]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4399]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3166:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4400:%.*]] = icmp ne i64 [[TMP3166]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4400]], label [[IF_THEN4401:%.*]], label [[IF_END4402:%.*]]
|
|
// SIMD-ONLY0: if.then4401:
|
|
// SIMD-ONLY0-NEXT: [[TMP3167:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3167]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4402]]
|
|
// SIMD-ONLY0: if.end4402:
|
|
// SIMD-ONLY0-NEXT: [[TMP3168:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3169:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4403:%.*]] = icmp eq i64 [[TMP3168]], [[TMP3169]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4404:%.*]] = zext i1 [[CMP4403]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4405:%.*]] = sext i32 [[CONV4404]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4405]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3170:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4406:%.*]] = icmp ne i64 [[TMP3170]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4406]], label [[IF_THEN4407:%.*]], label [[IF_END4408:%.*]]
|
|
// SIMD-ONLY0: if.then4407:
|
|
// SIMD-ONLY0-NEXT: [[TMP3171:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3171]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4408]]
|
|
// SIMD-ONLY0: if.end4408:
|
|
// SIMD-ONLY0-NEXT: [[TMP3172:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3173:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4409:%.*]] = icmp eq i64 [[TMP3172]], [[TMP3173]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4410:%.*]] = zext i1 [[CMP4409]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4411:%.*]] = sext i32 [[CONV4410]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4411]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3174:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4412:%.*]] = icmp ne i64 [[TMP3174]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4412]], label [[IF_THEN4413:%.*]], label [[IF_ELSE4414:%.*]]
|
|
// SIMD-ONLY0: if.then4413:
|
|
// SIMD-ONLY0-NEXT: [[TMP3175:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3175]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4415:%.*]]
|
|
// SIMD-ONLY0: if.else4414:
|
|
// SIMD-ONLY0-NEXT: [[TMP3176:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3176]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4415]]
|
|
// SIMD-ONLY0: if.end4415:
|
|
// SIMD-ONLY0-NEXT: [[TMP3177:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3178:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4416:%.*]] = icmp eq i64 [[TMP3177]], [[TMP3178]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4417:%.*]] = zext i1 [[CMP4416]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4418:%.*]] = sext i32 [[CONV4417]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4418]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3179:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4419:%.*]] = icmp ne i64 [[TMP3179]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4419]], label [[IF_THEN4420:%.*]], label [[IF_ELSE4421:%.*]]
|
|
// SIMD-ONLY0: if.then4420:
|
|
// SIMD-ONLY0-NEXT: [[TMP3180:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3180]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4422:%.*]]
|
|
// SIMD-ONLY0: if.else4421:
|
|
// SIMD-ONLY0-NEXT: [[TMP3181:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3181]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4422]]
|
|
// SIMD-ONLY0: if.end4422:
|
|
// SIMD-ONLY0-NEXT: [[TMP3182:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3182]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3183:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3184:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4423:%.*]] = icmp ugt i64 [[TMP3183]], [[TMP3184]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4423]], label [[IF_THEN4425:%.*]], label [[IF_END4426:%.*]]
|
|
// SIMD-ONLY0: if.then4425:
|
|
// SIMD-ONLY0-NEXT: [[TMP3185:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3185]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4426]]
|
|
// SIMD-ONLY0: if.end4426:
|
|
// SIMD-ONLY0-NEXT: [[TMP3186:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3186]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3187:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3188:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4427:%.*]] = icmp ugt i64 [[TMP3187]], [[TMP3188]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4427]], label [[IF_THEN4429:%.*]], label [[IF_END4430:%.*]]
|
|
// SIMD-ONLY0: if.then4429:
|
|
// SIMD-ONLY0-NEXT: [[TMP3189:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3189]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4430]]
|
|
// SIMD-ONLY0: if.end4430:
|
|
// SIMD-ONLY0-NEXT: [[TMP3190:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3190]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3191:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3192:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4431:%.*]] = icmp ult i64 [[TMP3191]], [[TMP3192]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4431]], label [[IF_THEN4433:%.*]], label [[IF_END4434:%.*]]
|
|
// SIMD-ONLY0: if.then4433:
|
|
// SIMD-ONLY0-NEXT: [[TMP3193:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3193]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4434]]
|
|
// SIMD-ONLY0: if.end4434:
|
|
// SIMD-ONLY0-NEXT: [[TMP3194:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3194]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3195:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3196:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4435:%.*]] = icmp ult i64 [[TMP3195]], [[TMP3196]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4435]], label [[IF_THEN4437:%.*]], label [[IF_END4438:%.*]]
|
|
// SIMD-ONLY0: if.then4437:
|
|
// SIMD-ONLY0-NEXT: [[TMP3197:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3197]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4438]]
|
|
// SIMD-ONLY0: if.end4438:
|
|
// SIMD-ONLY0-NEXT: [[TMP3198:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3198]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3199:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3200:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4439:%.*]] = icmp eq i64 [[TMP3199]], [[TMP3200]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4439]], label [[IF_THEN4441:%.*]], label [[IF_END4442:%.*]]
|
|
// SIMD-ONLY0: if.then4441:
|
|
// SIMD-ONLY0-NEXT: [[TMP3201:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3201]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4442]]
|
|
// SIMD-ONLY0: if.end4442:
|
|
// SIMD-ONLY0-NEXT: [[TMP3202:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3202]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3203:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3204:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4443:%.*]] = icmp eq i64 [[TMP3203]], [[TMP3204]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4443]], label [[IF_THEN4445:%.*]], label [[IF_END4446:%.*]]
|
|
// SIMD-ONLY0: if.then4445:
|
|
// SIMD-ONLY0-NEXT: [[TMP3205:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3205]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4446]]
|
|
// SIMD-ONLY0: if.end4446:
|
|
// SIMD-ONLY0-NEXT: [[TMP3206:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3207:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4447:%.*]] = icmp ugt i64 [[TMP3206]], [[TMP3207]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4447]], label [[IF_THEN4449:%.*]], label [[IF_END4450:%.*]]
|
|
// SIMD-ONLY0: if.then4449:
|
|
// SIMD-ONLY0-NEXT: [[TMP3208:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3208]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4450]]
|
|
// SIMD-ONLY0: if.end4450:
|
|
// SIMD-ONLY0-NEXT: [[TMP3209:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3209]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3210:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3211:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4451:%.*]] = icmp ugt i64 [[TMP3210]], [[TMP3211]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4451]], label [[IF_THEN4453:%.*]], label [[IF_END4454:%.*]]
|
|
// SIMD-ONLY0: if.then4453:
|
|
// SIMD-ONLY0-NEXT: [[TMP3212:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3212]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4454]]
|
|
// SIMD-ONLY0: if.end4454:
|
|
// SIMD-ONLY0-NEXT: [[TMP3213:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3213]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3214:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3215:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4455:%.*]] = icmp ult i64 [[TMP3214]], [[TMP3215]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4455]], label [[IF_THEN4457:%.*]], label [[IF_END4458:%.*]]
|
|
// SIMD-ONLY0: if.then4457:
|
|
// SIMD-ONLY0-NEXT: [[TMP3216:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3216]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4458]]
|
|
// SIMD-ONLY0: if.end4458:
|
|
// SIMD-ONLY0-NEXT: [[TMP3217:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3217]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3218:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3219:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4459:%.*]] = icmp ult i64 [[TMP3218]], [[TMP3219]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4459]], label [[IF_THEN4461:%.*]], label [[IF_END4462:%.*]]
|
|
// SIMD-ONLY0: if.then4461:
|
|
// SIMD-ONLY0-NEXT: [[TMP3220:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3220]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4462]]
|
|
// SIMD-ONLY0: if.end4462:
|
|
// SIMD-ONLY0-NEXT: [[TMP3221:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3221]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3222:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3223:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4463:%.*]] = icmp eq i64 [[TMP3222]], [[TMP3223]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4463]], label [[IF_THEN4465:%.*]], label [[IF_END4466:%.*]]
|
|
// SIMD-ONLY0: if.then4465:
|
|
// SIMD-ONLY0-NEXT: [[TMP3224:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3224]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4466]]
|
|
// SIMD-ONLY0: if.end4466:
|
|
// SIMD-ONLY0-NEXT: [[TMP3225:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3225]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3226:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3227:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4467:%.*]] = icmp eq i64 [[TMP3226]], [[TMP3227]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4467]], label [[IF_THEN4469:%.*]], label [[IF_END4470:%.*]]
|
|
// SIMD-ONLY0: if.then4469:
|
|
// SIMD-ONLY0-NEXT: [[TMP3228:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3228]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4470]]
|
|
// SIMD-ONLY0: if.end4470:
|
|
// SIMD-ONLY0-NEXT: [[TMP3229:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3229]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3230:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3231:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4471:%.*]] = icmp eq i64 [[TMP3230]], [[TMP3231]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4471]], label [[IF_THEN4473:%.*]], label [[IF_ELSE4474:%.*]]
|
|
// SIMD-ONLY0: if.then4473:
|
|
// SIMD-ONLY0-NEXT: [[TMP3232:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3232]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4475:%.*]]
|
|
// SIMD-ONLY0: if.else4474:
|
|
// SIMD-ONLY0-NEXT: [[TMP3233:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3233]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4475]]
|
|
// SIMD-ONLY0: if.end4475:
|
|
// SIMD-ONLY0-NEXT: [[TMP3234:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3235:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4476:%.*]] = icmp eq i64 [[TMP3234]], [[TMP3235]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4476]], label [[IF_THEN4478:%.*]], label [[IF_ELSE4479:%.*]]
|
|
// SIMD-ONLY0: if.then4478:
|
|
// SIMD-ONLY0-NEXT: [[TMP3236:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3236]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4480:%.*]]
|
|
// SIMD-ONLY0: if.else4479:
|
|
// SIMD-ONLY0-NEXT: [[TMP3237:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3237]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4480]]
|
|
// SIMD-ONLY0: if.end4480:
|
|
// SIMD-ONLY0-NEXT: [[TMP3238:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3239:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4481:%.*]] = icmp eq i64 [[TMP3238]], [[TMP3239]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4482:%.*]] = zext i1 [[CMP4481]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4483:%.*]] = sext i32 [[CONV4482]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4483]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3240:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4484:%.*]] = icmp ne i64 [[TMP3240]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4484]], label [[IF_THEN4485:%.*]], label [[IF_END4486:%.*]]
|
|
// SIMD-ONLY0: if.then4485:
|
|
// SIMD-ONLY0-NEXT: [[TMP3241:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3241]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4486]]
|
|
// SIMD-ONLY0: if.end4486:
|
|
// SIMD-ONLY0-NEXT: [[TMP3242:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3243:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4487:%.*]] = icmp eq i64 [[TMP3242]], [[TMP3243]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4488:%.*]] = zext i1 [[CMP4487]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4489:%.*]] = sext i32 [[CONV4488]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4489]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3244:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4490:%.*]] = icmp ne i64 [[TMP3244]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4490]], label [[IF_THEN4491:%.*]], label [[IF_END4492:%.*]]
|
|
// SIMD-ONLY0: if.then4491:
|
|
// SIMD-ONLY0-NEXT: [[TMP3245:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3245]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4492]]
|
|
// SIMD-ONLY0: if.end4492:
|
|
// SIMD-ONLY0-NEXT: [[TMP3246:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3247:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4493:%.*]] = icmp eq i64 [[TMP3246]], [[TMP3247]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4494:%.*]] = zext i1 [[CMP4493]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4495:%.*]] = sext i32 [[CONV4494]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4495]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3248:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4496:%.*]] = icmp ne i64 [[TMP3248]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4496]], label [[IF_THEN4497:%.*]], label [[IF_ELSE4498:%.*]]
|
|
// SIMD-ONLY0: if.then4497:
|
|
// SIMD-ONLY0-NEXT: [[TMP3249:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3249]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4499:%.*]]
|
|
// SIMD-ONLY0: if.else4498:
|
|
// SIMD-ONLY0-NEXT: [[TMP3250:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3250]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4499]]
|
|
// SIMD-ONLY0: if.end4499:
|
|
// SIMD-ONLY0-NEXT: [[TMP3251:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3252:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4500:%.*]] = icmp eq i64 [[TMP3251]], [[TMP3252]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4501:%.*]] = zext i1 [[CMP4500]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4502:%.*]] = sext i32 [[CONV4501]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4502]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3253:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4503:%.*]] = icmp ne i64 [[TMP3253]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4503]], label [[IF_THEN4504:%.*]], label [[IF_ELSE4505:%.*]]
|
|
// SIMD-ONLY0: if.then4504:
|
|
// SIMD-ONLY0-NEXT: [[TMP3254:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3254]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4506:%.*]]
|
|
// SIMD-ONLY0: if.else4505:
|
|
// SIMD-ONLY0-NEXT: [[TMP3255:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3255]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4506]]
|
|
// SIMD-ONLY0: if.end4506:
|
|
// SIMD-ONLY0-NEXT: [[TMP3256:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3256]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3257:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3258:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4507:%.*]] = icmp ugt i64 [[TMP3257]], [[TMP3258]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4507]], label [[IF_THEN4509:%.*]], label [[IF_END4510:%.*]]
|
|
// SIMD-ONLY0: if.then4509:
|
|
// SIMD-ONLY0-NEXT: [[TMP3259:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3259]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4510]]
|
|
// SIMD-ONLY0: if.end4510:
|
|
// SIMD-ONLY0-NEXT: [[TMP3260:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3260]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3261:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3262:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4511:%.*]] = icmp ugt i64 [[TMP3261]], [[TMP3262]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4511]], label [[IF_THEN4513:%.*]], label [[IF_END4514:%.*]]
|
|
// SIMD-ONLY0: if.then4513:
|
|
// SIMD-ONLY0-NEXT: [[TMP3263:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3263]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4514]]
|
|
// SIMD-ONLY0: if.end4514:
|
|
// SIMD-ONLY0-NEXT: [[TMP3264:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3264]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3265:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3266:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4515:%.*]] = icmp ult i64 [[TMP3265]], [[TMP3266]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4515]], label [[IF_THEN4517:%.*]], label [[IF_END4518:%.*]]
|
|
// SIMD-ONLY0: if.then4517:
|
|
// SIMD-ONLY0-NEXT: [[TMP3267:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3267]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4518]]
|
|
// SIMD-ONLY0: if.end4518:
|
|
// SIMD-ONLY0-NEXT: [[TMP3268:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3268]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3269:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3270:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4519:%.*]] = icmp ult i64 [[TMP3269]], [[TMP3270]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4519]], label [[IF_THEN4521:%.*]], label [[IF_END4522:%.*]]
|
|
// SIMD-ONLY0: if.then4521:
|
|
// SIMD-ONLY0-NEXT: [[TMP3271:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3271]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4522]]
|
|
// SIMD-ONLY0: if.end4522:
|
|
// SIMD-ONLY0-NEXT: [[TMP3272:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3272]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3273:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3274:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4523:%.*]] = icmp eq i64 [[TMP3273]], [[TMP3274]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4523]], label [[IF_THEN4525:%.*]], label [[IF_END4526:%.*]]
|
|
// SIMD-ONLY0: if.then4525:
|
|
// SIMD-ONLY0-NEXT: [[TMP3275:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3275]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4526]]
|
|
// SIMD-ONLY0: if.end4526:
|
|
// SIMD-ONLY0-NEXT: [[TMP3276:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3276]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3277:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3278:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4527:%.*]] = icmp eq i64 [[TMP3277]], [[TMP3278]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4527]], label [[IF_THEN4529:%.*]], label [[IF_END4530:%.*]]
|
|
// SIMD-ONLY0: if.then4529:
|
|
// SIMD-ONLY0-NEXT: [[TMP3279:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3279]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4530]]
|
|
// SIMD-ONLY0: if.end4530:
|
|
// SIMD-ONLY0-NEXT: [[TMP3280:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3281:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4531:%.*]] = icmp ugt i64 [[TMP3280]], [[TMP3281]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4531]], label [[IF_THEN4533:%.*]], label [[IF_END4534:%.*]]
|
|
// SIMD-ONLY0: if.then4533:
|
|
// SIMD-ONLY0-NEXT: [[TMP3282:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3282]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4534]]
|
|
// SIMD-ONLY0: if.end4534:
|
|
// SIMD-ONLY0-NEXT: [[TMP3283:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3283]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3284:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3285:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4535:%.*]] = icmp ugt i64 [[TMP3284]], [[TMP3285]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4535]], label [[IF_THEN4537:%.*]], label [[IF_END4538:%.*]]
|
|
// SIMD-ONLY0: if.then4537:
|
|
// SIMD-ONLY0-NEXT: [[TMP3286:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3286]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4538]]
|
|
// SIMD-ONLY0: if.end4538:
|
|
// SIMD-ONLY0-NEXT: [[TMP3287:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3287]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3288:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3289:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4539:%.*]] = icmp ult i64 [[TMP3288]], [[TMP3289]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4539]], label [[IF_THEN4541:%.*]], label [[IF_END4542:%.*]]
|
|
// SIMD-ONLY0: if.then4541:
|
|
// SIMD-ONLY0-NEXT: [[TMP3290:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3290]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4542]]
|
|
// SIMD-ONLY0: if.end4542:
|
|
// SIMD-ONLY0-NEXT: [[TMP3291:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3291]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3292:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3293:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4543:%.*]] = icmp ult i64 [[TMP3292]], [[TMP3293]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4543]], label [[IF_THEN4545:%.*]], label [[IF_END4546:%.*]]
|
|
// SIMD-ONLY0: if.then4545:
|
|
// SIMD-ONLY0-NEXT: [[TMP3294:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3294]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4546]]
|
|
// SIMD-ONLY0: if.end4546:
|
|
// SIMD-ONLY0-NEXT: [[TMP3295:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3295]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3296:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3297:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4547:%.*]] = icmp eq i64 [[TMP3296]], [[TMP3297]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4547]], label [[IF_THEN4549:%.*]], label [[IF_END4550:%.*]]
|
|
// SIMD-ONLY0: if.then4549:
|
|
// SIMD-ONLY0-NEXT: [[TMP3298:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3298]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4550]]
|
|
// SIMD-ONLY0: if.end4550:
|
|
// SIMD-ONLY0-NEXT: [[TMP3299:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3299]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3300:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3301:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4551:%.*]] = icmp eq i64 [[TMP3300]], [[TMP3301]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4551]], label [[IF_THEN4553:%.*]], label [[IF_END4554:%.*]]
|
|
// SIMD-ONLY0: if.then4553:
|
|
// SIMD-ONLY0-NEXT: [[TMP3302:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3302]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4554]]
|
|
// SIMD-ONLY0: if.end4554:
|
|
// SIMD-ONLY0-NEXT: [[TMP3303:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3303]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3304:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3305:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4555:%.*]] = icmp eq i64 [[TMP3304]], [[TMP3305]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4555]], label [[IF_THEN4557:%.*]], label [[IF_ELSE4558:%.*]]
|
|
// SIMD-ONLY0: if.then4557:
|
|
// SIMD-ONLY0-NEXT: [[TMP3306:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3306]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4559:%.*]]
|
|
// SIMD-ONLY0: if.else4558:
|
|
// SIMD-ONLY0-NEXT: [[TMP3307:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3307]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4559]]
|
|
// SIMD-ONLY0: if.end4559:
|
|
// SIMD-ONLY0-NEXT: [[TMP3308:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3309:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4560:%.*]] = icmp eq i64 [[TMP3308]], [[TMP3309]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4560]], label [[IF_THEN4562:%.*]], label [[IF_ELSE4563:%.*]]
|
|
// SIMD-ONLY0: if.then4562:
|
|
// SIMD-ONLY0-NEXT: [[TMP3310:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3310]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4564:%.*]]
|
|
// SIMD-ONLY0: if.else4563:
|
|
// SIMD-ONLY0-NEXT: [[TMP3311:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3311]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4564]]
|
|
// SIMD-ONLY0: if.end4564:
|
|
// SIMD-ONLY0-NEXT: [[TMP3312:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3313:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4565:%.*]] = icmp eq i64 [[TMP3312]], [[TMP3313]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4566:%.*]] = zext i1 [[CMP4565]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4567:%.*]] = sext i32 [[CONV4566]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4567]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3314:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4568:%.*]] = icmp ne i64 [[TMP3314]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4568]], label [[IF_THEN4569:%.*]], label [[IF_END4570:%.*]]
|
|
// SIMD-ONLY0: if.then4569:
|
|
// SIMD-ONLY0-NEXT: [[TMP3315:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3315]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4570]]
|
|
// SIMD-ONLY0: if.end4570:
|
|
// SIMD-ONLY0-NEXT: [[TMP3316:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3317:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4571:%.*]] = icmp eq i64 [[TMP3316]], [[TMP3317]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4572:%.*]] = zext i1 [[CMP4571]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4573:%.*]] = sext i32 [[CONV4572]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4573]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3318:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4574:%.*]] = icmp ne i64 [[TMP3318]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4574]], label [[IF_THEN4575:%.*]], label [[IF_END4576:%.*]]
|
|
// SIMD-ONLY0: if.then4575:
|
|
// SIMD-ONLY0-NEXT: [[TMP3319:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3319]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4576]]
|
|
// SIMD-ONLY0: if.end4576:
|
|
// SIMD-ONLY0-NEXT: [[TMP3320:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3321:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4577:%.*]] = icmp eq i64 [[TMP3320]], [[TMP3321]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4578:%.*]] = zext i1 [[CMP4577]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4579:%.*]] = sext i32 [[CONV4578]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4579]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3322:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4580:%.*]] = icmp ne i64 [[TMP3322]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4580]], label [[IF_THEN4581:%.*]], label [[IF_ELSE4582:%.*]]
|
|
// SIMD-ONLY0: if.then4581:
|
|
// SIMD-ONLY0-NEXT: [[TMP3323:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3323]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4583:%.*]]
|
|
// SIMD-ONLY0: if.else4582:
|
|
// SIMD-ONLY0-NEXT: [[TMP3324:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3324]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4583]]
|
|
// SIMD-ONLY0: if.end4583:
|
|
// SIMD-ONLY0-NEXT: [[TMP3325:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3326:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4584:%.*]] = icmp eq i64 [[TMP3325]], [[TMP3326]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4585:%.*]] = zext i1 [[CMP4584]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4586:%.*]] = sext i32 [[CONV4585]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4586]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3327:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4587:%.*]] = icmp ne i64 [[TMP3327]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4587]], label [[IF_THEN4588:%.*]], label [[IF_ELSE4589:%.*]]
|
|
// SIMD-ONLY0: if.then4588:
|
|
// SIMD-ONLY0-NEXT: [[TMP3328:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3328]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4590:%.*]]
|
|
// SIMD-ONLY0: if.else4589:
|
|
// SIMD-ONLY0-NEXT: [[TMP3329:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3329]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4590]]
|
|
// SIMD-ONLY0: if.end4590:
|
|
// SIMD-ONLY0-NEXT: [[TMP3330:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3330]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3331:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3332:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4591:%.*]] = icmp ugt i64 [[TMP3331]], [[TMP3332]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4591]], label [[IF_THEN4593:%.*]], label [[IF_END4594:%.*]]
|
|
// SIMD-ONLY0: if.then4593:
|
|
// SIMD-ONLY0-NEXT: [[TMP3333:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3333]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4594]]
|
|
// SIMD-ONLY0: if.end4594:
|
|
// SIMD-ONLY0-NEXT: [[TMP3334:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3334]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3335:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3336:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4595:%.*]] = icmp ugt i64 [[TMP3335]], [[TMP3336]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4595]], label [[IF_THEN4597:%.*]], label [[IF_END4598:%.*]]
|
|
// SIMD-ONLY0: if.then4597:
|
|
// SIMD-ONLY0-NEXT: [[TMP3337:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3337]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4598]]
|
|
// SIMD-ONLY0: if.end4598:
|
|
// SIMD-ONLY0-NEXT: [[TMP3338:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3338]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3339:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3340:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4599:%.*]] = icmp ult i64 [[TMP3339]], [[TMP3340]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4599]], label [[IF_THEN4601:%.*]], label [[IF_END4602:%.*]]
|
|
// SIMD-ONLY0: if.then4601:
|
|
// SIMD-ONLY0-NEXT: [[TMP3341:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3341]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4602]]
|
|
// SIMD-ONLY0: if.end4602:
|
|
// SIMD-ONLY0-NEXT: [[TMP3342:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3342]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3343:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3344:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4603:%.*]] = icmp ult i64 [[TMP3343]], [[TMP3344]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4603]], label [[IF_THEN4605:%.*]], label [[IF_END4606:%.*]]
|
|
// SIMD-ONLY0: if.then4605:
|
|
// SIMD-ONLY0-NEXT: [[TMP3345:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3345]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4606]]
|
|
// SIMD-ONLY0: if.end4606:
|
|
// SIMD-ONLY0-NEXT: [[TMP3346:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3346]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3347:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3348:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4607:%.*]] = icmp eq i64 [[TMP3347]], [[TMP3348]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4607]], label [[IF_THEN4609:%.*]], label [[IF_END4610:%.*]]
|
|
// SIMD-ONLY0: if.then4609:
|
|
// SIMD-ONLY0-NEXT: [[TMP3349:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3349]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4610]]
|
|
// SIMD-ONLY0: if.end4610:
|
|
// SIMD-ONLY0-NEXT: [[TMP3350:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3350]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3351:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3352:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4611:%.*]] = icmp eq i64 [[TMP3351]], [[TMP3352]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4611]], label [[IF_THEN4613:%.*]], label [[IF_END4614:%.*]]
|
|
// SIMD-ONLY0: if.then4613:
|
|
// SIMD-ONLY0-NEXT: [[TMP3353:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3353]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4614]]
|
|
// SIMD-ONLY0: if.end4614:
|
|
// SIMD-ONLY0-NEXT: [[TMP3354:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3355:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4615:%.*]] = icmp ugt i64 [[TMP3354]], [[TMP3355]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4615]], label [[IF_THEN4617:%.*]], label [[IF_END4618:%.*]]
|
|
// SIMD-ONLY0: if.then4617:
|
|
// SIMD-ONLY0-NEXT: [[TMP3356:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3356]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4618]]
|
|
// SIMD-ONLY0: if.end4618:
|
|
// SIMD-ONLY0-NEXT: [[TMP3357:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3357]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3358:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3359:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4619:%.*]] = icmp ugt i64 [[TMP3358]], [[TMP3359]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4619]], label [[IF_THEN4621:%.*]], label [[IF_END4622:%.*]]
|
|
// SIMD-ONLY0: if.then4621:
|
|
// SIMD-ONLY0-NEXT: [[TMP3360:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3360]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4622]]
|
|
// SIMD-ONLY0: if.end4622:
|
|
// SIMD-ONLY0-NEXT: [[TMP3361:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3361]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3362:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3363:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4623:%.*]] = icmp ult i64 [[TMP3362]], [[TMP3363]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4623]], label [[IF_THEN4625:%.*]], label [[IF_END4626:%.*]]
|
|
// SIMD-ONLY0: if.then4625:
|
|
// SIMD-ONLY0-NEXT: [[TMP3364:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3364]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4626]]
|
|
// SIMD-ONLY0: if.end4626:
|
|
// SIMD-ONLY0-NEXT: [[TMP3365:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3365]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3366:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3367:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4627:%.*]] = icmp ult i64 [[TMP3366]], [[TMP3367]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4627]], label [[IF_THEN4629:%.*]], label [[IF_END4630:%.*]]
|
|
// SIMD-ONLY0: if.then4629:
|
|
// SIMD-ONLY0-NEXT: [[TMP3368:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3368]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4630]]
|
|
// SIMD-ONLY0: if.end4630:
|
|
// SIMD-ONLY0-NEXT: [[TMP3369:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3369]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3370:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3371:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4631:%.*]] = icmp eq i64 [[TMP3370]], [[TMP3371]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4631]], label [[IF_THEN4633:%.*]], label [[IF_END4634:%.*]]
|
|
// SIMD-ONLY0: if.then4633:
|
|
// SIMD-ONLY0-NEXT: [[TMP3372:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3372]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4634]]
|
|
// SIMD-ONLY0: if.end4634:
|
|
// SIMD-ONLY0-NEXT: [[TMP3373:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3373]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3374:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3375:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4635:%.*]] = icmp eq i64 [[TMP3374]], [[TMP3375]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4635]], label [[IF_THEN4637:%.*]], label [[IF_END4638:%.*]]
|
|
// SIMD-ONLY0: if.then4637:
|
|
// SIMD-ONLY0-NEXT: [[TMP3376:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3376]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4638]]
|
|
// SIMD-ONLY0: if.end4638:
|
|
// SIMD-ONLY0-NEXT: [[TMP3377:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3377]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3378:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3379:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4639:%.*]] = icmp eq i64 [[TMP3378]], [[TMP3379]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4639]], label [[IF_THEN4641:%.*]], label [[IF_ELSE4642:%.*]]
|
|
// SIMD-ONLY0: if.then4641:
|
|
// SIMD-ONLY0-NEXT: [[TMP3380:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3380]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4643:%.*]]
|
|
// SIMD-ONLY0: if.else4642:
|
|
// SIMD-ONLY0-NEXT: [[TMP3381:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3381]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4643]]
|
|
// SIMD-ONLY0: if.end4643:
|
|
// SIMD-ONLY0-NEXT: [[TMP3382:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3383:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4644:%.*]] = icmp eq i64 [[TMP3382]], [[TMP3383]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4644]], label [[IF_THEN4646:%.*]], label [[IF_ELSE4647:%.*]]
|
|
// SIMD-ONLY0: if.then4646:
|
|
// SIMD-ONLY0-NEXT: [[TMP3384:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3384]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4648:%.*]]
|
|
// SIMD-ONLY0: if.else4647:
|
|
// SIMD-ONLY0-NEXT: [[TMP3385:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3385]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4648]]
|
|
// SIMD-ONLY0: if.end4648:
|
|
// SIMD-ONLY0-NEXT: [[TMP3386:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3387:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4649:%.*]] = icmp eq i64 [[TMP3386]], [[TMP3387]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4650:%.*]] = zext i1 [[CMP4649]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4651:%.*]] = sext i32 [[CONV4650]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4651]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3388:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4652:%.*]] = icmp ne i64 [[TMP3388]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4652]], label [[IF_THEN4653:%.*]], label [[IF_END4654:%.*]]
|
|
// SIMD-ONLY0: if.then4653:
|
|
// SIMD-ONLY0-NEXT: [[TMP3389:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3389]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4654]]
|
|
// SIMD-ONLY0: if.end4654:
|
|
// SIMD-ONLY0-NEXT: [[TMP3390:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3391:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4655:%.*]] = icmp eq i64 [[TMP3390]], [[TMP3391]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4656:%.*]] = zext i1 [[CMP4655]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4657:%.*]] = sext i32 [[CONV4656]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4657]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3392:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4658:%.*]] = icmp ne i64 [[TMP3392]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4658]], label [[IF_THEN4659:%.*]], label [[IF_END4660:%.*]]
|
|
// SIMD-ONLY0: if.then4659:
|
|
// SIMD-ONLY0-NEXT: [[TMP3393:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3393]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4660]]
|
|
// SIMD-ONLY0: if.end4660:
|
|
// SIMD-ONLY0-NEXT: [[TMP3394:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3395:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4661:%.*]] = icmp eq i64 [[TMP3394]], [[TMP3395]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4662:%.*]] = zext i1 [[CMP4661]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4663:%.*]] = sext i32 [[CONV4662]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4663]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3396:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4664:%.*]] = icmp ne i64 [[TMP3396]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4664]], label [[IF_THEN4665:%.*]], label [[IF_ELSE4666:%.*]]
|
|
// SIMD-ONLY0: if.then4665:
|
|
// SIMD-ONLY0-NEXT: [[TMP3397:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3397]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4667:%.*]]
|
|
// SIMD-ONLY0: if.else4666:
|
|
// SIMD-ONLY0-NEXT: [[TMP3398:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3398]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4667]]
|
|
// SIMD-ONLY0: if.end4667:
|
|
// SIMD-ONLY0-NEXT: [[TMP3399:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3400:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4668:%.*]] = icmp eq i64 [[TMP3399]], [[TMP3400]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4669:%.*]] = zext i1 [[CMP4668]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4670:%.*]] = sext i32 [[CONV4669]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4670]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3401:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4671:%.*]] = icmp ne i64 [[TMP3401]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4671]], label [[IF_THEN4672:%.*]], label [[IF_ELSE4673:%.*]]
|
|
// SIMD-ONLY0: if.then4672:
|
|
// SIMD-ONLY0-NEXT: [[TMP3402:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3402]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4674:%.*]]
|
|
// SIMD-ONLY0: if.else4673:
|
|
// SIMD-ONLY0-NEXT: [[TMP3403:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3403]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4674]]
|
|
// SIMD-ONLY0: if.end4674:
|
|
// SIMD-ONLY0-NEXT: [[TMP3404:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3404]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3405:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3406:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4675:%.*]] = icmp ugt i64 [[TMP3405]], [[TMP3406]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4675]], label [[IF_THEN4677:%.*]], label [[IF_END4678:%.*]]
|
|
// SIMD-ONLY0: if.then4677:
|
|
// SIMD-ONLY0-NEXT: [[TMP3407:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3407]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4678]]
|
|
// SIMD-ONLY0: if.end4678:
|
|
// SIMD-ONLY0-NEXT: [[TMP3408:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3408]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3409:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3410:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4679:%.*]] = icmp ugt i64 [[TMP3409]], [[TMP3410]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4679]], label [[IF_THEN4681:%.*]], label [[IF_END4682:%.*]]
|
|
// SIMD-ONLY0: if.then4681:
|
|
// SIMD-ONLY0-NEXT: [[TMP3411:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3411]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4682]]
|
|
// SIMD-ONLY0: if.end4682:
|
|
// SIMD-ONLY0-NEXT: [[TMP3412:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3412]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3413:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3414:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4683:%.*]] = icmp ult i64 [[TMP3413]], [[TMP3414]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4683]], label [[IF_THEN4685:%.*]], label [[IF_END4686:%.*]]
|
|
// SIMD-ONLY0: if.then4685:
|
|
// SIMD-ONLY0-NEXT: [[TMP3415:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3415]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4686]]
|
|
// SIMD-ONLY0: if.end4686:
|
|
// SIMD-ONLY0-NEXT: [[TMP3416:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3416]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3417:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3418:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4687:%.*]] = icmp ult i64 [[TMP3417]], [[TMP3418]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4687]], label [[IF_THEN4689:%.*]], label [[IF_END4690:%.*]]
|
|
// SIMD-ONLY0: if.then4689:
|
|
// SIMD-ONLY0-NEXT: [[TMP3419:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3419]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4690]]
|
|
// SIMD-ONLY0: if.end4690:
|
|
// SIMD-ONLY0-NEXT: [[TMP3420:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3420]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3421:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3422:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4691:%.*]] = icmp eq i64 [[TMP3421]], [[TMP3422]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4691]], label [[IF_THEN4693:%.*]], label [[IF_END4694:%.*]]
|
|
// SIMD-ONLY0: if.then4693:
|
|
// SIMD-ONLY0-NEXT: [[TMP3423:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3423]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4694]]
|
|
// SIMD-ONLY0: if.end4694:
|
|
// SIMD-ONLY0-NEXT: [[TMP3424:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3424]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3425:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3426:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4695:%.*]] = icmp eq i64 [[TMP3425]], [[TMP3426]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4695]], label [[IF_THEN4697:%.*]], label [[IF_END4698:%.*]]
|
|
// SIMD-ONLY0: if.then4697:
|
|
// SIMD-ONLY0-NEXT: [[TMP3427:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3427]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4698]]
|
|
// SIMD-ONLY0: if.end4698:
|
|
// SIMD-ONLY0-NEXT: [[TMP3428:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3429:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4699:%.*]] = icmp ugt i64 [[TMP3428]], [[TMP3429]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4699]], label [[IF_THEN4701:%.*]], label [[IF_END4702:%.*]]
|
|
// SIMD-ONLY0: if.then4701:
|
|
// SIMD-ONLY0-NEXT: [[TMP3430:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3430]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4702]]
|
|
// SIMD-ONLY0: if.end4702:
|
|
// SIMD-ONLY0-NEXT: [[TMP3431:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3431]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3432:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3433:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4703:%.*]] = icmp ugt i64 [[TMP3432]], [[TMP3433]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4703]], label [[IF_THEN4705:%.*]], label [[IF_END4706:%.*]]
|
|
// SIMD-ONLY0: if.then4705:
|
|
// SIMD-ONLY0-NEXT: [[TMP3434:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3434]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4706]]
|
|
// SIMD-ONLY0: if.end4706:
|
|
// SIMD-ONLY0-NEXT: [[TMP3435:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3435]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3436:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3437:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4707:%.*]] = icmp ult i64 [[TMP3436]], [[TMP3437]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4707]], label [[IF_THEN4709:%.*]], label [[IF_END4710:%.*]]
|
|
// SIMD-ONLY0: if.then4709:
|
|
// SIMD-ONLY0-NEXT: [[TMP3438:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3438]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4710]]
|
|
// SIMD-ONLY0: if.end4710:
|
|
// SIMD-ONLY0-NEXT: [[TMP3439:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3439]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3440:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3441:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4711:%.*]] = icmp ult i64 [[TMP3440]], [[TMP3441]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4711]], label [[IF_THEN4713:%.*]], label [[IF_END4714:%.*]]
|
|
// SIMD-ONLY0: if.then4713:
|
|
// SIMD-ONLY0-NEXT: [[TMP3442:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3442]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4714]]
|
|
// SIMD-ONLY0: if.end4714:
|
|
// SIMD-ONLY0-NEXT: [[TMP3443:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3443]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3444:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3445:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4715:%.*]] = icmp eq i64 [[TMP3444]], [[TMP3445]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4715]], label [[IF_THEN4717:%.*]], label [[IF_END4718:%.*]]
|
|
// SIMD-ONLY0: if.then4717:
|
|
// SIMD-ONLY0-NEXT: [[TMP3446:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3446]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4718]]
|
|
// SIMD-ONLY0: if.end4718:
|
|
// SIMD-ONLY0-NEXT: [[TMP3447:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3447]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3448:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3449:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4719:%.*]] = icmp eq i64 [[TMP3448]], [[TMP3449]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4719]], label [[IF_THEN4721:%.*]], label [[IF_END4722:%.*]]
|
|
// SIMD-ONLY0: if.then4721:
|
|
// SIMD-ONLY0-NEXT: [[TMP3450:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3450]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4722]]
|
|
// SIMD-ONLY0: if.end4722:
|
|
// SIMD-ONLY0-NEXT: [[TMP3451:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3451]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3452:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3453:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4723:%.*]] = icmp eq i64 [[TMP3452]], [[TMP3453]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4723]], label [[IF_THEN4725:%.*]], label [[IF_ELSE4726:%.*]]
|
|
// SIMD-ONLY0: if.then4725:
|
|
// SIMD-ONLY0-NEXT: [[TMP3454:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3454]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4727:%.*]]
|
|
// SIMD-ONLY0: if.else4726:
|
|
// SIMD-ONLY0-NEXT: [[TMP3455:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3455]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4727]]
|
|
// SIMD-ONLY0: if.end4727:
|
|
// SIMD-ONLY0-NEXT: [[TMP3456:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3457:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4728:%.*]] = icmp eq i64 [[TMP3456]], [[TMP3457]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4728]], label [[IF_THEN4730:%.*]], label [[IF_ELSE4731:%.*]]
|
|
// SIMD-ONLY0: if.then4730:
|
|
// SIMD-ONLY0-NEXT: [[TMP3458:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3458]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4732:%.*]]
|
|
// SIMD-ONLY0: if.else4731:
|
|
// SIMD-ONLY0-NEXT: [[TMP3459:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3459]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4732]]
|
|
// SIMD-ONLY0: if.end4732:
|
|
// SIMD-ONLY0-NEXT: [[TMP3460:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3461:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4733:%.*]] = icmp eq i64 [[TMP3460]], [[TMP3461]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4734:%.*]] = zext i1 [[CMP4733]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4735:%.*]] = sext i32 [[CONV4734]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4735]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3462:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4736:%.*]] = icmp ne i64 [[TMP3462]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4736]], label [[IF_THEN4737:%.*]], label [[IF_END4738:%.*]]
|
|
// SIMD-ONLY0: if.then4737:
|
|
// SIMD-ONLY0-NEXT: [[TMP3463:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3463]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4738]]
|
|
// SIMD-ONLY0: if.end4738:
|
|
// SIMD-ONLY0-NEXT: [[TMP3464:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3465:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4739:%.*]] = icmp eq i64 [[TMP3464]], [[TMP3465]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4740:%.*]] = zext i1 [[CMP4739]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4741:%.*]] = sext i32 [[CONV4740]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4741]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3466:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4742:%.*]] = icmp ne i64 [[TMP3466]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4742]], label [[IF_THEN4743:%.*]], label [[IF_END4744:%.*]]
|
|
// SIMD-ONLY0: if.then4743:
|
|
// SIMD-ONLY0-NEXT: [[TMP3467:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3467]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4744]]
|
|
// SIMD-ONLY0: if.end4744:
|
|
// SIMD-ONLY0-NEXT: [[TMP3468:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3469:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4745:%.*]] = icmp eq i64 [[TMP3468]], [[TMP3469]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4746:%.*]] = zext i1 [[CMP4745]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4747:%.*]] = sext i32 [[CONV4746]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4747]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3470:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4748:%.*]] = icmp ne i64 [[TMP3470]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4748]], label [[IF_THEN4749:%.*]], label [[IF_ELSE4750:%.*]]
|
|
// SIMD-ONLY0: if.then4749:
|
|
// SIMD-ONLY0-NEXT: [[TMP3471:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3471]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4751:%.*]]
|
|
// SIMD-ONLY0: if.else4750:
|
|
// SIMD-ONLY0-NEXT: [[TMP3472:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3472]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4751]]
|
|
// SIMD-ONLY0: if.end4751:
|
|
// SIMD-ONLY0-NEXT: [[TMP3473:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3474:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4752:%.*]] = icmp eq i64 [[TMP3473]], [[TMP3474]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4753:%.*]] = zext i1 [[CMP4752]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4754:%.*]] = sext i32 [[CONV4753]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4754]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3475:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4755:%.*]] = icmp ne i64 [[TMP3475]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4755]], label [[IF_THEN4756:%.*]], label [[IF_ELSE4757:%.*]]
|
|
// SIMD-ONLY0: if.then4756:
|
|
// SIMD-ONLY0-NEXT: [[TMP3476:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3476]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4758:%.*]]
|
|
// SIMD-ONLY0: if.else4757:
|
|
// SIMD-ONLY0-NEXT: [[TMP3477:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3477]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4758]]
|
|
// SIMD-ONLY0: if.end4758:
|
|
// SIMD-ONLY0-NEXT: [[TMP3478:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3478]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3479:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3480:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4759:%.*]] = icmp ugt i64 [[TMP3479]], [[TMP3480]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4759]], label [[IF_THEN4761:%.*]], label [[IF_END4762:%.*]]
|
|
// SIMD-ONLY0: if.then4761:
|
|
// SIMD-ONLY0-NEXT: [[TMP3481:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3481]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4762]]
|
|
// SIMD-ONLY0: if.end4762:
|
|
// SIMD-ONLY0-NEXT: [[TMP3482:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3482]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3483:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3484:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4763:%.*]] = icmp ugt i64 [[TMP3483]], [[TMP3484]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4763]], label [[IF_THEN4765:%.*]], label [[IF_END4766:%.*]]
|
|
// SIMD-ONLY0: if.then4765:
|
|
// SIMD-ONLY0-NEXT: [[TMP3485:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3485]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4766]]
|
|
// SIMD-ONLY0: if.end4766:
|
|
// SIMD-ONLY0-NEXT: [[TMP3486:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3486]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3487:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3488:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4767:%.*]] = icmp ult i64 [[TMP3487]], [[TMP3488]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4767]], label [[IF_THEN4769:%.*]], label [[IF_END4770:%.*]]
|
|
// SIMD-ONLY0: if.then4769:
|
|
// SIMD-ONLY0-NEXT: [[TMP3489:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3489]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4770]]
|
|
// SIMD-ONLY0: if.end4770:
|
|
// SIMD-ONLY0-NEXT: [[TMP3490:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3490]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3491:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3492:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4771:%.*]] = icmp ult i64 [[TMP3491]], [[TMP3492]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4771]], label [[IF_THEN4773:%.*]], label [[IF_END4774:%.*]]
|
|
// SIMD-ONLY0: if.then4773:
|
|
// SIMD-ONLY0-NEXT: [[TMP3493:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3493]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4774]]
|
|
// SIMD-ONLY0: if.end4774:
|
|
// SIMD-ONLY0-NEXT: [[TMP3494:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3494]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3495:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3496:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4775:%.*]] = icmp eq i64 [[TMP3495]], [[TMP3496]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4775]], label [[IF_THEN4777:%.*]], label [[IF_END4778:%.*]]
|
|
// SIMD-ONLY0: if.then4777:
|
|
// SIMD-ONLY0-NEXT: [[TMP3497:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3497]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4778]]
|
|
// SIMD-ONLY0: if.end4778:
|
|
// SIMD-ONLY0-NEXT: [[TMP3498:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3498]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3499:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3500:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4779:%.*]] = icmp eq i64 [[TMP3499]], [[TMP3500]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4779]], label [[IF_THEN4781:%.*]], label [[IF_END4782:%.*]]
|
|
// SIMD-ONLY0: if.then4781:
|
|
// SIMD-ONLY0-NEXT: [[TMP3501:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3501]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4782]]
|
|
// SIMD-ONLY0: if.end4782:
|
|
// SIMD-ONLY0-NEXT: [[TMP3502:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3503:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4783:%.*]] = icmp ugt i64 [[TMP3502]], [[TMP3503]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4783]], label [[IF_THEN4785:%.*]], label [[IF_END4786:%.*]]
|
|
// SIMD-ONLY0: if.then4785:
|
|
// SIMD-ONLY0-NEXT: [[TMP3504:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3504]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4786]]
|
|
// SIMD-ONLY0: if.end4786:
|
|
// SIMD-ONLY0-NEXT: [[TMP3505:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3505]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3506:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3507:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4787:%.*]] = icmp ugt i64 [[TMP3506]], [[TMP3507]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4787]], label [[IF_THEN4789:%.*]], label [[IF_END4790:%.*]]
|
|
// SIMD-ONLY0: if.then4789:
|
|
// SIMD-ONLY0-NEXT: [[TMP3508:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3508]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4790]]
|
|
// SIMD-ONLY0: if.end4790:
|
|
// SIMD-ONLY0-NEXT: [[TMP3509:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3509]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3510:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3511:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4791:%.*]] = icmp ult i64 [[TMP3510]], [[TMP3511]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4791]], label [[IF_THEN4793:%.*]], label [[IF_END4794:%.*]]
|
|
// SIMD-ONLY0: if.then4793:
|
|
// SIMD-ONLY0-NEXT: [[TMP3512:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3512]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4794]]
|
|
// SIMD-ONLY0: if.end4794:
|
|
// SIMD-ONLY0-NEXT: [[TMP3513:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3513]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3514:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3515:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4795:%.*]] = icmp ult i64 [[TMP3514]], [[TMP3515]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4795]], label [[IF_THEN4797:%.*]], label [[IF_END4798:%.*]]
|
|
// SIMD-ONLY0: if.then4797:
|
|
// SIMD-ONLY0-NEXT: [[TMP3516:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3516]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4798]]
|
|
// SIMD-ONLY0: if.end4798:
|
|
// SIMD-ONLY0-NEXT: [[TMP3517:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3517]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3518:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3519:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4799:%.*]] = icmp eq i64 [[TMP3518]], [[TMP3519]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4799]], label [[IF_THEN4801:%.*]], label [[IF_END4802:%.*]]
|
|
// SIMD-ONLY0: if.then4801:
|
|
// SIMD-ONLY0-NEXT: [[TMP3520:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3520]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4802]]
|
|
// SIMD-ONLY0: if.end4802:
|
|
// SIMD-ONLY0-NEXT: [[TMP3521:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3521]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3522:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3523:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4803:%.*]] = icmp eq i64 [[TMP3522]], [[TMP3523]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4803]], label [[IF_THEN4805:%.*]], label [[IF_END4806:%.*]]
|
|
// SIMD-ONLY0: if.then4805:
|
|
// SIMD-ONLY0-NEXT: [[TMP3524:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3524]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4806]]
|
|
// SIMD-ONLY0: if.end4806:
|
|
// SIMD-ONLY0-NEXT: [[TMP3525:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3525]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3526:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3527:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4807:%.*]] = icmp eq i64 [[TMP3526]], [[TMP3527]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4807]], label [[IF_THEN4809:%.*]], label [[IF_ELSE4810:%.*]]
|
|
// SIMD-ONLY0: if.then4809:
|
|
// SIMD-ONLY0-NEXT: [[TMP3528:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3528]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4811:%.*]]
|
|
// SIMD-ONLY0: if.else4810:
|
|
// SIMD-ONLY0-NEXT: [[TMP3529:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3529]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4811]]
|
|
// SIMD-ONLY0: if.end4811:
|
|
// SIMD-ONLY0-NEXT: [[TMP3530:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3531:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4812:%.*]] = icmp eq i64 [[TMP3530]], [[TMP3531]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4812]], label [[IF_THEN4814:%.*]], label [[IF_ELSE4815:%.*]]
|
|
// SIMD-ONLY0: if.then4814:
|
|
// SIMD-ONLY0-NEXT: [[TMP3532:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3532]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4816:%.*]]
|
|
// SIMD-ONLY0: if.else4815:
|
|
// SIMD-ONLY0-NEXT: [[TMP3533:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3533]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4816]]
|
|
// SIMD-ONLY0: if.end4816:
|
|
// SIMD-ONLY0-NEXT: [[TMP3534:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3535:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4817:%.*]] = icmp eq i64 [[TMP3534]], [[TMP3535]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4818:%.*]] = zext i1 [[CMP4817]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4819:%.*]] = sext i32 [[CONV4818]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4819]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3536:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4820:%.*]] = icmp ne i64 [[TMP3536]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4820]], label [[IF_THEN4821:%.*]], label [[IF_END4822:%.*]]
|
|
// SIMD-ONLY0: if.then4821:
|
|
// SIMD-ONLY0-NEXT: [[TMP3537:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3537]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4822]]
|
|
// SIMD-ONLY0: if.end4822:
|
|
// SIMD-ONLY0-NEXT: [[TMP3538:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3539:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4823:%.*]] = icmp eq i64 [[TMP3538]], [[TMP3539]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4824:%.*]] = zext i1 [[CMP4823]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4825:%.*]] = sext i32 [[CONV4824]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4825]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3540:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4826:%.*]] = icmp ne i64 [[TMP3540]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4826]], label [[IF_THEN4827:%.*]], label [[IF_END4828:%.*]]
|
|
// SIMD-ONLY0: if.then4827:
|
|
// SIMD-ONLY0-NEXT: [[TMP3541:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3541]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4828]]
|
|
// SIMD-ONLY0: if.end4828:
|
|
// SIMD-ONLY0-NEXT: [[TMP3542:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3543:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4829:%.*]] = icmp eq i64 [[TMP3542]], [[TMP3543]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4830:%.*]] = zext i1 [[CMP4829]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4831:%.*]] = sext i32 [[CONV4830]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4831]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3544:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4832:%.*]] = icmp ne i64 [[TMP3544]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4832]], label [[IF_THEN4833:%.*]], label [[IF_ELSE4834:%.*]]
|
|
// SIMD-ONLY0: if.then4833:
|
|
// SIMD-ONLY0-NEXT: [[TMP3545:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3545]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4835:%.*]]
|
|
// SIMD-ONLY0: if.else4834:
|
|
// SIMD-ONLY0-NEXT: [[TMP3546:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3546]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4835]]
|
|
// SIMD-ONLY0: if.end4835:
|
|
// SIMD-ONLY0-NEXT: [[TMP3547:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3548:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4836:%.*]] = icmp eq i64 [[TMP3547]], [[TMP3548]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4837:%.*]] = zext i1 [[CMP4836]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4838:%.*]] = sext i32 [[CONV4837]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4838]], ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3549:%.*]] = load i64, ptr [[ULR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4839:%.*]] = icmp ne i64 [[TMP3549]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4839]], label [[IF_THEN4840:%.*]], label [[IF_ELSE4841:%.*]]
|
|
// SIMD-ONLY0: if.then4840:
|
|
// SIMD-ONLY0-NEXT: [[TMP3550:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3550]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4842:%.*]]
|
|
// SIMD-ONLY0: if.else4841:
|
|
// SIMD-ONLY0-NEXT: [[TMP3551:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3551]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4842]]
|
|
// SIMD-ONLY0: if.end4842:
|
|
// SIMD-ONLY0-NEXT: [[TMP3552:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3552]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3553:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3554:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4843:%.*]] = icmp sgt i64 [[TMP3553]], [[TMP3554]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4843]], label [[IF_THEN4845:%.*]], label [[IF_END4846:%.*]]
|
|
// SIMD-ONLY0: if.then4845:
|
|
// SIMD-ONLY0-NEXT: [[TMP3555:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3555]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4846]]
|
|
// SIMD-ONLY0: if.end4846:
|
|
// SIMD-ONLY0-NEXT: [[TMP3556:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3556]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3557:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3558:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4847:%.*]] = icmp sgt i64 [[TMP3557]], [[TMP3558]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4847]], label [[IF_THEN4849:%.*]], label [[IF_END4850:%.*]]
|
|
// SIMD-ONLY0: if.then4849:
|
|
// SIMD-ONLY0-NEXT: [[TMP3559:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3559]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4850]]
|
|
// SIMD-ONLY0: if.end4850:
|
|
// SIMD-ONLY0-NEXT: [[TMP3560:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3560]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3561:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3562:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4851:%.*]] = icmp slt i64 [[TMP3561]], [[TMP3562]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4851]], label [[IF_THEN4853:%.*]], label [[IF_END4854:%.*]]
|
|
// SIMD-ONLY0: if.then4853:
|
|
// SIMD-ONLY0-NEXT: [[TMP3563:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3563]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4854]]
|
|
// SIMD-ONLY0: if.end4854:
|
|
// SIMD-ONLY0-NEXT: [[TMP3564:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3564]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3565:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3566:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4855:%.*]] = icmp slt i64 [[TMP3565]], [[TMP3566]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4855]], label [[IF_THEN4857:%.*]], label [[IF_END4858:%.*]]
|
|
// SIMD-ONLY0: if.then4857:
|
|
// SIMD-ONLY0-NEXT: [[TMP3567:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3567]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4858]]
|
|
// SIMD-ONLY0: if.end4858:
|
|
// SIMD-ONLY0-NEXT: [[TMP3568:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3568]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3569:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3570:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4859:%.*]] = icmp eq i64 [[TMP3569]], [[TMP3570]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4859]], label [[IF_THEN4861:%.*]], label [[IF_END4862:%.*]]
|
|
// SIMD-ONLY0: if.then4861:
|
|
// SIMD-ONLY0-NEXT: [[TMP3571:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3571]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4862]]
|
|
// SIMD-ONLY0: if.end4862:
|
|
// SIMD-ONLY0-NEXT: [[TMP3572:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3572]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3573:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3574:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4863:%.*]] = icmp eq i64 [[TMP3573]], [[TMP3574]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4863]], label [[IF_THEN4865:%.*]], label [[IF_END4866:%.*]]
|
|
// SIMD-ONLY0: if.then4865:
|
|
// SIMD-ONLY0-NEXT: [[TMP3575:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3575]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4866]]
|
|
// SIMD-ONLY0: if.end4866:
|
|
// SIMD-ONLY0-NEXT: [[TMP3576:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3577:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4867:%.*]] = icmp sgt i64 [[TMP3576]], [[TMP3577]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4867]], label [[IF_THEN4869:%.*]], label [[IF_END4870:%.*]]
|
|
// SIMD-ONLY0: if.then4869:
|
|
// SIMD-ONLY0-NEXT: [[TMP3578:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3578]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4870]]
|
|
// SIMD-ONLY0: if.end4870:
|
|
// SIMD-ONLY0-NEXT: [[TMP3579:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3579]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3580:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3581:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4871:%.*]] = icmp sgt i64 [[TMP3580]], [[TMP3581]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4871]], label [[IF_THEN4873:%.*]], label [[IF_END4874:%.*]]
|
|
// SIMD-ONLY0: if.then4873:
|
|
// SIMD-ONLY0-NEXT: [[TMP3582:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3582]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4874]]
|
|
// SIMD-ONLY0: if.end4874:
|
|
// SIMD-ONLY0-NEXT: [[TMP3583:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3583]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3584:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3585:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4875:%.*]] = icmp slt i64 [[TMP3584]], [[TMP3585]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4875]], label [[IF_THEN4877:%.*]], label [[IF_END4878:%.*]]
|
|
// SIMD-ONLY0: if.then4877:
|
|
// SIMD-ONLY0-NEXT: [[TMP3586:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3586]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4878]]
|
|
// SIMD-ONLY0: if.end4878:
|
|
// SIMD-ONLY0-NEXT: [[TMP3587:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3587]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3588:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3589:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4879:%.*]] = icmp slt i64 [[TMP3588]], [[TMP3589]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4879]], label [[IF_THEN4881:%.*]], label [[IF_END4882:%.*]]
|
|
// SIMD-ONLY0: if.then4881:
|
|
// SIMD-ONLY0-NEXT: [[TMP3590:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3590]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4882]]
|
|
// SIMD-ONLY0: if.end4882:
|
|
// SIMD-ONLY0-NEXT: [[TMP3591:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3591]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3592:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3593:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4883:%.*]] = icmp eq i64 [[TMP3592]], [[TMP3593]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4883]], label [[IF_THEN4885:%.*]], label [[IF_END4886:%.*]]
|
|
// SIMD-ONLY0: if.then4885:
|
|
// SIMD-ONLY0-NEXT: [[TMP3594:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3594]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4886]]
|
|
// SIMD-ONLY0: if.end4886:
|
|
// SIMD-ONLY0-NEXT: [[TMP3595:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3595]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3596:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3597:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4887:%.*]] = icmp eq i64 [[TMP3596]], [[TMP3597]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4887]], label [[IF_THEN4889:%.*]], label [[IF_END4890:%.*]]
|
|
// SIMD-ONLY0: if.then4889:
|
|
// SIMD-ONLY0-NEXT: [[TMP3598:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3598]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4890]]
|
|
// SIMD-ONLY0: if.end4890:
|
|
// SIMD-ONLY0-NEXT: [[TMP3599:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3599]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3600:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3601:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4891:%.*]] = icmp eq i64 [[TMP3600]], [[TMP3601]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4891]], label [[IF_THEN4893:%.*]], label [[IF_ELSE4894:%.*]]
|
|
// SIMD-ONLY0: if.then4893:
|
|
// SIMD-ONLY0-NEXT: [[TMP3602:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3602]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4895:%.*]]
|
|
// SIMD-ONLY0: if.else4894:
|
|
// SIMD-ONLY0-NEXT: [[TMP3603:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3603]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4895]]
|
|
// SIMD-ONLY0: if.end4895:
|
|
// SIMD-ONLY0-NEXT: [[TMP3604:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3605:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4896:%.*]] = icmp eq i64 [[TMP3604]], [[TMP3605]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4896]], label [[IF_THEN4898:%.*]], label [[IF_ELSE4899:%.*]]
|
|
// SIMD-ONLY0: if.then4898:
|
|
// SIMD-ONLY0-NEXT: [[TMP3606:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3606]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4900:%.*]]
|
|
// SIMD-ONLY0: if.else4899:
|
|
// SIMD-ONLY0-NEXT: [[TMP3607:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3607]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4900]]
|
|
// SIMD-ONLY0: if.end4900:
|
|
// SIMD-ONLY0-NEXT: [[TMP3608:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3609:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4901:%.*]] = icmp eq i64 [[TMP3608]], [[TMP3609]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4902:%.*]] = zext i1 [[CMP4901]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4903:%.*]] = sext i32 [[CONV4902]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4903]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3610:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4904:%.*]] = icmp ne i64 [[TMP3610]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4904]], label [[IF_THEN4905:%.*]], label [[IF_END4906:%.*]]
|
|
// SIMD-ONLY0: if.then4905:
|
|
// SIMD-ONLY0-NEXT: [[TMP3611:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3611]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4906]]
|
|
// SIMD-ONLY0: if.end4906:
|
|
// SIMD-ONLY0-NEXT: [[TMP3612:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3613:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4907:%.*]] = icmp eq i64 [[TMP3612]], [[TMP3613]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4908:%.*]] = zext i1 [[CMP4907]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4909:%.*]] = sext i32 [[CONV4908]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4909]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3614:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4910:%.*]] = icmp ne i64 [[TMP3614]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4910]], label [[IF_THEN4911:%.*]], label [[IF_END4912:%.*]]
|
|
// SIMD-ONLY0: if.then4911:
|
|
// SIMD-ONLY0-NEXT: [[TMP3615:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3615]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4912]]
|
|
// SIMD-ONLY0: if.end4912:
|
|
// SIMD-ONLY0-NEXT: [[TMP3616:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3617:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4913:%.*]] = icmp eq i64 [[TMP3616]], [[TMP3617]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4914:%.*]] = zext i1 [[CMP4913]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4915:%.*]] = sext i32 [[CONV4914]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4915]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3618:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4916:%.*]] = icmp ne i64 [[TMP3618]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4916]], label [[IF_THEN4917:%.*]], label [[IF_ELSE4918:%.*]]
|
|
// SIMD-ONLY0: if.then4917:
|
|
// SIMD-ONLY0-NEXT: [[TMP3619:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3619]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4919:%.*]]
|
|
// SIMD-ONLY0: if.else4918:
|
|
// SIMD-ONLY0-NEXT: [[TMP3620:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3620]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4919]]
|
|
// SIMD-ONLY0: if.end4919:
|
|
// SIMD-ONLY0-NEXT: [[TMP3621:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3622:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4920:%.*]] = icmp eq i64 [[TMP3621]], [[TMP3622]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4921:%.*]] = zext i1 [[CMP4920]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4922:%.*]] = sext i32 [[CONV4921]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4922]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3623:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4923:%.*]] = icmp ne i64 [[TMP3623]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4923]], label [[IF_THEN4924:%.*]], label [[IF_ELSE4925:%.*]]
|
|
// SIMD-ONLY0: if.then4924:
|
|
// SIMD-ONLY0-NEXT: [[TMP3624:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3624]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4926:%.*]]
|
|
// SIMD-ONLY0: if.else4925:
|
|
// SIMD-ONLY0-NEXT: [[TMP3625:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3625]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4926]]
|
|
// SIMD-ONLY0: if.end4926:
|
|
// SIMD-ONLY0-NEXT: [[TMP3626:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3626]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3627:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3628:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4927:%.*]] = icmp sgt i64 [[TMP3627]], [[TMP3628]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4927]], label [[IF_THEN4929:%.*]], label [[IF_END4930:%.*]]
|
|
// SIMD-ONLY0: if.then4929:
|
|
// SIMD-ONLY0-NEXT: [[TMP3629:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3629]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4930]]
|
|
// SIMD-ONLY0: if.end4930:
|
|
// SIMD-ONLY0-NEXT: [[TMP3630:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3630]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3631:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3632:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4931:%.*]] = icmp sgt i64 [[TMP3631]], [[TMP3632]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4931]], label [[IF_THEN4933:%.*]], label [[IF_END4934:%.*]]
|
|
// SIMD-ONLY0: if.then4933:
|
|
// SIMD-ONLY0-NEXT: [[TMP3633:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3633]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4934]]
|
|
// SIMD-ONLY0: if.end4934:
|
|
// SIMD-ONLY0-NEXT: [[TMP3634:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3634]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3635:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3636:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4935:%.*]] = icmp slt i64 [[TMP3635]], [[TMP3636]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4935]], label [[IF_THEN4937:%.*]], label [[IF_END4938:%.*]]
|
|
// SIMD-ONLY0: if.then4937:
|
|
// SIMD-ONLY0-NEXT: [[TMP3637:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3637]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4938]]
|
|
// SIMD-ONLY0: if.end4938:
|
|
// SIMD-ONLY0-NEXT: [[TMP3638:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3638]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3639:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3640:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4939:%.*]] = icmp slt i64 [[TMP3639]], [[TMP3640]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4939]], label [[IF_THEN4941:%.*]], label [[IF_END4942:%.*]]
|
|
// SIMD-ONLY0: if.then4941:
|
|
// SIMD-ONLY0-NEXT: [[TMP3641:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3641]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4942]]
|
|
// SIMD-ONLY0: if.end4942:
|
|
// SIMD-ONLY0-NEXT: [[TMP3642:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3642]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3643:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3644:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4943:%.*]] = icmp eq i64 [[TMP3643]], [[TMP3644]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4943]], label [[IF_THEN4945:%.*]], label [[IF_END4946:%.*]]
|
|
// SIMD-ONLY0: if.then4945:
|
|
// SIMD-ONLY0-NEXT: [[TMP3645:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3645]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4946]]
|
|
// SIMD-ONLY0: if.end4946:
|
|
// SIMD-ONLY0-NEXT: [[TMP3646:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3646]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3647:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3648:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4947:%.*]] = icmp eq i64 [[TMP3647]], [[TMP3648]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4947]], label [[IF_THEN4949:%.*]], label [[IF_END4950:%.*]]
|
|
// SIMD-ONLY0: if.then4949:
|
|
// SIMD-ONLY0-NEXT: [[TMP3649:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3649]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4950]]
|
|
// SIMD-ONLY0: if.end4950:
|
|
// SIMD-ONLY0-NEXT: [[TMP3650:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3651:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4951:%.*]] = icmp sgt i64 [[TMP3650]], [[TMP3651]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4951]], label [[IF_THEN4953:%.*]], label [[IF_END4954:%.*]]
|
|
// SIMD-ONLY0: if.then4953:
|
|
// SIMD-ONLY0-NEXT: [[TMP3652:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3652]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4954]]
|
|
// SIMD-ONLY0: if.end4954:
|
|
// SIMD-ONLY0-NEXT: [[TMP3653:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3653]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3654:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3655:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4955:%.*]] = icmp sgt i64 [[TMP3654]], [[TMP3655]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4955]], label [[IF_THEN4957:%.*]], label [[IF_END4958:%.*]]
|
|
// SIMD-ONLY0: if.then4957:
|
|
// SIMD-ONLY0-NEXT: [[TMP3656:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3656]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4958]]
|
|
// SIMD-ONLY0: if.end4958:
|
|
// SIMD-ONLY0-NEXT: [[TMP3657:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3657]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3658:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3659:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4959:%.*]] = icmp slt i64 [[TMP3658]], [[TMP3659]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4959]], label [[IF_THEN4961:%.*]], label [[IF_END4962:%.*]]
|
|
// SIMD-ONLY0: if.then4961:
|
|
// SIMD-ONLY0-NEXT: [[TMP3660:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3660]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4962]]
|
|
// SIMD-ONLY0: if.end4962:
|
|
// SIMD-ONLY0-NEXT: [[TMP3661:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3661]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3662:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3663:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4963:%.*]] = icmp slt i64 [[TMP3662]], [[TMP3663]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4963]], label [[IF_THEN4965:%.*]], label [[IF_END4966:%.*]]
|
|
// SIMD-ONLY0: if.then4965:
|
|
// SIMD-ONLY0-NEXT: [[TMP3664:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3664]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4966]]
|
|
// SIMD-ONLY0: if.end4966:
|
|
// SIMD-ONLY0-NEXT: [[TMP3665:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3665]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3666:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3667:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4967:%.*]] = icmp eq i64 [[TMP3666]], [[TMP3667]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4967]], label [[IF_THEN4969:%.*]], label [[IF_END4970:%.*]]
|
|
// SIMD-ONLY0: if.then4969:
|
|
// SIMD-ONLY0-NEXT: [[TMP3668:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3668]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4970]]
|
|
// SIMD-ONLY0: if.end4970:
|
|
// SIMD-ONLY0-NEXT: [[TMP3669:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3669]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3670:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3671:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4971:%.*]] = icmp eq i64 [[TMP3670]], [[TMP3671]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4971]], label [[IF_THEN4973:%.*]], label [[IF_END4974:%.*]]
|
|
// SIMD-ONLY0: if.then4973:
|
|
// SIMD-ONLY0-NEXT: [[TMP3672:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3672]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4974]]
|
|
// SIMD-ONLY0: if.end4974:
|
|
// SIMD-ONLY0-NEXT: [[TMP3673:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3673]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3674:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3675:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4975:%.*]] = icmp eq i64 [[TMP3674]], [[TMP3675]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4975]], label [[IF_THEN4977:%.*]], label [[IF_ELSE4978:%.*]]
|
|
// SIMD-ONLY0: if.then4977:
|
|
// SIMD-ONLY0-NEXT: [[TMP3676:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3676]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4979:%.*]]
|
|
// SIMD-ONLY0: if.else4978:
|
|
// SIMD-ONLY0-NEXT: [[TMP3677:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3677]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4979]]
|
|
// SIMD-ONLY0: if.end4979:
|
|
// SIMD-ONLY0-NEXT: [[TMP3678:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3679:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4980:%.*]] = icmp eq i64 [[TMP3678]], [[TMP3679]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP4980]], label [[IF_THEN4982:%.*]], label [[IF_ELSE4983:%.*]]
|
|
// SIMD-ONLY0: if.then4982:
|
|
// SIMD-ONLY0-NEXT: [[TMP3680:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3680]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4984:%.*]]
|
|
// SIMD-ONLY0: if.else4983:
|
|
// SIMD-ONLY0-NEXT: [[TMP3681:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3681]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4984]]
|
|
// SIMD-ONLY0: if.end4984:
|
|
// SIMD-ONLY0-NEXT: [[TMP3682:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3683:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4985:%.*]] = icmp eq i64 [[TMP3682]], [[TMP3683]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4986:%.*]] = zext i1 [[CMP4985]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4987:%.*]] = sext i32 [[CONV4986]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4987]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3684:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4988:%.*]] = icmp ne i64 [[TMP3684]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4988]], label [[IF_THEN4989:%.*]], label [[IF_END4990:%.*]]
|
|
// SIMD-ONLY0: if.then4989:
|
|
// SIMD-ONLY0-NEXT: [[TMP3685:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3685]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4990]]
|
|
// SIMD-ONLY0: if.end4990:
|
|
// SIMD-ONLY0-NEXT: [[TMP3686:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3687:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4991:%.*]] = icmp eq i64 [[TMP3686]], [[TMP3687]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4992:%.*]] = zext i1 [[CMP4991]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4993:%.*]] = sext i32 [[CONV4992]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4993]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3688:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL4994:%.*]] = icmp ne i64 [[TMP3688]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL4994]], label [[IF_THEN4995:%.*]], label [[IF_END4996:%.*]]
|
|
// SIMD-ONLY0: if.then4995:
|
|
// SIMD-ONLY0-NEXT: [[TMP3689:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3689]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END4996]]
|
|
// SIMD-ONLY0: if.end4996:
|
|
// SIMD-ONLY0-NEXT: [[TMP3690:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3691:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP4997:%.*]] = icmp eq i64 [[TMP3690]], [[TMP3691]]
|
|
// SIMD-ONLY0-NEXT: [[CONV4998:%.*]] = zext i1 [[CMP4997]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV4999:%.*]] = sext i32 [[CONV4998]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV4999]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3692:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5000:%.*]] = icmp ne i64 [[TMP3692]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5000]], label [[IF_THEN5001:%.*]], label [[IF_ELSE5002:%.*]]
|
|
// SIMD-ONLY0: if.then5001:
|
|
// SIMD-ONLY0-NEXT: [[TMP3693:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3693]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5003:%.*]]
|
|
// SIMD-ONLY0: if.else5002:
|
|
// SIMD-ONLY0-NEXT: [[TMP3694:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3694]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5003]]
|
|
// SIMD-ONLY0: if.end5003:
|
|
// SIMD-ONLY0-NEXT: [[TMP3695:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3696:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5004:%.*]] = icmp eq i64 [[TMP3695]], [[TMP3696]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5005:%.*]] = zext i1 [[CMP5004]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5006:%.*]] = sext i32 [[CONV5005]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5006]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3697:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5007:%.*]] = icmp ne i64 [[TMP3697]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5007]], label [[IF_THEN5008:%.*]], label [[IF_ELSE5009:%.*]]
|
|
// SIMD-ONLY0: if.then5008:
|
|
// SIMD-ONLY0-NEXT: [[TMP3698:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3698]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5010:%.*]]
|
|
// SIMD-ONLY0: if.else5009:
|
|
// SIMD-ONLY0-NEXT: [[TMP3699:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3699]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5010]]
|
|
// SIMD-ONLY0: if.end5010:
|
|
// SIMD-ONLY0-NEXT: [[TMP3700:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3700]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3701:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3702:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5011:%.*]] = icmp sgt i64 [[TMP3701]], [[TMP3702]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5011]], label [[IF_THEN5013:%.*]], label [[IF_END5014:%.*]]
|
|
// SIMD-ONLY0: if.then5013:
|
|
// SIMD-ONLY0-NEXT: [[TMP3703:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3703]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5014]]
|
|
// SIMD-ONLY0: if.end5014:
|
|
// SIMD-ONLY0-NEXT: [[TMP3704:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3704]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3705:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3706:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5015:%.*]] = icmp sgt i64 [[TMP3705]], [[TMP3706]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5015]], label [[IF_THEN5017:%.*]], label [[IF_END5018:%.*]]
|
|
// SIMD-ONLY0: if.then5017:
|
|
// SIMD-ONLY0-NEXT: [[TMP3707:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3707]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5018]]
|
|
// SIMD-ONLY0: if.end5018:
|
|
// SIMD-ONLY0-NEXT: [[TMP3708:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3708]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3709:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3710:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5019:%.*]] = icmp slt i64 [[TMP3709]], [[TMP3710]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5019]], label [[IF_THEN5021:%.*]], label [[IF_END5022:%.*]]
|
|
// SIMD-ONLY0: if.then5021:
|
|
// SIMD-ONLY0-NEXT: [[TMP3711:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3711]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5022]]
|
|
// SIMD-ONLY0: if.end5022:
|
|
// SIMD-ONLY0-NEXT: [[TMP3712:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3712]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3713:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3714:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5023:%.*]] = icmp slt i64 [[TMP3713]], [[TMP3714]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5023]], label [[IF_THEN5025:%.*]], label [[IF_END5026:%.*]]
|
|
// SIMD-ONLY0: if.then5025:
|
|
// SIMD-ONLY0-NEXT: [[TMP3715:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3715]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5026]]
|
|
// SIMD-ONLY0: if.end5026:
|
|
// SIMD-ONLY0-NEXT: [[TMP3716:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3716]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3717:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3718:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5027:%.*]] = icmp eq i64 [[TMP3717]], [[TMP3718]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5027]], label [[IF_THEN5029:%.*]], label [[IF_END5030:%.*]]
|
|
// SIMD-ONLY0: if.then5029:
|
|
// SIMD-ONLY0-NEXT: [[TMP3719:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3719]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5030]]
|
|
// SIMD-ONLY0: if.end5030:
|
|
// SIMD-ONLY0-NEXT: [[TMP3720:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3720]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3721:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3722:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5031:%.*]] = icmp eq i64 [[TMP3721]], [[TMP3722]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5031]], label [[IF_THEN5033:%.*]], label [[IF_END5034:%.*]]
|
|
// SIMD-ONLY0: if.then5033:
|
|
// SIMD-ONLY0-NEXT: [[TMP3723:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3723]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5034]]
|
|
// SIMD-ONLY0: if.end5034:
|
|
// SIMD-ONLY0-NEXT: [[TMP3724:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3725:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5035:%.*]] = icmp sgt i64 [[TMP3724]], [[TMP3725]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5035]], label [[IF_THEN5037:%.*]], label [[IF_END5038:%.*]]
|
|
// SIMD-ONLY0: if.then5037:
|
|
// SIMD-ONLY0-NEXT: [[TMP3726:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3726]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5038]]
|
|
// SIMD-ONLY0: if.end5038:
|
|
// SIMD-ONLY0-NEXT: [[TMP3727:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3727]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3728:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3729:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5039:%.*]] = icmp sgt i64 [[TMP3728]], [[TMP3729]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5039]], label [[IF_THEN5041:%.*]], label [[IF_END5042:%.*]]
|
|
// SIMD-ONLY0: if.then5041:
|
|
// SIMD-ONLY0-NEXT: [[TMP3730:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3730]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5042]]
|
|
// SIMD-ONLY0: if.end5042:
|
|
// SIMD-ONLY0-NEXT: [[TMP3731:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3731]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3732:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3733:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5043:%.*]] = icmp slt i64 [[TMP3732]], [[TMP3733]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5043]], label [[IF_THEN5045:%.*]], label [[IF_END5046:%.*]]
|
|
// SIMD-ONLY0: if.then5045:
|
|
// SIMD-ONLY0-NEXT: [[TMP3734:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3734]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5046]]
|
|
// SIMD-ONLY0: if.end5046:
|
|
// SIMD-ONLY0-NEXT: [[TMP3735:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3735]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3736:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3737:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5047:%.*]] = icmp slt i64 [[TMP3736]], [[TMP3737]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5047]], label [[IF_THEN5049:%.*]], label [[IF_END5050:%.*]]
|
|
// SIMD-ONLY0: if.then5049:
|
|
// SIMD-ONLY0-NEXT: [[TMP3738:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3738]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5050]]
|
|
// SIMD-ONLY0: if.end5050:
|
|
// SIMD-ONLY0-NEXT: [[TMP3739:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3739]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3740:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3741:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5051:%.*]] = icmp eq i64 [[TMP3740]], [[TMP3741]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5051]], label [[IF_THEN5053:%.*]], label [[IF_END5054:%.*]]
|
|
// SIMD-ONLY0: if.then5053:
|
|
// SIMD-ONLY0-NEXT: [[TMP3742:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3742]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5054]]
|
|
// SIMD-ONLY0: if.end5054:
|
|
// SIMD-ONLY0-NEXT: [[TMP3743:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3743]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3744:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3745:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5055:%.*]] = icmp eq i64 [[TMP3744]], [[TMP3745]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5055]], label [[IF_THEN5057:%.*]], label [[IF_END5058:%.*]]
|
|
// SIMD-ONLY0: if.then5057:
|
|
// SIMD-ONLY0-NEXT: [[TMP3746:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3746]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5058]]
|
|
// SIMD-ONLY0: if.end5058:
|
|
// SIMD-ONLY0-NEXT: [[TMP3747:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3747]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3748:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3749:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5059:%.*]] = icmp eq i64 [[TMP3748]], [[TMP3749]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5059]], label [[IF_THEN5061:%.*]], label [[IF_ELSE5062:%.*]]
|
|
// SIMD-ONLY0: if.then5061:
|
|
// SIMD-ONLY0-NEXT: [[TMP3750:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3750]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5063:%.*]]
|
|
// SIMD-ONLY0: if.else5062:
|
|
// SIMD-ONLY0-NEXT: [[TMP3751:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3751]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5063]]
|
|
// SIMD-ONLY0: if.end5063:
|
|
// SIMD-ONLY0-NEXT: [[TMP3752:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3753:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5064:%.*]] = icmp eq i64 [[TMP3752]], [[TMP3753]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5064]], label [[IF_THEN5066:%.*]], label [[IF_ELSE5067:%.*]]
|
|
// SIMD-ONLY0: if.then5066:
|
|
// SIMD-ONLY0-NEXT: [[TMP3754:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3754]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5068:%.*]]
|
|
// SIMD-ONLY0: if.else5067:
|
|
// SIMD-ONLY0-NEXT: [[TMP3755:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3755]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5068]]
|
|
// SIMD-ONLY0: if.end5068:
|
|
// SIMD-ONLY0-NEXT: [[TMP3756:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3757:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5069:%.*]] = icmp eq i64 [[TMP3756]], [[TMP3757]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5070:%.*]] = zext i1 [[CMP5069]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5071:%.*]] = sext i32 [[CONV5070]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5071]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3758:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5072:%.*]] = icmp ne i64 [[TMP3758]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5072]], label [[IF_THEN5073:%.*]], label [[IF_END5074:%.*]]
|
|
// SIMD-ONLY0: if.then5073:
|
|
// SIMD-ONLY0-NEXT: [[TMP3759:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3759]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5074]]
|
|
// SIMD-ONLY0: if.end5074:
|
|
// SIMD-ONLY0-NEXT: [[TMP3760:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3761:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5075:%.*]] = icmp eq i64 [[TMP3760]], [[TMP3761]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5076:%.*]] = zext i1 [[CMP5075]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5077:%.*]] = sext i32 [[CONV5076]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5077]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3762:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5078:%.*]] = icmp ne i64 [[TMP3762]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5078]], label [[IF_THEN5079:%.*]], label [[IF_END5080:%.*]]
|
|
// SIMD-ONLY0: if.then5079:
|
|
// SIMD-ONLY0-NEXT: [[TMP3763:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3763]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5080]]
|
|
// SIMD-ONLY0: if.end5080:
|
|
// SIMD-ONLY0-NEXT: [[TMP3764:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3765:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5081:%.*]] = icmp eq i64 [[TMP3764]], [[TMP3765]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5082:%.*]] = zext i1 [[CMP5081]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5083:%.*]] = sext i32 [[CONV5082]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5083]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3766:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5084:%.*]] = icmp ne i64 [[TMP3766]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5084]], label [[IF_THEN5085:%.*]], label [[IF_ELSE5086:%.*]]
|
|
// SIMD-ONLY0: if.then5085:
|
|
// SIMD-ONLY0-NEXT: [[TMP3767:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3767]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5087:%.*]]
|
|
// SIMD-ONLY0: if.else5086:
|
|
// SIMD-ONLY0-NEXT: [[TMP3768:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3768]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5087]]
|
|
// SIMD-ONLY0: if.end5087:
|
|
// SIMD-ONLY0-NEXT: [[TMP3769:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3770:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5088:%.*]] = icmp eq i64 [[TMP3769]], [[TMP3770]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5089:%.*]] = zext i1 [[CMP5088]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5090:%.*]] = sext i32 [[CONV5089]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5090]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3771:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5091:%.*]] = icmp ne i64 [[TMP3771]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5091]], label [[IF_THEN5092:%.*]], label [[IF_ELSE5093:%.*]]
|
|
// SIMD-ONLY0: if.then5092:
|
|
// SIMD-ONLY0-NEXT: [[TMP3772:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3772]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5094:%.*]]
|
|
// SIMD-ONLY0: if.else5093:
|
|
// SIMD-ONLY0-NEXT: [[TMP3773:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3773]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5094]]
|
|
// SIMD-ONLY0: if.end5094:
|
|
// SIMD-ONLY0-NEXT: [[TMP3774:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3774]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3775:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3776:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5095:%.*]] = icmp sgt i64 [[TMP3775]], [[TMP3776]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5095]], label [[IF_THEN5097:%.*]], label [[IF_END5098:%.*]]
|
|
// SIMD-ONLY0: if.then5097:
|
|
// SIMD-ONLY0-NEXT: [[TMP3777:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3777]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5098]]
|
|
// SIMD-ONLY0: if.end5098:
|
|
// SIMD-ONLY0-NEXT: [[TMP3778:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3778]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3779:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3780:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5099:%.*]] = icmp sgt i64 [[TMP3779]], [[TMP3780]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5099]], label [[IF_THEN5101:%.*]], label [[IF_END5102:%.*]]
|
|
// SIMD-ONLY0: if.then5101:
|
|
// SIMD-ONLY0-NEXT: [[TMP3781:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3781]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5102]]
|
|
// SIMD-ONLY0: if.end5102:
|
|
// SIMD-ONLY0-NEXT: [[TMP3782:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3782]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3783:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3784:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5103:%.*]] = icmp slt i64 [[TMP3783]], [[TMP3784]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5103]], label [[IF_THEN5105:%.*]], label [[IF_END5106:%.*]]
|
|
// SIMD-ONLY0: if.then5105:
|
|
// SIMD-ONLY0-NEXT: [[TMP3785:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3785]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5106]]
|
|
// SIMD-ONLY0: if.end5106:
|
|
// SIMD-ONLY0-NEXT: [[TMP3786:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3786]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3787:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3788:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5107:%.*]] = icmp slt i64 [[TMP3787]], [[TMP3788]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5107]], label [[IF_THEN5109:%.*]], label [[IF_END5110:%.*]]
|
|
// SIMD-ONLY0: if.then5109:
|
|
// SIMD-ONLY0-NEXT: [[TMP3789:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3789]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5110]]
|
|
// SIMD-ONLY0: if.end5110:
|
|
// SIMD-ONLY0-NEXT: [[TMP3790:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3790]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3791:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3792:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5111:%.*]] = icmp eq i64 [[TMP3791]], [[TMP3792]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5111]], label [[IF_THEN5113:%.*]], label [[IF_END5114:%.*]]
|
|
// SIMD-ONLY0: if.then5113:
|
|
// SIMD-ONLY0-NEXT: [[TMP3793:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3793]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5114]]
|
|
// SIMD-ONLY0: if.end5114:
|
|
// SIMD-ONLY0-NEXT: [[TMP3794:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3794]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3795:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3796:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5115:%.*]] = icmp eq i64 [[TMP3795]], [[TMP3796]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5115]], label [[IF_THEN5117:%.*]], label [[IF_END5118:%.*]]
|
|
// SIMD-ONLY0: if.then5117:
|
|
// SIMD-ONLY0-NEXT: [[TMP3797:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3797]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5118]]
|
|
// SIMD-ONLY0: if.end5118:
|
|
// SIMD-ONLY0-NEXT: [[TMP3798:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3799:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5119:%.*]] = icmp sgt i64 [[TMP3798]], [[TMP3799]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5119]], label [[IF_THEN5121:%.*]], label [[IF_END5122:%.*]]
|
|
// SIMD-ONLY0: if.then5121:
|
|
// SIMD-ONLY0-NEXT: [[TMP3800:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3800]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5122]]
|
|
// SIMD-ONLY0: if.end5122:
|
|
// SIMD-ONLY0-NEXT: [[TMP3801:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3801]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3802:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3803:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5123:%.*]] = icmp sgt i64 [[TMP3802]], [[TMP3803]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5123]], label [[IF_THEN5125:%.*]], label [[IF_END5126:%.*]]
|
|
// SIMD-ONLY0: if.then5125:
|
|
// SIMD-ONLY0-NEXT: [[TMP3804:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3804]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5126]]
|
|
// SIMD-ONLY0: if.end5126:
|
|
// SIMD-ONLY0-NEXT: [[TMP3805:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3805]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3806:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3807:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5127:%.*]] = icmp slt i64 [[TMP3806]], [[TMP3807]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5127]], label [[IF_THEN5129:%.*]], label [[IF_END5130:%.*]]
|
|
// SIMD-ONLY0: if.then5129:
|
|
// SIMD-ONLY0-NEXT: [[TMP3808:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3808]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5130]]
|
|
// SIMD-ONLY0: if.end5130:
|
|
// SIMD-ONLY0-NEXT: [[TMP3809:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3809]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3810:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3811:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5131:%.*]] = icmp slt i64 [[TMP3810]], [[TMP3811]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5131]], label [[IF_THEN5133:%.*]], label [[IF_END5134:%.*]]
|
|
// SIMD-ONLY0: if.then5133:
|
|
// SIMD-ONLY0-NEXT: [[TMP3812:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3812]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5134]]
|
|
// SIMD-ONLY0: if.end5134:
|
|
// SIMD-ONLY0-NEXT: [[TMP3813:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3813]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3814:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3815:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5135:%.*]] = icmp eq i64 [[TMP3814]], [[TMP3815]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5135]], label [[IF_THEN5137:%.*]], label [[IF_END5138:%.*]]
|
|
// SIMD-ONLY0: if.then5137:
|
|
// SIMD-ONLY0-NEXT: [[TMP3816:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3816]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5138]]
|
|
// SIMD-ONLY0: if.end5138:
|
|
// SIMD-ONLY0-NEXT: [[TMP3817:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3817]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3818:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3819:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5139:%.*]] = icmp eq i64 [[TMP3818]], [[TMP3819]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5139]], label [[IF_THEN5141:%.*]], label [[IF_END5142:%.*]]
|
|
// SIMD-ONLY0: if.then5141:
|
|
// SIMD-ONLY0-NEXT: [[TMP3820:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3820]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5142]]
|
|
// SIMD-ONLY0: if.end5142:
|
|
// SIMD-ONLY0-NEXT: [[TMP3821:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3821]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3822:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3823:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5143:%.*]] = icmp eq i64 [[TMP3822]], [[TMP3823]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5143]], label [[IF_THEN5145:%.*]], label [[IF_ELSE5146:%.*]]
|
|
// SIMD-ONLY0: if.then5145:
|
|
// SIMD-ONLY0-NEXT: [[TMP3824:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3824]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5147:%.*]]
|
|
// SIMD-ONLY0: if.else5146:
|
|
// SIMD-ONLY0-NEXT: [[TMP3825:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3825]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5147]]
|
|
// SIMD-ONLY0: if.end5147:
|
|
// SIMD-ONLY0-NEXT: [[TMP3826:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3827:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5148:%.*]] = icmp eq i64 [[TMP3826]], [[TMP3827]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5148]], label [[IF_THEN5150:%.*]], label [[IF_ELSE5151:%.*]]
|
|
// SIMD-ONLY0: if.then5150:
|
|
// SIMD-ONLY0-NEXT: [[TMP3828:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3828]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5152:%.*]]
|
|
// SIMD-ONLY0: if.else5151:
|
|
// SIMD-ONLY0-NEXT: [[TMP3829:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3829]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5152]]
|
|
// SIMD-ONLY0: if.end5152:
|
|
// SIMD-ONLY0-NEXT: [[TMP3830:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3831:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5153:%.*]] = icmp eq i64 [[TMP3830]], [[TMP3831]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5154:%.*]] = zext i1 [[CMP5153]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5155:%.*]] = sext i32 [[CONV5154]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5155]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3832:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5156:%.*]] = icmp ne i64 [[TMP3832]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5156]], label [[IF_THEN5157:%.*]], label [[IF_END5158:%.*]]
|
|
// SIMD-ONLY0: if.then5157:
|
|
// SIMD-ONLY0-NEXT: [[TMP3833:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3833]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5158]]
|
|
// SIMD-ONLY0: if.end5158:
|
|
// SIMD-ONLY0-NEXT: [[TMP3834:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3835:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5159:%.*]] = icmp eq i64 [[TMP3834]], [[TMP3835]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5160:%.*]] = zext i1 [[CMP5159]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5161:%.*]] = sext i32 [[CONV5160]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5161]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3836:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5162:%.*]] = icmp ne i64 [[TMP3836]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5162]], label [[IF_THEN5163:%.*]], label [[IF_END5164:%.*]]
|
|
// SIMD-ONLY0: if.then5163:
|
|
// SIMD-ONLY0-NEXT: [[TMP3837:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3837]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5164]]
|
|
// SIMD-ONLY0: if.end5164:
|
|
// SIMD-ONLY0-NEXT: [[TMP3838:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3839:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5165:%.*]] = icmp eq i64 [[TMP3838]], [[TMP3839]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5166:%.*]] = zext i1 [[CMP5165]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5167:%.*]] = sext i32 [[CONV5166]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5167]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3840:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5168:%.*]] = icmp ne i64 [[TMP3840]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5168]], label [[IF_THEN5169:%.*]], label [[IF_ELSE5170:%.*]]
|
|
// SIMD-ONLY0: if.then5169:
|
|
// SIMD-ONLY0-NEXT: [[TMP3841:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3841]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5171:%.*]]
|
|
// SIMD-ONLY0: if.else5170:
|
|
// SIMD-ONLY0-NEXT: [[TMP3842:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3842]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5171]]
|
|
// SIMD-ONLY0: if.end5171:
|
|
// SIMD-ONLY0-NEXT: [[TMP3843:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3844:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5172:%.*]] = icmp eq i64 [[TMP3843]], [[TMP3844]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5173:%.*]] = zext i1 [[CMP5172]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5174:%.*]] = sext i32 [[CONV5173]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5174]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3845:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5175:%.*]] = icmp ne i64 [[TMP3845]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5175]], label [[IF_THEN5176:%.*]], label [[IF_ELSE5177:%.*]]
|
|
// SIMD-ONLY0: if.then5176:
|
|
// SIMD-ONLY0-NEXT: [[TMP3846:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3846]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5178:%.*]]
|
|
// SIMD-ONLY0: if.else5177:
|
|
// SIMD-ONLY0-NEXT: [[TMP3847:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3847]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5178]]
|
|
// SIMD-ONLY0: if.end5178:
|
|
// SIMD-ONLY0-NEXT: [[TMP3848:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3848]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3849:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3850:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5179:%.*]] = icmp sgt i64 [[TMP3849]], [[TMP3850]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5179]], label [[IF_THEN5181:%.*]], label [[IF_END5182:%.*]]
|
|
// SIMD-ONLY0: if.then5181:
|
|
// SIMD-ONLY0-NEXT: [[TMP3851:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3851]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5182]]
|
|
// SIMD-ONLY0: if.end5182:
|
|
// SIMD-ONLY0-NEXT: [[TMP3852:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3852]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3853:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3854:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5183:%.*]] = icmp sgt i64 [[TMP3853]], [[TMP3854]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5183]], label [[IF_THEN5185:%.*]], label [[IF_END5186:%.*]]
|
|
// SIMD-ONLY0: if.then5185:
|
|
// SIMD-ONLY0-NEXT: [[TMP3855:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3855]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5186]]
|
|
// SIMD-ONLY0: if.end5186:
|
|
// SIMD-ONLY0-NEXT: [[TMP3856:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3856]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3857:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3858:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5187:%.*]] = icmp slt i64 [[TMP3857]], [[TMP3858]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5187]], label [[IF_THEN5189:%.*]], label [[IF_END5190:%.*]]
|
|
// SIMD-ONLY0: if.then5189:
|
|
// SIMD-ONLY0-NEXT: [[TMP3859:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3859]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5190]]
|
|
// SIMD-ONLY0: if.end5190:
|
|
// SIMD-ONLY0-NEXT: [[TMP3860:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3860]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3861:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3862:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5191:%.*]] = icmp slt i64 [[TMP3861]], [[TMP3862]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5191]], label [[IF_THEN5193:%.*]], label [[IF_END5194:%.*]]
|
|
// SIMD-ONLY0: if.then5193:
|
|
// SIMD-ONLY0-NEXT: [[TMP3863:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3863]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5194]]
|
|
// SIMD-ONLY0: if.end5194:
|
|
// SIMD-ONLY0-NEXT: [[TMP3864:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3864]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3865:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3866:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5195:%.*]] = icmp eq i64 [[TMP3865]], [[TMP3866]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5195]], label [[IF_THEN5197:%.*]], label [[IF_END5198:%.*]]
|
|
// SIMD-ONLY0: if.then5197:
|
|
// SIMD-ONLY0-NEXT: [[TMP3867:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3867]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5198]]
|
|
// SIMD-ONLY0: if.end5198:
|
|
// SIMD-ONLY0-NEXT: [[TMP3868:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3868]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3869:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3870:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5199:%.*]] = icmp eq i64 [[TMP3869]], [[TMP3870]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5199]], label [[IF_THEN5201:%.*]], label [[IF_END5202:%.*]]
|
|
// SIMD-ONLY0: if.then5201:
|
|
// SIMD-ONLY0-NEXT: [[TMP3871:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3871]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5202]]
|
|
// SIMD-ONLY0: if.end5202:
|
|
// SIMD-ONLY0-NEXT: [[TMP3872:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3873:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5203:%.*]] = icmp sgt i64 [[TMP3872]], [[TMP3873]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5203]], label [[IF_THEN5205:%.*]], label [[IF_END5206:%.*]]
|
|
// SIMD-ONLY0: if.then5205:
|
|
// SIMD-ONLY0-NEXT: [[TMP3874:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3874]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5206]]
|
|
// SIMD-ONLY0: if.end5206:
|
|
// SIMD-ONLY0-NEXT: [[TMP3875:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3875]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3876:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3877:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5207:%.*]] = icmp sgt i64 [[TMP3876]], [[TMP3877]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5207]], label [[IF_THEN5209:%.*]], label [[IF_END5210:%.*]]
|
|
// SIMD-ONLY0: if.then5209:
|
|
// SIMD-ONLY0-NEXT: [[TMP3878:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3878]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5210]]
|
|
// SIMD-ONLY0: if.end5210:
|
|
// SIMD-ONLY0-NEXT: [[TMP3879:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3879]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3880:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3881:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5211:%.*]] = icmp slt i64 [[TMP3880]], [[TMP3881]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5211]], label [[IF_THEN5213:%.*]], label [[IF_END5214:%.*]]
|
|
// SIMD-ONLY0: if.then5213:
|
|
// SIMD-ONLY0-NEXT: [[TMP3882:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3882]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5214]]
|
|
// SIMD-ONLY0: if.end5214:
|
|
// SIMD-ONLY0-NEXT: [[TMP3883:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3883]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3884:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3885:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5215:%.*]] = icmp slt i64 [[TMP3884]], [[TMP3885]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5215]], label [[IF_THEN5217:%.*]], label [[IF_END5218:%.*]]
|
|
// SIMD-ONLY0: if.then5217:
|
|
// SIMD-ONLY0-NEXT: [[TMP3886:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3886]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5218]]
|
|
// SIMD-ONLY0: if.end5218:
|
|
// SIMD-ONLY0-NEXT: [[TMP3887:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3887]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3888:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3889:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5219:%.*]] = icmp eq i64 [[TMP3888]], [[TMP3889]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5219]], label [[IF_THEN5221:%.*]], label [[IF_END5222:%.*]]
|
|
// SIMD-ONLY0: if.then5221:
|
|
// SIMD-ONLY0-NEXT: [[TMP3890:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3890]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5222]]
|
|
// SIMD-ONLY0: if.end5222:
|
|
// SIMD-ONLY0-NEXT: [[TMP3891:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3891]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3892:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3893:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5223:%.*]] = icmp eq i64 [[TMP3892]], [[TMP3893]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5223]], label [[IF_THEN5225:%.*]], label [[IF_END5226:%.*]]
|
|
// SIMD-ONLY0: if.then5225:
|
|
// SIMD-ONLY0-NEXT: [[TMP3894:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3894]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5226]]
|
|
// SIMD-ONLY0: if.end5226:
|
|
// SIMD-ONLY0-NEXT: [[TMP3895:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3895]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3896:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3897:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5227:%.*]] = icmp eq i64 [[TMP3896]], [[TMP3897]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5227]], label [[IF_THEN5229:%.*]], label [[IF_ELSE5230:%.*]]
|
|
// SIMD-ONLY0: if.then5229:
|
|
// SIMD-ONLY0-NEXT: [[TMP3898:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3898]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5231:%.*]]
|
|
// SIMD-ONLY0: if.else5230:
|
|
// SIMD-ONLY0-NEXT: [[TMP3899:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3899]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5231]]
|
|
// SIMD-ONLY0: if.end5231:
|
|
// SIMD-ONLY0-NEXT: [[TMP3900:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3901:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5232:%.*]] = icmp eq i64 [[TMP3900]], [[TMP3901]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5232]], label [[IF_THEN5234:%.*]], label [[IF_ELSE5235:%.*]]
|
|
// SIMD-ONLY0: if.then5234:
|
|
// SIMD-ONLY0-NEXT: [[TMP3902:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3902]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5236:%.*]]
|
|
// SIMD-ONLY0: if.else5235:
|
|
// SIMD-ONLY0-NEXT: [[TMP3903:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3903]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5236]]
|
|
// SIMD-ONLY0: if.end5236:
|
|
// SIMD-ONLY0-NEXT: [[TMP3904:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3905:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5237:%.*]] = icmp eq i64 [[TMP3904]], [[TMP3905]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5238:%.*]] = zext i1 [[CMP5237]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5239:%.*]] = sext i32 [[CONV5238]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5239]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3906:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5240:%.*]] = icmp ne i64 [[TMP3906]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5240]], label [[IF_THEN5241:%.*]], label [[IF_END5242:%.*]]
|
|
// SIMD-ONLY0: if.then5241:
|
|
// SIMD-ONLY0-NEXT: [[TMP3907:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3907]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5242]]
|
|
// SIMD-ONLY0: if.end5242:
|
|
// SIMD-ONLY0-NEXT: [[TMP3908:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3909:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5243:%.*]] = icmp eq i64 [[TMP3908]], [[TMP3909]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5244:%.*]] = zext i1 [[CMP5243]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5245:%.*]] = sext i32 [[CONV5244]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5245]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3910:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5246:%.*]] = icmp ne i64 [[TMP3910]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5246]], label [[IF_THEN5247:%.*]], label [[IF_END5248:%.*]]
|
|
// SIMD-ONLY0: if.then5247:
|
|
// SIMD-ONLY0-NEXT: [[TMP3911:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3911]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5248]]
|
|
// SIMD-ONLY0: if.end5248:
|
|
// SIMD-ONLY0-NEXT: [[TMP3912:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3913:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5249:%.*]] = icmp eq i64 [[TMP3912]], [[TMP3913]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5250:%.*]] = zext i1 [[CMP5249]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5251:%.*]] = sext i32 [[CONV5250]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5251]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3914:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5252:%.*]] = icmp ne i64 [[TMP3914]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5252]], label [[IF_THEN5253:%.*]], label [[IF_ELSE5254:%.*]]
|
|
// SIMD-ONLY0: if.then5253:
|
|
// SIMD-ONLY0-NEXT: [[TMP3915:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3915]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5255:%.*]]
|
|
// SIMD-ONLY0: if.else5254:
|
|
// SIMD-ONLY0-NEXT: [[TMP3916:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3916]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5255]]
|
|
// SIMD-ONLY0: if.end5255:
|
|
// SIMD-ONLY0-NEXT: [[TMP3917:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3918:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5256:%.*]] = icmp eq i64 [[TMP3917]], [[TMP3918]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5257:%.*]] = zext i1 [[CMP5256]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5258:%.*]] = sext i32 [[CONV5257]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5258]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3919:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5259:%.*]] = icmp ne i64 [[TMP3919]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5259]], label [[IF_THEN5260:%.*]], label [[IF_ELSE5261:%.*]]
|
|
// SIMD-ONLY0: if.then5260:
|
|
// SIMD-ONLY0-NEXT: [[TMP3920:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3920]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5262:%.*]]
|
|
// SIMD-ONLY0: if.else5261:
|
|
// SIMD-ONLY0-NEXT: [[TMP3921:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3921]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5262]]
|
|
// SIMD-ONLY0: if.end5262:
|
|
// SIMD-ONLY0-NEXT: [[TMP3922:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3922]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3923:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3924:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5263:%.*]] = icmp sgt i64 [[TMP3923]], [[TMP3924]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5263]], label [[IF_THEN5265:%.*]], label [[IF_END5266:%.*]]
|
|
// SIMD-ONLY0: if.then5265:
|
|
// SIMD-ONLY0-NEXT: [[TMP3925:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3925]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5266]]
|
|
// SIMD-ONLY0: if.end5266:
|
|
// SIMD-ONLY0-NEXT: [[TMP3926:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3926]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3927:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3928:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5267:%.*]] = icmp sgt i64 [[TMP3927]], [[TMP3928]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5267]], label [[IF_THEN5269:%.*]], label [[IF_END5270:%.*]]
|
|
// SIMD-ONLY0: if.then5269:
|
|
// SIMD-ONLY0-NEXT: [[TMP3929:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3929]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5270]]
|
|
// SIMD-ONLY0: if.end5270:
|
|
// SIMD-ONLY0-NEXT: [[TMP3930:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3930]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3931:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3932:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5271:%.*]] = icmp slt i64 [[TMP3931]], [[TMP3932]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5271]], label [[IF_THEN5273:%.*]], label [[IF_END5274:%.*]]
|
|
// SIMD-ONLY0: if.then5273:
|
|
// SIMD-ONLY0-NEXT: [[TMP3933:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3933]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5274]]
|
|
// SIMD-ONLY0: if.end5274:
|
|
// SIMD-ONLY0-NEXT: [[TMP3934:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3934]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3935:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3936:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5275:%.*]] = icmp slt i64 [[TMP3935]], [[TMP3936]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5275]], label [[IF_THEN5277:%.*]], label [[IF_END5278:%.*]]
|
|
// SIMD-ONLY0: if.then5277:
|
|
// SIMD-ONLY0-NEXT: [[TMP3937:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3937]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5278]]
|
|
// SIMD-ONLY0: if.end5278:
|
|
// SIMD-ONLY0-NEXT: [[TMP3938:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3938]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3939:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3940:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5279:%.*]] = icmp eq i64 [[TMP3939]], [[TMP3940]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5279]], label [[IF_THEN5281:%.*]], label [[IF_END5282:%.*]]
|
|
// SIMD-ONLY0: if.then5281:
|
|
// SIMD-ONLY0-NEXT: [[TMP3941:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3941]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5282]]
|
|
// SIMD-ONLY0: if.end5282:
|
|
// SIMD-ONLY0-NEXT: [[TMP3942:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3942]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3943:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3944:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5283:%.*]] = icmp eq i64 [[TMP3943]], [[TMP3944]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5283]], label [[IF_THEN5285:%.*]], label [[IF_END5286:%.*]]
|
|
// SIMD-ONLY0: if.then5285:
|
|
// SIMD-ONLY0-NEXT: [[TMP3945:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3945]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5286]]
|
|
// SIMD-ONLY0: if.end5286:
|
|
// SIMD-ONLY0-NEXT: [[TMP3946:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3947:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5287:%.*]] = icmp sgt i64 [[TMP3946]], [[TMP3947]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5287]], label [[IF_THEN5289:%.*]], label [[IF_END5290:%.*]]
|
|
// SIMD-ONLY0: if.then5289:
|
|
// SIMD-ONLY0-NEXT: [[TMP3948:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3948]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5290]]
|
|
// SIMD-ONLY0: if.end5290:
|
|
// SIMD-ONLY0-NEXT: [[TMP3949:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3949]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3950:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3951:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5291:%.*]] = icmp sgt i64 [[TMP3950]], [[TMP3951]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5291]], label [[IF_THEN5293:%.*]], label [[IF_END5294:%.*]]
|
|
// SIMD-ONLY0: if.then5293:
|
|
// SIMD-ONLY0-NEXT: [[TMP3952:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3952]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5294]]
|
|
// SIMD-ONLY0: if.end5294:
|
|
// SIMD-ONLY0-NEXT: [[TMP3953:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3953]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3954:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3955:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5295:%.*]] = icmp slt i64 [[TMP3954]], [[TMP3955]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5295]], label [[IF_THEN5297:%.*]], label [[IF_END5298:%.*]]
|
|
// SIMD-ONLY0: if.then5297:
|
|
// SIMD-ONLY0-NEXT: [[TMP3956:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3956]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5298]]
|
|
// SIMD-ONLY0: if.end5298:
|
|
// SIMD-ONLY0-NEXT: [[TMP3957:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3957]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3958:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3959:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5299:%.*]] = icmp slt i64 [[TMP3958]], [[TMP3959]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5299]], label [[IF_THEN5301:%.*]], label [[IF_END5302:%.*]]
|
|
// SIMD-ONLY0: if.then5301:
|
|
// SIMD-ONLY0-NEXT: [[TMP3960:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3960]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5302]]
|
|
// SIMD-ONLY0: if.end5302:
|
|
// SIMD-ONLY0-NEXT: [[TMP3961:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3961]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3962:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3963:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5303:%.*]] = icmp eq i64 [[TMP3962]], [[TMP3963]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5303]], label [[IF_THEN5305:%.*]], label [[IF_END5306:%.*]]
|
|
// SIMD-ONLY0: if.then5305:
|
|
// SIMD-ONLY0-NEXT: [[TMP3964:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3964]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5306]]
|
|
// SIMD-ONLY0: if.end5306:
|
|
// SIMD-ONLY0-NEXT: [[TMP3965:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3965]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3966:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3967:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5307:%.*]] = icmp eq i64 [[TMP3966]], [[TMP3967]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5307]], label [[IF_THEN5309:%.*]], label [[IF_END5310:%.*]]
|
|
// SIMD-ONLY0: if.then5309:
|
|
// SIMD-ONLY0-NEXT: [[TMP3968:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3968]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5310]]
|
|
// SIMD-ONLY0: if.end5310:
|
|
// SIMD-ONLY0-NEXT: [[TMP3969:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3969]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3970:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3971:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5311:%.*]] = icmp eq i64 [[TMP3970]], [[TMP3971]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5311]], label [[IF_THEN5313:%.*]], label [[IF_ELSE5314:%.*]]
|
|
// SIMD-ONLY0: if.then5313:
|
|
// SIMD-ONLY0-NEXT: [[TMP3972:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3972]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5315:%.*]]
|
|
// SIMD-ONLY0: if.else5314:
|
|
// SIMD-ONLY0-NEXT: [[TMP3973:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3973]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5315]]
|
|
// SIMD-ONLY0: if.end5315:
|
|
// SIMD-ONLY0-NEXT: [[TMP3974:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3975:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5316:%.*]] = icmp eq i64 [[TMP3974]], [[TMP3975]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5316]], label [[IF_THEN5318:%.*]], label [[IF_ELSE5319:%.*]]
|
|
// SIMD-ONLY0: if.then5318:
|
|
// SIMD-ONLY0-NEXT: [[TMP3976:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3976]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5320:%.*]]
|
|
// SIMD-ONLY0: if.else5319:
|
|
// SIMD-ONLY0-NEXT: [[TMP3977:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3977]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5320]]
|
|
// SIMD-ONLY0: if.end5320:
|
|
// SIMD-ONLY0-NEXT: [[TMP3978:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3979:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5321:%.*]] = icmp eq i64 [[TMP3978]], [[TMP3979]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5322:%.*]] = zext i1 [[CMP5321]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5323:%.*]] = sext i32 [[CONV5322]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5323]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3980:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5324:%.*]] = icmp ne i64 [[TMP3980]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5324]], label [[IF_THEN5325:%.*]], label [[IF_END5326:%.*]]
|
|
// SIMD-ONLY0: if.then5325:
|
|
// SIMD-ONLY0-NEXT: [[TMP3981:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3981]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5326]]
|
|
// SIMD-ONLY0: if.end5326:
|
|
// SIMD-ONLY0-NEXT: [[TMP3982:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3983:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5327:%.*]] = icmp eq i64 [[TMP3982]], [[TMP3983]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5328:%.*]] = zext i1 [[CMP5327]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5329:%.*]] = sext i32 [[CONV5328]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5329]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3984:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5330:%.*]] = icmp ne i64 [[TMP3984]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5330]], label [[IF_THEN5331:%.*]], label [[IF_END5332:%.*]]
|
|
// SIMD-ONLY0: if.then5331:
|
|
// SIMD-ONLY0-NEXT: [[TMP3985:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3985]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5332]]
|
|
// SIMD-ONLY0: if.end5332:
|
|
// SIMD-ONLY0-NEXT: [[TMP3986:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3987:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5333:%.*]] = icmp eq i64 [[TMP3986]], [[TMP3987]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5334:%.*]] = zext i1 [[CMP5333]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5335:%.*]] = sext i32 [[CONV5334]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5335]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3988:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5336:%.*]] = icmp ne i64 [[TMP3988]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5336]], label [[IF_THEN5337:%.*]], label [[IF_ELSE5338:%.*]]
|
|
// SIMD-ONLY0: if.then5337:
|
|
// SIMD-ONLY0-NEXT: [[TMP3989:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3989]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5339:%.*]]
|
|
// SIMD-ONLY0: if.else5338:
|
|
// SIMD-ONLY0-NEXT: [[TMP3990:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3990]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5339]]
|
|
// SIMD-ONLY0: if.end5339:
|
|
// SIMD-ONLY0-NEXT: [[TMP3991:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3992:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5340:%.*]] = icmp eq i64 [[TMP3991]], [[TMP3992]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5341:%.*]] = zext i1 [[CMP5340]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5342:%.*]] = sext i32 [[CONV5341]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5342]], ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3993:%.*]] = load i64, ptr [[LLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5343:%.*]] = icmp ne i64 [[TMP3993]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5343]], label [[IF_THEN5344:%.*]], label [[IF_ELSE5345:%.*]]
|
|
// SIMD-ONLY0: if.then5344:
|
|
// SIMD-ONLY0-NEXT: [[TMP3994:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3994]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5346:%.*]]
|
|
// SIMD-ONLY0: if.else5345:
|
|
// SIMD-ONLY0-NEXT: [[TMP3995:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3995]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5346]]
|
|
// SIMD-ONLY0: if.end5346:
|
|
// SIMD-ONLY0-NEXT: [[TMP3996:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3996]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3997:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP3998:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5347:%.*]] = icmp ugt i64 [[TMP3997]], [[TMP3998]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5347]], label [[IF_THEN5349:%.*]], label [[IF_END5350:%.*]]
|
|
// SIMD-ONLY0: if.then5349:
|
|
// SIMD-ONLY0-NEXT: [[TMP3999:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP3999]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5350]]
|
|
// SIMD-ONLY0: if.end5350:
|
|
// SIMD-ONLY0-NEXT: [[TMP4000:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4000]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4001:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4002:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5351:%.*]] = icmp ugt i64 [[TMP4001]], [[TMP4002]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5351]], label [[IF_THEN5353:%.*]], label [[IF_END5354:%.*]]
|
|
// SIMD-ONLY0: if.then5353:
|
|
// SIMD-ONLY0-NEXT: [[TMP4003:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4003]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5354]]
|
|
// SIMD-ONLY0: if.end5354:
|
|
// SIMD-ONLY0-NEXT: [[TMP4004:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4004]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4005:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4006:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5355:%.*]] = icmp ult i64 [[TMP4005]], [[TMP4006]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5355]], label [[IF_THEN5357:%.*]], label [[IF_END5358:%.*]]
|
|
// SIMD-ONLY0: if.then5357:
|
|
// SIMD-ONLY0-NEXT: [[TMP4007:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4007]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5358]]
|
|
// SIMD-ONLY0: if.end5358:
|
|
// SIMD-ONLY0-NEXT: [[TMP4008:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4008]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4009:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4010:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5359:%.*]] = icmp ult i64 [[TMP4009]], [[TMP4010]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5359]], label [[IF_THEN5361:%.*]], label [[IF_END5362:%.*]]
|
|
// SIMD-ONLY0: if.then5361:
|
|
// SIMD-ONLY0-NEXT: [[TMP4011:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4011]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5362]]
|
|
// SIMD-ONLY0: if.end5362:
|
|
// SIMD-ONLY0-NEXT: [[TMP4012:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4012]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4013:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4014:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5363:%.*]] = icmp eq i64 [[TMP4013]], [[TMP4014]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5363]], label [[IF_THEN5365:%.*]], label [[IF_END5366:%.*]]
|
|
// SIMD-ONLY0: if.then5365:
|
|
// SIMD-ONLY0-NEXT: [[TMP4015:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4015]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5366]]
|
|
// SIMD-ONLY0: if.end5366:
|
|
// SIMD-ONLY0-NEXT: [[TMP4016:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4016]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4017:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4018:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5367:%.*]] = icmp eq i64 [[TMP4017]], [[TMP4018]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5367]], label [[IF_THEN5369:%.*]], label [[IF_END5370:%.*]]
|
|
// SIMD-ONLY0: if.then5369:
|
|
// SIMD-ONLY0-NEXT: [[TMP4019:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4019]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5370]]
|
|
// SIMD-ONLY0: if.end5370:
|
|
// SIMD-ONLY0-NEXT: [[TMP4020:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4021:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5371:%.*]] = icmp ugt i64 [[TMP4020]], [[TMP4021]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5371]], label [[IF_THEN5373:%.*]], label [[IF_END5374:%.*]]
|
|
// SIMD-ONLY0: if.then5373:
|
|
// SIMD-ONLY0-NEXT: [[TMP4022:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4022]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5374]]
|
|
// SIMD-ONLY0: if.end5374:
|
|
// SIMD-ONLY0-NEXT: [[TMP4023:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4023]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4024:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4025:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5375:%.*]] = icmp ugt i64 [[TMP4024]], [[TMP4025]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5375]], label [[IF_THEN5377:%.*]], label [[IF_END5378:%.*]]
|
|
// SIMD-ONLY0: if.then5377:
|
|
// SIMD-ONLY0-NEXT: [[TMP4026:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4026]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5378]]
|
|
// SIMD-ONLY0: if.end5378:
|
|
// SIMD-ONLY0-NEXT: [[TMP4027:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4027]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4028:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4029:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5379:%.*]] = icmp ult i64 [[TMP4028]], [[TMP4029]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5379]], label [[IF_THEN5381:%.*]], label [[IF_END5382:%.*]]
|
|
// SIMD-ONLY0: if.then5381:
|
|
// SIMD-ONLY0-NEXT: [[TMP4030:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4030]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5382]]
|
|
// SIMD-ONLY0: if.end5382:
|
|
// SIMD-ONLY0-NEXT: [[TMP4031:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4031]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4032:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4033:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5383:%.*]] = icmp ult i64 [[TMP4032]], [[TMP4033]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5383]], label [[IF_THEN5385:%.*]], label [[IF_END5386:%.*]]
|
|
// SIMD-ONLY0: if.then5385:
|
|
// SIMD-ONLY0-NEXT: [[TMP4034:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4034]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5386]]
|
|
// SIMD-ONLY0: if.end5386:
|
|
// SIMD-ONLY0-NEXT: [[TMP4035:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4035]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4036:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4037:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5387:%.*]] = icmp eq i64 [[TMP4036]], [[TMP4037]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5387]], label [[IF_THEN5389:%.*]], label [[IF_END5390:%.*]]
|
|
// SIMD-ONLY0: if.then5389:
|
|
// SIMD-ONLY0-NEXT: [[TMP4038:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4038]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5390]]
|
|
// SIMD-ONLY0: if.end5390:
|
|
// SIMD-ONLY0-NEXT: [[TMP4039:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4039]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4040:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4041:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5391:%.*]] = icmp eq i64 [[TMP4040]], [[TMP4041]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5391]], label [[IF_THEN5393:%.*]], label [[IF_END5394:%.*]]
|
|
// SIMD-ONLY0: if.then5393:
|
|
// SIMD-ONLY0-NEXT: [[TMP4042:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4042]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5394]]
|
|
// SIMD-ONLY0: if.end5394:
|
|
// SIMD-ONLY0-NEXT: [[TMP4043:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4043]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4044:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4045:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5395:%.*]] = icmp eq i64 [[TMP4044]], [[TMP4045]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5395]], label [[IF_THEN5397:%.*]], label [[IF_ELSE5398:%.*]]
|
|
// SIMD-ONLY0: if.then5397:
|
|
// SIMD-ONLY0-NEXT: [[TMP4046:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4046]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5399:%.*]]
|
|
// SIMD-ONLY0: if.else5398:
|
|
// SIMD-ONLY0-NEXT: [[TMP4047:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4047]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5399]]
|
|
// SIMD-ONLY0: if.end5399:
|
|
// SIMD-ONLY0-NEXT: [[TMP4048:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4049:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5400:%.*]] = icmp eq i64 [[TMP4048]], [[TMP4049]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5400]], label [[IF_THEN5402:%.*]], label [[IF_ELSE5403:%.*]]
|
|
// SIMD-ONLY0: if.then5402:
|
|
// SIMD-ONLY0-NEXT: [[TMP4050:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4050]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5404:%.*]]
|
|
// SIMD-ONLY0: if.else5403:
|
|
// SIMD-ONLY0-NEXT: [[TMP4051:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4051]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5404]]
|
|
// SIMD-ONLY0: if.end5404:
|
|
// SIMD-ONLY0-NEXT: [[TMP4052:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4053:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5405:%.*]] = icmp eq i64 [[TMP4052]], [[TMP4053]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5406:%.*]] = zext i1 [[CMP5405]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5407:%.*]] = sext i32 [[CONV5406]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5407]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4054:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5408:%.*]] = icmp ne i64 [[TMP4054]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5408]], label [[IF_THEN5409:%.*]], label [[IF_END5410:%.*]]
|
|
// SIMD-ONLY0: if.then5409:
|
|
// SIMD-ONLY0-NEXT: [[TMP4055:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4055]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5410]]
|
|
// SIMD-ONLY0: if.end5410:
|
|
// SIMD-ONLY0-NEXT: [[TMP4056:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4057:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5411:%.*]] = icmp eq i64 [[TMP4056]], [[TMP4057]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5412:%.*]] = zext i1 [[CMP5411]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5413:%.*]] = sext i32 [[CONV5412]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5413]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4058:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5414:%.*]] = icmp ne i64 [[TMP4058]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5414]], label [[IF_THEN5415:%.*]], label [[IF_END5416:%.*]]
|
|
// SIMD-ONLY0: if.then5415:
|
|
// SIMD-ONLY0-NEXT: [[TMP4059:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4059]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5416]]
|
|
// SIMD-ONLY0: if.end5416:
|
|
// SIMD-ONLY0-NEXT: [[TMP4060:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4061:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5417:%.*]] = icmp eq i64 [[TMP4060]], [[TMP4061]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5418:%.*]] = zext i1 [[CMP5417]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5419:%.*]] = sext i32 [[CONV5418]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5419]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4062:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5420:%.*]] = icmp ne i64 [[TMP4062]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5420]], label [[IF_THEN5421:%.*]], label [[IF_ELSE5422:%.*]]
|
|
// SIMD-ONLY0: if.then5421:
|
|
// SIMD-ONLY0-NEXT: [[TMP4063:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4063]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5423:%.*]]
|
|
// SIMD-ONLY0: if.else5422:
|
|
// SIMD-ONLY0-NEXT: [[TMP4064:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4064]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5423]]
|
|
// SIMD-ONLY0: if.end5423:
|
|
// SIMD-ONLY0-NEXT: [[TMP4065:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4066:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5424:%.*]] = icmp eq i64 [[TMP4065]], [[TMP4066]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5425:%.*]] = zext i1 [[CMP5424]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5426:%.*]] = sext i32 [[CONV5425]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5426]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4067:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5427:%.*]] = icmp ne i64 [[TMP4067]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5427]], label [[IF_THEN5428:%.*]], label [[IF_ELSE5429:%.*]]
|
|
// SIMD-ONLY0: if.then5428:
|
|
// SIMD-ONLY0-NEXT: [[TMP4068:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4068]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5430:%.*]]
|
|
// SIMD-ONLY0: if.else5429:
|
|
// SIMD-ONLY0-NEXT: [[TMP4069:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4069]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5430]]
|
|
// SIMD-ONLY0: if.end5430:
|
|
// SIMD-ONLY0-NEXT: [[TMP4070:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4070]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4071:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4072:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5431:%.*]] = icmp ugt i64 [[TMP4071]], [[TMP4072]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5431]], label [[IF_THEN5433:%.*]], label [[IF_END5434:%.*]]
|
|
// SIMD-ONLY0: if.then5433:
|
|
// SIMD-ONLY0-NEXT: [[TMP4073:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4073]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5434]]
|
|
// SIMD-ONLY0: if.end5434:
|
|
// SIMD-ONLY0-NEXT: [[TMP4074:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4074]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4075:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4076:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5435:%.*]] = icmp ugt i64 [[TMP4075]], [[TMP4076]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5435]], label [[IF_THEN5437:%.*]], label [[IF_END5438:%.*]]
|
|
// SIMD-ONLY0: if.then5437:
|
|
// SIMD-ONLY0-NEXT: [[TMP4077:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4077]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5438]]
|
|
// SIMD-ONLY0: if.end5438:
|
|
// SIMD-ONLY0-NEXT: [[TMP4078:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4078]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4079:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4080:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5439:%.*]] = icmp ult i64 [[TMP4079]], [[TMP4080]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5439]], label [[IF_THEN5441:%.*]], label [[IF_END5442:%.*]]
|
|
// SIMD-ONLY0: if.then5441:
|
|
// SIMD-ONLY0-NEXT: [[TMP4081:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4081]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5442]]
|
|
// SIMD-ONLY0: if.end5442:
|
|
// SIMD-ONLY0-NEXT: [[TMP4082:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4082]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4083:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4084:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5443:%.*]] = icmp ult i64 [[TMP4083]], [[TMP4084]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5443]], label [[IF_THEN5445:%.*]], label [[IF_END5446:%.*]]
|
|
// SIMD-ONLY0: if.then5445:
|
|
// SIMD-ONLY0-NEXT: [[TMP4085:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4085]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5446]]
|
|
// SIMD-ONLY0: if.end5446:
|
|
// SIMD-ONLY0-NEXT: [[TMP4086:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4086]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4087:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4088:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5447:%.*]] = icmp eq i64 [[TMP4087]], [[TMP4088]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5447]], label [[IF_THEN5449:%.*]], label [[IF_END5450:%.*]]
|
|
// SIMD-ONLY0: if.then5449:
|
|
// SIMD-ONLY0-NEXT: [[TMP4089:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4089]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5450]]
|
|
// SIMD-ONLY0: if.end5450:
|
|
// SIMD-ONLY0-NEXT: [[TMP4090:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4090]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4091:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4092:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5451:%.*]] = icmp eq i64 [[TMP4091]], [[TMP4092]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5451]], label [[IF_THEN5453:%.*]], label [[IF_END5454:%.*]]
|
|
// SIMD-ONLY0: if.then5453:
|
|
// SIMD-ONLY0-NEXT: [[TMP4093:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4093]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5454]]
|
|
// SIMD-ONLY0: if.end5454:
|
|
// SIMD-ONLY0-NEXT: [[TMP4094:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4095:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5455:%.*]] = icmp ugt i64 [[TMP4094]], [[TMP4095]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5455]], label [[IF_THEN5457:%.*]], label [[IF_END5458:%.*]]
|
|
// SIMD-ONLY0: if.then5457:
|
|
// SIMD-ONLY0-NEXT: [[TMP4096:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4096]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5458]]
|
|
// SIMD-ONLY0: if.end5458:
|
|
// SIMD-ONLY0-NEXT: [[TMP4097:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4097]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4098:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4099:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5459:%.*]] = icmp ugt i64 [[TMP4098]], [[TMP4099]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5459]], label [[IF_THEN5461:%.*]], label [[IF_END5462:%.*]]
|
|
// SIMD-ONLY0: if.then5461:
|
|
// SIMD-ONLY0-NEXT: [[TMP4100:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4100]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5462]]
|
|
// SIMD-ONLY0: if.end5462:
|
|
// SIMD-ONLY0-NEXT: [[TMP4101:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4101]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4102:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4103:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5463:%.*]] = icmp ult i64 [[TMP4102]], [[TMP4103]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5463]], label [[IF_THEN5465:%.*]], label [[IF_END5466:%.*]]
|
|
// SIMD-ONLY0: if.then5465:
|
|
// SIMD-ONLY0-NEXT: [[TMP4104:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4104]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5466]]
|
|
// SIMD-ONLY0: if.end5466:
|
|
// SIMD-ONLY0-NEXT: [[TMP4105:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4105]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4106:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4107:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5467:%.*]] = icmp ult i64 [[TMP4106]], [[TMP4107]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5467]], label [[IF_THEN5469:%.*]], label [[IF_END5470:%.*]]
|
|
// SIMD-ONLY0: if.then5469:
|
|
// SIMD-ONLY0-NEXT: [[TMP4108:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4108]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5470]]
|
|
// SIMD-ONLY0: if.end5470:
|
|
// SIMD-ONLY0-NEXT: [[TMP4109:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4109]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4110:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4111:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5471:%.*]] = icmp eq i64 [[TMP4110]], [[TMP4111]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5471]], label [[IF_THEN5473:%.*]], label [[IF_END5474:%.*]]
|
|
// SIMD-ONLY0: if.then5473:
|
|
// SIMD-ONLY0-NEXT: [[TMP4112:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4112]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5474]]
|
|
// SIMD-ONLY0: if.end5474:
|
|
// SIMD-ONLY0-NEXT: [[TMP4113:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4113]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4114:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4115:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5475:%.*]] = icmp eq i64 [[TMP4114]], [[TMP4115]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5475]], label [[IF_THEN5477:%.*]], label [[IF_END5478:%.*]]
|
|
// SIMD-ONLY0: if.then5477:
|
|
// SIMD-ONLY0-NEXT: [[TMP4116:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4116]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5478]]
|
|
// SIMD-ONLY0: if.end5478:
|
|
// SIMD-ONLY0-NEXT: [[TMP4117:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4117]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4118:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4119:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5479:%.*]] = icmp eq i64 [[TMP4118]], [[TMP4119]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5479]], label [[IF_THEN5481:%.*]], label [[IF_ELSE5482:%.*]]
|
|
// SIMD-ONLY0: if.then5481:
|
|
// SIMD-ONLY0-NEXT: [[TMP4120:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4120]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5483:%.*]]
|
|
// SIMD-ONLY0: if.else5482:
|
|
// SIMD-ONLY0-NEXT: [[TMP4121:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4121]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5483]]
|
|
// SIMD-ONLY0: if.end5483:
|
|
// SIMD-ONLY0-NEXT: [[TMP4122:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4123:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5484:%.*]] = icmp eq i64 [[TMP4122]], [[TMP4123]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5484]], label [[IF_THEN5486:%.*]], label [[IF_ELSE5487:%.*]]
|
|
// SIMD-ONLY0: if.then5486:
|
|
// SIMD-ONLY0-NEXT: [[TMP4124:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4124]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5488:%.*]]
|
|
// SIMD-ONLY0: if.else5487:
|
|
// SIMD-ONLY0-NEXT: [[TMP4125:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4125]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5488]]
|
|
// SIMD-ONLY0: if.end5488:
|
|
// SIMD-ONLY0-NEXT: [[TMP4126:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4127:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5489:%.*]] = icmp eq i64 [[TMP4126]], [[TMP4127]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5490:%.*]] = zext i1 [[CMP5489]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5491:%.*]] = sext i32 [[CONV5490]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5491]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4128:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5492:%.*]] = icmp ne i64 [[TMP4128]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5492]], label [[IF_THEN5493:%.*]], label [[IF_END5494:%.*]]
|
|
// SIMD-ONLY0: if.then5493:
|
|
// SIMD-ONLY0-NEXT: [[TMP4129:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4129]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5494]]
|
|
// SIMD-ONLY0: if.end5494:
|
|
// SIMD-ONLY0-NEXT: [[TMP4130:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4131:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5495:%.*]] = icmp eq i64 [[TMP4130]], [[TMP4131]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5496:%.*]] = zext i1 [[CMP5495]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5497:%.*]] = sext i32 [[CONV5496]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5497]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4132:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5498:%.*]] = icmp ne i64 [[TMP4132]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5498]], label [[IF_THEN5499:%.*]], label [[IF_END5500:%.*]]
|
|
// SIMD-ONLY0: if.then5499:
|
|
// SIMD-ONLY0-NEXT: [[TMP4133:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4133]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5500]]
|
|
// SIMD-ONLY0: if.end5500:
|
|
// SIMD-ONLY0-NEXT: [[TMP4134:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4135:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5501:%.*]] = icmp eq i64 [[TMP4134]], [[TMP4135]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5502:%.*]] = zext i1 [[CMP5501]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5503:%.*]] = sext i32 [[CONV5502]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5503]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4136:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5504:%.*]] = icmp ne i64 [[TMP4136]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5504]], label [[IF_THEN5505:%.*]], label [[IF_ELSE5506:%.*]]
|
|
// SIMD-ONLY0: if.then5505:
|
|
// SIMD-ONLY0-NEXT: [[TMP4137:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4137]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5507:%.*]]
|
|
// SIMD-ONLY0: if.else5506:
|
|
// SIMD-ONLY0-NEXT: [[TMP4138:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4138]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5507]]
|
|
// SIMD-ONLY0: if.end5507:
|
|
// SIMD-ONLY0-NEXT: [[TMP4139:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4140:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5508:%.*]] = icmp eq i64 [[TMP4139]], [[TMP4140]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5509:%.*]] = zext i1 [[CMP5508]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5510:%.*]] = sext i32 [[CONV5509]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5510]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4141:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5511:%.*]] = icmp ne i64 [[TMP4141]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5511]], label [[IF_THEN5512:%.*]], label [[IF_ELSE5513:%.*]]
|
|
// SIMD-ONLY0: if.then5512:
|
|
// SIMD-ONLY0-NEXT: [[TMP4142:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4142]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5514:%.*]]
|
|
// SIMD-ONLY0: if.else5513:
|
|
// SIMD-ONLY0-NEXT: [[TMP4143:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4143]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5514]]
|
|
// SIMD-ONLY0: if.end5514:
|
|
// SIMD-ONLY0-NEXT: [[TMP4144:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4144]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4145:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4146:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5515:%.*]] = icmp ugt i64 [[TMP4145]], [[TMP4146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5515]], label [[IF_THEN5517:%.*]], label [[IF_END5518:%.*]]
|
|
// SIMD-ONLY0: if.then5517:
|
|
// SIMD-ONLY0-NEXT: [[TMP4147:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4147]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5518]]
|
|
// SIMD-ONLY0: if.end5518:
|
|
// SIMD-ONLY0-NEXT: [[TMP4148:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4148]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4149:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4150:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5519:%.*]] = icmp ugt i64 [[TMP4149]], [[TMP4150]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5519]], label [[IF_THEN5521:%.*]], label [[IF_END5522:%.*]]
|
|
// SIMD-ONLY0: if.then5521:
|
|
// SIMD-ONLY0-NEXT: [[TMP4151:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4151]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5522]]
|
|
// SIMD-ONLY0: if.end5522:
|
|
// SIMD-ONLY0-NEXT: [[TMP4152:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4152]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4153:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4154:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5523:%.*]] = icmp ult i64 [[TMP4153]], [[TMP4154]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5523]], label [[IF_THEN5525:%.*]], label [[IF_END5526:%.*]]
|
|
// SIMD-ONLY0: if.then5525:
|
|
// SIMD-ONLY0-NEXT: [[TMP4155:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4155]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5526]]
|
|
// SIMD-ONLY0: if.end5526:
|
|
// SIMD-ONLY0-NEXT: [[TMP4156:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4156]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4157:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4158:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5527:%.*]] = icmp ult i64 [[TMP4157]], [[TMP4158]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5527]], label [[IF_THEN5529:%.*]], label [[IF_END5530:%.*]]
|
|
// SIMD-ONLY0: if.then5529:
|
|
// SIMD-ONLY0-NEXT: [[TMP4159:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4159]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5530]]
|
|
// SIMD-ONLY0: if.end5530:
|
|
// SIMD-ONLY0-NEXT: [[TMP4160:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4160]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4161:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4162:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5531:%.*]] = icmp eq i64 [[TMP4161]], [[TMP4162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5531]], label [[IF_THEN5533:%.*]], label [[IF_END5534:%.*]]
|
|
// SIMD-ONLY0: if.then5533:
|
|
// SIMD-ONLY0-NEXT: [[TMP4163:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4163]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5534]]
|
|
// SIMD-ONLY0: if.end5534:
|
|
// SIMD-ONLY0-NEXT: [[TMP4164:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4164]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4165:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4166:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5535:%.*]] = icmp eq i64 [[TMP4165]], [[TMP4166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5535]], label [[IF_THEN5537:%.*]], label [[IF_END5538:%.*]]
|
|
// SIMD-ONLY0: if.then5537:
|
|
// SIMD-ONLY0-NEXT: [[TMP4167:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4167]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5538]]
|
|
// SIMD-ONLY0: if.end5538:
|
|
// SIMD-ONLY0-NEXT: [[TMP4168:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4169:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5539:%.*]] = icmp ugt i64 [[TMP4168]], [[TMP4169]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5539]], label [[IF_THEN5541:%.*]], label [[IF_END5542:%.*]]
|
|
// SIMD-ONLY0: if.then5541:
|
|
// SIMD-ONLY0-NEXT: [[TMP4170:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4170]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5542]]
|
|
// SIMD-ONLY0: if.end5542:
|
|
// SIMD-ONLY0-NEXT: [[TMP4171:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4171]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4172:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4173:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5543:%.*]] = icmp ugt i64 [[TMP4172]], [[TMP4173]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5543]], label [[IF_THEN5545:%.*]], label [[IF_END5546:%.*]]
|
|
// SIMD-ONLY0: if.then5545:
|
|
// SIMD-ONLY0-NEXT: [[TMP4174:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4174]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5546]]
|
|
// SIMD-ONLY0: if.end5546:
|
|
// SIMD-ONLY0-NEXT: [[TMP4175:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4175]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4176:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4177:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5547:%.*]] = icmp ult i64 [[TMP4176]], [[TMP4177]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5547]], label [[IF_THEN5549:%.*]], label [[IF_END5550:%.*]]
|
|
// SIMD-ONLY0: if.then5549:
|
|
// SIMD-ONLY0-NEXT: [[TMP4178:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4178]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5550]]
|
|
// SIMD-ONLY0: if.end5550:
|
|
// SIMD-ONLY0-NEXT: [[TMP4179:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4179]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4180:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4181:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5551:%.*]] = icmp ult i64 [[TMP4180]], [[TMP4181]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5551]], label [[IF_THEN5553:%.*]], label [[IF_END5554:%.*]]
|
|
// SIMD-ONLY0: if.then5553:
|
|
// SIMD-ONLY0-NEXT: [[TMP4182:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4182]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5554]]
|
|
// SIMD-ONLY0: if.end5554:
|
|
// SIMD-ONLY0-NEXT: [[TMP4183:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4183]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4184:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4185:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5555:%.*]] = icmp eq i64 [[TMP4184]], [[TMP4185]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5555]], label [[IF_THEN5557:%.*]], label [[IF_END5558:%.*]]
|
|
// SIMD-ONLY0: if.then5557:
|
|
// SIMD-ONLY0-NEXT: [[TMP4186:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4186]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5558]]
|
|
// SIMD-ONLY0: if.end5558:
|
|
// SIMD-ONLY0-NEXT: [[TMP4187:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4187]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4188:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4189:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5559:%.*]] = icmp eq i64 [[TMP4188]], [[TMP4189]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5559]], label [[IF_THEN5561:%.*]], label [[IF_END5562:%.*]]
|
|
// SIMD-ONLY0: if.then5561:
|
|
// SIMD-ONLY0-NEXT: [[TMP4190:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4190]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5562]]
|
|
// SIMD-ONLY0: if.end5562:
|
|
// SIMD-ONLY0-NEXT: [[TMP4191:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4191]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4192:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4193:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5563:%.*]] = icmp eq i64 [[TMP4192]], [[TMP4193]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5563]], label [[IF_THEN5565:%.*]], label [[IF_ELSE5566:%.*]]
|
|
// SIMD-ONLY0: if.then5565:
|
|
// SIMD-ONLY0-NEXT: [[TMP4194:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4194]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5567:%.*]]
|
|
// SIMD-ONLY0: if.else5566:
|
|
// SIMD-ONLY0-NEXT: [[TMP4195:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4195]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5567]]
|
|
// SIMD-ONLY0: if.end5567:
|
|
// SIMD-ONLY0-NEXT: [[TMP4196:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4197:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5568:%.*]] = icmp eq i64 [[TMP4196]], [[TMP4197]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5568]], label [[IF_THEN5570:%.*]], label [[IF_ELSE5571:%.*]]
|
|
// SIMD-ONLY0: if.then5570:
|
|
// SIMD-ONLY0-NEXT: [[TMP4198:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4198]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5572:%.*]]
|
|
// SIMD-ONLY0: if.else5571:
|
|
// SIMD-ONLY0-NEXT: [[TMP4199:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4199]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5572]]
|
|
// SIMD-ONLY0: if.end5572:
|
|
// SIMD-ONLY0-NEXT: [[TMP4200:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4201:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5573:%.*]] = icmp eq i64 [[TMP4200]], [[TMP4201]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5574:%.*]] = zext i1 [[CMP5573]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5575:%.*]] = sext i32 [[CONV5574]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5575]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4202:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5576:%.*]] = icmp ne i64 [[TMP4202]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5576]], label [[IF_THEN5577:%.*]], label [[IF_END5578:%.*]]
|
|
// SIMD-ONLY0: if.then5577:
|
|
// SIMD-ONLY0-NEXT: [[TMP4203:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4203]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5578]]
|
|
// SIMD-ONLY0: if.end5578:
|
|
// SIMD-ONLY0-NEXT: [[TMP4204:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4205:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5579:%.*]] = icmp eq i64 [[TMP4204]], [[TMP4205]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5580:%.*]] = zext i1 [[CMP5579]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5581:%.*]] = sext i32 [[CONV5580]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5581]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4206:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5582:%.*]] = icmp ne i64 [[TMP4206]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5582]], label [[IF_THEN5583:%.*]], label [[IF_END5584:%.*]]
|
|
// SIMD-ONLY0: if.then5583:
|
|
// SIMD-ONLY0-NEXT: [[TMP4207:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4207]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5584]]
|
|
// SIMD-ONLY0: if.end5584:
|
|
// SIMD-ONLY0-NEXT: [[TMP4208:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4209:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5585:%.*]] = icmp eq i64 [[TMP4208]], [[TMP4209]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5586:%.*]] = zext i1 [[CMP5585]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5587:%.*]] = sext i32 [[CONV5586]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5587]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4210:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5588:%.*]] = icmp ne i64 [[TMP4210]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5588]], label [[IF_THEN5589:%.*]], label [[IF_ELSE5590:%.*]]
|
|
// SIMD-ONLY0: if.then5589:
|
|
// SIMD-ONLY0-NEXT: [[TMP4211:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4211]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5591:%.*]]
|
|
// SIMD-ONLY0: if.else5590:
|
|
// SIMD-ONLY0-NEXT: [[TMP4212:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4212]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5591]]
|
|
// SIMD-ONLY0: if.end5591:
|
|
// SIMD-ONLY0-NEXT: [[TMP4213:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4214:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5592:%.*]] = icmp eq i64 [[TMP4213]], [[TMP4214]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5593:%.*]] = zext i1 [[CMP5592]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5594:%.*]] = sext i32 [[CONV5593]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5594]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4215:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5595:%.*]] = icmp ne i64 [[TMP4215]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5595]], label [[IF_THEN5596:%.*]], label [[IF_ELSE5597:%.*]]
|
|
// SIMD-ONLY0: if.then5596:
|
|
// SIMD-ONLY0-NEXT: [[TMP4216:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4216]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5598:%.*]]
|
|
// SIMD-ONLY0: if.else5597:
|
|
// SIMD-ONLY0-NEXT: [[TMP4217:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4217]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5598]]
|
|
// SIMD-ONLY0: if.end5598:
|
|
// SIMD-ONLY0-NEXT: [[TMP4218:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4218]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4219:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4220:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5599:%.*]] = icmp ugt i64 [[TMP4219]], [[TMP4220]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5599]], label [[IF_THEN5601:%.*]], label [[IF_END5602:%.*]]
|
|
// SIMD-ONLY0: if.then5601:
|
|
// SIMD-ONLY0-NEXT: [[TMP4221:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4221]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5602]]
|
|
// SIMD-ONLY0: if.end5602:
|
|
// SIMD-ONLY0-NEXT: [[TMP4222:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4222]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4223:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4224:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5603:%.*]] = icmp ugt i64 [[TMP4223]], [[TMP4224]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5603]], label [[IF_THEN5605:%.*]], label [[IF_END5606:%.*]]
|
|
// SIMD-ONLY0: if.then5605:
|
|
// SIMD-ONLY0-NEXT: [[TMP4225:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4225]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5606]]
|
|
// SIMD-ONLY0: if.end5606:
|
|
// SIMD-ONLY0-NEXT: [[TMP4226:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4226]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4227:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4228:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5607:%.*]] = icmp ult i64 [[TMP4227]], [[TMP4228]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5607]], label [[IF_THEN5609:%.*]], label [[IF_END5610:%.*]]
|
|
// SIMD-ONLY0: if.then5609:
|
|
// SIMD-ONLY0-NEXT: [[TMP4229:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4229]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5610]]
|
|
// SIMD-ONLY0: if.end5610:
|
|
// SIMD-ONLY0-NEXT: [[TMP4230:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4230]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4231:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4232:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5611:%.*]] = icmp ult i64 [[TMP4231]], [[TMP4232]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5611]], label [[IF_THEN5613:%.*]], label [[IF_END5614:%.*]]
|
|
// SIMD-ONLY0: if.then5613:
|
|
// SIMD-ONLY0-NEXT: [[TMP4233:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4233]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5614]]
|
|
// SIMD-ONLY0: if.end5614:
|
|
// SIMD-ONLY0-NEXT: [[TMP4234:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4234]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4235:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4236:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5615:%.*]] = icmp eq i64 [[TMP4235]], [[TMP4236]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5615]], label [[IF_THEN5617:%.*]], label [[IF_END5618:%.*]]
|
|
// SIMD-ONLY0: if.then5617:
|
|
// SIMD-ONLY0-NEXT: [[TMP4237:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4237]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5618]]
|
|
// SIMD-ONLY0: if.end5618:
|
|
// SIMD-ONLY0-NEXT: [[TMP4238:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4238]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4239:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4240:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5619:%.*]] = icmp eq i64 [[TMP4239]], [[TMP4240]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5619]], label [[IF_THEN5621:%.*]], label [[IF_END5622:%.*]]
|
|
// SIMD-ONLY0: if.then5621:
|
|
// SIMD-ONLY0-NEXT: [[TMP4241:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4241]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5622]]
|
|
// SIMD-ONLY0: if.end5622:
|
|
// SIMD-ONLY0-NEXT: [[TMP4242:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4243:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5623:%.*]] = icmp ugt i64 [[TMP4242]], [[TMP4243]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5623]], label [[IF_THEN5625:%.*]], label [[IF_END5626:%.*]]
|
|
// SIMD-ONLY0: if.then5625:
|
|
// SIMD-ONLY0-NEXT: [[TMP4244:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4244]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5626]]
|
|
// SIMD-ONLY0: if.end5626:
|
|
// SIMD-ONLY0-NEXT: [[TMP4245:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4245]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4246:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4247:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5627:%.*]] = icmp ugt i64 [[TMP4246]], [[TMP4247]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5627]], label [[IF_THEN5629:%.*]], label [[IF_END5630:%.*]]
|
|
// SIMD-ONLY0: if.then5629:
|
|
// SIMD-ONLY0-NEXT: [[TMP4248:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4248]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5630]]
|
|
// SIMD-ONLY0: if.end5630:
|
|
// SIMD-ONLY0-NEXT: [[TMP4249:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4249]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4250:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4251:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5631:%.*]] = icmp ult i64 [[TMP4250]], [[TMP4251]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5631]], label [[IF_THEN5633:%.*]], label [[IF_END5634:%.*]]
|
|
// SIMD-ONLY0: if.then5633:
|
|
// SIMD-ONLY0-NEXT: [[TMP4252:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4252]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5634]]
|
|
// SIMD-ONLY0: if.end5634:
|
|
// SIMD-ONLY0-NEXT: [[TMP4253:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4253]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4254:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4255:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5635:%.*]] = icmp ult i64 [[TMP4254]], [[TMP4255]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5635]], label [[IF_THEN5637:%.*]], label [[IF_END5638:%.*]]
|
|
// SIMD-ONLY0: if.then5637:
|
|
// SIMD-ONLY0-NEXT: [[TMP4256:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4256]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5638]]
|
|
// SIMD-ONLY0: if.end5638:
|
|
// SIMD-ONLY0-NEXT: [[TMP4257:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4257]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4258:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4259:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5639:%.*]] = icmp eq i64 [[TMP4258]], [[TMP4259]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5639]], label [[IF_THEN5641:%.*]], label [[IF_END5642:%.*]]
|
|
// SIMD-ONLY0: if.then5641:
|
|
// SIMD-ONLY0-NEXT: [[TMP4260:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4260]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5642]]
|
|
// SIMD-ONLY0: if.end5642:
|
|
// SIMD-ONLY0-NEXT: [[TMP4261:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4261]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4262:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4263:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5643:%.*]] = icmp eq i64 [[TMP4262]], [[TMP4263]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5643]], label [[IF_THEN5645:%.*]], label [[IF_END5646:%.*]]
|
|
// SIMD-ONLY0: if.then5645:
|
|
// SIMD-ONLY0-NEXT: [[TMP4264:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4264]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5646]]
|
|
// SIMD-ONLY0: if.end5646:
|
|
// SIMD-ONLY0-NEXT: [[TMP4265:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4265]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4266:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4267:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5647:%.*]] = icmp eq i64 [[TMP4266]], [[TMP4267]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5647]], label [[IF_THEN5649:%.*]], label [[IF_ELSE5650:%.*]]
|
|
// SIMD-ONLY0: if.then5649:
|
|
// SIMD-ONLY0-NEXT: [[TMP4268:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4268]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5651:%.*]]
|
|
// SIMD-ONLY0: if.else5650:
|
|
// SIMD-ONLY0-NEXT: [[TMP4269:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4269]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5651]]
|
|
// SIMD-ONLY0: if.end5651:
|
|
// SIMD-ONLY0-NEXT: [[TMP4270:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4271:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5652:%.*]] = icmp eq i64 [[TMP4270]], [[TMP4271]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5652]], label [[IF_THEN5654:%.*]], label [[IF_ELSE5655:%.*]]
|
|
// SIMD-ONLY0: if.then5654:
|
|
// SIMD-ONLY0-NEXT: [[TMP4272:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4272]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5656:%.*]]
|
|
// SIMD-ONLY0: if.else5655:
|
|
// SIMD-ONLY0-NEXT: [[TMP4273:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4273]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5656]]
|
|
// SIMD-ONLY0: if.end5656:
|
|
// SIMD-ONLY0-NEXT: [[TMP4274:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4275:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5657:%.*]] = icmp eq i64 [[TMP4274]], [[TMP4275]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5658:%.*]] = zext i1 [[CMP5657]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5659:%.*]] = sext i32 [[CONV5658]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5659]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4276:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5660:%.*]] = icmp ne i64 [[TMP4276]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5660]], label [[IF_THEN5661:%.*]], label [[IF_END5662:%.*]]
|
|
// SIMD-ONLY0: if.then5661:
|
|
// SIMD-ONLY0-NEXT: [[TMP4277:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4277]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5662]]
|
|
// SIMD-ONLY0: if.end5662:
|
|
// SIMD-ONLY0-NEXT: [[TMP4278:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4279:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5663:%.*]] = icmp eq i64 [[TMP4278]], [[TMP4279]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5664:%.*]] = zext i1 [[CMP5663]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5665:%.*]] = sext i32 [[CONV5664]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5665]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4280:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5666:%.*]] = icmp ne i64 [[TMP4280]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5666]], label [[IF_THEN5667:%.*]], label [[IF_END5668:%.*]]
|
|
// SIMD-ONLY0: if.then5667:
|
|
// SIMD-ONLY0-NEXT: [[TMP4281:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4281]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5668]]
|
|
// SIMD-ONLY0: if.end5668:
|
|
// SIMD-ONLY0-NEXT: [[TMP4282:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4283:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5669:%.*]] = icmp eq i64 [[TMP4282]], [[TMP4283]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5670:%.*]] = zext i1 [[CMP5669]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5671:%.*]] = sext i32 [[CONV5670]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5671]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4284:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5672:%.*]] = icmp ne i64 [[TMP4284]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5672]], label [[IF_THEN5673:%.*]], label [[IF_ELSE5674:%.*]]
|
|
// SIMD-ONLY0: if.then5673:
|
|
// SIMD-ONLY0-NEXT: [[TMP4285:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4285]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5675:%.*]]
|
|
// SIMD-ONLY0: if.else5674:
|
|
// SIMD-ONLY0-NEXT: [[TMP4286:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4286]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5675]]
|
|
// SIMD-ONLY0: if.end5675:
|
|
// SIMD-ONLY0-NEXT: [[TMP4287:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4288:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5676:%.*]] = icmp eq i64 [[TMP4287]], [[TMP4288]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5677:%.*]] = zext i1 [[CMP5676]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5678:%.*]] = sext i32 [[CONV5677]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5678]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4289:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5679:%.*]] = icmp ne i64 [[TMP4289]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5679]], label [[IF_THEN5680:%.*]], label [[IF_ELSE5681:%.*]]
|
|
// SIMD-ONLY0: if.then5680:
|
|
// SIMD-ONLY0-NEXT: [[TMP4290:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4290]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5682:%.*]]
|
|
// SIMD-ONLY0: if.else5681:
|
|
// SIMD-ONLY0-NEXT: [[TMP4291:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4291]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5682]]
|
|
// SIMD-ONLY0: if.end5682:
|
|
// SIMD-ONLY0-NEXT: [[TMP4292:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4292]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4293:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4294:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5683:%.*]] = icmp ugt i64 [[TMP4293]], [[TMP4294]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5683]], label [[IF_THEN5685:%.*]], label [[IF_END5686:%.*]]
|
|
// SIMD-ONLY0: if.then5685:
|
|
// SIMD-ONLY0-NEXT: [[TMP4295:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4295]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5686]]
|
|
// SIMD-ONLY0: if.end5686:
|
|
// SIMD-ONLY0-NEXT: [[TMP4296:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4296]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4297:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4298:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5687:%.*]] = icmp ugt i64 [[TMP4297]], [[TMP4298]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5687]], label [[IF_THEN5689:%.*]], label [[IF_END5690:%.*]]
|
|
// SIMD-ONLY0: if.then5689:
|
|
// SIMD-ONLY0-NEXT: [[TMP4299:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4299]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5690]]
|
|
// SIMD-ONLY0: if.end5690:
|
|
// SIMD-ONLY0-NEXT: [[TMP4300:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4300]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4301:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4302:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5691:%.*]] = icmp ult i64 [[TMP4301]], [[TMP4302]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5691]], label [[IF_THEN5693:%.*]], label [[IF_END5694:%.*]]
|
|
// SIMD-ONLY0: if.then5693:
|
|
// SIMD-ONLY0-NEXT: [[TMP4303:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4303]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5694]]
|
|
// SIMD-ONLY0: if.end5694:
|
|
// SIMD-ONLY0-NEXT: [[TMP4304:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4304]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4305:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4306:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5695:%.*]] = icmp ult i64 [[TMP4305]], [[TMP4306]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5695]], label [[IF_THEN5697:%.*]], label [[IF_END5698:%.*]]
|
|
// SIMD-ONLY0: if.then5697:
|
|
// SIMD-ONLY0-NEXT: [[TMP4307:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4307]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5698]]
|
|
// SIMD-ONLY0: if.end5698:
|
|
// SIMD-ONLY0-NEXT: [[TMP4308:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4308]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4309:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4310:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5699:%.*]] = icmp eq i64 [[TMP4309]], [[TMP4310]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5699]], label [[IF_THEN5701:%.*]], label [[IF_END5702:%.*]]
|
|
// SIMD-ONLY0: if.then5701:
|
|
// SIMD-ONLY0-NEXT: [[TMP4311:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4311]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5702]]
|
|
// SIMD-ONLY0: if.end5702:
|
|
// SIMD-ONLY0-NEXT: [[TMP4312:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4312]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4313:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4314:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5703:%.*]] = icmp eq i64 [[TMP4313]], [[TMP4314]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5703]], label [[IF_THEN5705:%.*]], label [[IF_END5706:%.*]]
|
|
// SIMD-ONLY0: if.then5705:
|
|
// SIMD-ONLY0-NEXT: [[TMP4315:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4315]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5706]]
|
|
// SIMD-ONLY0: if.end5706:
|
|
// SIMD-ONLY0-NEXT: [[TMP4316:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4317:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5707:%.*]] = icmp ugt i64 [[TMP4316]], [[TMP4317]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5707]], label [[IF_THEN5709:%.*]], label [[IF_END5710:%.*]]
|
|
// SIMD-ONLY0: if.then5709:
|
|
// SIMD-ONLY0-NEXT: [[TMP4318:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4318]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5710]]
|
|
// SIMD-ONLY0: if.end5710:
|
|
// SIMD-ONLY0-NEXT: [[TMP4319:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4319]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4320:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4321:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5711:%.*]] = icmp ugt i64 [[TMP4320]], [[TMP4321]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5711]], label [[IF_THEN5713:%.*]], label [[IF_END5714:%.*]]
|
|
// SIMD-ONLY0: if.then5713:
|
|
// SIMD-ONLY0-NEXT: [[TMP4322:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4322]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5714]]
|
|
// SIMD-ONLY0: if.end5714:
|
|
// SIMD-ONLY0-NEXT: [[TMP4323:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4323]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4324:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4325:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5715:%.*]] = icmp ult i64 [[TMP4324]], [[TMP4325]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5715]], label [[IF_THEN5717:%.*]], label [[IF_END5718:%.*]]
|
|
// SIMD-ONLY0: if.then5717:
|
|
// SIMD-ONLY0-NEXT: [[TMP4326:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4326]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5718]]
|
|
// SIMD-ONLY0: if.end5718:
|
|
// SIMD-ONLY0-NEXT: [[TMP4327:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4327]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4328:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4329:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5719:%.*]] = icmp ult i64 [[TMP4328]], [[TMP4329]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5719]], label [[IF_THEN5721:%.*]], label [[IF_END5722:%.*]]
|
|
// SIMD-ONLY0: if.then5721:
|
|
// SIMD-ONLY0-NEXT: [[TMP4330:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4330]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5722]]
|
|
// SIMD-ONLY0: if.end5722:
|
|
// SIMD-ONLY0-NEXT: [[TMP4331:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4331]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4332:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4333:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5723:%.*]] = icmp eq i64 [[TMP4332]], [[TMP4333]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5723]], label [[IF_THEN5725:%.*]], label [[IF_END5726:%.*]]
|
|
// SIMD-ONLY0: if.then5725:
|
|
// SIMD-ONLY0-NEXT: [[TMP4334:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4334]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5726]]
|
|
// SIMD-ONLY0: if.end5726:
|
|
// SIMD-ONLY0-NEXT: [[TMP4335:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4335]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4336:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4337:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5727:%.*]] = icmp eq i64 [[TMP4336]], [[TMP4337]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5727]], label [[IF_THEN5729:%.*]], label [[IF_END5730:%.*]]
|
|
// SIMD-ONLY0: if.then5729:
|
|
// SIMD-ONLY0-NEXT: [[TMP4338:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4338]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5730]]
|
|
// SIMD-ONLY0: if.end5730:
|
|
// SIMD-ONLY0-NEXT: [[TMP4339:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4339]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4340:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4341:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5731:%.*]] = icmp eq i64 [[TMP4340]], [[TMP4341]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5731]], label [[IF_THEN5733:%.*]], label [[IF_ELSE5734:%.*]]
|
|
// SIMD-ONLY0: if.then5733:
|
|
// SIMD-ONLY0-NEXT: [[TMP4342:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4342]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5735:%.*]]
|
|
// SIMD-ONLY0: if.else5734:
|
|
// SIMD-ONLY0-NEXT: [[TMP4343:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4343]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5735]]
|
|
// SIMD-ONLY0: if.end5735:
|
|
// SIMD-ONLY0-NEXT: [[TMP4344:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4345:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5736:%.*]] = icmp eq i64 [[TMP4344]], [[TMP4345]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5736]], label [[IF_THEN5738:%.*]], label [[IF_ELSE5739:%.*]]
|
|
// SIMD-ONLY0: if.then5738:
|
|
// SIMD-ONLY0-NEXT: [[TMP4346:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4346]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5740:%.*]]
|
|
// SIMD-ONLY0: if.else5739:
|
|
// SIMD-ONLY0-NEXT: [[TMP4347:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4347]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5740]]
|
|
// SIMD-ONLY0: if.end5740:
|
|
// SIMD-ONLY0-NEXT: [[TMP4348:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4349:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5741:%.*]] = icmp eq i64 [[TMP4348]], [[TMP4349]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5742:%.*]] = zext i1 [[CMP5741]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5743:%.*]] = sext i32 [[CONV5742]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5743]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4350:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5744:%.*]] = icmp ne i64 [[TMP4350]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5744]], label [[IF_THEN5745:%.*]], label [[IF_END5746:%.*]]
|
|
// SIMD-ONLY0: if.then5745:
|
|
// SIMD-ONLY0-NEXT: [[TMP4351:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4351]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5746]]
|
|
// SIMD-ONLY0: if.end5746:
|
|
// SIMD-ONLY0-NEXT: [[TMP4352:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4353:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5747:%.*]] = icmp eq i64 [[TMP4352]], [[TMP4353]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5748:%.*]] = zext i1 [[CMP5747]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5749:%.*]] = sext i32 [[CONV5748]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5749]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4354:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5750:%.*]] = icmp ne i64 [[TMP4354]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5750]], label [[IF_THEN5751:%.*]], label [[IF_END5752:%.*]]
|
|
// SIMD-ONLY0: if.then5751:
|
|
// SIMD-ONLY0-NEXT: [[TMP4355:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4355]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5752]]
|
|
// SIMD-ONLY0: if.end5752:
|
|
// SIMD-ONLY0-NEXT: [[TMP4356:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4357:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5753:%.*]] = icmp eq i64 [[TMP4356]], [[TMP4357]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5754:%.*]] = zext i1 [[CMP5753]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5755:%.*]] = sext i32 [[CONV5754]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5755]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4358:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5756:%.*]] = icmp ne i64 [[TMP4358]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5756]], label [[IF_THEN5757:%.*]], label [[IF_ELSE5758:%.*]]
|
|
// SIMD-ONLY0: if.then5757:
|
|
// SIMD-ONLY0-NEXT: [[TMP4359:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4359]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5759:%.*]]
|
|
// SIMD-ONLY0: if.else5758:
|
|
// SIMD-ONLY0-NEXT: [[TMP4360:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4360]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5759]]
|
|
// SIMD-ONLY0: if.end5759:
|
|
// SIMD-ONLY0-NEXT: [[TMP4361:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4362:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5760:%.*]] = icmp eq i64 [[TMP4361]], [[TMP4362]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5761:%.*]] = zext i1 [[CMP5760]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5762:%.*]] = sext i32 [[CONV5761]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5762]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4363:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5763:%.*]] = icmp ne i64 [[TMP4363]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5763]], label [[IF_THEN5764:%.*]], label [[IF_ELSE5765:%.*]]
|
|
// SIMD-ONLY0: if.then5764:
|
|
// SIMD-ONLY0-NEXT: [[TMP4364:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4364]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5766:%.*]]
|
|
// SIMD-ONLY0: if.else5765:
|
|
// SIMD-ONLY0-NEXT: [[TMP4365:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4365]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5766]]
|
|
// SIMD-ONLY0: if.end5766:
|
|
// SIMD-ONLY0-NEXT: [[TMP4366:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4366]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4367:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4368:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5767:%.*]] = icmp ugt i64 [[TMP4367]], [[TMP4368]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5767]], label [[IF_THEN5769:%.*]], label [[IF_END5770:%.*]]
|
|
// SIMD-ONLY0: if.then5769:
|
|
// SIMD-ONLY0-NEXT: [[TMP4369:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4369]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5770]]
|
|
// SIMD-ONLY0: if.end5770:
|
|
// SIMD-ONLY0-NEXT: [[TMP4370:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4370]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4371:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4372:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5771:%.*]] = icmp ugt i64 [[TMP4371]], [[TMP4372]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5771]], label [[IF_THEN5773:%.*]], label [[IF_END5774:%.*]]
|
|
// SIMD-ONLY0: if.then5773:
|
|
// SIMD-ONLY0-NEXT: [[TMP4373:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4373]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5774]]
|
|
// SIMD-ONLY0: if.end5774:
|
|
// SIMD-ONLY0-NEXT: [[TMP4374:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4374]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4375:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4376:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5775:%.*]] = icmp ult i64 [[TMP4375]], [[TMP4376]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5775]], label [[IF_THEN5777:%.*]], label [[IF_END5778:%.*]]
|
|
// SIMD-ONLY0: if.then5777:
|
|
// SIMD-ONLY0-NEXT: [[TMP4377:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4377]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5778]]
|
|
// SIMD-ONLY0: if.end5778:
|
|
// SIMD-ONLY0-NEXT: [[TMP4378:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4378]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4379:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4380:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5779:%.*]] = icmp ult i64 [[TMP4379]], [[TMP4380]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5779]], label [[IF_THEN5781:%.*]], label [[IF_END5782:%.*]]
|
|
// SIMD-ONLY0: if.then5781:
|
|
// SIMD-ONLY0-NEXT: [[TMP4381:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4381]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5782]]
|
|
// SIMD-ONLY0: if.end5782:
|
|
// SIMD-ONLY0-NEXT: [[TMP4382:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4382]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4383:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4384:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5783:%.*]] = icmp eq i64 [[TMP4383]], [[TMP4384]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5783]], label [[IF_THEN5785:%.*]], label [[IF_END5786:%.*]]
|
|
// SIMD-ONLY0: if.then5785:
|
|
// SIMD-ONLY0-NEXT: [[TMP4385:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4385]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5786]]
|
|
// SIMD-ONLY0: if.end5786:
|
|
// SIMD-ONLY0-NEXT: [[TMP4386:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4386]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4387:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4388:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5787:%.*]] = icmp eq i64 [[TMP4387]], [[TMP4388]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5787]], label [[IF_THEN5789:%.*]], label [[IF_END5790:%.*]]
|
|
// SIMD-ONLY0: if.then5789:
|
|
// SIMD-ONLY0-NEXT: [[TMP4389:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4389]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5790]]
|
|
// SIMD-ONLY0: if.end5790:
|
|
// SIMD-ONLY0-NEXT: [[TMP4390:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4391:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5791:%.*]] = icmp ugt i64 [[TMP4390]], [[TMP4391]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5791]], label [[IF_THEN5793:%.*]], label [[IF_END5794:%.*]]
|
|
// SIMD-ONLY0: if.then5793:
|
|
// SIMD-ONLY0-NEXT: [[TMP4392:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4392]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5794]]
|
|
// SIMD-ONLY0: if.end5794:
|
|
// SIMD-ONLY0-NEXT: [[TMP4393:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4393]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4394:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4395:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5795:%.*]] = icmp ugt i64 [[TMP4394]], [[TMP4395]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5795]], label [[IF_THEN5797:%.*]], label [[IF_END5798:%.*]]
|
|
// SIMD-ONLY0: if.then5797:
|
|
// SIMD-ONLY0-NEXT: [[TMP4396:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4396]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5798]]
|
|
// SIMD-ONLY0: if.end5798:
|
|
// SIMD-ONLY0-NEXT: [[TMP4397:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4397]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4398:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4399:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5799:%.*]] = icmp ult i64 [[TMP4398]], [[TMP4399]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5799]], label [[IF_THEN5801:%.*]], label [[IF_END5802:%.*]]
|
|
// SIMD-ONLY0: if.then5801:
|
|
// SIMD-ONLY0-NEXT: [[TMP4400:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4400]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5802]]
|
|
// SIMD-ONLY0: if.end5802:
|
|
// SIMD-ONLY0-NEXT: [[TMP4401:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4401]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4402:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4403:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5803:%.*]] = icmp ult i64 [[TMP4402]], [[TMP4403]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5803]], label [[IF_THEN5805:%.*]], label [[IF_END5806:%.*]]
|
|
// SIMD-ONLY0: if.then5805:
|
|
// SIMD-ONLY0-NEXT: [[TMP4404:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4404]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5806]]
|
|
// SIMD-ONLY0: if.end5806:
|
|
// SIMD-ONLY0-NEXT: [[TMP4405:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4405]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4406:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4407:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5807:%.*]] = icmp eq i64 [[TMP4406]], [[TMP4407]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5807]], label [[IF_THEN5809:%.*]], label [[IF_END5810:%.*]]
|
|
// SIMD-ONLY0: if.then5809:
|
|
// SIMD-ONLY0-NEXT: [[TMP4408:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4408]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5810]]
|
|
// SIMD-ONLY0: if.end5810:
|
|
// SIMD-ONLY0-NEXT: [[TMP4409:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4409]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4410:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4411:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5811:%.*]] = icmp eq i64 [[TMP4410]], [[TMP4411]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5811]], label [[IF_THEN5813:%.*]], label [[IF_END5814:%.*]]
|
|
// SIMD-ONLY0: if.then5813:
|
|
// SIMD-ONLY0-NEXT: [[TMP4412:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4412]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5814]]
|
|
// SIMD-ONLY0: if.end5814:
|
|
// SIMD-ONLY0-NEXT: [[TMP4413:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4413]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4414:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4415:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5815:%.*]] = icmp eq i64 [[TMP4414]], [[TMP4415]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5815]], label [[IF_THEN5817:%.*]], label [[IF_ELSE5818:%.*]]
|
|
// SIMD-ONLY0: if.then5817:
|
|
// SIMD-ONLY0-NEXT: [[TMP4416:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4416]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5819:%.*]]
|
|
// SIMD-ONLY0: if.else5818:
|
|
// SIMD-ONLY0-NEXT: [[TMP4417:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4417]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5819]]
|
|
// SIMD-ONLY0: if.end5819:
|
|
// SIMD-ONLY0-NEXT: [[TMP4418:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4419:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5820:%.*]] = icmp eq i64 [[TMP4418]], [[TMP4419]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5820]], label [[IF_THEN5822:%.*]], label [[IF_ELSE5823:%.*]]
|
|
// SIMD-ONLY0: if.then5822:
|
|
// SIMD-ONLY0-NEXT: [[TMP4420:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4420]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5824:%.*]]
|
|
// SIMD-ONLY0: if.else5823:
|
|
// SIMD-ONLY0-NEXT: [[TMP4421:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4421]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5824]]
|
|
// SIMD-ONLY0: if.end5824:
|
|
// SIMD-ONLY0-NEXT: [[TMP4422:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4423:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5825:%.*]] = icmp eq i64 [[TMP4422]], [[TMP4423]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5826:%.*]] = zext i1 [[CMP5825]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5827:%.*]] = sext i32 [[CONV5826]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5827]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4424:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5828:%.*]] = icmp ne i64 [[TMP4424]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5828]], label [[IF_THEN5829:%.*]], label [[IF_END5830:%.*]]
|
|
// SIMD-ONLY0: if.then5829:
|
|
// SIMD-ONLY0-NEXT: [[TMP4425:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4425]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5830]]
|
|
// SIMD-ONLY0: if.end5830:
|
|
// SIMD-ONLY0-NEXT: [[TMP4426:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4427:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5831:%.*]] = icmp eq i64 [[TMP4426]], [[TMP4427]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5832:%.*]] = zext i1 [[CMP5831]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5833:%.*]] = sext i32 [[CONV5832]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5833]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4428:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5834:%.*]] = icmp ne i64 [[TMP4428]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5834]], label [[IF_THEN5835:%.*]], label [[IF_END5836:%.*]]
|
|
// SIMD-ONLY0: if.then5835:
|
|
// SIMD-ONLY0-NEXT: [[TMP4429:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4429]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5836]]
|
|
// SIMD-ONLY0: if.end5836:
|
|
// SIMD-ONLY0-NEXT: [[TMP4430:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4431:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5837:%.*]] = icmp eq i64 [[TMP4430]], [[TMP4431]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5838:%.*]] = zext i1 [[CMP5837]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5839:%.*]] = sext i32 [[CONV5838]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5839]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4432:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5840:%.*]] = icmp ne i64 [[TMP4432]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5840]], label [[IF_THEN5841:%.*]], label [[IF_ELSE5842:%.*]]
|
|
// SIMD-ONLY0: if.then5841:
|
|
// SIMD-ONLY0-NEXT: [[TMP4433:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4433]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5843:%.*]]
|
|
// SIMD-ONLY0: if.else5842:
|
|
// SIMD-ONLY0-NEXT: [[TMP4434:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4434]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5843]]
|
|
// SIMD-ONLY0: if.end5843:
|
|
// SIMD-ONLY0-NEXT: [[TMP4435:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4436:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP5844:%.*]] = icmp eq i64 [[TMP4435]], [[TMP4436]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5845:%.*]] = zext i1 [[CMP5844]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CONV5846:%.*]] = sext i32 [[CONV5845]] to i64
|
|
// SIMD-ONLY0-NEXT: store i64 [[CONV5846]], ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4437:%.*]] = load i64, ptr [[ULLR]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5847:%.*]] = icmp ne i64 [[TMP4437]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5847]], label [[IF_THEN5848:%.*]], label [[IF_ELSE5849:%.*]]
|
|
// SIMD-ONLY0: if.then5848:
|
|
// SIMD-ONLY0-NEXT: [[TMP4438:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4438]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5850:%.*]]
|
|
// SIMD-ONLY0: if.else5849:
|
|
// SIMD-ONLY0-NEXT: [[TMP4439:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP4439]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5850]]
|
|
// SIMD-ONLY0: if.end5850:
|
|
// SIMD-ONLY0-NEXT: [[TMP4440:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4440]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4441:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4442:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5851:%.*]] = fcmp ogt float [[TMP4441]], [[TMP4442]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5851]], label [[IF_THEN5853:%.*]], label [[IF_END5854:%.*]]
|
|
// SIMD-ONLY0: if.then5853:
|
|
// SIMD-ONLY0-NEXT: [[TMP4443:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4443]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5854]]
|
|
// SIMD-ONLY0: if.end5854:
|
|
// SIMD-ONLY0-NEXT: [[TMP4444:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4444]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4445:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4446:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5855:%.*]] = fcmp ogt float [[TMP4445]], [[TMP4446]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5855]], label [[IF_THEN5857:%.*]], label [[IF_END5858:%.*]]
|
|
// SIMD-ONLY0: if.then5857:
|
|
// SIMD-ONLY0-NEXT: [[TMP4447:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4447]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5858]]
|
|
// SIMD-ONLY0: if.end5858:
|
|
// SIMD-ONLY0-NEXT: [[TMP4448:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4448]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4449:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4450:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5859:%.*]] = fcmp olt float [[TMP4449]], [[TMP4450]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5859]], label [[IF_THEN5861:%.*]], label [[IF_END5862:%.*]]
|
|
// SIMD-ONLY0: if.then5861:
|
|
// SIMD-ONLY0-NEXT: [[TMP4451:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4451]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5862]]
|
|
// SIMD-ONLY0: if.end5862:
|
|
// SIMD-ONLY0-NEXT: [[TMP4452:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4452]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4453:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4454:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5863:%.*]] = fcmp olt float [[TMP4453]], [[TMP4454]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5863]], label [[IF_THEN5865:%.*]], label [[IF_END5866:%.*]]
|
|
// SIMD-ONLY0: if.then5865:
|
|
// SIMD-ONLY0-NEXT: [[TMP4455:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4455]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5866]]
|
|
// SIMD-ONLY0: if.end5866:
|
|
// SIMD-ONLY0-NEXT: [[TMP4456:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4456]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4457:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4458:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5867:%.*]] = fcmp oeq float [[TMP4457]], [[TMP4458]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5867]], label [[IF_THEN5869:%.*]], label [[IF_END5870:%.*]]
|
|
// SIMD-ONLY0: if.then5869:
|
|
// SIMD-ONLY0-NEXT: [[TMP4459:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4459]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5870]]
|
|
// SIMD-ONLY0: if.end5870:
|
|
// SIMD-ONLY0-NEXT: [[TMP4460:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4460]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4461:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4462:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5871:%.*]] = fcmp oeq float [[TMP4461]], [[TMP4462]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5871]], label [[IF_THEN5873:%.*]], label [[IF_END5874:%.*]]
|
|
// SIMD-ONLY0: if.then5873:
|
|
// SIMD-ONLY0-NEXT: [[TMP4463:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4463]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5874]]
|
|
// SIMD-ONLY0: if.end5874:
|
|
// SIMD-ONLY0-NEXT: [[TMP4464:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4465:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5875:%.*]] = fcmp ogt float [[TMP4464]], [[TMP4465]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5875]], label [[IF_THEN5877:%.*]], label [[IF_END5878:%.*]]
|
|
// SIMD-ONLY0: if.then5877:
|
|
// SIMD-ONLY0-NEXT: [[TMP4466:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4466]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5878]]
|
|
// SIMD-ONLY0: if.end5878:
|
|
// SIMD-ONLY0-NEXT: [[TMP4467:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4467]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4468:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4469:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5879:%.*]] = fcmp ogt float [[TMP4468]], [[TMP4469]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5879]], label [[IF_THEN5881:%.*]], label [[IF_END5882:%.*]]
|
|
// SIMD-ONLY0: if.then5881:
|
|
// SIMD-ONLY0-NEXT: [[TMP4470:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4470]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5882]]
|
|
// SIMD-ONLY0: if.end5882:
|
|
// SIMD-ONLY0-NEXT: [[TMP4471:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4471]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4472:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4473:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5883:%.*]] = fcmp olt float [[TMP4472]], [[TMP4473]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5883]], label [[IF_THEN5885:%.*]], label [[IF_END5886:%.*]]
|
|
// SIMD-ONLY0: if.then5885:
|
|
// SIMD-ONLY0-NEXT: [[TMP4474:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4474]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5886]]
|
|
// SIMD-ONLY0: if.end5886:
|
|
// SIMD-ONLY0-NEXT: [[TMP4475:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4475]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4476:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4477:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5887:%.*]] = fcmp olt float [[TMP4476]], [[TMP4477]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5887]], label [[IF_THEN5889:%.*]], label [[IF_END5890:%.*]]
|
|
// SIMD-ONLY0: if.then5889:
|
|
// SIMD-ONLY0-NEXT: [[TMP4478:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4478]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5890]]
|
|
// SIMD-ONLY0: if.end5890:
|
|
// SIMD-ONLY0-NEXT: [[TMP4479:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4479]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4480:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4481:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5891:%.*]] = fcmp oeq float [[TMP4480]], [[TMP4481]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5891]], label [[IF_THEN5893:%.*]], label [[IF_END5894:%.*]]
|
|
// SIMD-ONLY0: if.then5893:
|
|
// SIMD-ONLY0-NEXT: [[TMP4482:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4482]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5894]]
|
|
// SIMD-ONLY0: if.end5894:
|
|
// SIMD-ONLY0-NEXT: [[TMP4483:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4483]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4484:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4485:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5895:%.*]] = fcmp oeq float [[TMP4484]], [[TMP4485]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5895]], label [[IF_THEN5897:%.*]], label [[IF_END5898:%.*]]
|
|
// SIMD-ONLY0: if.then5897:
|
|
// SIMD-ONLY0-NEXT: [[TMP4486:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4486]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5898]]
|
|
// SIMD-ONLY0: if.end5898:
|
|
// SIMD-ONLY0-NEXT: [[TMP4487:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4487]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4488:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4489:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5899:%.*]] = fcmp oeq float [[TMP4488]], [[TMP4489]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5899]], label [[IF_THEN5901:%.*]], label [[IF_ELSE5902:%.*]]
|
|
// SIMD-ONLY0: if.then5901:
|
|
// SIMD-ONLY0-NEXT: [[TMP4490:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4490]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5903:%.*]]
|
|
// SIMD-ONLY0: if.else5902:
|
|
// SIMD-ONLY0-NEXT: [[TMP4491:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4491]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5903]]
|
|
// SIMD-ONLY0: if.end5903:
|
|
// SIMD-ONLY0-NEXT: [[TMP4492:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4493:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5904:%.*]] = fcmp oeq float [[TMP4492]], [[TMP4493]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5904]], label [[IF_THEN5906:%.*]], label [[IF_ELSE5907:%.*]]
|
|
// SIMD-ONLY0: if.then5906:
|
|
// SIMD-ONLY0-NEXT: [[TMP4494:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4494]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5908:%.*]]
|
|
// SIMD-ONLY0: if.else5907:
|
|
// SIMD-ONLY0-NEXT: [[TMP4495:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4495]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5908]]
|
|
// SIMD-ONLY0: if.end5908:
|
|
// SIMD-ONLY0-NEXT: [[TMP4496:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4497:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5909:%.*]] = fcmp oeq float [[TMP4496]], [[TMP4497]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5910:%.*]] = zext i1 [[CMP5909]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV5910]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4498:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5911:%.*]] = icmp ne i32 [[TMP4498]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5911]], label [[IF_THEN5912:%.*]], label [[IF_END5913:%.*]]
|
|
// SIMD-ONLY0: if.then5912:
|
|
// SIMD-ONLY0-NEXT: [[TMP4499:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4499]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5913]]
|
|
// SIMD-ONLY0: if.end5913:
|
|
// SIMD-ONLY0-NEXT: [[TMP4500:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4501:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5914:%.*]] = fcmp oeq float [[TMP4500]], [[TMP4501]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5915:%.*]] = zext i1 [[CMP5914]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV5915]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4502:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5916:%.*]] = icmp ne i32 [[TMP4502]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5916]], label [[IF_THEN5917:%.*]], label [[IF_END5918:%.*]]
|
|
// SIMD-ONLY0: if.then5917:
|
|
// SIMD-ONLY0-NEXT: [[TMP4503:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4503]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5918]]
|
|
// SIMD-ONLY0: if.end5918:
|
|
// SIMD-ONLY0-NEXT: [[TMP4504:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4505:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5919:%.*]] = fcmp oeq float [[TMP4504]], [[TMP4505]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5920:%.*]] = zext i1 [[CMP5919]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV5920]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4506:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5921:%.*]] = icmp ne i32 [[TMP4506]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5921]], label [[IF_THEN5922:%.*]], label [[IF_ELSE5923:%.*]]
|
|
// SIMD-ONLY0: if.then5922:
|
|
// SIMD-ONLY0-NEXT: [[TMP4507:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4507]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5924:%.*]]
|
|
// SIMD-ONLY0: if.else5923:
|
|
// SIMD-ONLY0-NEXT: [[TMP4508:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4508]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5924]]
|
|
// SIMD-ONLY0: if.end5924:
|
|
// SIMD-ONLY0-NEXT: [[TMP4509:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4510:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5925:%.*]] = fcmp oeq float [[TMP4509]], [[TMP4510]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5926:%.*]] = zext i1 [[CMP5925]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV5926]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4511:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5927:%.*]] = icmp ne i32 [[TMP4511]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5927]], label [[IF_THEN5928:%.*]], label [[IF_ELSE5929:%.*]]
|
|
// SIMD-ONLY0: if.then5928:
|
|
// SIMD-ONLY0-NEXT: [[TMP4512:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4512]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5930:%.*]]
|
|
// SIMD-ONLY0: if.else5929:
|
|
// SIMD-ONLY0-NEXT: [[TMP4513:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4513]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5930]]
|
|
// SIMD-ONLY0: if.end5930:
|
|
// SIMD-ONLY0-NEXT: [[TMP4514:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4514]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4515:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4516:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5931:%.*]] = fcmp ogt float [[TMP4515]], [[TMP4516]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5931]], label [[IF_THEN5933:%.*]], label [[IF_END5934:%.*]]
|
|
// SIMD-ONLY0: if.then5933:
|
|
// SIMD-ONLY0-NEXT: [[TMP4517:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4517]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5934]]
|
|
// SIMD-ONLY0: if.end5934:
|
|
// SIMD-ONLY0-NEXT: [[TMP4518:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4518]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4519:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4520:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5935:%.*]] = fcmp ogt float [[TMP4519]], [[TMP4520]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5935]], label [[IF_THEN5937:%.*]], label [[IF_END5938:%.*]]
|
|
// SIMD-ONLY0: if.then5937:
|
|
// SIMD-ONLY0-NEXT: [[TMP4521:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4521]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5938]]
|
|
// SIMD-ONLY0: if.end5938:
|
|
// SIMD-ONLY0-NEXT: [[TMP4522:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4522]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4523:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4524:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5939:%.*]] = fcmp olt float [[TMP4523]], [[TMP4524]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5939]], label [[IF_THEN5941:%.*]], label [[IF_END5942:%.*]]
|
|
// SIMD-ONLY0: if.then5941:
|
|
// SIMD-ONLY0-NEXT: [[TMP4525:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4525]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5942]]
|
|
// SIMD-ONLY0: if.end5942:
|
|
// SIMD-ONLY0-NEXT: [[TMP4526:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4526]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4527:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4528:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5943:%.*]] = fcmp olt float [[TMP4527]], [[TMP4528]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5943]], label [[IF_THEN5945:%.*]], label [[IF_END5946:%.*]]
|
|
// SIMD-ONLY0: if.then5945:
|
|
// SIMD-ONLY0-NEXT: [[TMP4529:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4529]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5946]]
|
|
// SIMD-ONLY0: if.end5946:
|
|
// SIMD-ONLY0-NEXT: [[TMP4530:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4530]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4531:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4532:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5947:%.*]] = fcmp oeq float [[TMP4531]], [[TMP4532]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5947]], label [[IF_THEN5949:%.*]], label [[IF_END5950:%.*]]
|
|
// SIMD-ONLY0: if.then5949:
|
|
// SIMD-ONLY0-NEXT: [[TMP4533:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4533]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5950]]
|
|
// SIMD-ONLY0: if.end5950:
|
|
// SIMD-ONLY0-NEXT: [[TMP4534:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4534]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4535:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4536:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5951:%.*]] = fcmp oeq float [[TMP4535]], [[TMP4536]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5951]], label [[IF_THEN5953:%.*]], label [[IF_END5954:%.*]]
|
|
// SIMD-ONLY0: if.then5953:
|
|
// SIMD-ONLY0-NEXT: [[TMP4537:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4537]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5954]]
|
|
// SIMD-ONLY0: if.end5954:
|
|
// SIMD-ONLY0-NEXT: [[TMP4538:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4539:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5955:%.*]] = fcmp ogt float [[TMP4538]], [[TMP4539]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5955]], label [[IF_THEN5957:%.*]], label [[IF_END5958:%.*]]
|
|
// SIMD-ONLY0: if.then5957:
|
|
// SIMD-ONLY0-NEXT: [[TMP4540:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4540]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5958]]
|
|
// SIMD-ONLY0: if.end5958:
|
|
// SIMD-ONLY0-NEXT: [[TMP4541:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4541]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4542:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4543:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5959:%.*]] = fcmp ogt float [[TMP4542]], [[TMP4543]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5959]], label [[IF_THEN5961:%.*]], label [[IF_END5962:%.*]]
|
|
// SIMD-ONLY0: if.then5961:
|
|
// SIMD-ONLY0-NEXT: [[TMP4544:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4544]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5962]]
|
|
// SIMD-ONLY0: if.end5962:
|
|
// SIMD-ONLY0-NEXT: [[TMP4545:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4545]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4546:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4547:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5963:%.*]] = fcmp olt float [[TMP4546]], [[TMP4547]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5963]], label [[IF_THEN5965:%.*]], label [[IF_END5966:%.*]]
|
|
// SIMD-ONLY0: if.then5965:
|
|
// SIMD-ONLY0-NEXT: [[TMP4548:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4548]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5966]]
|
|
// SIMD-ONLY0: if.end5966:
|
|
// SIMD-ONLY0-NEXT: [[TMP4549:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4549]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4550:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4551:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5967:%.*]] = fcmp olt float [[TMP4550]], [[TMP4551]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5967]], label [[IF_THEN5969:%.*]], label [[IF_END5970:%.*]]
|
|
// SIMD-ONLY0: if.then5969:
|
|
// SIMD-ONLY0-NEXT: [[TMP4552:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4552]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5970]]
|
|
// SIMD-ONLY0: if.end5970:
|
|
// SIMD-ONLY0-NEXT: [[TMP4553:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4553]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4554:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4555:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5971:%.*]] = fcmp oeq float [[TMP4554]], [[TMP4555]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5971]], label [[IF_THEN5973:%.*]], label [[IF_END5974:%.*]]
|
|
// SIMD-ONLY0: if.then5973:
|
|
// SIMD-ONLY0-NEXT: [[TMP4556:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4556]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5974]]
|
|
// SIMD-ONLY0: if.end5974:
|
|
// SIMD-ONLY0-NEXT: [[TMP4557:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4557]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4558:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4559:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5975:%.*]] = fcmp oeq float [[TMP4558]], [[TMP4559]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5975]], label [[IF_THEN5977:%.*]], label [[IF_END5978:%.*]]
|
|
// SIMD-ONLY0: if.then5977:
|
|
// SIMD-ONLY0-NEXT: [[TMP4560:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4560]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5978]]
|
|
// SIMD-ONLY0: if.end5978:
|
|
// SIMD-ONLY0-NEXT: [[TMP4561:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4561]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4562:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4563:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5979:%.*]] = fcmp oeq float [[TMP4562]], [[TMP4563]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5979]], label [[IF_THEN5981:%.*]], label [[IF_ELSE5982:%.*]]
|
|
// SIMD-ONLY0: if.then5981:
|
|
// SIMD-ONLY0-NEXT: [[TMP4564:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4564]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5983:%.*]]
|
|
// SIMD-ONLY0: if.else5982:
|
|
// SIMD-ONLY0-NEXT: [[TMP4565:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4565]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5983]]
|
|
// SIMD-ONLY0: if.end5983:
|
|
// SIMD-ONLY0-NEXT: [[TMP4566:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4567:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5984:%.*]] = fcmp oeq float [[TMP4566]], [[TMP4567]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP5984]], label [[IF_THEN5986:%.*]], label [[IF_ELSE5987:%.*]]
|
|
// SIMD-ONLY0: if.then5986:
|
|
// SIMD-ONLY0-NEXT: [[TMP4568:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4568]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5988:%.*]]
|
|
// SIMD-ONLY0: if.else5987:
|
|
// SIMD-ONLY0-NEXT: [[TMP4569:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4569]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5988]]
|
|
// SIMD-ONLY0: if.end5988:
|
|
// SIMD-ONLY0-NEXT: [[TMP4570:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4571:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5989:%.*]] = fcmp oeq float [[TMP4570]], [[TMP4571]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5990:%.*]] = zext i1 [[CMP5989]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV5990]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4572:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5991:%.*]] = icmp ne i32 [[TMP4572]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5991]], label [[IF_THEN5992:%.*]], label [[IF_END5993:%.*]]
|
|
// SIMD-ONLY0: if.then5992:
|
|
// SIMD-ONLY0-NEXT: [[TMP4573:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4573]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5993]]
|
|
// SIMD-ONLY0: if.end5993:
|
|
// SIMD-ONLY0-NEXT: [[TMP4574:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4575:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5994:%.*]] = fcmp oeq float [[TMP4574]], [[TMP4575]]
|
|
// SIMD-ONLY0-NEXT: [[CONV5995:%.*]] = zext i1 [[CMP5994]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV5995]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4576:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL5996:%.*]] = icmp ne i32 [[TMP4576]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL5996]], label [[IF_THEN5997:%.*]], label [[IF_END5998:%.*]]
|
|
// SIMD-ONLY0: if.then5997:
|
|
// SIMD-ONLY0-NEXT: [[TMP4577:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4577]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END5998]]
|
|
// SIMD-ONLY0: if.end5998:
|
|
// SIMD-ONLY0-NEXT: [[TMP4578:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4579:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP5999:%.*]] = fcmp oeq float [[TMP4578]], [[TMP4579]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6000:%.*]] = zext i1 [[CMP5999]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6000]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4580:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6001:%.*]] = icmp ne i32 [[TMP4580]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6001]], label [[IF_THEN6002:%.*]], label [[IF_ELSE6003:%.*]]
|
|
// SIMD-ONLY0: if.then6002:
|
|
// SIMD-ONLY0-NEXT: [[TMP4581:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4581]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6004:%.*]]
|
|
// SIMD-ONLY0: if.else6003:
|
|
// SIMD-ONLY0-NEXT: [[TMP4582:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4582]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6004]]
|
|
// SIMD-ONLY0: if.end6004:
|
|
// SIMD-ONLY0-NEXT: [[TMP4583:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4584:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6005:%.*]] = fcmp oeq float [[TMP4583]], [[TMP4584]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6006:%.*]] = zext i1 [[CMP6005]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6006]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4585:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6007:%.*]] = icmp ne i32 [[TMP4585]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6007]], label [[IF_THEN6008:%.*]], label [[IF_ELSE6009:%.*]]
|
|
// SIMD-ONLY0: if.then6008:
|
|
// SIMD-ONLY0-NEXT: [[TMP4586:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4586]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6010:%.*]]
|
|
// SIMD-ONLY0: if.else6009:
|
|
// SIMD-ONLY0-NEXT: [[TMP4587:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4587]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6010]]
|
|
// SIMD-ONLY0: if.end6010:
|
|
// SIMD-ONLY0-NEXT: [[TMP4588:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4588]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4589:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4590:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6011:%.*]] = fcmp ogt float [[TMP4589]], [[TMP4590]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6011]], label [[IF_THEN6013:%.*]], label [[IF_END6014:%.*]]
|
|
// SIMD-ONLY0: if.then6013:
|
|
// SIMD-ONLY0-NEXT: [[TMP4591:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4591]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6014]]
|
|
// SIMD-ONLY0: if.end6014:
|
|
// SIMD-ONLY0-NEXT: [[TMP4592:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4592]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4593:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4594:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6015:%.*]] = fcmp ogt float [[TMP4593]], [[TMP4594]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6015]], label [[IF_THEN6017:%.*]], label [[IF_END6018:%.*]]
|
|
// SIMD-ONLY0: if.then6017:
|
|
// SIMD-ONLY0-NEXT: [[TMP4595:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4595]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6018]]
|
|
// SIMD-ONLY0: if.end6018:
|
|
// SIMD-ONLY0-NEXT: [[TMP4596:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4596]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4597:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4598:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6019:%.*]] = fcmp olt float [[TMP4597]], [[TMP4598]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6019]], label [[IF_THEN6021:%.*]], label [[IF_END6022:%.*]]
|
|
// SIMD-ONLY0: if.then6021:
|
|
// SIMD-ONLY0-NEXT: [[TMP4599:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4599]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6022]]
|
|
// SIMD-ONLY0: if.end6022:
|
|
// SIMD-ONLY0-NEXT: [[TMP4600:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4600]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4601:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4602:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6023:%.*]] = fcmp olt float [[TMP4601]], [[TMP4602]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6023]], label [[IF_THEN6025:%.*]], label [[IF_END6026:%.*]]
|
|
// SIMD-ONLY0: if.then6025:
|
|
// SIMD-ONLY0-NEXT: [[TMP4603:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4603]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6026]]
|
|
// SIMD-ONLY0: if.end6026:
|
|
// SIMD-ONLY0-NEXT: [[TMP4604:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4604]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4605:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4606:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6027:%.*]] = fcmp oeq float [[TMP4605]], [[TMP4606]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6027]], label [[IF_THEN6029:%.*]], label [[IF_END6030:%.*]]
|
|
// SIMD-ONLY0: if.then6029:
|
|
// SIMD-ONLY0-NEXT: [[TMP4607:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4607]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6030]]
|
|
// SIMD-ONLY0: if.end6030:
|
|
// SIMD-ONLY0-NEXT: [[TMP4608:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4608]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4609:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4610:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6031:%.*]] = fcmp oeq float [[TMP4609]], [[TMP4610]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6031]], label [[IF_THEN6033:%.*]], label [[IF_END6034:%.*]]
|
|
// SIMD-ONLY0: if.then6033:
|
|
// SIMD-ONLY0-NEXT: [[TMP4611:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4611]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6034]]
|
|
// SIMD-ONLY0: if.end6034:
|
|
// SIMD-ONLY0-NEXT: [[TMP4612:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4613:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6035:%.*]] = fcmp ogt float [[TMP4612]], [[TMP4613]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6035]], label [[IF_THEN6037:%.*]], label [[IF_END6038:%.*]]
|
|
// SIMD-ONLY0: if.then6037:
|
|
// SIMD-ONLY0-NEXT: [[TMP4614:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4614]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6038]]
|
|
// SIMD-ONLY0: if.end6038:
|
|
// SIMD-ONLY0-NEXT: [[TMP4615:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4615]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4616:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4617:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6039:%.*]] = fcmp ogt float [[TMP4616]], [[TMP4617]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6039]], label [[IF_THEN6041:%.*]], label [[IF_END6042:%.*]]
|
|
// SIMD-ONLY0: if.then6041:
|
|
// SIMD-ONLY0-NEXT: [[TMP4618:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4618]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6042]]
|
|
// SIMD-ONLY0: if.end6042:
|
|
// SIMD-ONLY0-NEXT: [[TMP4619:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4619]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4620:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4621:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6043:%.*]] = fcmp olt float [[TMP4620]], [[TMP4621]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6043]], label [[IF_THEN6045:%.*]], label [[IF_END6046:%.*]]
|
|
// SIMD-ONLY0: if.then6045:
|
|
// SIMD-ONLY0-NEXT: [[TMP4622:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4622]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6046]]
|
|
// SIMD-ONLY0: if.end6046:
|
|
// SIMD-ONLY0-NEXT: [[TMP4623:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4623]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4624:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4625:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6047:%.*]] = fcmp olt float [[TMP4624]], [[TMP4625]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6047]], label [[IF_THEN6049:%.*]], label [[IF_END6050:%.*]]
|
|
// SIMD-ONLY0: if.then6049:
|
|
// SIMD-ONLY0-NEXT: [[TMP4626:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4626]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6050]]
|
|
// SIMD-ONLY0: if.end6050:
|
|
// SIMD-ONLY0-NEXT: [[TMP4627:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4627]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4628:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4629:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6051:%.*]] = fcmp oeq float [[TMP4628]], [[TMP4629]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6051]], label [[IF_THEN6053:%.*]], label [[IF_END6054:%.*]]
|
|
// SIMD-ONLY0: if.then6053:
|
|
// SIMD-ONLY0-NEXT: [[TMP4630:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4630]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6054]]
|
|
// SIMD-ONLY0: if.end6054:
|
|
// SIMD-ONLY0-NEXT: [[TMP4631:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4631]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4632:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4633:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6055:%.*]] = fcmp oeq float [[TMP4632]], [[TMP4633]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6055]], label [[IF_THEN6057:%.*]], label [[IF_END6058:%.*]]
|
|
// SIMD-ONLY0: if.then6057:
|
|
// SIMD-ONLY0-NEXT: [[TMP4634:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4634]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6058]]
|
|
// SIMD-ONLY0: if.end6058:
|
|
// SIMD-ONLY0-NEXT: [[TMP4635:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4635]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4636:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4637:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6059:%.*]] = fcmp oeq float [[TMP4636]], [[TMP4637]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6059]], label [[IF_THEN6061:%.*]], label [[IF_ELSE6062:%.*]]
|
|
// SIMD-ONLY0: if.then6061:
|
|
// SIMD-ONLY0-NEXT: [[TMP4638:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4638]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6063:%.*]]
|
|
// SIMD-ONLY0: if.else6062:
|
|
// SIMD-ONLY0-NEXT: [[TMP4639:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4639]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6063]]
|
|
// SIMD-ONLY0: if.end6063:
|
|
// SIMD-ONLY0-NEXT: [[TMP4640:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4641:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6064:%.*]] = fcmp oeq float [[TMP4640]], [[TMP4641]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6064]], label [[IF_THEN6066:%.*]], label [[IF_ELSE6067:%.*]]
|
|
// SIMD-ONLY0: if.then6066:
|
|
// SIMD-ONLY0-NEXT: [[TMP4642:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4642]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6068:%.*]]
|
|
// SIMD-ONLY0: if.else6067:
|
|
// SIMD-ONLY0-NEXT: [[TMP4643:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4643]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6068]]
|
|
// SIMD-ONLY0: if.end6068:
|
|
// SIMD-ONLY0-NEXT: [[TMP4644:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4645:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6069:%.*]] = fcmp oeq float [[TMP4644]], [[TMP4645]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6070:%.*]] = zext i1 [[CMP6069]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6070]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4646:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6071:%.*]] = icmp ne i32 [[TMP4646]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6071]], label [[IF_THEN6072:%.*]], label [[IF_END6073:%.*]]
|
|
// SIMD-ONLY0: if.then6072:
|
|
// SIMD-ONLY0-NEXT: [[TMP4647:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4647]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6073]]
|
|
// SIMD-ONLY0: if.end6073:
|
|
// SIMD-ONLY0-NEXT: [[TMP4648:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4649:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6074:%.*]] = fcmp oeq float [[TMP4648]], [[TMP4649]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6075:%.*]] = zext i1 [[CMP6074]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6075]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4650:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6076:%.*]] = icmp ne i32 [[TMP4650]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6076]], label [[IF_THEN6077:%.*]], label [[IF_END6078:%.*]]
|
|
// SIMD-ONLY0: if.then6077:
|
|
// SIMD-ONLY0-NEXT: [[TMP4651:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4651]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6078]]
|
|
// SIMD-ONLY0: if.end6078:
|
|
// SIMD-ONLY0-NEXT: [[TMP4652:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4653:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6079:%.*]] = fcmp oeq float [[TMP4652]], [[TMP4653]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6080:%.*]] = zext i1 [[CMP6079]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6080]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4654:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6081:%.*]] = icmp ne i32 [[TMP4654]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6081]], label [[IF_THEN6082:%.*]], label [[IF_ELSE6083:%.*]]
|
|
// SIMD-ONLY0: if.then6082:
|
|
// SIMD-ONLY0-NEXT: [[TMP4655:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4655]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6084:%.*]]
|
|
// SIMD-ONLY0: if.else6083:
|
|
// SIMD-ONLY0-NEXT: [[TMP4656:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4656]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6084]]
|
|
// SIMD-ONLY0: if.end6084:
|
|
// SIMD-ONLY0-NEXT: [[TMP4657:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4658:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6085:%.*]] = fcmp oeq float [[TMP4657]], [[TMP4658]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6086:%.*]] = zext i1 [[CMP6085]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6086]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4659:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6087:%.*]] = icmp ne i32 [[TMP4659]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6087]], label [[IF_THEN6088:%.*]], label [[IF_ELSE6089:%.*]]
|
|
// SIMD-ONLY0: if.then6088:
|
|
// SIMD-ONLY0-NEXT: [[TMP4660:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4660]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6090:%.*]]
|
|
// SIMD-ONLY0: if.else6089:
|
|
// SIMD-ONLY0-NEXT: [[TMP4661:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4661]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6090]]
|
|
// SIMD-ONLY0: if.end6090:
|
|
// SIMD-ONLY0-NEXT: [[TMP4662:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4662]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4663:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4664:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6091:%.*]] = fcmp ogt float [[TMP4663]], [[TMP4664]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6091]], label [[IF_THEN6093:%.*]], label [[IF_END6094:%.*]]
|
|
// SIMD-ONLY0: if.then6093:
|
|
// SIMD-ONLY0-NEXT: [[TMP4665:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4665]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6094]]
|
|
// SIMD-ONLY0: if.end6094:
|
|
// SIMD-ONLY0-NEXT: [[TMP4666:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4666]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4667:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4668:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6095:%.*]] = fcmp ogt float [[TMP4667]], [[TMP4668]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6095]], label [[IF_THEN6097:%.*]], label [[IF_END6098:%.*]]
|
|
// SIMD-ONLY0: if.then6097:
|
|
// SIMD-ONLY0-NEXT: [[TMP4669:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4669]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6098]]
|
|
// SIMD-ONLY0: if.end6098:
|
|
// SIMD-ONLY0-NEXT: [[TMP4670:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4670]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4671:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4672:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6099:%.*]] = fcmp olt float [[TMP4671]], [[TMP4672]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6099]], label [[IF_THEN6101:%.*]], label [[IF_END6102:%.*]]
|
|
// SIMD-ONLY0: if.then6101:
|
|
// SIMD-ONLY0-NEXT: [[TMP4673:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4673]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6102]]
|
|
// SIMD-ONLY0: if.end6102:
|
|
// SIMD-ONLY0-NEXT: [[TMP4674:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4674]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4675:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4676:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6103:%.*]] = fcmp olt float [[TMP4675]], [[TMP4676]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6103]], label [[IF_THEN6105:%.*]], label [[IF_END6106:%.*]]
|
|
// SIMD-ONLY0: if.then6105:
|
|
// SIMD-ONLY0-NEXT: [[TMP4677:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4677]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6106]]
|
|
// SIMD-ONLY0: if.end6106:
|
|
// SIMD-ONLY0-NEXT: [[TMP4678:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4678]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4679:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4680:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6107:%.*]] = fcmp oeq float [[TMP4679]], [[TMP4680]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6107]], label [[IF_THEN6109:%.*]], label [[IF_END6110:%.*]]
|
|
// SIMD-ONLY0: if.then6109:
|
|
// SIMD-ONLY0-NEXT: [[TMP4681:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4681]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6110]]
|
|
// SIMD-ONLY0: if.end6110:
|
|
// SIMD-ONLY0-NEXT: [[TMP4682:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4682]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4683:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4684:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6111:%.*]] = fcmp oeq float [[TMP4683]], [[TMP4684]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6111]], label [[IF_THEN6113:%.*]], label [[IF_END6114:%.*]]
|
|
// SIMD-ONLY0: if.then6113:
|
|
// SIMD-ONLY0-NEXT: [[TMP4685:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4685]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6114]]
|
|
// SIMD-ONLY0: if.end6114:
|
|
// SIMD-ONLY0-NEXT: [[TMP4686:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4687:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6115:%.*]] = fcmp ogt float [[TMP4686]], [[TMP4687]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6115]], label [[IF_THEN6117:%.*]], label [[IF_END6118:%.*]]
|
|
// SIMD-ONLY0: if.then6117:
|
|
// SIMD-ONLY0-NEXT: [[TMP4688:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4688]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6118]]
|
|
// SIMD-ONLY0: if.end6118:
|
|
// SIMD-ONLY0-NEXT: [[TMP4689:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4689]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4690:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4691:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6119:%.*]] = fcmp ogt float [[TMP4690]], [[TMP4691]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6119]], label [[IF_THEN6121:%.*]], label [[IF_END6122:%.*]]
|
|
// SIMD-ONLY0: if.then6121:
|
|
// SIMD-ONLY0-NEXT: [[TMP4692:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4692]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6122]]
|
|
// SIMD-ONLY0: if.end6122:
|
|
// SIMD-ONLY0-NEXT: [[TMP4693:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4693]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4694:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4695:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6123:%.*]] = fcmp olt float [[TMP4694]], [[TMP4695]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6123]], label [[IF_THEN6125:%.*]], label [[IF_END6126:%.*]]
|
|
// SIMD-ONLY0: if.then6125:
|
|
// SIMD-ONLY0-NEXT: [[TMP4696:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4696]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6126]]
|
|
// SIMD-ONLY0: if.end6126:
|
|
// SIMD-ONLY0-NEXT: [[TMP4697:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4697]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4698:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4699:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6127:%.*]] = fcmp olt float [[TMP4698]], [[TMP4699]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6127]], label [[IF_THEN6129:%.*]], label [[IF_END6130:%.*]]
|
|
// SIMD-ONLY0: if.then6129:
|
|
// SIMD-ONLY0-NEXT: [[TMP4700:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4700]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6130]]
|
|
// SIMD-ONLY0: if.end6130:
|
|
// SIMD-ONLY0-NEXT: [[TMP4701:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4701]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4702:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4703:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6131:%.*]] = fcmp oeq float [[TMP4702]], [[TMP4703]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6131]], label [[IF_THEN6133:%.*]], label [[IF_END6134:%.*]]
|
|
// SIMD-ONLY0: if.then6133:
|
|
// SIMD-ONLY0-NEXT: [[TMP4704:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4704]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6134]]
|
|
// SIMD-ONLY0: if.end6134:
|
|
// SIMD-ONLY0-NEXT: [[TMP4705:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4705]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4706:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4707:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6135:%.*]] = fcmp oeq float [[TMP4706]], [[TMP4707]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6135]], label [[IF_THEN6137:%.*]], label [[IF_END6138:%.*]]
|
|
// SIMD-ONLY0: if.then6137:
|
|
// SIMD-ONLY0-NEXT: [[TMP4708:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4708]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6138]]
|
|
// SIMD-ONLY0: if.end6138:
|
|
// SIMD-ONLY0-NEXT: [[TMP4709:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4709]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4710:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4711:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6139:%.*]] = fcmp oeq float [[TMP4710]], [[TMP4711]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6139]], label [[IF_THEN6141:%.*]], label [[IF_ELSE6142:%.*]]
|
|
// SIMD-ONLY0: if.then6141:
|
|
// SIMD-ONLY0-NEXT: [[TMP4712:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4712]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6143:%.*]]
|
|
// SIMD-ONLY0: if.else6142:
|
|
// SIMD-ONLY0-NEXT: [[TMP4713:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4713]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6143]]
|
|
// SIMD-ONLY0: if.end6143:
|
|
// SIMD-ONLY0-NEXT: [[TMP4714:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4715:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6144:%.*]] = fcmp oeq float [[TMP4714]], [[TMP4715]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6144]], label [[IF_THEN6146:%.*]], label [[IF_ELSE6147:%.*]]
|
|
// SIMD-ONLY0: if.then6146:
|
|
// SIMD-ONLY0-NEXT: [[TMP4716:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4716]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6148:%.*]]
|
|
// SIMD-ONLY0: if.else6147:
|
|
// SIMD-ONLY0-NEXT: [[TMP4717:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4717]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6148]]
|
|
// SIMD-ONLY0: if.end6148:
|
|
// SIMD-ONLY0-NEXT: [[TMP4718:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4719:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6149:%.*]] = fcmp oeq float [[TMP4718]], [[TMP4719]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6150:%.*]] = zext i1 [[CMP6149]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6150]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4720:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6151:%.*]] = icmp ne i32 [[TMP4720]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6151]], label [[IF_THEN6152:%.*]], label [[IF_END6153:%.*]]
|
|
// SIMD-ONLY0: if.then6152:
|
|
// SIMD-ONLY0-NEXT: [[TMP4721:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4721]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6153]]
|
|
// SIMD-ONLY0: if.end6153:
|
|
// SIMD-ONLY0-NEXT: [[TMP4722:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4723:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6154:%.*]] = fcmp oeq float [[TMP4722]], [[TMP4723]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6155:%.*]] = zext i1 [[CMP6154]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6155]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4724:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6156:%.*]] = icmp ne i32 [[TMP4724]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6156]], label [[IF_THEN6157:%.*]], label [[IF_END6158:%.*]]
|
|
// SIMD-ONLY0: if.then6157:
|
|
// SIMD-ONLY0-NEXT: [[TMP4725:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4725]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6158]]
|
|
// SIMD-ONLY0: if.end6158:
|
|
// SIMD-ONLY0-NEXT: [[TMP4726:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4727:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6159:%.*]] = fcmp oeq float [[TMP4726]], [[TMP4727]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6160:%.*]] = zext i1 [[CMP6159]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6160]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4728:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6161:%.*]] = icmp ne i32 [[TMP4728]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6161]], label [[IF_THEN6162:%.*]], label [[IF_ELSE6163:%.*]]
|
|
// SIMD-ONLY0: if.then6162:
|
|
// SIMD-ONLY0-NEXT: [[TMP4729:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4729]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6164:%.*]]
|
|
// SIMD-ONLY0: if.else6163:
|
|
// SIMD-ONLY0-NEXT: [[TMP4730:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4730]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6164]]
|
|
// SIMD-ONLY0: if.end6164:
|
|
// SIMD-ONLY0-NEXT: [[TMP4731:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4732:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6165:%.*]] = fcmp oeq float [[TMP4731]], [[TMP4732]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6166:%.*]] = zext i1 [[CMP6165]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6166]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4733:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6167:%.*]] = icmp ne i32 [[TMP4733]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6167]], label [[IF_THEN6168:%.*]], label [[IF_ELSE6169:%.*]]
|
|
// SIMD-ONLY0: if.then6168:
|
|
// SIMD-ONLY0-NEXT: [[TMP4734:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4734]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6170:%.*]]
|
|
// SIMD-ONLY0: if.else6169:
|
|
// SIMD-ONLY0-NEXT: [[TMP4735:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4735]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6170]]
|
|
// SIMD-ONLY0: if.end6170:
|
|
// SIMD-ONLY0-NEXT: [[TMP4736:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4736]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4737:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4738:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6171:%.*]] = fcmp ogt float [[TMP4737]], [[TMP4738]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6171]], label [[IF_THEN6173:%.*]], label [[IF_END6174:%.*]]
|
|
// SIMD-ONLY0: if.then6173:
|
|
// SIMD-ONLY0-NEXT: [[TMP4739:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4739]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6174]]
|
|
// SIMD-ONLY0: if.end6174:
|
|
// SIMD-ONLY0-NEXT: [[TMP4740:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4740]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4741:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4742:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6175:%.*]] = fcmp ogt float [[TMP4741]], [[TMP4742]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6175]], label [[IF_THEN6177:%.*]], label [[IF_END6178:%.*]]
|
|
// SIMD-ONLY0: if.then6177:
|
|
// SIMD-ONLY0-NEXT: [[TMP4743:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4743]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6178]]
|
|
// SIMD-ONLY0: if.end6178:
|
|
// SIMD-ONLY0-NEXT: [[TMP4744:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4744]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4745:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4746:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6179:%.*]] = fcmp olt float [[TMP4745]], [[TMP4746]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6179]], label [[IF_THEN6181:%.*]], label [[IF_END6182:%.*]]
|
|
// SIMD-ONLY0: if.then6181:
|
|
// SIMD-ONLY0-NEXT: [[TMP4747:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4747]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6182]]
|
|
// SIMD-ONLY0: if.end6182:
|
|
// SIMD-ONLY0-NEXT: [[TMP4748:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4748]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4749:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4750:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6183:%.*]] = fcmp olt float [[TMP4749]], [[TMP4750]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6183]], label [[IF_THEN6185:%.*]], label [[IF_END6186:%.*]]
|
|
// SIMD-ONLY0: if.then6185:
|
|
// SIMD-ONLY0-NEXT: [[TMP4751:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4751]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6186]]
|
|
// SIMD-ONLY0: if.end6186:
|
|
// SIMD-ONLY0-NEXT: [[TMP4752:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4752]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4753:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4754:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6187:%.*]] = fcmp oeq float [[TMP4753]], [[TMP4754]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6187]], label [[IF_THEN6189:%.*]], label [[IF_END6190:%.*]]
|
|
// SIMD-ONLY0: if.then6189:
|
|
// SIMD-ONLY0-NEXT: [[TMP4755:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4755]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6190]]
|
|
// SIMD-ONLY0: if.end6190:
|
|
// SIMD-ONLY0-NEXT: [[TMP4756:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4756]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4757:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4758:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6191:%.*]] = fcmp oeq float [[TMP4757]], [[TMP4758]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6191]], label [[IF_THEN6193:%.*]], label [[IF_END6194:%.*]]
|
|
// SIMD-ONLY0: if.then6193:
|
|
// SIMD-ONLY0-NEXT: [[TMP4759:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4759]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6194]]
|
|
// SIMD-ONLY0: if.end6194:
|
|
// SIMD-ONLY0-NEXT: [[TMP4760:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4761:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6195:%.*]] = fcmp ogt float [[TMP4760]], [[TMP4761]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6195]], label [[IF_THEN6197:%.*]], label [[IF_END6198:%.*]]
|
|
// SIMD-ONLY0: if.then6197:
|
|
// SIMD-ONLY0-NEXT: [[TMP4762:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4762]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6198]]
|
|
// SIMD-ONLY0: if.end6198:
|
|
// SIMD-ONLY0-NEXT: [[TMP4763:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4763]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4764:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4765:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6199:%.*]] = fcmp ogt float [[TMP4764]], [[TMP4765]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6199]], label [[IF_THEN6201:%.*]], label [[IF_END6202:%.*]]
|
|
// SIMD-ONLY0: if.then6201:
|
|
// SIMD-ONLY0-NEXT: [[TMP4766:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4766]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6202]]
|
|
// SIMD-ONLY0: if.end6202:
|
|
// SIMD-ONLY0-NEXT: [[TMP4767:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4767]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4768:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4769:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6203:%.*]] = fcmp olt float [[TMP4768]], [[TMP4769]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6203]], label [[IF_THEN6205:%.*]], label [[IF_END6206:%.*]]
|
|
// SIMD-ONLY0: if.then6205:
|
|
// SIMD-ONLY0-NEXT: [[TMP4770:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4770]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6206]]
|
|
// SIMD-ONLY0: if.end6206:
|
|
// SIMD-ONLY0-NEXT: [[TMP4771:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4771]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4772:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4773:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6207:%.*]] = fcmp olt float [[TMP4772]], [[TMP4773]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6207]], label [[IF_THEN6209:%.*]], label [[IF_END6210:%.*]]
|
|
// SIMD-ONLY0: if.then6209:
|
|
// SIMD-ONLY0-NEXT: [[TMP4774:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4774]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6210]]
|
|
// SIMD-ONLY0: if.end6210:
|
|
// SIMD-ONLY0-NEXT: [[TMP4775:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4775]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4776:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4777:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6211:%.*]] = fcmp oeq float [[TMP4776]], [[TMP4777]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6211]], label [[IF_THEN6213:%.*]], label [[IF_END6214:%.*]]
|
|
// SIMD-ONLY0: if.then6213:
|
|
// SIMD-ONLY0-NEXT: [[TMP4778:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4778]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6214]]
|
|
// SIMD-ONLY0: if.end6214:
|
|
// SIMD-ONLY0-NEXT: [[TMP4779:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4779]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4780:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4781:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6215:%.*]] = fcmp oeq float [[TMP4780]], [[TMP4781]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6215]], label [[IF_THEN6217:%.*]], label [[IF_END6218:%.*]]
|
|
// SIMD-ONLY0: if.then6217:
|
|
// SIMD-ONLY0-NEXT: [[TMP4782:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4782]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6218]]
|
|
// SIMD-ONLY0: if.end6218:
|
|
// SIMD-ONLY0-NEXT: [[TMP4783:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4783]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4784:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4785:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6219:%.*]] = fcmp oeq float [[TMP4784]], [[TMP4785]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6219]], label [[IF_THEN6221:%.*]], label [[IF_ELSE6222:%.*]]
|
|
// SIMD-ONLY0: if.then6221:
|
|
// SIMD-ONLY0-NEXT: [[TMP4786:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4786]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6223:%.*]]
|
|
// SIMD-ONLY0: if.else6222:
|
|
// SIMD-ONLY0-NEXT: [[TMP4787:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4787]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6223]]
|
|
// SIMD-ONLY0: if.end6223:
|
|
// SIMD-ONLY0-NEXT: [[TMP4788:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4789:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6224:%.*]] = fcmp oeq float [[TMP4788]], [[TMP4789]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6224]], label [[IF_THEN6226:%.*]], label [[IF_ELSE6227:%.*]]
|
|
// SIMD-ONLY0: if.then6226:
|
|
// SIMD-ONLY0-NEXT: [[TMP4790:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4790]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6228:%.*]]
|
|
// SIMD-ONLY0: if.else6227:
|
|
// SIMD-ONLY0-NEXT: [[TMP4791:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4791]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6228]]
|
|
// SIMD-ONLY0: if.end6228:
|
|
// SIMD-ONLY0-NEXT: [[TMP4792:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4793:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6229:%.*]] = fcmp oeq float [[TMP4792]], [[TMP4793]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6230:%.*]] = zext i1 [[CMP6229]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6230]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4794:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6231:%.*]] = icmp ne i32 [[TMP4794]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6231]], label [[IF_THEN6232:%.*]], label [[IF_END6233:%.*]]
|
|
// SIMD-ONLY0: if.then6232:
|
|
// SIMD-ONLY0-NEXT: [[TMP4795:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4795]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6233]]
|
|
// SIMD-ONLY0: if.end6233:
|
|
// SIMD-ONLY0-NEXT: [[TMP4796:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4797:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6234:%.*]] = fcmp oeq float [[TMP4796]], [[TMP4797]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6235:%.*]] = zext i1 [[CMP6234]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6235]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4798:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6236:%.*]] = icmp ne i32 [[TMP4798]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6236]], label [[IF_THEN6237:%.*]], label [[IF_END6238:%.*]]
|
|
// SIMD-ONLY0: if.then6237:
|
|
// SIMD-ONLY0-NEXT: [[TMP4799:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4799]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6238]]
|
|
// SIMD-ONLY0: if.end6238:
|
|
// SIMD-ONLY0-NEXT: [[TMP4800:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4801:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6239:%.*]] = fcmp oeq float [[TMP4800]], [[TMP4801]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6240:%.*]] = zext i1 [[CMP6239]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6240]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4802:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6241:%.*]] = icmp ne i32 [[TMP4802]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6241]], label [[IF_THEN6242:%.*]], label [[IF_ELSE6243:%.*]]
|
|
// SIMD-ONLY0: if.then6242:
|
|
// SIMD-ONLY0-NEXT: [[TMP4803:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4803]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6244:%.*]]
|
|
// SIMD-ONLY0: if.else6243:
|
|
// SIMD-ONLY0-NEXT: [[TMP4804:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4804]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6244]]
|
|
// SIMD-ONLY0: if.end6244:
|
|
// SIMD-ONLY0-NEXT: [[TMP4805:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4806:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6245:%.*]] = fcmp oeq float [[TMP4805]], [[TMP4806]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6246:%.*]] = zext i1 [[CMP6245]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6246]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4807:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6247:%.*]] = icmp ne i32 [[TMP4807]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6247]], label [[IF_THEN6248:%.*]], label [[IF_ELSE6249:%.*]]
|
|
// SIMD-ONLY0: if.then6248:
|
|
// SIMD-ONLY0-NEXT: [[TMP4808:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4808]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6250:%.*]]
|
|
// SIMD-ONLY0: if.else6249:
|
|
// SIMD-ONLY0-NEXT: [[TMP4809:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4809]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6250]]
|
|
// SIMD-ONLY0: if.end6250:
|
|
// SIMD-ONLY0-NEXT: [[TMP4810:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4810]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4811:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4812:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6251:%.*]] = fcmp ogt float [[TMP4811]], [[TMP4812]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6251]], label [[IF_THEN6253:%.*]], label [[IF_END6254:%.*]]
|
|
// SIMD-ONLY0: if.then6253:
|
|
// SIMD-ONLY0-NEXT: [[TMP4813:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4813]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6254]]
|
|
// SIMD-ONLY0: if.end6254:
|
|
// SIMD-ONLY0-NEXT: [[TMP4814:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4814]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4815:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4816:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6255:%.*]] = fcmp ogt float [[TMP4815]], [[TMP4816]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6255]], label [[IF_THEN6257:%.*]], label [[IF_END6258:%.*]]
|
|
// SIMD-ONLY0: if.then6257:
|
|
// SIMD-ONLY0-NEXT: [[TMP4817:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4817]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6258]]
|
|
// SIMD-ONLY0: if.end6258:
|
|
// SIMD-ONLY0-NEXT: [[TMP4818:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4818]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4819:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4820:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6259:%.*]] = fcmp olt float [[TMP4819]], [[TMP4820]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6259]], label [[IF_THEN6261:%.*]], label [[IF_END6262:%.*]]
|
|
// SIMD-ONLY0: if.then6261:
|
|
// SIMD-ONLY0-NEXT: [[TMP4821:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4821]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6262]]
|
|
// SIMD-ONLY0: if.end6262:
|
|
// SIMD-ONLY0-NEXT: [[TMP4822:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4822]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4823:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4824:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6263:%.*]] = fcmp olt float [[TMP4823]], [[TMP4824]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6263]], label [[IF_THEN6265:%.*]], label [[IF_END6266:%.*]]
|
|
// SIMD-ONLY0: if.then6265:
|
|
// SIMD-ONLY0-NEXT: [[TMP4825:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4825]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6266]]
|
|
// SIMD-ONLY0: if.end6266:
|
|
// SIMD-ONLY0-NEXT: [[TMP4826:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4826]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4827:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4828:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6267:%.*]] = fcmp oeq float [[TMP4827]], [[TMP4828]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6267]], label [[IF_THEN6269:%.*]], label [[IF_END6270:%.*]]
|
|
// SIMD-ONLY0: if.then6269:
|
|
// SIMD-ONLY0-NEXT: [[TMP4829:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4829]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6270]]
|
|
// SIMD-ONLY0: if.end6270:
|
|
// SIMD-ONLY0-NEXT: [[TMP4830:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4830]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4831:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4832:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6271:%.*]] = fcmp oeq float [[TMP4831]], [[TMP4832]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6271]], label [[IF_THEN6273:%.*]], label [[IF_END6274:%.*]]
|
|
// SIMD-ONLY0: if.then6273:
|
|
// SIMD-ONLY0-NEXT: [[TMP4833:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4833]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6274]]
|
|
// SIMD-ONLY0: if.end6274:
|
|
// SIMD-ONLY0-NEXT: [[TMP4834:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4835:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6275:%.*]] = fcmp ogt float [[TMP4834]], [[TMP4835]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6275]], label [[IF_THEN6277:%.*]], label [[IF_END6278:%.*]]
|
|
// SIMD-ONLY0: if.then6277:
|
|
// SIMD-ONLY0-NEXT: [[TMP4836:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4836]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6278]]
|
|
// SIMD-ONLY0: if.end6278:
|
|
// SIMD-ONLY0-NEXT: [[TMP4837:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4837]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4838:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4839:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6279:%.*]] = fcmp ogt float [[TMP4838]], [[TMP4839]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6279]], label [[IF_THEN6281:%.*]], label [[IF_END6282:%.*]]
|
|
// SIMD-ONLY0: if.then6281:
|
|
// SIMD-ONLY0-NEXT: [[TMP4840:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4840]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6282]]
|
|
// SIMD-ONLY0: if.end6282:
|
|
// SIMD-ONLY0-NEXT: [[TMP4841:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4841]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4842:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4843:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6283:%.*]] = fcmp olt float [[TMP4842]], [[TMP4843]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6283]], label [[IF_THEN6285:%.*]], label [[IF_END6286:%.*]]
|
|
// SIMD-ONLY0: if.then6285:
|
|
// SIMD-ONLY0-NEXT: [[TMP4844:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4844]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6286]]
|
|
// SIMD-ONLY0: if.end6286:
|
|
// SIMD-ONLY0-NEXT: [[TMP4845:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4845]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4846:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4847:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6287:%.*]] = fcmp olt float [[TMP4846]], [[TMP4847]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6287]], label [[IF_THEN6289:%.*]], label [[IF_END6290:%.*]]
|
|
// SIMD-ONLY0: if.then6289:
|
|
// SIMD-ONLY0-NEXT: [[TMP4848:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4848]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6290]]
|
|
// SIMD-ONLY0: if.end6290:
|
|
// SIMD-ONLY0-NEXT: [[TMP4849:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4849]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4850:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4851:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6291:%.*]] = fcmp oeq float [[TMP4850]], [[TMP4851]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6291]], label [[IF_THEN6293:%.*]], label [[IF_END6294:%.*]]
|
|
// SIMD-ONLY0: if.then6293:
|
|
// SIMD-ONLY0-NEXT: [[TMP4852:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4852]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6294]]
|
|
// SIMD-ONLY0: if.end6294:
|
|
// SIMD-ONLY0-NEXT: [[TMP4853:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4853]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4854:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4855:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6295:%.*]] = fcmp oeq float [[TMP4854]], [[TMP4855]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6295]], label [[IF_THEN6297:%.*]], label [[IF_END6298:%.*]]
|
|
// SIMD-ONLY0: if.then6297:
|
|
// SIMD-ONLY0-NEXT: [[TMP4856:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4856]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6298]]
|
|
// SIMD-ONLY0: if.end6298:
|
|
// SIMD-ONLY0-NEXT: [[TMP4857:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4857]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4858:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4859:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6299:%.*]] = fcmp oeq float [[TMP4858]], [[TMP4859]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6299]], label [[IF_THEN6301:%.*]], label [[IF_ELSE6302:%.*]]
|
|
// SIMD-ONLY0: if.then6301:
|
|
// SIMD-ONLY0-NEXT: [[TMP4860:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4860]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6303:%.*]]
|
|
// SIMD-ONLY0: if.else6302:
|
|
// SIMD-ONLY0-NEXT: [[TMP4861:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4861]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6303]]
|
|
// SIMD-ONLY0: if.end6303:
|
|
// SIMD-ONLY0-NEXT: [[TMP4862:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4863:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6304:%.*]] = fcmp oeq float [[TMP4862]], [[TMP4863]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6304]], label [[IF_THEN6306:%.*]], label [[IF_ELSE6307:%.*]]
|
|
// SIMD-ONLY0: if.then6306:
|
|
// SIMD-ONLY0-NEXT: [[TMP4864:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4864]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6308:%.*]]
|
|
// SIMD-ONLY0: if.else6307:
|
|
// SIMD-ONLY0-NEXT: [[TMP4865:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4865]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6308]]
|
|
// SIMD-ONLY0: if.end6308:
|
|
// SIMD-ONLY0-NEXT: [[TMP4866:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4867:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6309:%.*]] = fcmp oeq float [[TMP4866]], [[TMP4867]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6310:%.*]] = zext i1 [[CMP6309]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6310]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4868:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6311:%.*]] = icmp ne i32 [[TMP4868]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6311]], label [[IF_THEN6312:%.*]], label [[IF_END6313:%.*]]
|
|
// SIMD-ONLY0: if.then6312:
|
|
// SIMD-ONLY0-NEXT: [[TMP4869:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4869]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6313]]
|
|
// SIMD-ONLY0: if.end6313:
|
|
// SIMD-ONLY0-NEXT: [[TMP4870:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4871:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6314:%.*]] = fcmp oeq float [[TMP4870]], [[TMP4871]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6315:%.*]] = zext i1 [[CMP6314]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6315]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4872:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6316:%.*]] = icmp ne i32 [[TMP4872]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6316]], label [[IF_THEN6317:%.*]], label [[IF_END6318:%.*]]
|
|
// SIMD-ONLY0: if.then6317:
|
|
// SIMD-ONLY0-NEXT: [[TMP4873:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4873]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6318]]
|
|
// SIMD-ONLY0: if.end6318:
|
|
// SIMD-ONLY0-NEXT: [[TMP4874:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4875:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6319:%.*]] = fcmp oeq float [[TMP4874]], [[TMP4875]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6320:%.*]] = zext i1 [[CMP6319]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6320]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4876:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6321:%.*]] = icmp ne i32 [[TMP4876]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6321]], label [[IF_THEN6322:%.*]], label [[IF_ELSE6323:%.*]]
|
|
// SIMD-ONLY0: if.then6322:
|
|
// SIMD-ONLY0-NEXT: [[TMP4877:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4877]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6324:%.*]]
|
|
// SIMD-ONLY0: if.else6323:
|
|
// SIMD-ONLY0-NEXT: [[TMP4878:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4878]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6324]]
|
|
// SIMD-ONLY0: if.end6324:
|
|
// SIMD-ONLY0-NEXT: [[TMP4879:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4880:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6325:%.*]] = fcmp oeq float [[TMP4879]], [[TMP4880]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6326:%.*]] = zext i1 [[CMP6325]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6326]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4881:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6327:%.*]] = icmp ne i32 [[TMP4881]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6327]], label [[IF_THEN6328:%.*]], label [[IF_ELSE6329:%.*]]
|
|
// SIMD-ONLY0: if.then6328:
|
|
// SIMD-ONLY0-NEXT: [[TMP4882:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4882]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6330:%.*]]
|
|
// SIMD-ONLY0: if.else6329:
|
|
// SIMD-ONLY0-NEXT: [[TMP4883:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP4883]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6330]]
|
|
// SIMD-ONLY0: if.end6330:
|
|
// SIMD-ONLY0-NEXT: [[TMP4884:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4884]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4885:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4886:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6331:%.*]] = fcmp ogt double [[TMP4885]], [[TMP4886]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6331]], label [[IF_THEN6333:%.*]], label [[IF_END6334:%.*]]
|
|
// SIMD-ONLY0: if.then6333:
|
|
// SIMD-ONLY0-NEXT: [[TMP4887:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4887]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6334]]
|
|
// SIMD-ONLY0: if.end6334:
|
|
// SIMD-ONLY0-NEXT: [[TMP4888:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4888]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4889:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4890:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6335:%.*]] = fcmp ogt double [[TMP4889]], [[TMP4890]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6335]], label [[IF_THEN6337:%.*]], label [[IF_END6338:%.*]]
|
|
// SIMD-ONLY0: if.then6337:
|
|
// SIMD-ONLY0-NEXT: [[TMP4891:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4891]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6338]]
|
|
// SIMD-ONLY0: if.end6338:
|
|
// SIMD-ONLY0-NEXT: [[TMP4892:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4892]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4893:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4894:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6339:%.*]] = fcmp olt double [[TMP4893]], [[TMP4894]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6339]], label [[IF_THEN6341:%.*]], label [[IF_END6342:%.*]]
|
|
// SIMD-ONLY0: if.then6341:
|
|
// SIMD-ONLY0-NEXT: [[TMP4895:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4895]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6342]]
|
|
// SIMD-ONLY0: if.end6342:
|
|
// SIMD-ONLY0-NEXT: [[TMP4896:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4896]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4897:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4898:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6343:%.*]] = fcmp olt double [[TMP4897]], [[TMP4898]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6343]], label [[IF_THEN6345:%.*]], label [[IF_END6346:%.*]]
|
|
// SIMD-ONLY0: if.then6345:
|
|
// SIMD-ONLY0-NEXT: [[TMP4899:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4899]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6346]]
|
|
// SIMD-ONLY0: if.end6346:
|
|
// SIMD-ONLY0-NEXT: [[TMP4900:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4900]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4901:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4902:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6347:%.*]] = fcmp oeq double [[TMP4901]], [[TMP4902]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6347]], label [[IF_THEN6349:%.*]], label [[IF_END6350:%.*]]
|
|
// SIMD-ONLY0: if.then6349:
|
|
// SIMD-ONLY0-NEXT: [[TMP4903:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4903]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6350]]
|
|
// SIMD-ONLY0: if.end6350:
|
|
// SIMD-ONLY0-NEXT: [[TMP4904:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4904]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4905:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4906:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6351:%.*]] = fcmp oeq double [[TMP4905]], [[TMP4906]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6351]], label [[IF_THEN6353:%.*]], label [[IF_END6354:%.*]]
|
|
// SIMD-ONLY0: if.then6353:
|
|
// SIMD-ONLY0-NEXT: [[TMP4907:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4907]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6354]]
|
|
// SIMD-ONLY0: if.end6354:
|
|
// SIMD-ONLY0-NEXT: [[TMP4908:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4909:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6355:%.*]] = fcmp ogt double [[TMP4908]], [[TMP4909]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6355]], label [[IF_THEN6357:%.*]], label [[IF_END6358:%.*]]
|
|
// SIMD-ONLY0: if.then6357:
|
|
// SIMD-ONLY0-NEXT: [[TMP4910:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4910]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6358]]
|
|
// SIMD-ONLY0: if.end6358:
|
|
// SIMD-ONLY0-NEXT: [[TMP4911:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4911]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4912:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4913:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6359:%.*]] = fcmp ogt double [[TMP4912]], [[TMP4913]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6359]], label [[IF_THEN6361:%.*]], label [[IF_END6362:%.*]]
|
|
// SIMD-ONLY0: if.then6361:
|
|
// SIMD-ONLY0-NEXT: [[TMP4914:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4914]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6362]]
|
|
// SIMD-ONLY0: if.end6362:
|
|
// SIMD-ONLY0-NEXT: [[TMP4915:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4915]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4916:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4917:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6363:%.*]] = fcmp olt double [[TMP4916]], [[TMP4917]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6363]], label [[IF_THEN6365:%.*]], label [[IF_END6366:%.*]]
|
|
// SIMD-ONLY0: if.then6365:
|
|
// SIMD-ONLY0-NEXT: [[TMP4918:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4918]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6366]]
|
|
// SIMD-ONLY0: if.end6366:
|
|
// SIMD-ONLY0-NEXT: [[TMP4919:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4919]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4920:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4921:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6367:%.*]] = fcmp olt double [[TMP4920]], [[TMP4921]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6367]], label [[IF_THEN6369:%.*]], label [[IF_END6370:%.*]]
|
|
// SIMD-ONLY0: if.then6369:
|
|
// SIMD-ONLY0-NEXT: [[TMP4922:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4922]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6370]]
|
|
// SIMD-ONLY0: if.end6370:
|
|
// SIMD-ONLY0-NEXT: [[TMP4923:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4923]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4924:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4925:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6371:%.*]] = fcmp oeq double [[TMP4924]], [[TMP4925]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6371]], label [[IF_THEN6373:%.*]], label [[IF_END6374:%.*]]
|
|
// SIMD-ONLY0: if.then6373:
|
|
// SIMD-ONLY0-NEXT: [[TMP4926:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4926]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6374]]
|
|
// SIMD-ONLY0: if.end6374:
|
|
// SIMD-ONLY0-NEXT: [[TMP4927:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4927]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4928:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4929:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6375:%.*]] = fcmp oeq double [[TMP4928]], [[TMP4929]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6375]], label [[IF_THEN6377:%.*]], label [[IF_END6378:%.*]]
|
|
// SIMD-ONLY0: if.then6377:
|
|
// SIMD-ONLY0-NEXT: [[TMP4930:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4930]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6378]]
|
|
// SIMD-ONLY0: if.end6378:
|
|
// SIMD-ONLY0-NEXT: [[TMP4931:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4931]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4932:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4933:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6379:%.*]] = fcmp oeq double [[TMP4932]], [[TMP4933]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6379]], label [[IF_THEN6381:%.*]], label [[IF_ELSE6382:%.*]]
|
|
// SIMD-ONLY0: if.then6381:
|
|
// SIMD-ONLY0-NEXT: [[TMP4934:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4934]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6383:%.*]]
|
|
// SIMD-ONLY0: if.else6382:
|
|
// SIMD-ONLY0-NEXT: [[TMP4935:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4935]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6383]]
|
|
// SIMD-ONLY0: if.end6383:
|
|
// SIMD-ONLY0-NEXT: [[TMP4936:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4937:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6384:%.*]] = fcmp oeq double [[TMP4936]], [[TMP4937]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6384]], label [[IF_THEN6386:%.*]], label [[IF_ELSE6387:%.*]]
|
|
// SIMD-ONLY0: if.then6386:
|
|
// SIMD-ONLY0-NEXT: [[TMP4938:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4938]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6388:%.*]]
|
|
// SIMD-ONLY0: if.else6387:
|
|
// SIMD-ONLY0-NEXT: [[TMP4939:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4939]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6388]]
|
|
// SIMD-ONLY0: if.end6388:
|
|
// SIMD-ONLY0-NEXT: [[TMP4940:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4941:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6389:%.*]] = fcmp oeq double [[TMP4940]], [[TMP4941]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6390:%.*]] = zext i1 [[CMP6389]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6390]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4942:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6391:%.*]] = icmp ne i32 [[TMP4942]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6391]], label [[IF_THEN6392:%.*]], label [[IF_END6393:%.*]]
|
|
// SIMD-ONLY0: if.then6392:
|
|
// SIMD-ONLY0-NEXT: [[TMP4943:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4943]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6393]]
|
|
// SIMD-ONLY0: if.end6393:
|
|
// SIMD-ONLY0-NEXT: [[TMP4944:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4945:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6394:%.*]] = fcmp oeq double [[TMP4944]], [[TMP4945]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6395:%.*]] = zext i1 [[CMP6394]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6395]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4946:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6396:%.*]] = icmp ne i32 [[TMP4946]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6396]], label [[IF_THEN6397:%.*]], label [[IF_END6398:%.*]]
|
|
// SIMD-ONLY0: if.then6397:
|
|
// SIMD-ONLY0-NEXT: [[TMP4947:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4947]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6398]]
|
|
// SIMD-ONLY0: if.end6398:
|
|
// SIMD-ONLY0-NEXT: [[TMP4948:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4949:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6399:%.*]] = fcmp oeq double [[TMP4948]], [[TMP4949]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6400:%.*]] = zext i1 [[CMP6399]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6400]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4950:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6401:%.*]] = icmp ne i32 [[TMP4950]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6401]], label [[IF_THEN6402:%.*]], label [[IF_ELSE6403:%.*]]
|
|
// SIMD-ONLY0: if.then6402:
|
|
// SIMD-ONLY0-NEXT: [[TMP4951:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4951]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6404:%.*]]
|
|
// SIMD-ONLY0: if.else6403:
|
|
// SIMD-ONLY0-NEXT: [[TMP4952:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4952]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6404]]
|
|
// SIMD-ONLY0: if.end6404:
|
|
// SIMD-ONLY0-NEXT: [[TMP4953:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4954:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6405:%.*]] = fcmp oeq double [[TMP4953]], [[TMP4954]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6406:%.*]] = zext i1 [[CMP6405]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6406]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP4955:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6407:%.*]] = icmp ne i32 [[TMP4955]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6407]], label [[IF_THEN6408:%.*]], label [[IF_ELSE6409:%.*]]
|
|
// SIMD-ONLY0: if.then6408:
|
|
// SIMD-ONLY0-NEXT: [[TMP4956:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4956]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6410:%.*]]
|
|
// SIMD-ONLY0: if.else6409:
|
|
// SIMD-ONLY0-NEXT: [[TMP4957:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4957]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6410]]
|
|
// SIMD-ONLY0: if.end6410:
|
|
// SIMD-ONLY0-NEXT: [[TMP4958:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4958]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4959:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4960:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6411:%.*]] = fcmp ogt double [[TMP4959]], [[TMP4960]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6411]], label [[IF_THEN6413:%.*]], label [[IF_END6414:%.*]]
|
|
// SIMD-ONLY0: if.then6413:
|
|
// SIMD-ONLY0-NEXT: [[TMP4961:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4961]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6414]]
|
|
// SIMD-ONLY0: if.end6414:
|
|
// SIMD-ONLY0-NEXT: [[TMP4962:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4962]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4963:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4964:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6415:%.*]] = fcmp ogt double [[TMP4963]], [[TMP4964]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6415]], label [[IF_THEN6417:%.*]], label [[IF_END6418:%.*]]
|
|
// SIMD-ONLY0: if.then6417:
|
|
// SIMD-ONLY0-NEXT: [[TMP4965:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4965]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6418]]
|
|
// SIMD-ONLY0: if.end6418:
|
|
// SIMD-ONLY0-NEXT: [[TMP4966:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4966]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4967:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4968:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6419:%.*]] = fcmp olt double [[TMP4967]], [[TMP4968]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6419]], label [[IF_THEN6421:%.*]], label [[IF_END6422:%.*]]
|
|
// SIMD-ONLY0: if.then6421:
|
|
// SIMD-ONLY0-NEXT: [[TMP4969:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4969]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6422]]
|
|
// SIMD-ONLY0: if.end6422:
|
|
// SIMD-ONLY0-NEXT: [[TMP4970:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4970]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4971:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4972:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6423:%.*]] = fcmp olt double [[TMP4971]], [[TMP4972]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6423]], label [[IF_THEN6425:%.*]], label [[IF_END6426:%.*]]
|
|
// SIMD-ONLY0: if.then6425:
|
|
// SIMD-ONLY0-NEXT: [[TMP4973:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4973]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6426]]
|
|
// SIMD-ONLY0: if.end6426:
|
|
// SIMD-ONLY0-NEXT: [[TMP4974:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4974]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4975:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4976:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6427:%.*]] = fcmp oeq double [[TMP4975]], [[TMP4976]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6427]], label [[IF_THEN6429:%.*]], label [[IF_END6430:%.*]]
|
|
// SIMD-ONLY0: if.then6429:
|
|
// SIMD-ONLY0-NEXT: [[TMP4977:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4977]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6430]]
|
|
// SIMD-ONLY0: if.end6430:
|
|
// SIMD-ONLY0-NEXT: [[TMP4978:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4978]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4979:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4980:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6431:%.*]] = fcmp oeq double [[TMP4979]], [[TMP4980]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6431]], label [[IF_THEN6433:%.*]], label [[IF_END6434:%.*]]
|
|
// SIMD-ONLY0: if.then6433:
|
|
// SIMD-ONLY0-NEXT: [[TMP4981:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4981]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6434]]
|
|
// SIMD-ONLY0: if.end6434:
|
|
// SIMD-ONLY0-NEXT: [[TMP4982:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4983:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6435:%.*]] = fcmp ogt double [[TMP4982]], [[TMP4983]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6435]], label [[IF_THEN6437:%.*]], label [[IF_END6438:%.*]]
|
|
// SIMD-ONLY0: if.then6437:
|
|
// SIMD-ONLY0-NEXT: [[TMP4984:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4984]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6438]]
|
|
// SIMD-ONLY0: if.end6438:
|
|
// SIMD-ONLY0-NEXT: [[TMP4985:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4985]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4986:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4987:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6439:%.*]] = fcmp ogt double [[TMP4986]], [[TMP4987]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6439]], label [[IF_THEN6441:%.*]], label [[IF_END6442:%.*]]
|
|
// SIMD-ONLY0: if.then6441:
|
|
// SIMD-ONLY0-NEXT: [[TMP4988:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4988]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6442]]
|
|
// SIMD-ONLY0: if.end6442:
|
|
// SIMD-ONLY0-NEXT: [[TMP4989:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4989]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4990:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4991:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6443:%.*]] = fcmp olt double [[TMP4990]], [[TMP4991]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6443]], label [[IF_THEN6445:%.*]], label [[IF_END6446:%.*]]
|
|
// SIMD-ONLY0: if.then6445:
|
|
// SIMD-ONLY0-NEXT: [[TMP4992:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4992]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6446]]
|
|
// SIMD-ONLY0: if.end6446:
|
|
// SIMD-ONLY0-NEXT: [[TMP4993:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4993]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4994:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4995:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6447:%.*]] = fcmp olt double [[TMP4994]], [[TMP4995]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6447]], label [[IF_THEN6449:%.*]], label [[IF_END6450:%.*]]
|
|
// SIMD-ONLY0: if.then6449:
|
|
// SIMD-ONLY0-NEXT: [[TMP4996:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4996]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6450]]
|
|
// SIMD-ONLY0: if.end6450:
|
|
// SIMD-ONLY0-NEXT: [[TMP4997:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP4997]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4998:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP4999:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6451:%.*]] = fcmp oeq double [[TMP4998]], [[TMP4999]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6451]], label [[IF_THEN6453:%.*]], label [[IF_END6454:%.*]]
|
|
// SIMD-ONLY0: if.then6453:
|
|
// SIMD-ONLY0-NEXT: [[TMP5000:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5000]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6454]]
|
|
// SIMD-ONLY0: if.end6454:
|
|
// SIMD-ONLY0-NEXT: [[TMP5001:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5001]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5002:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5003:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6455:%.*]] = fcmp oeq double [[TMP5002]], [[TMP5003]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6455]], label [[IF_THEN6457:%.*]], label [[IF_END6458:%.*]]
|
|
// SIMD-ONLY0: if.then6457:
|
|
// SIMD-ONLY0-NEXT: [[TMP5004:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5004]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6458]]
|
|
// SIMD-ONLY0: if.end6458:
|
|
// SIMD-ONLY0-NEXT: [[TMP5005:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5005]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5006:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5007:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6459:%.*]] = fcmp oeq double [[TMP5006]], [[TMP5007]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6459]], label [[IF_THEN6461:%.*]], label [[IF_ELSE6462:%.*]]
|
|
// SIMD-ONLY0: if.then6461:
|
|
// SIMD-ONLY0-NEXT: [[TMP5008:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5008]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6463:%.*]]
|
|
// SIMD-ONLY0: if.else6462:
|
|
// SIMD-ONLY0-NEXT: [[TMP5009:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5009]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6463]]
|
|
// SIMD-ONLY0: if.end6463:
|
|
// SIMD-ONLY0-NEXT: [[TMP5010:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5011:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6464:%.*]] = fcmp oeq double [[TMP5010]], [[TMP5011]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6464]], label [[IF_THEN6466:%.*]], label [[IF_ELSE6467:%.*]]
|
|
// SIMD-ONLY0: if.then6466:
|
|
// SIMD-ONLY0-NEXT: [[TMP5012:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5012]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6468:%.*]]
|
|
// SIMD-ONLY0: if.else6467:
|
|
// SIMD-ONLY0-NEXT: [[TMP5013:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5013]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6468]]
|
|
// SIMD-ONLY0: if.end6468:
|
|
// SIMD-ONLY0-NEXT: [[TMP5014:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5015:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6469:%.*]] = fcmp oeq double [[TMP5014]], [[TMP5015]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6470:%.*]] = zext i1 [[CMP6469]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6470]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5016:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6471:%.*]] = icmp ne i32 [[TMP5016]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6471]], label [[IF_THEN6472:%.*]], label [[IF_END6473:%.*]]
|
|
// SIMD-ONLY0: if.then6472:
|
|
// SIMD-ONLY0-NEXT: [[TMP5017:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5017]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6473]]
|
|
// SIMD-ONLY0: if.end6473:
|
|
// SIMD-ONLY0-NEXT: [[TMP5018:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5019:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6474:%.*]] = fcmp oeq double [[TMP5018]], [[TMP5019]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6475:%.*]] = zext i1 [[CMP6474]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6475]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5020:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6476:%.*]] = icmp ne i32 [[TMP5020]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6476]], label [[IF_THEN6477:%.*]], label [[IF_END6478:%.*]]
|
|
// SIMD-ONLY0: if.then6477:
|
|
// SIMD-ONLY0-NEXT: [[TMP5021:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5021]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6478]]
|
|
// SIMD-ONLY0: if.end6478:
|
|
// SIMD-ONLY0-NEXT: [[TMP5022:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5023:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6479:%.*]] = fcmp oeq double [[TMP5022]], [[TMP5023]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6480:%.*]] = zext i1 [[CMP6479]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6480]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5024:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6481:%.*]] = icmp ne i32 [[TMP5024]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6481]], label [[IF_THEN6482:%.*]], label [[IF_ELSE6483:%.*]]
|
|
// SIMD-ONLY0: if.then6482:
|
|
// SIMD-ONLY0-NEXT: [[TMP5025:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5025]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6484:%.*]]
|
|
// SIMD-ONLY0: if.else6483:
|
|
// SIMD-ONLY0-NEXT: [[TMP5026:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5026]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6484]]
|
|
// SIMD-ONLY0: if.end6484:
|
|
// SIMD-ONLY0-NEXT: [[TMP5027:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5028:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6485:%.*]] = fcmp oeq double [[TMP5027]], [[TMP5028]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6486:%.*]] = zext i1 [[CMP6485]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6486]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5029:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6487:%.*]] = icmp ne i32 [[TMP5029]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6487]], label [[IF_THEN6488:%.*]], label [[IF_ELSE6489:%.*]]
|
|
// SIMD-ONLY0: if.then6488:
|
|
// SIMD-ONLY0-NEXT: [[TMP5030:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5030]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6490:%.*]]
|
|
// SIMD-ONLY0: if.else6489:
|
|
// SIMD-ONLY0-NEXT: [[TMP5031:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5031]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6490]]
|
|
// SIMD-ONLY0: if.end6490:
|
|
// SIMD-ONLY0-NEXT: [[TMP5032:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5032]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5033:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5034:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6491:%.*]] = fcmp ogt double [[TMP5033]], [[TMP5034]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6491]], label [[IF_THEN6493:%.*]], label [[IF_END6494:%.*]]
|
|
// SIMD-ONLY0: if.then6493:
|
|
// SIMD-ONLY0-NEXT: [[TMP5035:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5035]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6494]]
|
|
// SIMD-ONLY0: if.end6494:
|
|
// SIMD-ONLY0-NEXT: [[TMP5036:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5036]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5037:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5038:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6495:%.*]] = fcmp ogt double [[TMP5037]], [[TMP5038]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6495]], label [[IF_THEN6497:%.*]], label [[IF_END6498:%.*]]
|
|
// SIMD-ONLY0: if.then6497:
|
|
// SIMD-ONLY0-NEXT: [[TMP5039:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5039]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6498]]
|
|
// SIMD-ONLY0: if.end6498:
|
|
// SIMD-ONLY0-NEXT: [[TMP5040:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5040]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5041:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5042:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6499:%.*]] = fcmp olt double [[TMP5041]], [[TMP5042]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6499]], label [[IF_THEN6501:%.*]], label [[IF_END6502:%.*]]
|
|
// SIMD-ONLY0: if.then6501:
|
|
// SIMD-ONLY0-NEXT: [[TMP5043:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5043]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6502]]
|
|
// SIMD-ONLY0: if.end6502:
|
|
// SIMD-ONLY0-NEXT: [[TMP5044:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5044]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5045:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5046:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6503:%.*]] = fcmp olt double [[TMP5045]], [[TMP5046]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6503]], label [[IF_THEN6505:%.*]], label [[IF_END6506:%.*]]
|
|
// SIMD-ONLY0: if.then6505:
|
|
// SIMD-ONLY0-NEXT: [[TMP5047:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5047]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6506]]
|
|
// SIMD-ONLY0: if.end6506:
|
|
// SIMD-ONLY0-NEXT: [[TMP5048:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5048]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5049:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5050:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6507:%.*]] = fcmp oeq double [[TMP5049]], [[TMP5050]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6507]], label [[IF_THEN6509:%.*]], label [[IF_END6510:%.*]]
|
|
// SIMD-ONLY0: if.then6509:
|
|
// SIMD-ONLY0-NEXT: [[TMP5051:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5051]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6510]]
|
|
// SIMD-ONLY0: if.end6510:
|
|
// SIMD-ONLY0-NEXT: [[TMP5052:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5052]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5053:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5054:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6511:%.*]] = fcmp oeq double [[TMP5053]], [[TMP5054]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6511]], label [[IF_THEN6513:%.*]], label [[IF_END6514:%.*]]
|
|
// SIMD-ONLY0: if.then6513:
|
|
// SIMD-ONLY0-NEXT: [[TMP5055:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5055]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6514]]
|
|
// SIMD-ONLY0: if.end6514:
|
|
// SIMD-ONLY0-NEXT: [[TMP5056:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5057:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6515:%.*]] = fcmp ogt double [[TMP5056]], [[TMP5057]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6515]], label [[IF_THEN6517:%.*]], label [[IF_END6518:%.*]]
|
|
// SIMD-ONLY0: if.then6517:
|
|
// SIMD-ONLY0-NEXT: [[TMP5058:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5058]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6518]]
|
|
// SIMD-ONLY0: if.end6518:
|
|
// SIMD-ONLY0-NEXT: [[TMP5059:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5059]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5060:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5061:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6519:%.*]] = fcmp ogt double [[TMP5060]], [[TMP5061]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6519]], label [[IF_THEN6521:%.*]], label [[IF_END6522:%.*]]
|
|
// SIMD-ONLY0: if.then6521:
|
|
// SIMD-ONLY0-NEXT: [[TMP5062:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5062]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6522]]
|
|
// SIMD-ONLY0: if.end6522:
|
|
// SIMD-ONLY0-NEXT: [[TMP5063:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5063]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5064:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5065:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6523:%.*]] = fcmp olt double [[TMP5064]], [[TMP5065]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6523]], label [[IF_THEN6525:%.*]], label [[IF_END6526:%.*]]
|
|
// SIMD-ONLY0: if.then6525:
|
|
// SIMD-ONLY0-NEXT: [[TMP5066:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5066]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6526]]
|
|
// SIMD-ONLY0: if.end6526:
|
|
// SIMD-ONLY0-NEXT: [[TMP5067:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5067]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5068:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5069:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6527:%.*]] = fcmp olt double [[TMP5068]], [[TMP5069]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6527]], label [[IF_THEN6529:%.*]], label [[IF_END6530:%.*]]
|
|
// SIMD-ONLY0: if.then6529:
|
|
// SIMD-ONLY0-NEXT: [[TMP5070:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5070]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6530]]
|
|
// SIMD-ONLY0: if.end6530:
|
|
// SIMD-ONLY0-NEXT: [[TMP5071:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5071]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5072:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5073:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6531:%.*]] = fcmp oeq double [[TMP5072]], [[TMP5073]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6531]], label [[IF_THEN6533:%.*]], label [[IF_END6534:%.*]]
|
|
// SIMD-ONLY0: if.then6533:
|
|
// SIMD-ONLY0-NEXT: [[TMP5074:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5074]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6534]]
|
|
// SIMD-ONLY0: if.end6534:
|
|
// SIMD-ONLY0-NEXT: [[TMP5075:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5075]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5076:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5077:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6535:%.*]] = fcmp oeq double [[TMP5076]], [[TMP5077]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6535]], label [[IF_THEN6537:%.*]], label [[IF_END6538:%.*]]
|
|
// SIMD-ONLY0: if.then6537:
|
|
// SIMD-ONLY0-NEXT: [[TMP5078:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5078]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6538]]
|
|
// SIMD-ONLY0: if.end6538:
|
|
// SIMD-ONLY0-NEXT: [[TMP5079:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5079]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5080:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5081:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6539:%.*]] = fcmp oeq double [[TMP5080]], [[TMP5081]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6539]], label [[IF_THEN6541:%.*]], label [[IF_ELSE6542:%.*]]
|
|
// SIMD-ONLY0: if.then6541:
|
|
// SIMD-ONLY0-NEXT: [[TMP5082:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5082]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6543:%.*]]
|
|
// SIMD-ONLY0: if.else6542:
|
|
// SIMD-ONLY0-NEXT: [[TMP5083:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5083]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6543]]
|
|
// SIMD-ONLY0: if.end6543:
|
|
// SIMD-ONLY0-NEXT: [[TMP5084:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5085:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6544:%.*]] = fcmp oeq double [[TMP5084]], [[TMP5085]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6544]], label [[IF_THEN6546:%.*]], label [[IF_ELSE6547:%.*]]
|
|
// SIMD-ONLY0: if.then6546:
|
|
// SIMD-ONLY0-NEXT: [[TMP5086:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5086]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6548:%.*]]
|
|
// SIMD-ONLY0: if.else6547:
|
|
// SIMD-ONLY0-NEXT: [[TMP5087:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5087]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6548]]
|
|
// SIMD-ONLY0: if.end6548:
|
|
// SIMD-ONLY0-NEXT: [[TMP5088:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5089:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6549:%.*]] = fcmp oeq double [[TMP5088]], [[TMP5089]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6550:%.*]] = zext i1 [[CMP6549]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6550]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5090:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6551:%.*]] = icmp ne i32 [[TMP5090]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6551]], label [[IF_THEN6552:%.*]], label [[IF_END6553:%.*]]
|
|
// SIMD-ONLY0: if.then6552:
|
|
// SIMD-ONLY0-NEXT: [[TMP5091:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5091]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6553]]
|
|
// SIMD-ONLY0: if.end6553:
|
|
// SIMD-ONLY0-NEXT: [[TMP5092:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5093:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6554:%.*]] = fcmp oeq double [[TMP5092]], [[TMP5093]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6555:%.*]] = zext i1 [[CMP6554]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6555]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5094:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6556:%.*]] = icmp ne i32 [[TMP5094]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6556]], label [[IF_THEN6557:%.*]], label [[IF_END6558:%.*]]
|
|
// SIMD-ONLY0: if.then6557:
|
|
// SIMD-ONLY0-NEXT: [[TMP5095:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5095]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6558]]
|
|
// SIMD-ONLY0: if.end6558:
|
|
// SIMD-ONLY0-NEXT: [[TMP5096:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5097:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6559:%.*]] = fcmp oeq double [[TMP5096]], [[TMP5097]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6560:%.*]] = zext i1 [[CMP6559]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6560]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5098:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6561:%.*]] = icmp ne i32 [[TMP5098]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6561]], label [[IF_THEN6562:%.*]], label [[IF_ELSE6563:%.*]]
|
|
// SIMD-ONLY0: if.then6562:
|
|
// SIMD-ONLY0-NEXT: [[TMP5099:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5099]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6564:%.*]]
|
|
// SIMD-ONLY0: if.else6563:
|
|
// SIMD-ONLY0-NEXT: [[TMP5100:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5100]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6564]]
|
|
// SIMD-ONLY0: if.end6564:
|
|
// SIMD-ONLY0-NEXT: [[TMP5101:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5102:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6565:%.*]] = fcmp oeq double [[TMP5101]], [[TMP5102]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6566:%.*]] = zext i1 [[CMP6565]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6566]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5103:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6567:%.*]] = icmp ne i32 [[TMP5103]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6567]], label [[IF_THEN6568:%.*]], label [[IF_ELSE6569:%.*]]
|
|
// SIMD-ONLY0: if.then6568:
|
|
// SIMD-ONLY0-NEXT: [[TMP5104:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5104]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6570:%.*]]
|
|
// SIMD-ONLY0: if.else6569:
|
|
// SIMD-ONLY0-NEXT: [[TMP5105:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5105]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6570]]
|
|
// SIMD-ONLY0: if.end6570:
|
|
// SIMD-ONLY0-NEXT: [[TMP5106:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5106]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5107:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5108:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6571:%.*]] = fcmp ogt double [[TMP5107]], [[TMP5108]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6571]], label [[IF_THEN6573:%.*]], label [[IF_END6574:%.*]]
|
|
// SIMD-ONLY0: if.then6573:
|
|
// SIMD-ONLY0-NEXT: [[TMP5109:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5109]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6574]]
|
|
// SIMD-ONLY0: if.end6574:
|
|
// SIMD-ONLY0-NEXT: [[TMP5110:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5110]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5111:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5112:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6575:%.*]] = fcmp ogt double [[TMP5111]], [[TMP5112]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6575]], label [[IF_THEN6577:%.*]], label [[IF_END6578:%.*]]
|
|
// SIMD-ONLY0: if.then6577:
|
|
// SIMD-ONLY0-NEXT: [[TMP5113:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5113]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6578]]
|
|
// SIMD-ONLY0: if.end6578:
|
|
// SIMD-ONLY0-NEXT: [[TMP5114:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5114]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5115:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5116:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6579:%.*]] = fcmp olt double [[TMP5115]], [[TMP5116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6579]], label [[IF_THEN6581:%.*]], label [[IF_END6582:%.*]]
|
|
// SIMD-ONLY0: if.then6581:
|
|
// SIMD-ONLY0-NEXT: [[TMP5117:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5117]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6582]]
|
|
// SIMD-ONLY0: if.end6582:
|
|
// SIMD-ONLY0-NEXT: [[TMP5118:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5118]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5119:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5120:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6583:%.*]] = fcmp olt double [[TMP5119]], [[TMP5120]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6583]], label [[IF_THEN6585:%.*]], label [[IF_END6586:%.*]]
|
|
// SIMD-ONLY0: if.then6585:
|
|
// SIMD-ONLY0-NEXT: [[TMP5121:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5121]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6586]]
|
|
// SIMD-ONLY0: if.end6586:
|
|
// SIMD-ONLY0-NEXT: [[TMP5122:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5122]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5123:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5124:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6587:%.*]] = fcmp oeq double [[TMP5123]], [[TMP5124]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6587]], label [[IF_THEN6589:%.*]], label [[IF_END6590:%.*]]
|
|
// SIMD-ONLY0: if.then6589:
|
|
// SIMD-ONLY0-NEXT: [[TMP5125:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5125]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6590]]
|
|
// SIMD-ONLY0: if.end6590:
|
|
// SIMD-ONLY0-NEXT: [[TMP5126:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5126]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5127:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5128:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6591:%.*]] = fcmp oeq double [[TMP5127]], [[TMP5128]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6591]], label [[IF_THEN6593:%.*]], label [[IF_END6594:%.*]]
|
|
// SIMD-ONLY0: if.then6593:
|
|
// SIMD-ONLY0-NEXT: [[TMP5129:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5129]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6594]]
|
|
// SIMD-ONLY0: if.end6594:
|
|
// SIMD-ONLY0-NEXT: [[TMP5130:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5131:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6595:%.*]] = fcmp ogt double [[TMP5130]], [[TMP5131]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6595]], label [[IF_THEN6597:%.*]], label [[IF_END6598:%.*]]
|
|
// SIMD-ONLY0: if.then6597:
|
|
// SIMD-ONLY0-NEXT: [[TMP5132:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5132]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6598]]
|
|
// SIMD-ONLY0: if.end6598:
|
|
// SIMD-ONLY0-NEXT: [[TMP5133:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5133]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5134:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5135:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6599:%.*]] = fcmp ogt double [[TMP5134]], [[TMP5135]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6599]], label [[IF_THEN6601:%.*]], label [[IF_END6602:%.*]]
|
|
// SIMD-ONLY0: if.then6601:
|
|
// SIMD-ONLY0-NEXT: [[TMP5136:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5136]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6602]]
|
|
// SIMD-ONLY0: if.end6602:
|
|
// SIMD-ONLY0-NEXT: [[TMP5137:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5137]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5138:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5139:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6603:%.*]] = fcmp olt double [[TMP5138]], [[TMP5139]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6603]], label [[IF_THEN6605:%.*]], label [[IF_END6606:%.*]]
|
|
// SIMD-ONLY0: if.then6605:
|
|
// SIMD-ONLY0-NEXT: [[TMP5140:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5140]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6606]]
|
|
// SIMD-ONLY0: if.end6606:
|
|
// SIMD-ONLY0-NEXT: [[TMP5141:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5141]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5142:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5143:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6607:%.*]] = fcmp olt double [[TMP5142]], [[TMP5143]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6607]], label [[IF_THEN6609:%.*]], label [[IF_END6610:%.*]]
|
|
// SIMD-ONLY0: if.then6609:
|
|
// SIMD-ONLY0-NEXT: [[TMP5144:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5144]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6610]]
|
|
// SIMD-ONLY0: if.end6610:
|
|
// SIMD-ONLY0-NEXT: [[TMP5145:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5145]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5146:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5147:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6611:%.*]] = fcmp oeq double [[TMP5146]], [[TMP5147]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6611]], label [[IF_THEN6613:%.*]], label [[IF_END6614:%.*]]
|
|
// SIMD-ONLY0: if.then6613:
|
|
// SIMD-ONLY0-NEXT: [[TMP5148:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5148]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6614]]
|
|
// SIMD-ONLY0: if.end6614:
|
|
// SIMD-ONLY0-NEXT: [[TMP5149:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5149]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5150:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5151:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6615:%.*]] = fcmp oeq double [[TMP5150]], [[TMP5151]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6615]], label [[IF_THEN6617:%.*]], label [[IF_END6618:%.*]]
|
|
// SIMD-ONLY0: if.then6617:
|
|
// SIMD-ONLY0-NEXT: [[TMP5152:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5152]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6618]]
|
|
// SIMD-ONLY0: if.end6618:
|
|
// SIMD-ONLY0-NEXT: [[TMP5153:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5153]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5154:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5155:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6619:%.*]] = fcmp oeq double [[TMP5154]], [[TMP5155]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6619]], label [[IF_THEN6621:%.*]], label [[IF_ELSE6622:%.*]]
|
|
// SIMD-ONLY0: if.then6621:
|
|
// SIMD-ONLY0-NEXT: [[TMP5156:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5156]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6623:%.*]]
|
|
// SIMD-ONLY0: if.else6622:
|
|
// SIMD-ONLY0-NEXT: [[TMP5157:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5157]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6623]]
|
|
// SIMD-ONLY0: if.end6623:
|
|
// SIMD-ONLY0-NEXT: [[TMP5158:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5159:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6624:%.*]] = fcmp oeq double [[TMP5158]], [[TMP5159]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6624]], label [[IF_THEN6626:%.*]], label [[IF_ELSE6627:%.*]]
|
|
// SIMD-ONLY0: if.then6626:
|
|
// SIMD-ONLY0-NEXT: [[TMP5160:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5160]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6628:%.*]]
|
|
// SIMD-ONLY0: if.else6627:
|
|
// SIMD-ONLY0-NEXT: [[TMP5161:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5161]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6628]]
|
|
// SIMD-ONLY0: if.end6628:
|
|
// SIMD-ONLY0-NEXT: [[TMP5162:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5163:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6629:%.*]] = fcmp oeq double [[TMP5162]], [[TMP5163]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6630:%.*]] = zext i1 [[CMP6629]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6630]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5164:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6631:%.*]] = icmp ne i32 [[TMP5164]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6631]], label [[IF_THEN6632:%.*]], label [[IF_END6633:%.*]]
|
|
// SIMD-ONLY0: if.then6632:
|
|
// SIMD-ONLY0-NEXT: [[TMP5165:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5165]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6633]]
|
|
// SIMD-ONLY0: if.end6633:
|
|
// SIMD-ONLY0-NEXT: [[TMP5166:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5167:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6634:%.*]] = fcmp oeq double [[TMP5166]], [[TMP5167]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6635:%.*]] = zext i1 [[CMP6634]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6635]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5168:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6636:%.*]] = icmp ne i32 [[TMP5168]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6636]], label [[IF_THEN6637:%.*]], label [[IF_END6638:%.*]]
|
|
// SIMD-ONLY0: if.then6637:
|
|
// SIMD-ONLY0-NEXT: [[TMP5169:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5169]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6638]]
|
|
// SIMD-ONLY0: if.end6638:
|
|
// SIMD-ONLY0-NEXT: [[TMP5170:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5171:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6639:%.*]] = fcmp oeq double [[TMP5170]], [[TMP5171]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6640:%.*]] = zext i1 [[CMP6639]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6640]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5172:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6641:%.*]] = icmp ne i32 [[TMP5172]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6641]], label [[IF_THEN6642:%.*]], label [[IF_ELSE6643:%.*]]
|
|
// SIMD-ONLY0: if.then6642:
|
|
// SIMD-ONLY0-NEXT: [[TMP5173:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5173]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6644:%.*]]
|
|
// SIMD-ONLY0: if.else6643:
|
|
// SIMD-ONLY0-NEXT: [[TMP5174:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5174]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6644]]
|
|
// SIMD-ONLY0: if.end6644:
|
|
// SIMD-ONLY0-NEXT: [[TMP5175:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5176:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6645:%.*]] = fcmp oeq double [[TMP5175]], [[TMP5176]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6646:%.*]] = zext i1 [[CMP6645]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6646]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5177:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6647:%.*]] = icmp ne i32 [[TMP5177]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6647]], label [[IF_THEN6648:%.*]], label [[IF_ELSE6649:%.*]]
|
|
// SIMD-ONLY0: if.then6648:
|
|
// SIMD-ONLY0-NEXT: [[TMP5178:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5178]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6650:%.*]]
|
|
// SIMD-ONLY0: if.else6649:
|
|
// SIMD-ONLY0-NEXT: [[TMP5179:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5179]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6650]]
|
|
// SIMD-ONLY0: if.end6650:
|
|
// SIMD-ONLY0-NEXT: [[TMP5180:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5180]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5181:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5182:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6651:%.*]] = fcmp ogt double [[TMP5181]], [[TMP5182]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6651]], label [[IF_THEN6653:%.*]], label [[IF_END6654:%.*]]
|
|
// SIMD-ONLY0: if.then6653:
|
|
// SIMD-ONLY0-NEXT: [[TMP5183:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5183]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6654]]
|
|
// SIMD-ONLY0: if.end6654:
|
|
// SIMD-ONLY0-NEXT: [[TMP5184:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5184]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5185:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5186:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6655:%.*]] = fcmp ogt double [[TMP5185]], [[TMP5186]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6655]], label [[IF_THEN6657:%.*]], label [[IF_END6658:%.*]]
|
|
// SIMD-ONLY0: if.then6657:
|
|
// SIMD-ONLY0-NEXT: [[TMP5187:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5187]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6658]]
|
|
// SIMD-ONLY0: if.end6658:
|
|
// SIMD-ONLY0-NEXT: [[TMP5188:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5188]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5189:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5190:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6659:%.*]] = fcmp olt double [[TMP5189]], [[TMP5190]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6659]], label [[IF_THEN6661:%.*]], label [[IF_END6662:%.*]]
|
|
// SIMD-ONLY0: if.then6661:
|
|
// SIMD-ONLY0-NEXT: [[TMP5191:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5191]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6662]]
|
|
// SIMD-ONLY0: if.end6662:
|
|
// SIMD-ONLY0-NEXT: [[TMP5192:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5192]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5193:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5194:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6663:%.*]] = fcmp olt double [[TMP5193]], [[TMP5194]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6663]], label [[IF_THEN6665:%.*]], label [[IF_END6666:%.*]]
|
|
// SIMD-ONLY0: if.then6665:
|
|
// SIMD-ONLY0-NEXT: [[TMP5195:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5195]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6666]]
|
|
// SIMD-ONLY0: if.end6666:
|
|
// SIMD-ONLY0-NEXT: [[TMP5196:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5196]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5197:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5198:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6667:%.*]] = fcmp oeq double [[TMP5197]], [[TMP5198]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6667]], label [[IF_THEN6669:%.*]], label [[IF_END6670:%.*]]
|
|
// SIMD-ONLY0: if.then6669:
|
|
// SIMD-ONLY0-NEXT: [[TMP5199:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5199]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6670]]
|
|
// SIMD-ONLY0: if.end6670:
|
|
// SIMD-ONLY0-NEXT: [[TMP5200:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5200]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5201:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5202:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6671:%.*]] = fcmp oeq double [[TMP5201]], [[TMP5202]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6671]], label [[IF_THEN6673:%.*]], label [[IF_END6674:%.*]]
|
|
// SIMD-ONLY0: if.then6673:
|
|
// SIMD-ONLY0-NEXT: [[TMP5203:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5203]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6674]]
|
|
// SIMD-ONLY0: if.end6674:
|
|
// SIMD-ONLY0-NEXT: [[TMP5204:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5205:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6675:%.*]] = fcmp ogt double [[TMP5204]], [[TMP5205]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6675]], label [[IF_THEN6677:%.*]], label [[IF_END6678:%.*]]
|
|
// SIMD-ONLY0: if.then6677:
|
|
// SIMD-ONLY0-NEXT: [[TMP5206:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5206]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6678]]
|
|
// SIMD-ONLY0: if.end6678:
|
|
// SIMD-ONLY0-NEXT: [[TMP5207:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5207]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5208:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5209:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6679:%.*]] = fcmp ogt double [[TMP5208]], [[TMP5209]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6679]], label [[IF_THEN6681:%.*]], label [[IF_END6682:%.*]]
|
|
// SIMD-ONLY0: if.then6681:
|
|
// SIMD-ONLY0-NEXT: [[TMP5210:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5210]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6682]]
|
|
// SIMD-ONLY0: if.end6682:
|
|
// SIMD-ONLY0-NEXT: [[TMP5211:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5211]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5212:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5213:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6683:%.*]] = fcmp olt double [[TMP5212]], [[TMP5213]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6683]], label [[IF_THEN6685:%.*]], label [[IF_END6686:%.*]]
|
|
// SIMD-ONLY0: if.then6685:
|
|
// SIMD-ONLY0-NEXT: [[TMP5214:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5214]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6686]]
|
|
// SIMD-ONLY0: if.end6686:
|
|
// SIMD-ONLY0-NEXT: [[TMP5215:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5215]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5216:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5217:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6687:%.*]] = fcmp olt double [[TMP5216]], [[TMP5217]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6687]], label [[IF_THEN6689:%.*]], label [[IF_END6690:%.*]]
|
|
// SIMD-ONLY0: if.then6689:
|
|
// SIMD-ONLY0-NEXT: [[TMP5218:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5218]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6690]]
|
|
// SIMD-ONLY0: if.end6690:
|
|
// SIMD-ONLY0-NEXT: [[TMP5219:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5219]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5220:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5221:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6691:%.*]] = fcmp oeq double [[TMP5220]], [[TMP5221]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6691]], label [[IF_THEN6693:%.*]], label [[IF_END6694:%.*]]
|
|
// SIMD-ONLY0: if.then6693:
|
|
// SIMD-ONLY0-NEXT: [[TMP5222:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5222]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6694]]
|
|
// SIMD-ONLY0: if.end6694:
|
|
// SIMD-ONLY0-NEXT: [[TMP5223:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5223]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5224:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5225:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6695:%.*]] = fcmp oeq double [[TMP5224]], [[TMP5225]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6695]], label [[IF_THEN6697:%.*]], label [[IF_END6698:%.*]]
|
|
// SIMD-ONLY0: if.then6697:
|
|
// SIMD-ONLY0-NEXT: [[TMP5226:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5226]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6698]]
|
|
// SIMD-ONLY0: if.end6698:
|
|
// SIMD-ONLY0-NEXT: [[TMP5227:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5227]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5228:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5229:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6699:%.*]] = fcmp oeq double [[TMP5228]], [[TMP5229]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6699]], label [[IF_THEN6701:%.*]], label [[IF_ELSE6702:%.*]]
|
|
// SIMD-ONLY0: if.then6701:
|
|
// SIMD-ONLY0-NEXT: [[TMP5230:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5230]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6703:%.*]]
|
|
// SIMD-ONLY0: if.else6702:
|
|
// SIMD-ONLY0-NEXT: [[TMP5231:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5231]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6703]]
|
|
// SIMD-ONLY0: if.end6703:
|
|
// SIMD-ONLY0-NEXT: [[TMP5232:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5233:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6704:%.*]] = fcmp oeq double [[TMP5232]], [[TMP5233]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6704]], label [[IF_THEN6706:%.*]], label [[IF_ELSE6707:%.*]]
|
|
// SIMD-ONLY0: if.then6706:
|
|
// SIMD-ONLY0-NEXT: [[TMP5234:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5234]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6708:%.*]]
|
|
// SIMD-ONLY0: if.else6707:
|
|
// SIMD-ONLY0-NEXT: [[TMP5235:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5235]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6708]]
|
|
// SIMD-ONLY0: if.end6708:
|
|
// SIMD-ONLY0-NEXT: [[TMP5236:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5237:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6709:%.*]] = fcmp oeq double [[TMP5236]], [[TMP5237]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6710:%.*]] = zext i1 [[CMP6709]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6710]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5238:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6711:%.*]] = icmp ne i32 [[TMP5238]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6711]], label [[IF_THEN6712:%.*]], label [[IF_END6713:%.*]]
|
|
// SIMD-ONLY0: if.then6712:
|
|
// SIMD-ONLY0-NEXT: [[TMP5239:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5239]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6713]]
|
|
// SIMD-ONLY0: if.end6713:
|
|
// SIMD-ONLY0-NEXT: [[TMP5240:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5241:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6714:%.*]] = fcmp oeq double [[TMP5240]], [[TMP5241]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6715:%.*]] = zext i1 [[CMP6714]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6715]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5242:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6716:%.*]] = icmp ne i32 [[TMP5242]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6716]], label [[IF_THEN6717:%.*]], label [[IF_END6718:%.*]]
|
|
// SIMD-ONLY0: if.then6717:
|
|
// SIMD-ONLY0-NEXT: [[TMP5243:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5243]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6718]]
|
|
// SIMD-ONLY0: if.end6718:
|
|
// SIMD-ONLY0-NEXT: [[TMP5244:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5245:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6719:%.*]] = fcmp oeq double [[TMP5244]], [[TMP5245]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6720:%.*]] = zext i1 [[CMP6719]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6720]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5246:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6721:%.*]] = icmp ne i32 [[TMP5246]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6721]], label [[IF_THEN6722:%.*]], label [[IF_ELSE6723:%.*]]
|
|
// SIMD-ONLY0: if.then6722:
|
|
// SIMD-ONLY0-NEXT: [[TMP5247:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5247]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6724:%.*]]
|
|
// SIMD-ONLY0: if.else6723:
|
|
// SIMD-ONLY0-NEXT: [[TMP5248:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5248]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6724]]
|
|
// SIMD-ONLY0: if.end6724:
|
|
// SIMD-ONLY0-NEXT: [[TMP5249:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5250:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6725:%.*]] = fcmp oeq double [[TMP5249]], [[TMP5250]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6726:%.*]] = zext i1 [[CMP6725]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6726]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5251:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6727:%.*]] = icmp ne i32 [[TMP5251]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6727]], label [[IF_THEN6728:%.*]], label [[IF_ELSE6729:%.*]]
|
|
// SIMD-ONLY0: if.then6728:
|
|
// SIMD-ONLY0-NEXT: [[TMP5252:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5252]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6730:%.*]]
|
|
// SIMD-ONLY0: if.else6729:
|
|
// SIMD-ONLY0-NEXT: [[TMP5253:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5253]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6730]]
|
|
// SIMD-ONLY0: if.end6730:
|
|
// SIMD-ONLY0-NEXT: [[TMP5254:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5254]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5255:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5256:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6731:%.*]] = fcmp ogt double [[TMP5255]], [[TMP5256]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6731]], label [[IF_THEN6733:%.*]], label [[IF_END6734:%.*]]
|
|
// SIMD-ONLY0: if.then6733:
|
|
// SIMD-ONLY0-NEXT: [[TMP5257:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5257]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6734]]
|
|
// SIMD-ONLY0: if.end6734:
|
|
// SIMD-ONLY0-NEXT: [[TMP5258:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5258]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5259:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5260:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6735:%.*]] = fcmp ogt double [[TMP5259]], [[TMP5260]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6735]], label [[IF_THEN6737:%.*]], label [[IF_END6738:%.*]]
|
|
// SIMD-ONLY0: if.then6737:
|
|
// SIMD-ONLY0-NEXT: [[TMP5261:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5261]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6738]]
|
|
// SIMD-ONLY0: if.end6738:
|
|
// SIMD-ONLY0-NEXT: [[TMP5262:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5262]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5263:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5264:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6739:%.*]] = fcmp olt double [[TMP5263]], [[TMP5264]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6739]], label [[IF_THEN6741:%.*]], label [[IF_END6742:%.*]]
|
|
// SIMD-ONLY0: if.then6741:
|
|
// SIMD-ONLY0-NEXT: [[TMP5265:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5265]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6742]]
|
|
// SIMD-ONLY0: if.end6742:
|
|
// SIMD-ONLY0-NEXT: [[TMP5266:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5266]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5267:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5268:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6743:%.*]] = fcmp olt double [[TMP5267]], [[TMP5268]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6743]], label [[IF_THEN6745:%.*]], label [[IF_END6746:%.*]]
|
|
// SIMD-ONLY0: if.then6745:
|
|
// SIMD-ONLY0-NEXT: [[TMP5269:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5269]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6746]]
|
|
// SIMD-ONLY0: if.end6746:
|
|
// SIMD-ONLY0-NEXT: [[TMP5270:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5270]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5271:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5272:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6747:%.*]] = fcmp oeq double [[TMP5271]], [[TMP5272]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6747]], label [[IF_THEN6749:%.*]], label [[IF_END6750:%.*]]
|
|
// SIMD-ONLY0: if.then6749:
|
|
// SIMD-ONLY0-NEXT: [[TMP5273:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5273]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6750]]
|
|
// SIMD-ONLY0: if.end6750:
|
|
// SIMD-ONLY0-NEXT: [[TMP5274:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5274]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5275:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5276:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6751:%.*]] = fcmp oeq double [[TMP5275]], [[TMP5276]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6751]], label [[IF_THEN6753:%.*]], label [[IF_END6754:%.*]]
|
|
// SIMD-ONLY0: if.then6753:
|
|
// SIMD-ONLY0-NEXT: [[TMP5277:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5277]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6754]]
|
|
// SIMD-ONLY0: if.end6754:
|
|
// SIMD-ONLY0-NEXT: [[TMP5278:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5279:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6755:%.*]] = fcmp ogt double [[TMP5278]], [[TMP5279]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6755]], label [[IF_THEN6757:%.*]], label [[IF_END6758:%.*]]
|
|
// SIMD-ONLY0: if.then6757:
|
|
// SIMD-ONLY0-NEXT: [[TMP5280:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5280]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6758]]
|
|
// SIMD-ONLY0: if.end6758:
|
|
// SIMD-ONLY0-NEXT: [[TMP5281:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5281]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5282:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5283:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6759:%.*]] = fcmp ogt double [[TMP5282]], [[TMP5283]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6759]], label [[IF_THEN6761:%.*]], label [[IF_END6762:%.*]]
|
|
// SIMD-ONLY0: if.then6761:
|
|
// SIMD-ONLY0-NEXT: [[TMP5284:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5284]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6762]]
|
|
// SIMD-ONLY0: if.end6762:
|
|
// SIMD-ONLY0-NEXT: [[TMP5285:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5285]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5286:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5287:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6763:%.*]] = fcmp olt double [[TMP5286]], [[TMP5287]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6763]], label [[IF_THEN6765:%.*]], label [[IF_END6766:%.*]]
|
|
// SIMD-ONLY0: if.then6765:
|
|
// SIMD-ONLY0-NEXT: [[TMP5288:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5288]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6766]]
|
|
// SIMD-ONLY0: if.end6766:
|
|
// SIMD-ONLY0-NEXT: [[TMP5289:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5289]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5290:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5291:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6767:%.*]] = fcmp olt double [[TMP5290]], [[TMP5291]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6767]], label [[IF_THEN6769:%.*]], label [[IF_END6770:%.*]]
|
|
// SIMD-ONLY0: if.then6769:
|
|
// SIMD-ONLY0-NEXT: [[TMP5292:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5292]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6770]]
|
|
// SIMD-ONLY0: if.end6770:
|
|
// SIMD-ONLY0-NEXT: [[TMP5293:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5293]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5294:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5295:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6771:%.*]] = fcmp oeq double [[TMP5294]], [[TMP5295]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6771]], label [[IF_THEN6773:%.*]], label [[IF_END6774:%.*]]
|
|
// SIMD-ONLY0: if.then6773:
|
|
// SIMD-ONLY0-NEXT: [[TMP5296:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5296]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6774]]
|
|
// SIMD-ONLY0: if.end6774:
|
|
// SIMD-ONLY0-NEXT: [[TMP5297:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5297]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5298:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5299:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6775:%.*]] = fcmp oeq double [[TMP5298]], [[TMP5299]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6775]], label [[IF_THEN6777:%.*]], label [[IF_END6778:%.*]]
|
|
// SIMD-ONLY0: if.then6777:
|
|
// SIMD-ONLY0-NEXT: [[TMP5300:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5300]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6778]]
|
|
// SIMD-ONLY0: if.end6778:
|
|
// SIMD-ONLY0-NEXT: [[TMP5301:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5301]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5302:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5303:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6779:%.*]] = fcmp oeq double [[TMP5302]], [[TMP5303]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6779]], label [[IF_THEN6781:%.*]], label [[IF_ELSE6782:%.*]]
|
|
// SIMD-ONLY0: if.then6781:
|
|
// SIMD-ONLY0-NEXT: [[TMP5304:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5304]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6783:%.*]]
|
|
// SIMD-ONLY0: if.else6782:
|
|
// SIMD-ONLY0-NEXT: [[TMP5305:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5305]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6783]]
|
|
// SIMD-ONLY0: if.end6783:
|
|
// SIMD-ONLY0-NEXT: [[TMP5306:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5307:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6784:%.*]] = fcmp oeq double [[TMP5306]], [[TMP5307]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6784]], label [[IF_THEN6786:%.*]], label [[IF_ELSE6787:%.*]]
|
|
// SIMD-ONLY0: if.then6786:
|
|
// SIMD-ONLY0-NEXT: [[TMP5308:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5308]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6788:%.*]]
|
|
// SIMD-ONLY0: if.else6787:
|
|
// SIMD-ONLY0-NEXT: [[TMP5309:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5309]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6788]]
|
|
// SIMD-ONLY0: if.end6788:
|
|
// SIMD-ONLY0-NEXT: [[TMP5310:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5311:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6789:%.*]] = fcmp oeq double [[TMP5310]], [[TMP5311]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6790:%.*]] = zext i1 [[CMP6789]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6790]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5312:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6791:%.*]] = icmp ne i32 [[TMP5312]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6791]], label [[IF_THEN6792:%.*]], label [[IF_END6793:%.*]]
|
|
// SIMD-ONLY0: if.then6792:
|
|
// SIMD-ONLY0-NEXT: [[TMP5313:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5313]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6793]]
|
|
// SIMD-ONLY0: if.end6793:
|
|
// SIMD-ONLY0-NEXT: [[TMP5314:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5315:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6794:%.*]] = fcmp oeq double [[TMP5314]], [[TMP5315]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6795:%.*]] = zext i1 [[CMP6794]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6795]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5316:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6796:%.*]] = icmp ne i32 [[TMP5316]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6796]], label [[IF_THEN6797:%.*]], label [[IF_END6798:%.*]]
|
|
// SIMD-ONLY0: if.then6797:
|
|
// SIMD-ONLY0-NEXT: [[TMP5317:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5317]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6798]]
|
|
// SIMD-ONLY0: if.end6798:
|
|
// SIMD-ONLY0-NEXT: [[TMP5318:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5319:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6799:%.*]] = fcmp oeq double [[TMP5318]], [[TMP5319]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6800:%.*]] = zext i1 [[CMP6799]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6800]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5320:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6801:%.*]] = icmp ne i32 [[TMP5320]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6801]], label [[IF_THEN6802:%.*]], label [[IF_ELSE6803:%.*]]
|
|
// SIMD-ONLY0: if.then6802:
|
|
// SIMD-ONLY0-NEXT: [[TMP5321:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5321]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6804:%.*]]
|
|
// SIMD-ONLY0: if.else6803:
|
|
// SIMD-ONLY0-NEXT: [[TMP5322:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5322]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6804]]
|
|
// SIMD-ONLY0: if.end6804:
|
|
// SIMD-ONLY0-NEXT: [[TMP5323:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5324:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6805:%.*]] = fcmp oeq double [[TMP5323]], [[TMP5324]]
|
|
// SIMD-ONLY0-NEXT: [[CONV6806:%.*]] = zext i1 [[CMP6805]] to i32
|
|
// SIMD-ONLY0-NEXT: store i32 [[CONV6806]], ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5325:%.*]] = load i32, ptr [[IR]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TOBOOL6807:%.*]] = icmp ne i32 [[TMP5325]], 0
|
|
// SIMD-ONLY0-NEXT: br i1 [[TOBOOL6807]], label [[IF_THEN6808:%.*]], label [[IF_ELSE6809:%.*]]
|
|
// SIMD-ONLY0: if.then6808:
|
|
// SIMD-ONLY0-NEXT: [[TMP5326:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5326]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6810:%.*]]
|
|
// SIMD-ONLY0: if.else6809:
|
|
// SIMD-ONLY0-NEXT: [[TMP5327:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5327]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[IF_END6810]]
|
|
// SIMD-ONLY0: if.end6810:
|
|
// SIMD-ONLY0-NEXT: ret void
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @cxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[CX:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[CV:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[CE:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[CD:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP0]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i8 [[TMP2]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV5:%.*]] = trunc i32 [[COND]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV5]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP5]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV6:%.*]] = sext i8 [[TMP6]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV7:%.*]] = sext i8 [[TMP7]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
|
|
// SIMD-ONLY0: cond.true10:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV11:%.*]] = sext i8 [[TMP8]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false12:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV13:%.*]] = sext i8 [[TMP9]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV16:%.*]] = trunc i32 [[COND15]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV16]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP10]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV17:%.*]] = sext i8 [[TMP11]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV18:%.*]] = sext i8 [[TMP12]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP19:%.*]] = icmp eq i32 [[CONV17]], [[CONV18]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true21:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV22:%.*]] = sext i8 [[TMP13]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV24:%.*]] = sext i8 [[TMP14]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25]]
|
|
// SIMD-ONLY0: cond.end25:
|
|
// SIMD-ONLY0-NEXT: [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV27:%.*]] = trunc i32 [[COND26]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV27]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV28:%.*]] = sext i8 [[TMP15]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV29:%.*]] = sext i8 [[TMP16]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP30:%.*]] = icmp sgt i32 [[CONV28]], [[CONV29]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV33:%.*]] = sext i8 [[TMP17]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36:%.*]]
|
|
// SIMD-ONLY0: cond.false34:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV35:%.*]] = sext i8 [[TMP18]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36]]
|
|
// SIMD-ONLY0: cond.end36:
|
|
// SIMD-ONLY0-NEXT: [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV38:%.*]] = trunc i32 [[COND37]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV38]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP19]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV39:%.*]] = sext i8 [[TMP20]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV40:%.*]] = sext i8 [[TMP21]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp slt i32 [[CONV39]], [[CONV40]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE43:%.*]], label [[COND_FALSE45:%.*]]
|
|
// SIMD-ONLY0: cond.true43:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV44:%.*]] = sext i8 [[TMP22]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END47:%.*]]
|
|
// SIMD-ONLY0: cond.false45:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV46:%.*]] = sext i8 [[TMP23]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END47]]
|
|
// SIMD-ONLY0: cond.end47:
|
|
// SIMD-ONLY0-NEXT: [[COND48:%.*]] = phi i32 [ [[CONV44]], [[COND_TRUE43]] ], [ [[CONV46]], [[COND_FALSE45]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV49:%.*]] = trunc i32 [[COND48]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV49]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP24]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV50:%.*]] = sext i8 [[TMP25]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV51:%.*]] = sext i8 [[TMP26]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP52:%.*]] = icmp eq i32 [[CONV50]], [[CONV51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP52]], label [[COND_TRUE54:%.*]], label [[COND_FALSE56:%.*]]
|
|
// SIMD-ONLY0: cond.true54:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV55:%.*]] = sext i8 [[TMP27]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END58:%.*]]
|
|
// SIMD-ONLY0: cond.false56:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV57:%.*]] = sext i8 [[TMP28]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END58]]
|
|
// SIMD-ONLY0: cond.end58:
|
|
// SIMD-ONLY0-NEXT: [[COND59:%.*]] = phi i32 [ [[CONV55]], [[COND_TRUE54]] ], [ [[CONV57]], [[COND_FALSE56]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV60:%.*]] = trunc i32 [[COND59]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV60]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP29]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP30]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV61:%.*]] = sext i8 [[TMP31]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV62:%.*]] = sext i8 [[TMP32]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP63:%.*]] = icmp sgt i32 [[CONV61]], [[CONV62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
|
|
// SIMD-ONLY0: cond.true65:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV66:%.*]] = sext i8 [[TMP33]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false67:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV68:%.*]] = sext i8 [[TMP34]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV71:%.*]] = trunc i32 [[COND70]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV71]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP35]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV72:%.*]] = sext i8 [[TMP36]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV73:%.*]] = sext i8 [[TMP37]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP74:%.*]] = icmp slt i32 [[CONV72]], [[CONV73]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true76:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV77:%.*]] = sext i8 [[TMP38]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV79:%.*]] = sext i8 [[TMP39]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80]]
|
|
// SIMD-ONLY0: cond.end80:
|
|
// SIMD-ONLY0-NEXT: [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV82:%.*]] = trunc i32 [[COND81]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV82]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP40]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV83:%.*]] = sext i8 [[TMP41]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV84:%.*]] = sext i8 [[TMP42]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP85]], label [[COND_TRUE87:%.*]], label [[COND_FALSE89:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV88:%.*]] = sext i8 [[TMP43]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END91:%.*]]
|
|
// SIMD-ONLY0: cond.false89:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV90:%.*]] = sext i8 [[TMP44]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END91]]
|
|
// SIMD-ONLY0: cond.end91:
|
|
// SIMD-ONLY0-NEXT: [[COND92:%.*]] = phi i32 [ [[CONV88]], [[COND_TRUE87]] ], [ [[CONV90]], [[COND_FALSE89]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV93:%.*]] = trunc i32 [[COND92]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV93]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV94:%.*]] = sext i8 [[TMP45]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV95:%.*]] = sext i8 [[TMP46]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp sgt i32 [[CONV94]], [[CONV95]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE98:%.*]], label [[COND_FALSE100:%.*]]
|
|
// SIMD-ONLY0: cond.true98:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV99:%.*]] = sext i8 [[TMP47]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END102:%.*]]
|
|
// SIMD-ONLY0: cond.false100:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV101:%.*]] = sext i8 [[TMP48]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END102]]
|
|
// SIMD-ONLY0: cond.end102:
|
|
// SIMD-ONLY0-NEXT: [[COND103:%.*]] = phi i32 [ [[CONV99]], [[COND_TRUE98]] ], [ [[CONV101]], [[COND_FALSE100]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV104:%.*]] = trunc i32 [[COND103]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV104]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP49]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV105:%.*]] = sext i8 [[TMP50]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV106:%.*]] = sext i8 [[TMP51]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP107:%.*]] = icmp slt i32 [[CONV105]], [[CONV106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP107]], label [[COND_TRUE109:%.*]], label [[COND_FALSE111:%.*]]
|
|
// SIMD-ONLY0: cond.true109:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV110:%.*]] = sext i8 [[TMP52]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END113:%.*]]
|
|
// SIMD-ONLY0: cond.false111:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV112:%.*]] = sext i8 [[TMP53]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END113]]
|
|
// SIMD-ONLY0: cond.end113:
|
|
// SIMD-ONLY0-NEXT: [[COND114:%.*]] = phi i32 [ [[CONV110]], [[COND_TRUE109]] ], [ [[CONV112]], [[COND_FALSE111]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV115:%.*]] = trunc i32 [[COND114]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV115]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP54]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV116:%.*]] = sext i8 [[TMP55]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV117:%.*]] = sext i8 [[TMP56]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP118:%.*]] = icmp eq i32 [[CONV116]], [[CONV117]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP118]], label [[COND_TRUE120:%.*]], label [[COND_FALSE122:%.*]]
|
|
// SIMD-ONLY0: cond.true120:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV121:%.*]] = sext i8 [[TMP57]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false122:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV123:%.*]] = sext i8 [[TMP58]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i32 [ [[CONV121]], [[COND_TRUE120]] ], [ [[CONV123]], [[COND_FALSE122]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV126:%.*]] = trunc i32 [[COND125]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV126]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP59]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP60]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV127:%.*]] = sext i8 [[TMP61]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV128:%.*]] = sext i8 [[TMP62]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP129:%.*]] = icmp sgt i32 [[CONV127]], [[CONV128]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP129]], label [[COND_TRUE131:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true131:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV132:%.*]] = sext i8 [[TMP63]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END135:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV134:%.*]] = sext i8 [[TMP64]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END135]]
|
|
// SIMD-ONLY0: cond.end135:
|
|
// SIMD-ONLY0-NEXT: [[COND136:%.*]] = phi i32 [ [[CONV132]], [[COND_TRUE131]] ], [ [[CONV134]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV137:%.*]] = trunc i32 [[COND136]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV137]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP65]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV138:%.*]] = sext i8 [[TMP66]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV139:%.*]] = sext i8 [[TMP67]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP140:%.*]] = icmp slt i32 [[CONV138]], [[CONV139]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP140]], label [[COND_TRUE142:%.*]], label [[COND_FALSE144:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV143:%.*]] = sext i8 [[TMP68]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END146:%.*]]
|
|
// SIMD-ONLY0: cond.false144:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV145:%.*]] = sext i8 [[TMP69]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END146]]
|
|
// SIMD-ONLY0: cond.end146:
|
|
// SIMD-ONLY0-NEXT: [[COND147:%.*]] = phi i32 [ [[CONV143]], [[COND_TRUE142]] ], [ [[CONV145]], [[COND_FALSE144]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV148:%.*]] = trunc i32 [[COND147]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV148]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP70]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV149:%.*]] = sext i8 [[TMP71]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV150:%.*]] = sext i8 [[TMP72]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp eq i32 [[CONV149]], [[CONV150]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE153:%.*]], label [[COND_FALSE155:%.*]]
|
|
// SIMD-ONLY0: cond.true153:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV154:%.*]] = sext i8 [[TMP73]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END157:%.*]]
|
|
// SIMD-ONLY0: cond.false155:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV156:%.*]] = sext i8 [[TMP74]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END157]]
|
|
// SIMD-ONLY0: cond.end157:
|
|
// SIMD-ONLY0-NEXT: [[COND158:%.*]] = phi i32 [ [[CONV154]], [[COND_TRUE153]] ], [ [[CONV156]], [[COND_FALSE155]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV159:%.*]] = trunc i32 [[COND158]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV159]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV160:%.*]] = sext i8 [[TMP75]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV161:%.*]] = sext i8 [[TMP76]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP162:%.*]] = icmp sgt i32 [[CONV160]], [[CONV161]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP162]], label [[COND_TRUE164:%.*]], label [[COND_FALSE166:%.*]]
|
|
// SIMD-ONLY0: cond.true164:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV165:%.*]] = sext i8 [[TMP77]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END168:%.*]]
|
|
// SIMD-ONLY0: cond.false166:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV167:%.*]] = sext i8 [[TMP78]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END168]]
|
|
// SIMD-ONLY0: cond.end168:
|
|
// SIMD-ONLY0-NEXT: [[COND169:%.*]] = phi i32 [ [[CONV165]], [[COND_TRUE164]] ], [ [[CONV167]], [[COND_FALSE166]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV170:%.*]] = trunc i32 [[COND169]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV170]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP79]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV171:%.*]] = sext i8 [[TMP80]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV172:%.*]] = sext i8 [[TMP81]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP173:%.*]] = icmp slt i32 [[CONV171]], [[CONV172]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP173]], label [[COND_TRUE175:%.*]], label [[COND_FALSE177:%.*]]
|
|
// SIMD-ONLY0: cond.true175:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV176:%.*]] = sext i8 [[TMP82]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END179:%.*]]
|
|
// SIMD-ONLY0: cond.false177:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV178:%.*]] = sext i8 [[TMP83]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END179]]
|
|
// SIMD-ONLY0: cond.end179:
|
|
// SIMD-ONLY0-NEXT: [[COND180:%.*]] = phi i32 [ [[CONV176]], [[COND_TRUE175]] ], [ [[CONV178]], [[COND_FALSE177]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV181:%.*]] = trunc i32 [[COND180]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV181]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP84]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV182:%.*]] = sext i8 [[TMP85]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV183:%.*]] = sext i8 [[TMP86]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP184:%.*]] = icmp eq i32 [[CONV182]], [[CONV183]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP184]], label [[COND_TRUE186:%.*]], label [[COND_FALSE188:%.*]]
|
|
// SIMD-ONLY0: cond.true186:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV187:%.*]] = sext i8 [[TMP87]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END190:%.*]]
|
|
// SIMD-ONLY0: cond.false188:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV189:%.*]] = sext i8 [[TMP88]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END190]]
|
|
// SIMD-ONLY0: cond.end190:
|
|
// SIMD-ONLY0-NEXT: [[COND191:%.*]] = phi i32 [ [[CONV187]], [[COND_TRUE186]] ], [ [[CONV189]], [[COND_FALSE188]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV192:%.*]] = trunc i32 [[COND191]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV192]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP89]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP90]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV193:%.*]] = sext i8 [[TMP91]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV194:%.*]] = sext i8 [[TMP92]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP195:%.*]] = icmp sgt i32 [[CONV193]], [[CONV194]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP195]], label [[COND_TRUE197:%.*]], label [[COND_FALSE199:%.*]]
|
|
// SIMD-ONLY0: cond.true197:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV198:%.*]] = sext i8 [[TMP93]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END201:%.*]]
|
|
// SIMD-ONLY0: cond.false199:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV200:%.*]] = sext i8 [[TMP94]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END201]]
|
|
// SIMD-ONLY0: cond.end201:
|
|
// SIMD-ONLY0-NEXT: [[COND202:%.*]] = phi i32 [ [[CONV198]], [[COND_TRUE197]] ], [ [[CONV200]], [[COND_FALSE199]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV203:%.*]] = trunc i32 [[COND202]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV203]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP95]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV204:%.*]] = sext i8 [[TMP96]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV205:%.*]] = sext i8 [[TMP97]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP206:%.*]] = icmp slt i32 [[CONV204]], [[CONV205]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP206]], label [[COND_TRUE208:%.*]], label [[COND_FALSE210:%.*]]
|
|
// SIMD-ONLY0: cond.true208:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV209:%.*]] = sext i8 [[TMP98]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END212:%.*]]
|
|
// SIMD-ONLY0: cond.false210:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV211:%.*]] = sext i8 [[TMP99]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END212]]
|
|
// SIMD-ONLY0: cond.end212:
|
|
// SIMD-ONLY0-NEXT: [[COND213:%.*]] = phi i32 [ [[CONV209]], [[COND_TRUE208]] ], [ [[CONV211]], [[COND_FALSE210]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV214:%.*]] = trunc i32 [[COND213]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV214]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP100]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV215:%.*]] = sext i8 [[TMP101]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV216:%.*]] = sext i8 [[TMP102]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP217:%.*]] = icmp eq i32 [[CONV215]], [[CONV216]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP217]], label [[COND_TRUE219:%.*]], label [[COND_FALSE221:%.*]]
|
|
// SIMD-ONLY0: cond.true219:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV220:%.*]] = sext i8 [[TMP103]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END223:%.*]]
|
|
// SIMD-ONLY0: cond.false221:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV222:%.*]] = sext i8 [[TMP104]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END223]]
|
|
// SIMD-ONLY0: cond.end223:
|
|
// SIMD-ONLY0-NEXT: [[COND224:%.*]] = phi i32 [ [[CONV220]], [[COND_TRUE219]] ], [ [[CONV222]], [[COND_FALSE221]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV225:%.*]] = trunc i32 [[COND224]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV225]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV226:%.*]] = sext i8 [[TMP105]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV227:%.*]] = sext i8 [[TMP106]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP228:%.*]] = icmp sgt i32 [[CONV226]], [[CONV227]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP228]], label [[COND_TRUE230:%.*]], label [[COND_FALSE232:%.*]]
|
|
// SIMD-ONLY0: cond.true230:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV231:%.*]] = sext i8 [[TMP107]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END234:%.*]]
|
|
// SIMD-ONLY0: cond.false232:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV233:%.*]] = sext i8 [[TMP108]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END234]]
|
|
// SIMD-ONLY0: cond.end234:
|
|
// SIMD-ONLY0-NEXT: [[COND235:%.*]] = phi i32 [ [[CONV231]], [[COND_TRUE230]] ], [ [[CONV233]], [[COND_FALSE232]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV236:%.*]] = trunc i32 [[COND235]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV236]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP109]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV237:%.*]] = sext i8 [[TMP110]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV238:%.*]] = sext i8 [[TMP111]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP239:%.*]] = icmp slt i32 [[CONV237]], [[CONV238]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP239]], label [[COND_TRUE241:%.*]], label [[COND_FALSE243:%.*]]
|
|
// SIMD-ONLY0: cond.true241:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV242:%.*]] = sext i8 [[TMP112]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END245:%.*]]
|
|
// SIMD-ONLY0: cond.false243:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV244:%.*]] = sext i8 [[TMP113]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END245]]
|
|
// SIMD-ONLY0: cond.end245:
|
|
// SIMD-ONLY0-NEXT: [[COND246:%.*]] = phi i32 [ [[CONV242]], [[COND_TRUE241]] ], [ [[CONV244]], [[COND_FALSE243]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV247:%.*]] = trunc i32 [[COND246]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV247]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP114]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV248:%.*]] = sext i8 [[TMP115]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV249:%.*]] = sext i8 [[TMP116]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP250:%.*]] = icmp eq i32 [[CONV248]], [[CONV249]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP250]], label [[COND_TRUE252:%.*]], label [[COND_FALSE254:%.*]]
|
|
// SIMD-ONLY0: cond.true252:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV253:%.*]] = sext i8 [[TMP117]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END256:%.*]]
|
|
// SIMD-ONLY0: cond.false254:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV255:%.*]] = sext i8 [[TMP118]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END256]]
|
|
// SIMD-ONLY0: cond.end256:
|
|
// SIMD-ONLY0-NEXT: [[COND257:%.*]] = phi i32 [ [[CONV253]], [[COND_TRUE252]] ], [ [[CONV255]], [[COND_FALSE254]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV258:%.*]] = trunc i32 [[COND257]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV258]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP119]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP120]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV259:%.*]] = sext i8 [[TMP121]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV260:%.*]] = sext i8 [[TMP122]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP261:%.*]] = icmp sgt i32 [[CONV259]], [[CONV260]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP261]], label [[COND_TRUE263:%.*]], label [[COND_FALSE265:%.*]]
|
|
// SIMD-ONLY0: cond.true263:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV264:%.*]] = sext i8 [[TMP123]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END267:%.*]]
|
|
// SIMD-ONLY0: cond.false265:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV266:%.*]] = sext i8 [[TMP124]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END267]]
|
|
// SIMD-ONLY0: cond.end267:
|
|
// SIMD-ONLY0-NEXT: [[COND268:%.*]] = phi i32 [ [[CONV264]], [[COND_TRUE263]] ], [ [[CONV266]], [[COND_FALSE265]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV269:%.*]] = trunc i32 [[COND268]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV269]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP125]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV270:%.*]] = sext i8 [[TMP126]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV271:%.*]] = sext i8 [[TMP127]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP272:%.*]] = icmp slt i32 [[CONV270]], [[CONV271]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP272]], label [[COND_TRUE274:%.*]], label [[COND_FALSE276:%.*]]
|
|
// SIMD-ONLY0: cond.true274:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV275:%.*]] = sext i8 [[TMP128]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END278:%.*]]
|
|
// SIMD-ONLY0: cond.false276:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV277:%.*]] = sext i8 [[TMP129]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END278]]
|
|
// SIMD-ONLY0: cond.end278:
|
|
// SIMD-ONLY0-NEXT: [[COND279:%.*]] = phi i32 [ [[CONV275]], [[COND_TRUE274]] ], [ [[CONV277]], [[COND_FALSE276]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV280:%.*]] = trunc i32 [[COND279]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV280]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP130]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV281:%.*]] = sext i8 [[TMP131]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV282:%.*]] = sext i8 [[TMP132]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP283:%.*]] = icmp eq i32 [[CONV281]], [[CONV282]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP283]], label [[COND_TRUE285:%.*]], label [[COND_FALSE287:%.*]]
|
|
// SIMD-ONLY0: cond.true285:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV286:%.*]] = sext i8 [[TMP133]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END289:%.*]]
|
|
// SIMD-ONLY0: cond.false287:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV288:%.*]] = sext i8 [[TMP134]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END289]]
|
|
// SIMD-ONLY0: cond.end289:
|
|
// SIMD-ONLY0-NEXT: [[COND290:%.*]] = phi i32 [ [[CONV286]], [[COND_TRUE285]] ], [ [[CONV288]], [[COND_FALSE287]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV291:%.*]] = trunc i32 [[COND290]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV291]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV292:%.*]] = sext i8 [[TMP135]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV293:%.*]] = sext i8 [[TMP136]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP294:%.*]] = icmp sgt i32 [[CONV292]], [[CONV293]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP294]], label [[COND_TRUE296:%.*]], label [[COND_FALSE298:%.*]]
|
|
// SIMD-ONLY0: cond.true296:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV297:%.*]] = sext i8 [[TMP137]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END300:%.*]]
|
|
// SIMD-ONLY0: cond.false298:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV299:%.*]] = sext i8 [[TMP138]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END300]]
|
|
// SIMD-ONLY0: cond.end300:
|
|
// SIMD-ONLY0-NEXT: [[COND301:%.*]] = phi i32 [ [[CONV297]], [[COND_TRUE296]] ], [ [[CONV299]], [[COND_FALSE298]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV302:%.*]] = trunc i32 [[COND301]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV302]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP139]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV303:%.*]] = sext i8 [[TMP140]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV304:%.*]] = sext i8 [[TMP141]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP305:%.*]] = icmp slt i32 [[CONV303]], [[CONV304]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP305]], label [[COND_TRUE307:%.*]], label [[COND_FALSE309:%.*]]
|
|
// SIMD-ONLY0: cond.true307:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV308:%.*]] = sext i8 [[TMP142]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END311:%.*]]
|
|
// SIMD-ONLY0: cond.false309:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV310:%.*]] = sext i8 [[TMP143]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END311]]
|
|
// SIMD-ONLY0: cond.end311:
|
|
// SIMD-ONLY0-NEXT: [[COND312:%.*]] = phi i32 [ [[CONV308]], [[COND_TRUE307]] ], [ [[CONV310]], [[COND_FALSE309]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV313:%.*]] = trunc i32 [[COND312]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV313]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP144]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV314:%.*]] = sext i8 [[TMP145]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV315:%.*]] = sext i8 [[TMP146]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP316]], label [[COND_TRUE318:%.*]], label [[COND_FALSE320:%.*]]
|
|
// SIMD-ONLY0: cond.true318:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV319:%.*]] = sext i8 [[TMP147]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END322:%.*]]
|
|
// SIMD-ONLY0: cond.false320:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV321:%.*]] = sext i8 [[TMP148]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END322]]
|
|
// SIMD-ONLY0: cond.end322:
|
|
// SIMD-ONLY0-NEXT: [[COND323:%.*]] = phi i32 [ [[CONV319]], [[COND_TRUE318]] ], [ [[CONV321]], [[COND_FALSE320]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV324:%.*]] = trunc i32 [[COND323]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV324]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP149]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP150]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV325:%.*]] = sext i8 [[TMP151]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV326:%.*]] = sext i8 [[TMP152]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP327:%.*]] = icmp sgt i32 [[CONV325]], [[CONV326]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP327]], label [[COND_TRUE329:%.*]], label [[COND_FALSE331:%.*]]
|
|
// SIMD-ONLY0: cond.true329:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV330:%.*]] = sext i8 [[TMP153]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END333:%.*]]
|
|
// SIMD-ONLY0: cond.false331:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV332:%.*]] = sext i8 [[TMP154]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END333]]
|
|
// SIMD-ONLY0: cond.end333:
|
|
// SIMD-ONLY0-NEXT: [[COND334:%.*]] = phi i32 [ [[CONV330]], [[COND_TRUE329]] ], [ [[CONV332]], [[COND_FALSE331]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV335:%.*]] = trunc i32 [[COND334]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV335]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP155]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV336:%.*]] = sext i8 [[TMP156]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV337:%.*]] = sext i8 [[TMP157]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP338:%.*]] = icmp slt i32 [[CONV336]], [[CONV337]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP338]], label [[COND_TRUE340:%.*]], label [[COND_FALSE342:%.*]]
|
|
// SIMD-ONLY0: cond.true340:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV341:%.*]] = sext i8 [[TMP158]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END344:%.*]]
|
|
// SIMD-ONLY0: cond.false342:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV343:%.*]] = sext i8 [[TMP159]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END344]]
|
|
// SIMD-ONLY0: cond.end344:
|
|
// SIMD-ONLY0-NEXT: [[COND345:%.*]] = phi i32 [ [[CONV341]], [[COND_TRUE340]] ], [ [[CONV343]], [[COND_FALSE342]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV346:%.*]] = trunc i32 [[COND345]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV346]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP160]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV347:%.*]] = sext i8 [[TMP161]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV348:%.*]] = sext i8 [[TMP162]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP349:%.*]] = icmp eq i32 [[CONV347]], [[CONV348]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP349]], label [[COND_TRUE351:%.*]], label [[COND_FALSE353:%.*]]
|
|
// SIMD-ONLY0: cond.true351:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV352:%.*]] = sext i8 [[TMP163]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END355:%.*]]
|
|
// SIMD-ONLY0: cond.false353:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV354:%.*]] = sext i8 [[TMP164]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END355]]
|
|
// SIMD-ONLY0: cond.end355:
|
|
// SIMD-ONLY0-NEXT: [[COND356:%.*]] = phi i32 [ [[CONV352]], [[COND_TRUE351]] ], [ [[CONV354]], [[COND_FALSE353]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV357:%.*]] = trunc i32 [[COND356]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV357]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV358:%.*]] = sext i8 [[TMP165]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV359:%.*]] = sext i8 [[TMP166]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP360:%.*]] = icmp sgt i32 [[CONV358]], [[CONV359]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP360]], label [[COND_TRUE362:%.*]], label [[COND_FALSE364:%.*]]
|
|
// SIMD-ONLY0: cond.true362:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV363:%.*]] = sext i8 [[TMP167]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END366:%.*]]
|
|
// SIMD-ONLY0: cond.false364:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV365:%.*]] = sext i8 [[TMP168]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END366]]
|
|
// SIMD-ONLY0: cond.end366:
|
|
// SIMD-ONLY0-NEXT: [[COND367:%.*]] = phi i32 [ [[CONV363]], [[COND_TRUE362]] ], [ [[CONV365]], [[COND_FALSE364]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV368:%.*]] = trunc i32 [[COND367]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV368]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP169]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV369:%.*]] = sext i8 [[TMP170]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV370:%.*]] = sext i8 [[TMP171]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP371:%.*]] = icmp slt i32 [[CONV369]], [[CONV370]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP371]], label [[COND_TRUE373:%.*]], label [[COND_FALSE375:%.*]]
|
|
// SIMD-ONLY0: cond.true373:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV374:%.*]] = sext i8 [[TMP172]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END377:%.*]]
|
|
// SIMD-ONLY0: cond.false375:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV376:%.*]] = sext i8 [[TMP173]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END377]]
|
|
// SIMD-ONLY0: cond.end377:
|
|
// SIMD-ONLY0-NEXT: [[COND378:%.*]] = phi i32 [ [[CONV374]], [[COND_TRUE373]] ], [ [[CONV376]], [[COND_FALSE375]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV379:%.*]] = trunc i32 [[COND378]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV379]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP174]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV380:%.*]] = sext i8 [[TMP175]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV381:%.*]] = sext i8 [[TMP176]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP382:%.*]] = icmp eq i32 [[CONV380]], [[CONV381]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP382]], label [[COND_TRUE384:%.*]], label [[COND_FALSE386:%.*]]
|
|
// SIMD-ONLY0: cond.true384:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i8, ptr [[CD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV385:%.*]] = sext i8 [[TMP177]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END388:%.*]]
|
|
// SIMD-ONLY0: cond.false386:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV387:%.*]] = sext i8 [[TMP178]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END388]]
|
|
// SIMD-ONLY0: cond.end388:
|
|
// SIMD-ONLY0-NEXT: [[COND389:%.*]] = phi i32 [ [[CONV385]], [[COND_TRUE384]] ], [ [[CONV387]], [[COND_FALSE386]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV390:%.*]] = trunc i32 [[COND389]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV390]], ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i8, ptr [[CX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP179]], ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i8, ptr [[CV]], align 1
|
|
// SIMD-ONLY0-NEXT: ret i8 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @ucxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[UCX:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCV:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCE:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[UCD:%.*]] = alloca i8, align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP0]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV:%.*]] = zext i8 [[TMP1]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = zext i8 [[TMP2]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV3:%.*]] = zext i8 [[TMP3]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV4:%.*]] = zext i8 [[TMP4]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV5:%.*]] = trunc i32 [[COND]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV5]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP5]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV6:%.*]] = zext i8 [[TMP6]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV7:%.*]] = zext i8 [[TMP7]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
|
|
// SIMD-ONLY0: cond.true10:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV11:%.*]] = zext i8 [[TMP8]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false12:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV13:%.*]] = zext i8 [[TMP9]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV16:%.*]] = trunc i32 [[COND15]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV16]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP10]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV17:%.*]] = zext i8 [[TMP11]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV18:%.*]] = zext i8 [[TMP12]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP19:%.*]] = icmp eq i32 [[CONV17]], [[CONV18]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true21:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV22:%.*]] = zext i8 [[TMP13]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV24:%.*]] = zext i8 [[TMP14]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25]]
|
|
// SIMD-ONLY0: cond.end25:
|
|
// SIMD-ONLY0-NEXT: [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV27:%.*]] = trunc i32 [[COND26]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV27]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV28:%.*]] = zext i8 [[TMP15]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV29:%.*]] = zext i8 [[TMP16]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP30:%.*]] = icmp sgt i32 [[CONV28]], [[CONV29]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV33:%.*]] = zext i8 [[TMP17]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36:%.*]]
|
|
// SIMD-ONLY0: cond.false34:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV35:%.*]] = zext i8 [[TMP18]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36]]
|
|
// SIMD-ONLY0: cond.end36:
|
|
// SIMD-ONLY0-NEXT: [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV38:%.*]] = trunc i32 [[COND37]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV38]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP19]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV39:%.*]] = zext i8 [[TMP20]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV40:%.*]] = zext i8 [[TMP21]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp slt i32 [[CONV39]], [[CONV40]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE43:%.*]], label [[COND_FALSE45:%.*]]
|
|
// SIMD-ONLY0: cond.true43:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV44:%.*]] = zext i8 [[TMP22]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END47:%.*]]
|
|
// SIMD-ONLY0: cond.false45:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV46:%.*]] = zext i8 [[TMP23]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END47]]
|
|
// SIMD-ONLY0: cond.end47:
|
|
// SIMD-ONLY0-NEXT: [[COND48:%.*]] = phi i32 [ [[CONV44]], [[COND_TRUE43]] ], [ [[CONV46]], [[COND_FALSE45]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV49:%.*]] = trunc i32 [[COND48]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV49]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP24]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV50:%.*]] = zext i8 [[TMP25]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV51:%.*]] = zext i8 [[TMP26]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP52:%.*]] = icmp eq i32 [[CONV50]], [[CONV51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP52]], label [[COND_TRUE54:%.*]], label [[COND_FALSE56:%.*]]
|
|
// SIMD-ONLY0: cond.true54:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV55:%.*]] = zext i8 [[TMP27]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END58:%.*]]
|
|
// SIMD-ONLY0: cond.false56:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV57:%.*]] = zext i8 [[TMP28]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END58]]
|
|
// SIMD-ONLY0: cond.end58:
|
|
// SIMD-ONLY0-NEXT: [[COND59:%.*]] = phi i32 [ [[CONV55]], [[COND_TRUE54]] ], [ [[CONV57]], [[COND_FALSE56]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV60:%.*]] = trunc i32 [[COND59]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV60]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP29]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP30]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV61:%.*]] = zext i8 [[TMP31]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV62:%.*]] = zext i8 [[TMP32]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP63:%.*]] = icmp sgt i32 [[CONV61]], [[CONV62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
|
|
// SIMD-ONLY0: cond.true65:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV66:%.*]] = zext i8 [[TMP33]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false67:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV68:%.*]] = zext i8 [[TMP34]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV71:%.*]] = trunc i32 [[COND70]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV71]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP35]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV72:%.*]] = zext i8 [[TMP36]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV73:%.*]] = zext i8 [[TMP37]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP74:%.*]] = icmp slt i32 [[CONV72]], [[CONV73]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true76:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV77:%.*]] = zext i8 [[TMP38]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV79:%.*]] = zext i8 [[TMP39]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80]]
|
|
// SIMD-ONLY0: cond.end80:
|
|
// SIMD-ONLY0-NEXT: [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV82:%.*]] = trunc i32 [[COND81]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV82]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP40]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV83:%.*]] = zext i8 [[TMP41]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV84:%.*]] = zext i8 [[TMP42]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP85]], label [[COND_TRUE87:%.*]], label [[COND_FALSE89:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV88:%.*]] = zext i8 [[TMP43]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END91:%.*]]
|
|
// SIMD-ONLY0: cond.false89:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV90:%.*]] = zext i8 [[TMP44]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END91]]
|
|
// SIMD-ONLY0: cond.end91:
|
|
// SIMD-ONLY0-NEXT: [[COND92:%.*]] = phi i32 [ [[CONV88]], [[COND_TRUE87]] ], [ [[CONV90]], [[COND_FALSE89]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV93:%.*]] = trunc i32 [[COND92]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV93]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV94:%.*]] = zext i8 [[TMP45]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV95:%.*]] = zext i8 [[TMP46]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp sgt i32 [[CONV94]], [[CONV95]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE98:%.*]], label [[COND_FALSE100:%.*]]
|
|
// SIMD-ONLY0: cond.true98:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV99:%.*]] = zext i8 [[TMP47]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END102:%.*]]
|
|
// SIMD-ONLY0: cond.false100:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV101:%.*]] = zext i8 [[TMP48]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END102]]
|
|
// SIMD-ONLY0: cond.end102:
|
|
// SIMD-ONLY0-NEXT: [[COND103:%.*]] = phi i32 [ [[CONV99]], [[COND_TRUE98]] ], [ [[CONV101]], [[COND_FALSE100]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV104:%.*]] = trunc i32 [[COND103]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV104]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP49]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV105:%.*]] = zext i8 [[TMP50]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV106:%.*]] = zext i8 [[TMP51]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP107:%.*]] = icmp slt i32 [[CONV105]], [[CONV106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP107]], label [[COND_TRUE109:%.*]], label [[COND_FALSE111:%.*]]
|
|
// SIMD-ONLY0: cond.true109:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV110:%.*]] = zext i8 [[TMP52]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END113:%.*]]
|
|
// SIMD-ONLY0: cond.false111:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV112:%.*]] = zext i8 [[TMP53]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END113]]
|
|
// SIMD-ONLY0: cond.end113:
|
|
// SIMD-ONLY0-NEXT: [[COND114:%.*]] = phi i32 [ [[CONV110]], [[COND_TRUE109]] ], [ [[CONV112]], [[COND_FALSE111]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV115:%.*]] = trunc i32 [[COND114]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV115]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP54]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV116:%.*]] = zext i8 [[TMP55]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV117:%.*]] = zext i8 [[TMP56]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP118:%.*]] = icmp eq i32 [[CONV116]], [[CONV117]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP118]], label [[COND_TRUE120:%.*]], label [[COND_FALSE122:%.*]]
|
|
// SIMD-ONLY0: cond.true120:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV121:%.*]] = zext i8 [[TMP57]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false122:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV123:%.*]] = zext i8 [[TMP58]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i32 [ [[CONV121]], [[COND_TRUE120]] ], [ [[CONV123]], [[COND_FALSE122]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV126:%.*]] = trunc i32 [[COND125]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV126]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP59]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP60]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV127:%.*]] = zext i8 [[TMP61]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV128:%.*]] = zext i8 [[TMP62]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP129:%.*]] = icmp sgt i32 [[CONV127]], [[CONV128]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP129]], label [[COND_TRUE131:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true131:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV132:%.*]] = zext i8 [[TMP63]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END135:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV134:%.*]] = zext i8 [[TMP64]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END135]]
|
|
// SIMD-ONLY0: cond.end135:
|
|
// SIMD-ONLY0-NEXT: [[COND136:%.*]] = phi i32 [ [[CONV132]], [[COND_TRUE131]] ], [ [[CONV134]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV137:%.*]] = trunc i32 [[COND136]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV137]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP65]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV138:%.*]] = zext i8 [[TMP66]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV139:%.*]] = zext i8 [[TMP67]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP140:%.*]] = icmp slt i32 [[CONV138]], [[CONV139]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP140]], label [[COND_TRUE142:%.*]], label [[COND_FALSE144:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV143:%.*]] = zext i8 [[TMP68]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END146:%.*]]
|
|
// SIMD-ONLY0: cond.false144:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV145:%.*]] = zext i8 [[TMP69]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END146]]
|
|
// SIMD-ONLY0: cond.end146:
|
|
// SIMD-ONLY0-NEXT: [[COND147:%.*]] = phi i32 [ [[CONV143]], [[COND_TRUE142]] ], [ [[CONV145]], [[COND_FALSE144]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV148:%.*]] = trunc i32 [[COND147]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV148]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP70]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV149:%.*]] = zext i8 [[TMP71]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV150:%.*]] = zext i8 [[TMP72]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp eq i32 [[CONV149]], [[CONV150]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE153:%.*]], label [[COND_FALSE155:%.*]]
|
|
// SIMD-ONLY0: cond.true153:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV154:%.*]] = zext i8 [[TMP73]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END157:%.*]]
|
|
// SIMD-ONLY0: cond.false155:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV156:%.*]] = zext i8 [[TMP74]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END157]]
|
|
// SIMD-ONLY0: cond.end157:
|
|
// SIMD-ONLY0-NEXT: [[COND158:%.*]] = phi i32 [ [[CONV154]], [[COND_TRUE153]] ], [ [[CONV156]], [[COND_FALSE155]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV159:%.*]] = trunc i32 [[COND158]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV159]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV160:%.*]] = zext i8 [[TMP75]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV161:%.*]] = zext i8 [[TMP76]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP162:%.*]] = icmp sgt i32 [[CONV160]], [[CONV161]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP162]], label [[COND_TRUE164:%.*]], label [[COND_FALSE166:%.*]]
|
|
// SIMD-ONLY0: cond.true164:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV165:%.*]] = zext i8 [[TMP77]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END168:%.*]]
|
|
// SIMD-ONLY0: cond.false166:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV167:%.*]] = zext i8 [[TMP78]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END168]]
|
|
// SIMD-ONLY0: cond.end168:
|
|
// SIMD-ONLY0-NEXT: [[COND169:%.*]] = phi i32 [ [[CONV165]], [[COND_TRUE164]] ], [ [[CONV167]], [[COND_FALSE166]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV170:%.*]] = trunc i32 [[COND169]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV170]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP79]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV171:%.*]] = zext i8 [[TMP80]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV172:%.*]] = zext i8 [[TMP81]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP173:%.*]] = icmp slt i32 [[CONV171]], [[CONV172]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP173]], label [[COND_TRUE175:%.*]], label [[COND_FALSE177:%.*]]
|
|
// SIMD-ONLY0: cond.true175:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV176:%.*]] = zext i8 [[TMP82]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END179:%.*]]
|
|
// SIMD-ONLY0: cond.false177:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV178:%.*]] = zext i8 [[TMP83]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END179]]
|
|
// SIMD-ONLY0: cond.end179:
|
|
// SIMD-ONLY0-NEXT: [[COND180:%.*]] = phi i32 [ [[CONV176]], [[COND_TRUE175]] ], [ [[CONV178]], [[COND_FALSE177]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV181:%.*]] = trunc i32 [[COND180]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV181]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP84]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV182:%.*]] = zext i8 [[TMP85]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV183:%.*]] = zext i8 [[TMP86]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP184:%.*]] = icmp eq i32 [[CONV182]], [[CONV183]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP184]], label [[COND_TRUE186:%.*]], label [[COND_FALSE188:%.*]]
|
|
// SIMD-ONLY0: cond.true186:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV187:%.*]] = zext i8 [[TMP87]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END190:%.*]]
|
|
// SIMD-ONLY0: cond.false188:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV189:%.*]] = zext i8 [[TMP88]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END190]]
|
|
// SIMD-ONLY0: cond.end190:
|
|
// SIMD-ONLY0-NEXT: [[COND191:%.*]] = phi i32 [ [[CONV187]], [[COND_TRUE186]] ], [ [[CONV189]], [[COND_FALSE188]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV192:%.*]] = trunc i32 [[COND191]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV192]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP89]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP90]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV193:%.*]] = zext i8 [[TMP91]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV194:%.*]] = zext i8 [[TMP92]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP195:%.*]] = icmp sgt i32 [[CONV193]], [[CONV194]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP195]], label [[COND_TRUE197:%.*]], label [[COND_FALSE199:%.*]]
|
|
// SIMD-ONLY0: cond.true197:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV198:%.*]] = zext i8 [[TMP93]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END201:%.*]]
|
|
// SIMD-ONLY0: cond.false199:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV200:%.*]] = zext i8 [[TMP94]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END201]]
|
|
// SIMD-ONLY0: cond.end201:
|
|
// SIMD-ONLY0-NEXT: [[COND202:%.*]] = phi i32 [ [[CONV198]], [[COND_TRUE197]] ], [ [[CONV200]], [[COND_FALSE199]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV203:%.*]] = trunc i32 [[COND202]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV203]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP95]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV204:%.*]] = zext i8 [[TMP96]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV205:%.*]] = zext i8 [[TMP97]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP206:%.*]] = icmp slt i32 [[CONV204]], [[CONV205]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP206]], label [[COND_TRUE208:%.*]], label [[COND_FALSE210:%.*]]
|
|
// SIMD-ONLY0: cond.true208:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV209:%.*]] = zext i8 [[TMP98]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END212:%.*]]
|
|
// SIMD-ONLY0: cond.false210:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV211:%.*]] = zext i8 [[TMP99]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END212]]
|
|
// SIMD-ONLY0: cond.end212:
|
|
// SIMD-ONLY0-NEXT: [[COND213:%.*]] = phi i32 [ [[CONV209]], [[COND_TRUE208]] ], [ [[CONV211]], [[COND_FALSE210]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV214:%.*]] = trunc i32 [[COND213]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV214]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP100]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV215:%.*]] = zext i8 [[TMP101]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV216:%.*]] = zext i8 [[TMP102]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP217:%.*]] = icmp eq i32 [[CONV215]], [[CONV216]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP217]], label [[COND_TRUE219:%.*]], label [[COND_FALSE221:%.*]]
|
|
// SIMD-ONLY0: cond.true219:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV220:%.*]] = zext i8 [[TMP103]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END223:%.*]]
|
|
// SIMD-ONLY0: cond.false221:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV222:%.*]] = zext i8 [[TMP104]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END223]]
|
|
// SIMD-ONLY0: cond.end223:
|
|
// SIMD-ONLY0-NEXT: [[COND224:%.*]] = phi i32 [ [[CONV220]], [[COND_TRUE219]] ], [ [[CONV222]], [[COND_FALSE221]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV225:%.*]] = trunc i32 [[COND224]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV225]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV226:%.*]] = zext i8 [[TMP105]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV227:%.*]] = zext i8 [[TMP106]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP228:%.*]] = icmp sgt i32 [[CONV226]], [[CONV227]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP228]], label [[COND_TRUE230:%.*]], label [[COND_FALSE232:%.*]]
|
|
// SIMD-ONLY0: cond.true230:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV231:%.*]] = zext i8 [[TMP107]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END234:%.*]]
|
|
// SIMD-ONLY0: cond.false232:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV233:%.*]] = zext i8 [[TMP108]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END234]]
|
|
// SIMD-ONLY0: cond.end234:
|
|
// SIMD-ONLY0-NEXT: [[COND235:%.*]] = phi i32 [ [[CONV231]], [[COND_TRUE230]] ], [ [[CONV233]], [[COND_FALSE232]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV236:%.*]] = trunc i32 [[COND235]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV236]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP109]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV237:%.*]] = zext i8 [[TMP110]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV238:%.*]] = zext i8 [[TMP111]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP239:%.*]] = icmp slt i32 [[CONV237]], [[CONV238]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP239]], label [[COND_TRUE241:%.*]], label [[COND_FALSE243:%.*]]
|
|
// SIMD-ONLY0: cond.true241:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV242:%.*]] = zext i8 [[TMP112]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END245:%.*]]
|
|
// SIMD-ONLY0: cond.false243:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV244:%.*]] = zext i8 [[TMP113]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END245]]
|
|
// SIMD-ONLY0: cond.end245:
|
|
// SIMD-ONLY0-NEXT: [[COND246:%.*]] = phi i32 [ [[CONV242]], [[COND_TRUE241]] ], [ [[CONV244]], [[COND_FALSE243]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV247:%.*]] = trunc i32 [[COND246]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV247]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP114]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV248:%.*]] = zext i8 [[TMP115]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV249:%.*]] = zext i8 [[TMP116]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP250:%.*]] = icmp eq i32 [[CONV248]], [[CONV249]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP250]], label [[COND_TRUE252:%.*]], label [[COND_FALSE254:%.*]]
|
|
// SIMD-ONLY0: cond.true252:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV253:%.*]] = zext i8 [[TMP117]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END256:%.*]]
|
|
// SIMD-ONLY0: cond.false254:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV255:%.*]] = zext i8 [[TMP118]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END256]]
|
|
// SIMD-ONLY0: cond.end256:
|
|
// SIMD-ONLY0-NEXT: [[COND257:%.*]] = phi i32 [ [[CONV253]], [[COND_TRUE252]] ], [ [[CONV255]], [[COND_FALSE254]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV258:%.*]] = trunc i32 [[COND257]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV258]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP119]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP120]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV259:%.*]] = zext i8 [[TMP121]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV260:%.*]] = zext i8 [[TMP122]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP261:%.*]] = icmp sgt i32 [[CONV259]], [[CONV260]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP261]], label [[COND_TRUE263:%.*]], label [[COND_FALSE265:%.*]]
|
|
// SIMD-ONLY0: cond.true263:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV264:%.*]] = zext i8 [[TMP123]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END267:%.*]]
|
|
// SIMD-ONLY0: cond.false265:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV266:%.*]] = zext i8 [[TMP124]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END267]]
|
|
// SIMD-ONLY0: cond.end267:
|
|
// SIMD-ONLY0-NEXT: [[COND268:%.*]] = phi i32 [ [[CONV264]], [[COND_TRUE263]] ], [ [[CONV266]], [[COND_FALSE265]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV269:%.*]] = trunc i32 [[COND268]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV269]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP125]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV270:%.*]] = zext i8 [[TMP126]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV271:%.*]] = zext i8 [[TMP127]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP272:%.*]] = icmp slt i32 [[CONV270]], [[CONV271]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP272]], label [[COND_TRUE274:%.*]], label [[COND_FALSE276:%.*]]
|
|
// SIMD-ONLY0: cond.true274:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV275:%.*]] = zext i8 [[TMP128]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END278:%.*]]
|
|
// SIMD-ONLY0: cond.false276:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV277:%.*]] = zext i8 [[TMP129]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END278]]
|
|
// SIMD-ONLY0: cond.end278:
|
|
// SIMD-ONLY0-NEXT: [[COND279:%.*]] = phi i32 [ [[CONV275]], [[COND_TRUE274]] ], [ [[CONV277]], [[COND_FALSE276]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV280:%.*]] = trunc i32 [[COND279]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV280]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP130]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV281:%.*]] = zext i8 [[TMP131]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV282:%.*]] = zext i8 [[TMP132]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP283:%.*]] = icmp eq i32 [[CONV281]], [[CONV282]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP283]], label [[COND_TRUE285:%.*]], label [[COND_FALSE287:%.*]]
|
|
// SIMD-ONLY0: cond.true285:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV286:%.*]] = zext i8 [[TMP133]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END289:%.*]]
|
|
// SIMD-ONLY0: cond.false287:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV288:%.*]] = zext i8 [[TMP134]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END289]]
|
|
// SIMD-ONLY0: cond.end289:
|
|
// SIMD-ONLY0-NEXT: [[COND290:%.*]] = phi i32 [ [[CONV286]], [[COND_TRUE285]] ], [ [[CONV288]], [[COND_FALSE287]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV291:%.*]] = trunc i32 [[COND290]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV291]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV292:%.*]] = zext i8 [[TMP135]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV293:%.*]] = zext i8 [[TMP136]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP294:%.*]] = icmp sgt i32 [[CONV292]], [[CONV293]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP294]], label [[COND_TRUE296:%.*]], label [[COND_FALSE298:%.*]]
|
|
// SIMD-ONLY0: cond.true296:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV297:%.*]] = zext i8 [[TMP137]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END300:%.*]]
|
|
// SIMD-ONLY0: cond.false298:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV299:%.*]] = zext i8 [[TMP138]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END300]]
|
|
// SIMD-ONLY0: cond.end300:
|
|
// SIMD-ONLY0-NEXT: [[COND301:%.*]] = phi i32 [ [[CONV297]], [[COND_TRUE296]] ], [ [[CONV299]], [[COND_FALSE298]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV302:%.*]] = trunc i32 [[COND301]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV302]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP139]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV303:%.*]] = zext i8 [[TMP140]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV304:%.*]] = zext i8 [[TMP141]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP305:%.*]] = icmp slt i32 [[CONV303]], [[CONV304]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP305]], label [[COND_TRUE307:%.*]], label [[COND_FALSE309:%.*]]
|
|
// SIMD-ONLY0: cond.true307:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV308:%.*]] = zext i8 [[TMP142]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END311:%.*]]
|
|
// SIMD-ONLY0: cond.false309:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV310:%.*]] = zext i8 [[TMP143]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END311]]
|
|
// SIMD-ONLY0: cond.end311:
|
|
// SIMD-ONLY0-NEXT: [[COND312:%.*]] = phi i32 [ [[CONV308]], [[COND_TRUE307]] ], [ [[CONV310]], [[COND_FALSE309]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV313:%.*]] = trunc i32 [[COND312]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV313]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP144]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV314:%.*]] = zext i8 [[TMP145]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV315:%.*]] = zext i8 [[TMP146]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP316]], label [[COND_TRUE318:%.*]], label [[COND_FALSE320:%.*]]
|
|
// SIMD-ONLY0: cond.true318:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV319:%.*]] = zext i8 [[TMP147]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END322:%.*]]
|
|
// SIMD-ONLY0: cond.false320:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV321:%.*]] = zext i8 [[TMP148]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END322]]
|
|
// SIMD-ONLY0: cond.end322:
|
|
// SIMD-ONLY0-NEXT: [[COND323:%.*]] = phi i32 [ [[CONV319]], [[COND_TRUE318]] ], [ [[CONV321]], [[COND_FALSE320]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV324:%.*]] = trunc i32 [[COND323]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV324]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP149]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP150]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV325:%.*]] = zext i8 [[TMP151]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV326:%.*]] = zext i8 [[TMP152]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP327:%.*]] = icmp sgt i32 [[CONV325]], [[CONV326]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP327]], label [[COND_TRUE329:%.*]], label [[COND_FALSE331:%.*]]
|
|
// SIMD-ONLY0: cond.true329:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV330:%.*]] = zext i8 [[TMP153]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END333:%.*]]
|
|
// SIMD-ONLY0: cond.false331:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV332:%.*]] = zext i8 [[TMP154]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END333]]
|
|
// SIMD-ONLY0: cond.end333:
|
|
// SIMD-ONLY0-NEXT: [[COND334:%.*]] = phi i32 [ [[CONV330]], [[COND_TRUE329]] ], [ [[CONV332]], [[COND_FALSE331]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV335:%.*]] = trunc i32 [[COND334]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV335]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP155]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV336:%.*]] = zext i8 [[TMP156]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV337:%.*]] = zext i8 [[TMP157]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP338:%.*]] = icmp slt i32 [[CONV336]], [[CONV337]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP338]], label [[COND_TRUE340:%.*]], label [[COND_FALSE342:%.*]]
|
|
// SIMD-ONLY0: cond.true340:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV341:%.*]] = zext i8 [[TMP158]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END344:%.*]]
|
|
// SIMD-ONLY0: cond.false342:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV343:%.*]] = zext i8 [[TMP159]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END344]]
|
|
// SIMD-ONLY0: cond.end344:
|
|
// SIMD-ONLY0-NEXT: [[COND345:%.*]] = phi i32 [ [[CONV341]], [[COND_TRUE340]] ], [ [[CONV343]], [[COND_FALSE342]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV346:%.*]] = trunc i32 [[COND345]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV346]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP160]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV347:%.*]] = zext i8 [[TMP161]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV348:%.*]] = zext i8 [[TMP162]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP349:%.*]] = icmp eq i32 [[CONV347]], [[CONV348]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP349]], label [[COND_TRUE351:%.*]], label [[COND_FALSE353:%.*]]
|
|
// SIMD-ONLY0: cond.true351:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV352:%.*]] = zext i8 [[TMP163]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END355:%.*]]
|
|
// SIMD-ONLY0: cond.false353:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV354:%.*]] = zext i8 [[TMP164]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END355]]
|
|
// SIMD-ONLY0: cond.end355:
|
|
// SIMD-ONLY0-NEXT: [[COND356:%.*]] = phi i32 [ [[CONV352]], [[COND_TRUE351]] ], [ [[CONV354]], [[COND_FALSE353]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV357:%.*]] = trunc i32 [[COND356]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV357]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV358:%.*]] = zext i8 [[TMP165]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV359:%.*]] = zext i8 [[TMP166]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP360:%.*]] = icmp sgt i32 [[CONV358]], [[CONV359]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP360]], label [[COND_TRUE362:%.*]], label [[COND_FALSE364:%.*]]
|
|
// SIMD-ONLY0: cond.true362:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV363:%.*]] = zext i8 [[TMP167]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END366:%.*]]
|
|
// SIMD-ONLY0: cond.false364:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV365:%.*]] = zext i8 [[TMP168]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END366]]
|
|
// SIMD-ONLY0: cond.end366:
|
|
// SIMD-ONLY0-NEXT: [[COND367:%.*]] = phi i32 [ [[CONV363]], [[COND_TRUE362]] ], [ [[CONV365]], [[COND_FALSE364]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV368:%.*]] = trunc i32 [[COND367]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV368]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP169]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV369:%.*]] = zext i8 [[TMP170]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV370:%.*]] = zext i8 [[TMP171]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP371:%.*]] = icmp slt i32 [[CONV369]], [[CONV370]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP371]], label [[COND_TRUE373:%.*]], label [[COND_FALSE375:%.*]]
|
|
// SIMD-ONLY0: cond.true373:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV374:%.*]] = zext i8 [[TMP172]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END377:%.*]]
|
|
// SIMD-ONLY0: cond.false375:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV376:%.*]] = zext i8 [[TMP173]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END377]]
|
|
// SIMD-ONLY0: cond.end377:
|
|
// SIMD-ONLY0-NEXT: [[COND378:%.*]] = phi i32 [ [[CONV374]], [[COND_TRUE373]] ], [ [[CONV376]], [[COND_FALSE375]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV379:%.*]] = trunc i32 [[COND378]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV379]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP174]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV380:%.*]] = zext i8 [[TMP175]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i8, ptr [[UCE]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV381:%.*]] = zext i8 [[TMP176]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP382:%.*]] = icmp eq i32 [[CONV380]], [[CONV381]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP382]], label [[COND_TRUE384:%.*]], label [[COND_FALSE386:%.*]]
|
|
// SIMD-ONLY0: cond.true384:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i8, ptr [[UCD]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV385:%.*]] = zext i8 [[TMP177]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END388:%.*]]
|
|
// SIMD-ONLY0: cond.false386:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[CONV387:%.*]] = zext i8 [[TMP178]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END388]]
|
|
// SIMD-ONLY0: cond.end388:
|
|
// SIMD-ONLY0-NEXT: [[COND389:%.*]] = phi i32 [ [[CONV385]], [[COND_TRUE384]] ], [ [[CONV387]], [[COND_FALSE386]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV390:%.*]] = trunc i32 [[COND389]] to i8
|
|
// SIMD-ONLY0-NEXT: store i8 [[CONV390]], ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i8, ptr [[UCX]], align 1
|
|
// SIMD-ONLY0-NEXT: store i8 [[TMP179]], ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i8, ptr [[UCV]], align 1
|
|
// SIMD-ONLY0-NEXT: ret i8 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @sxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[SX:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[SV:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[SE:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[SD:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP0]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV3:%.*]] = sext i16 [[TMP3]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV4:%.*]] = sext i16 [[TMP4]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV5:%.*]] = trunc i32 [[COND]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV5]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP5]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV6:%.*]] = sext i16 [[TMP6]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV7:%.*]] = sext i16 [[TMP7]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
|
|
// SIMD-ONLY0: cond.true10:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV11:%.*]] = sext i16 [[TMP8]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false12:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV13:%.*]] = sext i16 [[TMP9]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV16:%.*]] = trunc i32 [[COND15]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV16]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP10]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV17:%.*]] = sext i16 [[TMP11]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV18:%.*]] = sext i16 [[TMP12]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP19:%.*]] = icmp eq i32 [[CONV17]], [[CONV18]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true21:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV22:%.*]] = sext i16 [[TMP13]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV24:%.*]] = sext i16 [[TMP14]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25]]
|
|
// SIMD-ONLY0: cond.end25:
|
|
// SIMD-ONLY0-NEXT: [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV27:%.*]] = trunc i32 [[COND26]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV27]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV28:%.*]] = sext i16 [[TMP15]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV29:%.*]] = sext i16 [[TMP16]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP30:%.*]] = icmp sgt i32 [[CONV28]], [[CONV29]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV33:%.*]] = sext i16 [[TMP17]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36:%.*]]
|
|
// SIMD-ONLY0: cond.false34:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV35:%.*]] = sext i16 [[TMP18]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36]]
|
|
// SIMD-ONLY0: cond.end36:
|
|
// SIMD-ONLY0-NEXT: [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV38:%.*]] = trunc i32 [[COND37]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV38]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP19]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV39:%.*]] = sext i16 [[TMP20]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV40:%.*]] = sext i16 [[TMP21]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp slt i32 [[CONV39]], [[CONV40]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE43:%.*]], label [[COND_FALSE45:%.*]]
|
|
// SIMD-ONLY0: cond.true43:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV44:%.*]] = sext i16 [[TMP22]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END47:%.*]]
|
|
// SIMD-ONLY0: cond.false45:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV46:%.*]] = sext i16 [[TMP23]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END47]]
|
|
// SIMD-ONLY0: cond.end47:
|
|
// SIMD-ONLY0-NEXT: [[COND48:%.*]] = phi i32 [ [[CONV44]], [[COND_TRUE43]] ], [ [[CONV46]], [[COND_FALSE45]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV49:%.*]] = trunc i32 [[COND48]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV49]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP24]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV50:%.*]] = sext i16 [[TMP25]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV51:%.*]] = sext i16 [[TMP26]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP52:%.*]] = icmp eq i32 [[CONV50]], [[CONV51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP52]], label [[COND_TRUE54:%.*]], label [[COND_FALSE56:%.*]]
|
|
// SIMD-ONLY0: cond.true54:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV55:%.*]] = sext i16 [[TMP27]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END58:%.*]]
|
|
// SIMD-ONLY0: cond.false56:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV57:%.*]] = sext i16 [[TMP28]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END58]]
|
|
// SIMD-ONLY0: cond.end58:
|
|
// SIMD-ONLY0-NEXT: [[COND59:%.*]] = phi i32 [ [[CONV55]], [[COND_TRUE54]] ], [ [[CONV57]], [[COND_FALSE56]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV60:%.*]] = trunc i32 [[COND59]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV60]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP29]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP30]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV61:%.*]] = sext i16 [[TMP31]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV62:%.*]] = sext i16 [[TMP32]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP63:%.*]] = icmp sgt i32 [[CONV61]], [[CONV62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
|
|
// SIMD-ONLY0: cond.true65:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV66:%.*]] = sext i16 [[TMP33]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false67:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV68:%.*]] = sext i16 [[TMP34]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV71:%.*]] = trunc i32 [[COND70]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV71]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP35]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV72:%.*]] = sext i16 [[TMP36]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV73:%.*]] = sext i16 [[TMP37]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP74:%.*]] = icmp slt i32 [[CONV72]], [[CONV73]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true76:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV77:%.*]] = sext i16 [[TMP38]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV79:%.*]] = sext i16 [[TMP39]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80]]
|
|
// SIMD-ONLY0: cond.end80:
|
|
// SIMD-ONLY0-NEXT: [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV82:%.*]] = trunc i32 [[COND81]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV82]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP40]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV83:%.*]] = sext i16 [[TMP41]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV84:%.*]] = sext i16 [[TMP42]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP85]], label [[COND_TRUE87:%.*]], label [[COND_FALSE89:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV88:%.*]] = sext i16 [[TMP43]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END91:%.*]]
|
|
// SIMD-ONLY0: cond.false89:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV90:%.*]] = sext i16 [[TMP44]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END91]]
|
|
// SIMD-ONLY0: cond.end91:
|
|
// SIMD-ONLY0-NEXT: [[COND92:%.*]] = phi i32 [ [[CONV88]], [[COND_TRUE87]] ], [ [[CONV90]], [[COND_FALSE89]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV93:%.*]] = trunc i32 [[COND92]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV93]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV94:%.*]] = sext i16 [[TMP45]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV95:%.*]] = sext i16 [[TMP46]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp sgt i32 [[CONV94]], [[CONV95]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE98:%.*]], label [[COND_FALSE100:%.*]]
|
|
// SIMD-ONLY0: cond.true98:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV99:%.*]] = sext i16 [[TMP47]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END102:%.*]]
|
|
// SIMD-ONLY0: cond.false100:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV101:%.*]] = sext i16 [[TMP48]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END102]]
|
|
// SIMD-ONLY0: cond.end102:
|
|
// SIMD-ONLY0-NEXT: [[COND103:%.*]] = phi i32 [ [[CONV99]], [[COND_TRUE98]] ], [ [[CONV101]], [[COND_FALSE100]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV104:%.*]] = trunc i32 [[COND103]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV104]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP49]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV105:%.*]] = sext i16 [[TMP50]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV106:%.*]] = sext i16 [[TMP51]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP107:%.*]] = icmp slt i32 [[CONV105]], [[CONV106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP107]], label [[COND_TRUE109:%.*]], label [[COND_FALSE111:%.*]]
|
|
// SIMD-ONLY0: cond.true109:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV110:%.*]] = sext i16 [[TMP52]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END113:%.*]]
|
|
// SIMD-ONLY0: cond.false111:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV112:%.*]] = sext i16 [[TMP53]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END113]]
|
|
// SIMD-ONLY0: cond.end113:
|
|
// SIMD-ONLY0-NEXT: [[COND114:%.*]] = phi i32 [ [[CONV110]], [[COND_TRUE109]] ], [ [[CONV112]], [[COND_FALSE111]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV115:%.*]] = trunc i32 [[COND114]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV115]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP54]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV116:%.*]] = sext i16 [[TMP55]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV117:%.*]] = sext i16 [[TMP56]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP118:%.*]] = icmp eq i32 [[CONV116]], [[CONV117]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP118]], label [[COND_TRUE120:%.*]], label [[COND_FALSE122:%.*]]
|
|
// SIMD-ONLY0: cond.true120:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV121:%.*]] = sext i16 [[TMP57]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false122:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV123:%.*]] = sext i16 [[TMP58]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i32 [ [[CONV121]], [[COND_TRUE120]] ], [ [[CONV123]], [[COND_FALSE122]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV126:%.*]] = trunc i32 [[COND125]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV126]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP59]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP60]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV127:%.*]] = sext i16 [[TMP61]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV128:%.*]] = sext i16 [[TMP62]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP129:%.*]] = icmp sgt i32 [[CONV127]], [[CONV128]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP129]], label [[COND_TRUE131:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true131:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV132:%.*]] = sext i16 [[TMP63]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END135:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV134:%.*]] = sext i16 [[TMP64]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END135]]
|
|
// SIMD-ONLY0: cond.end135:
|
|
// SIMD-ONLY0-NEXT: [[COND136:%.*]] = phi i32 [ [[CONV132]], [[COND_TRUE131]] ], [ [[CONV134]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV137:%.*]] = trunc i32 [[COND136]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV137]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP65]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV138:%.*]] = sext i16 [[TMP66]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV139:%.*]] = sext i16 [[TMP67]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP140:%.*]] = icmp slt i32 [[CONV138]], [[CONV139]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP140]], label [[COND_TRUE142:%.*]], label [[COND_FALSE144:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV143:%.*]] = sext i16 [[TMP68]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END146:%.*]]
|
|
// SIMD-ONLY0: cond.false144:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV145:%.*]] = sext i16 [[TMP69]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END146]]
|
|
// SIMD-ONLY0: cond.end146:
|
|
// SIMD-ONLY0-NEXT: [[COND147:%.*]] = phi i32 [ [[CONV143]], [[COND_TRUE142]] ], [ [[CONV145]], [[COND_FALSE144]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV148:%.*]] = trunc i32 [[COND147]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV148]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP70]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV149:%.*]] = sext i16 [[TMP71]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV150:%.*]] = sext i16 [[TMP72]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp eq i32 [[CONV149]], [[CONV150]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE153:%.*]], label [[COND_FALSE155:%.*]]
|
|
// SIMD-ONLY0: cond.true153:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV154:%.*]] = sext i16 [[TMP73]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END157:%.*]]
|
|
// SIMD-ONLY0: cond.false155:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV156:%.*]] = sext i16 [[TMP74]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END157]]
|
|
// SIMD-ONLY0: cond.end157:
|
|
// SIMD-ONLY0-NEXT: [[COND158:%.*]] = phi i32 [ [[CONV154]], [[COND_TRUE153]] ], [ [[CONV156]], [[COND_FALSE155]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV159:%.*]] = trunc i32 [[COND158]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV159]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV160:%.*]] = sext i16 [[TMP75]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV161:%.*]] = sext i16 [[TMP76]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP162:%.*]] = icmp sgt i32 [[CONV160]], [[CONV161]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP162]], label [[COND_TRUE164:%.*]], label [[COND_FALSE166:%.*]]
|
|
// SIMD-ONLY0: cond.true164:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV165:%.*]] = sext i16 [[TMP77]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END168:%.*]]
|
|
// SIMD-ONLY0: cond.false166:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV167:%.*]] = sext i16 [[TMP78]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END168]]
|
|
// SIMD-ONLY0: cond.end168:
|
|
// SIMD-ONLY0-NEXT: [[COND169:%.*]] = phi i32 [ [[CONV165]], [[COND_TRUE164]] ], [ [[CONV167]], [[COND_FALSE166]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV170:%.*]] = trunc i32 [[COND169]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV170]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP79]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV171:%.*]] = sext i16 [[TMP80]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV172:%.*]] = sext i16 [[TMP81]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP173:%.*]] = icmp slt i32 [[CONV171]], [[CONV172]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP173]], label [[COND_TRUE175:%.*]], label [[COND_FALSE177:%.*]]
|
|
// SIMD-ONLY0: cond.true175:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV176:%.*]] = sext i16 [[TMP82]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END179:%.*]]
|
|
// SIMD-ONLY0: cond.false177:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV178:%.*]] = sext i16 [[TMP83]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END179]]
|
|
// SIMD-ONLY0: cond.end179:
|
|
// SIMD-ONLY0-NEXT: [[COND180:%.*]] = phi i32 [ [[CONV176]], [[COND_TRUE175]] ], [ [[CONV178]], [[COND_FALSE177]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV181:%.*]] = trunc i32 [[COND180]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV181]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP84]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV182:%.*]] = sext i16 [[TMP85]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV183:%.*]] = sext i16 [[TMP86]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP184:%.*]] = icmp eq i32 [[CONV182]], [[CONV183]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP184]], label [[COND_TRUE186:%.*]], label [[COND_FALSE188:%.*]]
|
|
// SIMD-ONLY0: cond.true186:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV187:%.*]] = sext i16 [[TMP87]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END190:%.*]]
|
|
// SIMD-ONLY0: cond.false188:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV189:%.*]] = sext i16 [[TMP88]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END190]]
|
|
// SIMD-ONLY0: cond.end190:
|
|
// SIMD-ONLY0-NEXT: [[COND191:%.*]] = phi i32 [ [[CONV187]], [[COND_TRUE186]] ], [ [[CONV189]], [[COND_FALSE188]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV192:%.*]] = trunc i32 [[COND191]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV192]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP89]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP90]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV193:%.*]] = sext i16 [[TMP91]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV194:%.*]] = sext i16 [[TMP92]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP195:%.*]] = icmp sgt i32 [[CONV193]], [[CONV194]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP195]], label [[COND_TRUE197:%.*]], label [[COND_FALSE199:%.*]]
|
|
// SIMD-ONLY0: cond.true197:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV198:%.*]] = sext i16 [[TMP93]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END201:%.*]]
|
|
// SIMD-ONLY0: cond.false199:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV200:%.*]] = sext i16 [[TMP94]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END201]]
|
|
// SIMD-ONLY0: cond.end201:
|
|
// SIMD-ONLY0-NEXT: [[COND202:%.*]] = phi i32 [ [[CONV198]], [[COND_TRUE197]] ], [ [[CONV200]], [[COND_FALSE199]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV203:%.*]] = trunc i32 [[COND202]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV203]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP95]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV204:%.*]] = sext i16 [[TMP96]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV205:%.*]] = sext i16 [[TMP97]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP206:%.*]] = icmp slt i32 [[CONV204]], [[CONV205]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP206]], label [[COND_TRUE208:%.*]], label [[COND_FALSE210:%.*]]
|
|
// SIMD-ONLY0: cond.true208:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV209:%.*]] = sext i16 [[TMP98]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END212:%.*]]
|
|
// SIMD-ONLY0: cond.false210:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV211:%.*]] = sext i16 [[TMP99]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END212]]
|
|
// SIMD-ONLY0: cond.end212:
|
|
// SIMD-ONLY0-NEXT: [[COND213:%.*]] = phi i32 [ [[CONV209]], [[COND_TRUE208]] ], [ [[CONV211]], [[COND_FALSE210]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV214:%.*]] = trunc i32 [[COND213]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV214]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP100]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV215:%.*]] = sext i16 [[TMP101]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV216:%.*]] = sext i16 [[TMP102]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP217:%.*]] = icmp eq i32 [[CONV215]], [[CONV216]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP217]], label [[COND_TRUE219:%.*]], label [[COND_FALSE221:%.*]]
|
|
// SIMD-ONLY0: cond.true219:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV220:%.*]] = sext i16 [[TMP103]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END223:%.*]]
|
|
// SIMD-ONLY0: cond.false221:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV222:%.*]] = sext i16 [[TMP104]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END223]]
|
|
// SIMD-ONLY0: cond.end223:
|
|
// SIMD-ONLY0-NEXT: [[COND224:%.*]] = phi i32 [ [[CONV220]], [[COND_TRUE219]] ], [ [[CONV222]], [[COND_FALSE221]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV225:%.*]] = trunc i32 [[COND224]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV225]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV226:%.*]] = sext i16 [[TMP105]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV227:%.*]] = sext i16 [[TMP106]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP228:%.*]] = icmp sgt i32 [[CONV226]], [[CONV227]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP228]], label [[COND_TRUE230:%.*]], label [[COND_FALSE232:%.*]]
|
|
// SIMD-ONLY0: cond.true230:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV231:%.*]] = sext i16 [[TMP107]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END234:%.*]]
|
|
// SIMD-ONLY0: cond.false232:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV233:%.*]] = sext i16 [[TMP108]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END234]]
|
|
// SIMD-ONLY0: cond.end234:
|
|
// SIMD-ONLY0-NEXT: [[COND235:%.*]] = phi i32 [ [[CONV231]], [[COND_TRUE230]] ], [ [[CONV233]], [[COND_FALSE232]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV236:%.*]] = trunc i32 [[COND235]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV236]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP109]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV237:%.*]] = sext i16 [[TMP110]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV238:%.*]] = sext i16 [[TMP111]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP239:%.*]] = icmp slt i32 [[CONV237]], [[CONV238]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP239]], label [[COND_TRUE241:%.*]], label [[COND_FALSE243:%.*]]
|
|
// SIMD-ONLY0: cond.true241:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV242:%.*]] = sext i16 [[TMP112]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END245:%.*]]
|
|
// SIMD-ONLY0: cond.false243:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV244:%.*]] = sext i16 [[TMP113]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END245]]
|
|
// SIMD-ONLY0: cond.end245:
|
|
// SIMD-ONLY0-NEXT: [[COND246:%.*]] = phi i32 [ [[CONV242]], [[COND_TRUE241]] ], [ [[CONV244]], [[COND_FALSE243]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV247:%.*]] = trunc i32 [[COND246]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV247]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP114]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV248:%.*]] = sext i16 [[TMP115]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV249:%.*]] = sext i16 [[TMP116]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP250:%.*]] = icmp eq i32 [[CONV248]], [[CONV249]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP250]], label [[COND_TRUE252:%.*]], label [[COND_FALSE254:%.*]]
|
|
// SIMD-ONLY0: cond.true252:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV253:%.*]] = sext i16 [[TMP117]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END256:%.*]]
|
|
// SIMD-ONLY0: cond.false254:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV255:%.*]] = sext i16 [[TMP118]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END256]]
|
|
// SIMD-ONLY0: cond.end256:
|
|
// SIMD-ONLY0-NEXT: [[COND257:%.*]] = phi i32 [ [[CONV253]], [[COND_TRUE252]] ], [ [[CONV255]], [[COND_FALSE254]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV258:%.*]] = trunc i32 [[COND257]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV258]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP119]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP120]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV259:%.*]] = sext i16 [[TMP121]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV260:%.*]] = sext i16 [[TMP122]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP261:%.*]] = icmp sgt i32 [[CONV259]], [[CONV260]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP261]], label [[COND_TRUE263:%.*]], label [[COND_FALSE265:%.*]]
|
|
// SIMD-ONLY0: cond.true263:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV264:%.*]] = sext i16 [[TMP123]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END267:%.*]]
|
|
// SIMD-ONLY0: cond.false265:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV266:%.*]] = sext i16 [[TMP124]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END267]]
|
|
// SIMD-ONLY0: cond.end267:
|
|
// SIMD-ONLY0-NEXT: [[COND268:%.*]] = phi i32 [ [[CONV264]], [[COND_TRUE263]] ], [ [[CONV266]], [[COND_FALSE265]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV269:%.*]] = trunc i32 [[COND268]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV269]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP125]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV270:%.*]] = sext i16 [[TMP126]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV271:%.*]] = sext i16 [[TMP127]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP272:%.*]] = icmp slt i32 [[CONV270]], [[CONV271]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP272]], label [[COND_TRUE274:%.*]], label [[COND_FALSE276:%.*]]
|
|
// SIMD-ONLY0: cond.true274:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV275:%.*]] = sext i16 [[TMP128]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END278:%.*]]
|
|
// SIMD-ONLY0: cond.false276:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV277:%.*]] = sext i16 [[TMP129]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END278]]
|
|
// SIMD-ONLY0: cond.end278:
|
|
// SIMD-ONLY0-NEXT: [[COND279:%.*]] = phi i32 [ [[CONV275]], [[COND_TRUE274]] ], [ [[CONV277]], [[COND_FALSE276]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV280:%.*]] = trunc i32 [[COND279]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV280]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP130]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV281:%.*]] = sext i16 [[TMP131]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV282:%.*]] = sext i16 [[TMP132]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP283:%.*]] = icmp eq i32 [[CONV281]], [[CONV282]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP283]], label [[COND_TRUE285:%.*]], label [[COND_FALSE287:%.*]]
|
|
// SIMD-ONLY0: cond.true285:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV286:%.*]] = sext i16 [[TMP133]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END289:%.*]]
|
|
// SIMD-ONLY0: cond.false287:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV288:%.*]] = sext i16 [[TMP134]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END289]]
|
|
// SIMD-ONLY0: cond.end289:
|
|
// SIMD-ONLY0-NEXT: [[COND290:%.*]] = phi i32 [ [[CONV286]], [[COND_TRUE285]] ], [ [[CONV288]], [[COND_FALSE287]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV291:%.*]] = trunc i32 [[COND290]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV291]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV292:%.*]] = sext i16 [[TMP135]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV293:%.*]] = sext i16 [[TMP136]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP294:%.*]] = icmp sgt i32 [[CONV292]], [[CONV293]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP294]], label [[COND_TRUE296:%.*]], label [[COND_FALSE298:%.*]]
|
|
// SIMD-ONLY0: cond.true296:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV297:%.*]] = sext i16 [[TMP137]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END300:%.*]]
|
|
// SIMD-ONLY0: cond.false298:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV299:%.*]] = sext i16 [[TMP138]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END300]]
|
|
// SIMD-ONLY0: cond.end300:
|
|
// SIMD-ONLY0-NEXT: [[COND301:%.*]] = phi i32 [ [[CONV297]], [[COND_TRUE296]] ], [ [[CONV299]], [[COND_FALSE298]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV302:%.*]] = trunc i32 [[COND301]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV302]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP139]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV303:%.*]] = sext i16 [[TMP140]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV304:%.*]] = sext i16 [[TMP141]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP305:%.*]] = icmp slt i32 [[CONV303]], [[CONV304]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP305]], label [[COND_TRUE307:%.*]], label [[COND_FALSE309:%.*]]
|
|
// SIMD-ONLY0: cond.true307:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV308:%.*]] = sext i16 [[TMP142]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END311:%.*]]
|
|
// SIMD-ONLY0: cond.false309:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV310:%.*]] = sext i16 [[TMP143]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END311]]
|
|
// SIMD-ONLY0: cond.end311:
|
|
// SIMD-ONLY0-NEXT: [[COND312:%.*]] = phi i32 [ [[CONV308]], [[COND_TRUE307]] ], [ [[CONV310]], [[COND_FALSE309]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV313:%.*]] = trunc i32 [[COND312]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV313]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP144]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV314:%.*]] = sext i16 [[TMP145]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV315:%.*]] = sext i16 [[TMP146]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP316]], label [[COND_TRUE318:%.*]], label [[COND_FALSE320:%.*]]
|
|
// SIMD-ONLY0: cond.true318:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV319:%.*]] = sext i16 [[TMP147]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END322:%.*]]
|
|
// SIMD-ONLY0: cond.false320:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV321:%.*]] = sext i16 [[TMP148]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END322]]
|
|
// SIMD-ONLY0: cond.end322:
|
|
// SIMD-ONLY0-NEXT: [[COND323:%.*]] = phi i32 [ [[CONV319]], [[COND_TRUE318]] ], [ [[CONV321]], [[COND_FALSE320]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV324:%.*]] = trunc i32 [[COND323]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV324]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP149]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP150]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV325:%.*]] = sext i16 [[TMP151]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV326:%.*]] = sext i16 [[TMP152]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP327:%.*]] = icmp sgt i32 [[CONV325]], [[CONV326]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP327]], label [[COND_TRUE329:%.*]], label [[COND_FALSE331:%.*]]
|
|
// SIMD-ONLY0: cond.true329:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV330:%.*]] = sext i16 [[TMP153]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END333:%.*]]
|
|
// SIMD-ONLY0: cond.false331:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV332:%.*]] = sext i16 [[TMP154]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END333]]
|
|
// SIMD-ONLY0: cond.end333:
|
|
// SIMD-ONLY0-NEXT: [[COND334:%.*]] = phi i32 [ [[CONV330]], [[COND_TRUE329]] ], [ [[CONV332]], [[COND_FALSE331]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV335:%.*]] = trunc i32 [[COND334]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV335]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP155]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV336:%.*]] = sext i16 [[TMP156]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV337:%.*]] = sext i16 [[TMP157]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP338:%.*]] = icmp slt i32 [[CONV336]], [[CONV337]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP338]], label [[COND_TRUE340:%.*]], label [[COND_FALSE342:%.*]]
|
|
// SIMD-ONLY0: cond.true340:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV341:%.*]] = sext i16 [[TMP158]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END344:%.*]]
|
|
// SIMD-ONLY0: cond.false342:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV343:%.*]] = sext i16 [[TMP159]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END344]]
|
|
// SIMD-ONLY0: cond.end344:
|
|
// SIMD-ONLY0-NEXT: [[COND345:%.*]] = phi i32 [ [[CONV341]], [[COND_TRUE340]] ], [ [[CONV343]], [[COND_FALSE342]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV346:%.*]] = trunc i32 [[COND345]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV346]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP160]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV347:%.*]] = sext i16 [[TMP161]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV348:%.*]] = sext i16 [[TMP162]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP349:%.*]] = icmp eq i32 [[CONV347]], [[CONV348]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP349]], label [[COND_TRUE351:%.*]], label [[COND_FALSE353:%.*]]
|
|
// SIMD-ONLY0: cond.true351:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV352:%.*]] = sext i16 [[TMP163]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END355:%.*]]
|
|
// SIMD-ONLY0: cond.false353:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV354:%.*]] = sext i16 [[TMP164]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END355]]
|
|
// SIMD-ONLY0: cond.end355:
|
|
// SIMD-ONLY0-NEXT: [[COND356:%.*]] = phi i32 [ [[CONV352]], [[COND_TRUE351]] ], [ [[CONV354]], [[COND_FALSE353]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV357:%.*]] = trunc i32 [[COND356]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV357]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV358:%.*]] = sext i16 [[TMP165]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV359:%.*]] = sext i16 [[TMP166]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP360:%.*]] = icmp sgt i32 [[CONV358]], [[CONV359]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP360]], label [[COND_TRUE362:%.*]], label [[COND_FALSE364:%.*]]
|
|
// SIMD-ONLY0: cond.true362:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV363:%.*]] = sext i16 [[TMP167]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END366:%.*]]
|
|
// SIMD-ONLY0: cond.false364:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV365:%.*]] = sext i16 [[TMP168]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END366]]
|
|
// SIMD-ONLY0: cond.end366:
|
|
// SIMD-ONLY0-NEXT: [[COND367:%.*]] = phi i32 [ [[CONV363]], [[COND_TRUE362]] ], [ [[CONV365]], [[COND_FALSE364]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV368:%.*]] = trunc i32 [[COND367]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV368]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP169]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV369:%.*]] = sext i16 [[TMP170]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV370:%.*]] = sext i16 [[TMP171]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP371:%.*]] = icmp slt i32 [[CONV369]], [[CONV370]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP371]], label [[COND_TRUE373:%.*]], label [[COND_FALSE375:%.*]]
|
|
// SIMD-ONLY0: cond.true373:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV374:%.*]] = sext i16 [[TMP172]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END377:%.*]]
|
|
// SIMD-ONLY0: cond.false375:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV376:%.*]] = sext i16 [[TMP173]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END377]]
|
|
// SIMD-ONLY0: cond.end377:
|
|
// SIMD-ONLY0-NEXT: [[COND378:%.*]] = phi i32 [ [[CONV374]], [[COND_TRUE373]] ], [ [[CONV376]], [[COND_FALSE375]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV379:%.*]] = trunc i32 [[COND378]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV379]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP174]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV380:%.*]] = sext i16 [[TMP175]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i16, ptr [[SE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV381:%.*]] = sext i16 [[TMP176]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP382:%.*]] = icmp eq i32 [[CONV380]], [[CONV381]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP382]], label [[COND_TRUE384:%.*]], label [[COND_FALSE386:%.*]]
|
|
// SIMD-ONLY0: cond.true384:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i16, ptr [[SD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV385:%.*]] = sext i16 [[TMP177]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END388:%.*]]
|
|
// SIMD-ONLY0: cond.false386:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV387:%.*]] = sext i16 [[TMP178]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END388]]
|
|
// SIMD-ONLY0: cond.end388:
|
|
// SIMD-ONLY0-NEXT: [[COND389:%.*]] = phi i32 [ [[CONV385]], [[COND_TRUE384]] ], [ [[CONV387]], [[COND_FALSE386]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV390:%.*]] = trunc i32 [[COND389]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV390]], ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i16, ptr [[SX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP179]], ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i16, ptr [[SV]], align 2
|
|
// SIMD-ONLY0-NEXT: ret i16 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @usxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[USX:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USV:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USE:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[USD:%.*]] = alloca i16, align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP0]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV:%.*]] = zext i16 [[TMP1]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = zext i16 [[TMP2]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CONV]], [[CONV1]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV3:%.*]] = zext i16 [[TMP3]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV4:%.*]] = zext i16 [[TMP4]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i32 [ [[CONV3]], [[COND_TRUE]] ], [ [[CONV4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV5:%.*]] = trunc i32 [[COND]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV5]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP5]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV6:%.*]] = zext i16 [[TMP6]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV7:%.*]] = zext i16 [[TMP7]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP8:%.*]] = icmp slt i32 [[CONV6]], [[CONV7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP8]], label [[COND_TRUE10:%.*]], label [[COND_FALSE12:%.*]]
|
|
// SIMD-ONLY0: cond.true10:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV11:%.*]] = zext i16 [[TMP8]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false12:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV13:%.*]] = zext i16 [[TMP9]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i32 [ [[CONV11]], [[COND_TRUE10]] ], [ [[CONV13]], [[COND_FALSE12]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV16:%.*]] = trunc i32 [[COND15]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV16]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP10]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV17:%.*]] = zext i16 [[TMP11]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV18:%.*]] = zext i16 [[TMP12]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP19:%.*]] = icmp eq i32 [[CONV17]], [[CONV18]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP19]], label [[COND_TRUE21:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true21:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV22:%.*]] = zext i16 [[TMP13]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV24:%.*]] = zext i16 [[TMP14]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END25]]
|
|
// SIMD-ONLY0: cond.end25:
|
|
// SIMD-ONLY0-NEXT: [[COND26:%.*]] = phi i32 [ [[CONV22]], [[COND_TRUE21]] ], [ [[CONV24]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV27:%.*]] = trunc i32 [[COND26]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV27]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV28:%.*]] = zext i16 [[TMP15]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV29:%.*]] = zext i16 [[TMP16]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP30:%.*]] = icmp sgt i32 [[CONV28]], [[CONV29]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP30]], label [[COND_TRUE32:%.*]], label [[COND_FALSE34:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV33:%.*]] = zext i16 [[TMP17]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36:%.*]]
|
|
// SIMD-ONLY0: cond.false34:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV35:%.*]] = zext i16 [[TMP18]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END36]]
|
|
// SIMD-ONLY0: cond.end36:
|
|
// SIMD-ONLY0-NEXT: [[COND37:%.*]] = phi i32 [ [[CONV33]], [[COND_TRUE32]] ], [ [[CONV35]], [[COND_FALSE34]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV38:%.*]] = trunc i32 [[COND37]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV38]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP19]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV39:%.*]] = zext i16 [[TMP20]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV40:%.*]] = zext i16 [[TMP21]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp slt i32 [[CONV39]], [[CONV40]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE43:%.*]], label [[COND_FALSE45:%.*]]
|
|
// SIMD-ONLY0: cond.true43:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV44:%.*]] = zext i16 [[TMP22]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END47:%.*]]
|
|
// SIMD-ONLY0: cond.false45:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV46:%.*]] = zext i16 [[TMP23]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END47]]
|
|
// SIMD-ONLY0: cond.end47:
|
|
// SIMD-ONLY0-NEXT: [[COND48:%.*]] = phi i32 [ [[CONV44]], [[COND_TRUE43]] ], [ [[CONV46]], [[COND_FALSE45]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV49:%.*]] = trunc i32 [[COND48]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV49]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP24]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV50:%.*]] = zext i16 [[TMP25]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV51:%.*]] = zext i16 [[TMP26]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP52:%.*]] = icmp eq i32 [[CONV50]], [[CONV51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP52]], label [[COND_TRUE54:%.*]], label [[COND_FALSE56:%.*]]
|
|
// SIMD-ONLY0: cond.true54:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV55:%.*]] = zext i16 [[TMP27]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END58:%.*]]
|
|
// SIMD-ONLY0: cond.false56:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV57:%.*]] = zext i16 [[TMP28]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END58]]
|
|
// SIMD-ONLY0: cond.end58:
|
|
// SIMD-ONLY0-NEXT: [[COND59:%.*]] = phi i32 [ [[CONV55]], [[COND_TRUE54]] ], [ [[CONV57]], [[COND_FALSE56]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV60:%.*]] = trunc i32 [[COND59]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV60]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP29]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP30]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV61:%.*]] = zext i16 [[TMP31]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV62:%.*]] = zext i16 [[TMP32]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP63:%.*]] = icmp sgt i32 [[CONV61]], [[CONV62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP63]], label [[COND_TRUE65:%.*]], label [[COND_FALSE67:%.*]]
|
|
// SIMD-ONLY0: cond.true65:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV66:%.*]] = zext i16 [[TMP33]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false67:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV68:%.*]] = zext i16 [[TMP34]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i32 [ [[CONV66]], [[COND_TRUE65]] ], [ [[CONV68]], [[COND_FALSE67]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV71:%.*]] = trunc i32 [[COND70]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV71]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP35]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV72:%.*]] = zext i16 [[TMP36]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV73:%.*]] = zext i16 [[TMP37]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP74:%.*]] = icmp slt i32 [[CONV72]], [[CONV73]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP74]], label [[COND_TRUE76:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true76:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV77:%.*]] = zext i16 [[TMP38]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV79:%.*]] = zext i16 [[TMP39]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END80]]
|
|
// SIMD-ONLY0: cond.end80:
|
|
// SIMD-ONLY0-NEXT: [[COND81:%.*]] = phi i32 [ [[CONV77]], [[COND_TRUE76]] ], [ [[CONV79]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV82:%.*]] = trunc i32 [[COND81]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV82]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP40]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV83:%.*]] = zext i16 [[TMP41]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV84:%.*]] = zext i16 [[TMP42]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP85:%.*]] = icmp eq i32 [[CONV83]], [[CONV84]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP85]], label [[COND_TRUE87:%.*]], label [[COND_FALSE89:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV88:%.*]] = zext i16 [[TMP43]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END91:%.*]]
|
|
// SIMD-ONLY0: cond.false89:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV90:%.*]] = zext i16 [[TMP44]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END91]]
|
|
// SIMD-ONLY0: cond.end91:
|
|
// SIMD-ONLY0-NEXT: [[COND92:%.*]] = phi i32 [ [[CONV88]], [[COND_TRUE87]] ], [ [[CONV90]], [[COND_FALSE89]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV93:%.*]] = trunc i32 [[COND92]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV93]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV94:%.*]] = zext i16 [[TMP45]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV95:%.*]] = zext i16 [[TMP46]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp sgt i32 [[CONV94]], [[CONV95]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE98:%.*]], label [[COND_FALSE100:%.*]]
|
|
// SIMD-ONLY0: cond.true98:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV99:%.*]] = zext i16 [[TMP47]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END102:%.*]]
|
|
// SIMD-ONLY0: cond.false100:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV101:%.*]] = zext i16 [[TMP48]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END102]]
|
|
// SIMD-ONLY0: cond.end102:
|
|
// SIMD-ONLY0-NEXT: [[COND103:%.*]] = phi i32 [ [[CONV99]], [[COND_TRUE98]] ], [ [[CONV101]], [[COND_FALSE100]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV104:%.*]] = trunc i32 [[COND103]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV104]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP49]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV105:%.*]] = zext i16 [[TMP50]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV106:%.*]] = zext i16 [[TMP51]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP107:%.*]] = icmp slt i32 [[CONV105]], [[CONV106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP107]], label [[COND_TRUE109:%.*]], label [[COND_FALSE111:%.*]]
|
|
// SIMD-ONLY0: cond.true109:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV110:%.*]] = zext i16 [[TMP52]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END113:%.*]]
|
|
// SIMD-ONLY0: cond.false111:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV112:%.*]] = zext i16 [[TMP53]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END113]]
|
|
// SIMD-ONLY0: cond.end113:
|
|
// SIMD-ONLY0-NEXT: [[COND114:%.*]] = phi i32 [ [[CONV110]], [[COND_TRUE109]] ], [ [[CONV112]], [[COND_FALSE111]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV115:%.*]] = trunc i32 [[COND114]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV115]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP54]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV116:%.*]] = zext i16 [[TMP55]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV117:%.*]] = zext i16 [[TMP56]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP118:%.*]] = icmp eq i32 [[CONV116]], [[CONV117]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP118]], label [[COND_TRUE120:%.*]], label [[COND_FALSE122:%.*]]
|
|
// SIMD-ONLY0: cond.true120:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV121:%.*]] = zext i16 [[TMP57]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false122:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV123:%.*]] = zext i16 [[TMP58]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i32 [ [[CONV121]], [[COND_TRUE120]] ], [ [[CONV123]], [[COND_FALSE122]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV126:%.*]] = trunc i32 [[COND125]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV126]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP59]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP60]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV127:%.*]] = zext i16 [[TMP61]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV128:%.*]] = zext i16 [[TMP62]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP129:%.*]] = icmp sgt i32 [[CONV127]], [[CONV128]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP129]], label [[COND_TRUE131:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true131:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV132:%.*]] = zext i16 [[TMP63]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END135:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV134:%.*]] = zext i16 [[TMP64]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END135]]
|
|
// SIMD-ONLY0: cond.end135:
|
|
// SIMD-ONLY0-NEXT: [[COND136:%.*]] = phi i32 [ [[CONV132]], [[COND_TRUE131]] ], [ [[CONV134]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV137:%.*]] = trunc i32 [[COND136]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV137]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP65]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV138:%.*]] = zext i16 [[TMP66]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV139:%.*]] = zext i16 [[TMP67]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP140:%.*]] = icmp slt i32 [[CONV138]], [[CONV139]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP140]], label [[COND_TRUE142:%.*]], label [[COND_FALSE144:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV143:%.*]] = zext i16 [[TMP68]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END146:%.*]]
|
|
// SIMD-ONLY0: cond.false144:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV145:%.*]] = zext i16 [[TMP69]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END146]]
|
|
// SIMD-ONLY0: cond.end146:
|
|
// SIMD-ONLY0-NEXT: [[COND147:%.*]] = phi i32 [ [[CONV143]], [[COND_TRUE142]] ], [ [[CONV145]], [[COND_FALSE144]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV148:%.*]] = trunc i32 [[COND147]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV148]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP70]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV149:%.*]] = zext i16 [[TMP71]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV150:%.*]] = zext i16 [[TMP72]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp eq i32 [[CONV149]], [[CONV150]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE153:%.*]], label [[COND_FALSE155:%.*]]
|
|
// SIMD-ONLY0: cond.true153:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV154:%.*]] = zext i16 [[TMP73]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END157:%.*]]
|
|
// SIMD-ONLY0: cond.false155:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV156:%.*]] = zext i16 [[TMP74]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END157]]
|
|
// SIMD-ONLY0: cond.end157:
|
|
// SIMD-ONLY0-NEXT: [[COND158:%.*]] = phi i32 [ [[CONV154]], [[COND_TRUE153]] ], [ [[CONV156]], [[COND_FALSE155]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV159:%.*]] = trunc i32 [[COND158]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV159]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV160:%.*]] = zext i16 [[TMP75]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV161:%.*]] = zext i16 [[TMP76]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP162:%.*]] = icmp sgt i32 [[CONV160]], [[CONV161]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP162]], label [[COND_TRUE164:%.*]], label [[COND_FALSE166:%.*]]
|
|
// SIMD-ONLY0: cond.true164:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV165:%.*]] = zext i16 [[TMP77]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END168:%.*]]
|
|
// SIMD-ONLY0: cond.false166:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV167:%.*]] = zext i16 [[TMP78]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END168]]
|
|
// SIMD-ONLY0: cond.end168:
|
|
// SIMD-ONLY0-NEXT: [[COND169:%.*]] = phi i32 [ [[CONV165]], [[COND_TRUE164]] ], [ [[CONV167]], [[COND_FALSE166]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV170:%.*]] = trunc i32 [[COND169]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV170]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP79]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV171:%.*]] = zext i16 [[TMP80]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV172:%.*]] = zext i16 [[TMP81]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP173:%.*]] = icmp slt i32 [[CONV171]], [[CONV172]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP173]], label [[COND_TRUE175:%.*]], label [[COND_FALSE177:%.*]]
|
|
// SIMD-ONLY0: cond.true175:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV176:%.*]] = zext i16 [[TMP82]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END179:%.*]]
|
|
// SIMD-ONLY0: cond.false177:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV178:%.*]] = zext i16 [[TMP83]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END179]]
|
|
// SIMD-ONLY0: cond.end179:
|
|
// SIMD-ONLY0-NEXT: [[COND180:%.*]] = phi i32 [ [[CONV176]], [[COND_TRUE175]] ], [ [[CONV178]], [[COND_FALSE177]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV181:%.*]] = trunc i32 [[COND180]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV181]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP84]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV182:%.*]] = zext i16 [[TMP85]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV183:%.*]] = zext i16 [[TMP86]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP184:%.*]] = icmp eq i32 [[CONV182]], [[CONV183]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP184]], label [[COND_TRUE186:%.*]], label [[COND_FALSE188:%.*]]
|
|
// SIMD-ONLY0: cond.true186:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV187:%.*]] = zext i16 [[TMP87]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END190:%.*]]
|
|
// SIMD-ONLY0: cond.false188:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV189:%.*]] = zext i16 [[TMP88]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END190]]
|
|
// SIMD-ONLY0: cond.end190:
|
|
// SIMD-ONLY0-NEXT: [[COND191:%.*]] = phi i32 [ [[CONV187]], [[COND_TRUE186]] ], [ [[CONV189]], [[COND_FALSE188]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV192:%.*]] = trunc i32 [[COND191]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV192]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP89]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP90]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV193:%.*]] = zext i16 [[TMP91]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV194:%.*]] = zext i16 [[TMP92]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP195:%.*]] = icmp sgt i32 [[CONV193]], [[CONV194]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP195]], label [[COND_TRUE197:%.*]], label [[COND_FALSE199:%.*]]
|
|
// SIMD-ONLY0: cond.true197:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV198:%.*]] = zext i16 [[TMP93]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END201:%.*]]
|
|
// SIMD-ONLY0: cond.false199:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV200:%.*]] = zext i16 [[TMP94]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END201]]
|
|
// SIMD-ONLY0: cond.end201:
|
|
// SIMD-ONLY0-NEXT: [[COND202:%.*]] = phi i32 [ [[CONV198]], [[COND_TRUE197]] ], [ [[CONV200]], [[COND_FALSE199]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV203:%.*]] = trunc i32 [[COND202]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV203]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP95]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV204:%.*]] = zext i16 [[TMP96]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV205:%.*]] = zext i16 [[TMP97]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP206:%.*]] = icmp slt i32 [[CONV204]], [[CONV205]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP206]], label [[COND_TRUE208:%.*]], label [[COND_FALSE210:%.*]]
|
|
// SIMD-ONLY0: cond.true208:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV209:%.*]] = zext i16 [[TMP98]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END212:%.*]]
|
|
// SIMD-ONLY0: cond.false210:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV211:%.*]] = zext i16 [[TMP99]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END212]]
|
|
// SIMD-ONLY0: cond.end212:
|
|
// SIMD-ONLY0-NEXT: [[COND213:%.*]] = phi i32 [ [[CONV209]], [[COND_TRUE208]] ], [ [[CONV211]], [[COND_FALSE210]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV214:%.*]] = trunc i32 [[COND213]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV214]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP100]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV215:%.*]] = zext i16 [[TMP101]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV216:%.*]] = zext i16 [[TMP102]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP217:%.*]] = icmp eq i32 [[CONV215]], [[CONV216]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP217]], label [[COND_TRUE219:%.*]], label [[COND_FALSE221:%.*]]
|
|
// SIMD-ONLY0: cond.true219:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV220:%.*]] = zext i16 [[TMP103]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END223:%.*]]
|
|
// SIMD-ONLY0: cond.false221:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV222:%.*]] = zext i16 [[TMP104]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END223]]
|
|
// SIMD-ONLY0: cond.end223:
|
|
// SIMD-ONLY0-NEXT: [[COND224:%.*]] = phi i32 [ [[CONV220]], [[COND_TRUE219]] ], [ [[CONV222]], [[COND_FALSE221]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV225:%.*]] = trunc i32 [[COND224]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV225]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV226:%.*]] = zext i16 [[TMP105]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV227:%.*]] = zext i16 [[TMP106]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP228:%.*]] = icmp sgt i32 [[CONV226]], [[CONV227]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP228]], label [[COND_TRUE230:%.*]], label [[COND_FALSE232:%.*]]
|
|
// SIMD-ONLY0: cond.true230:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV231:%.*]] = zext i16 [[TMP107]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END234:%.*]]
|
|
// SIMD-ONLY0: cond.false232:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV233:%.*]] = zext i16 [[TMP108]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END234]]
|
|
// SIMD-ONLY0: cond.end234:
|
|
// SIMD-ONLY0-NEXT: [[COND235:%.*]] = phi i32 [ [[CONV231]], [[COND_TRUE230]] ], [ [[CONV233]], [[COND_FALSE232]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV236:%.*]] = trunc i32 [[COND235]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV236]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP109]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV237:%.*]] = zext i16 [[TMP110]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV238:%.*]] = zext i16 [[TMP111]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP239:%.*]] = icmp slt i32 [[CONV237]], [[CONV238]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP239]], label [[COND_TRUE241:%.*]], label [[COND_FALSE243:%.*]]
|
|
// SIMD-ONLY0: cond.true241:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV242:%.*]] = zext i16 [[TMP112]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END245:%.*]]
|
|
// SIMD-ONLY0: cond.false243:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV244:%.*]] = zext i16 [[TMP113]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END245]]
|
|
// SIMD-ONLY0: cond.end245:
|
|
// SIMD-ONLY0-NEXT: [[COND246:%.*]] = phi i32 [ [[CONV242]], [[COND_TRUE241]] ], [ [[CONV244]], [[COND_FALSE243]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV247:%.*]] = trunc i32 [[COND246]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV247]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP114]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV248:%.*]] = zext i16 [[TMP115]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV249:%.*]] = zext i16 [[TMP116]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP250:%.*]] = icmp eq i32 [[CONV248]], [[CONV249]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP250]], label [[COND_TRUE252:%.*]], label [[COND_FALSE254:%.*]]
|
|
// SIMD-ONLY0: cond.true252:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV253:%.*]] = zext i16 [[TMP117]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END256:%.*]]
|
|
// SIMD-ONLY0: cond.false254:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV255:%.*]] = zext i16 [[TMP118]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END256]]
|
|
// SIMD-ONLY0: cond.end256:
|
|
// SIMD-ONLY0-NEXT: [[COND257:%.*]] = phi i32 [ [[CONV253]], [[COND_TRUE252]] ], [ [[CONV255]], [[COND_FALSE254]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV258:%.*]] = trunc i32 [[COND257]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV258]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP119]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP120]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV259:%.*]] = zext i16 [[TMP121]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV260:%.*]] = zext i16 [[TMP122]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP261:%.*]] = icmp sgt i32 [[CONV259]], [[CONV260]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP261]], label [[COND_TRUE263:%.*]], label [[COND_FALSE265:%.*]]
|
|
// SIMD-ONLY0: cond.true263:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV264:%.*]] = zext i16 [[TMP123]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END267:%.*]]
|
|
// SIMD-ONLY0: cond.false265:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV266:%.*]] = zext i16 [[TMP124]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END267]]
|
|
// SIMD-ONLY0: cond.end267:
|
|
// SIMD-ONLY0-NEXT: [[COND268:%.*]] = phi i32 [ [[CONV264]], [[COND_TRUE263]] ], [ [[CONV266]], [[COND_FALSE265]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV269:%.*]] = trunc i32 [[COND268]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV269]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP125]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV270:%.*]] = zext i16 [[TMP126]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV271:%.*]] = zext i16 [[TMP127]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP272:%.*]] = icmp slt i32 [[CONV270]], [[CONV271]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP272]], label [[COND_TRUE274:%.*]], label [[COND_FALSE276:%.*]]
|
|
// SIMD-ONLY0: cond.true274:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV275:%.*]] = zext i16 [[TMP128]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END278:%.*]]
|
|
// SIMD-ONLY0: cond.false276:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV277:%.*]] = zext i16 [[TMP129]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END278]]
|
|
// SIMD-ONLY0: cond.end278:
|
|
// SIMD-ONLY0-NEXT: [[COND279:%.*]] = phi i32 [ [[CONV275]], [[COND_TRUE274]] ], [ [[CONV277]], [[COND_FALSE276]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV280:%.*]] = trunc i32 [[COND279]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV280]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP130]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV281:%.*]] = zext i16 [[TMP131]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV282:%.*]] = zext i16 [[TMP132]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP283:%.*]] = icmp eq i32 [[CONV281]], [[CONV282]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP283]], label [[COND_TRUE285:%.*]], label [[COND_FALSE287:%.*]]
|
|
// SIMD-ONLY0: cond.true285:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV286:%.*]] = zext i16 [[TMP133]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END289:%.*]]
|
|
// SIMD-ONLY0: cond.false287:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV288:%.*]] = zext i16 [[TMP134]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END289]]
|
|
// SIMD-ONLY0: cond.end289:
|
|
// SIMD-ONLY0-NEXT: [[COND290:%.*]] = phi i32 [ [[CONV286]], [[COND_TRUE285]] ], [ [[CONV288]], [[COND_FALSE287]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV291:%.*]] = trunc i32 [[COND290]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV291]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV292:%.*]] = zext i16 [[TMP135]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV293:%.*]] = zext i16 [[TMP136]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP294:%.*]] = icmp sgt i32 [[CONV292]], [[CONV293]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP294]], label [[COND_TRUE296:%.*]], label [[COND_FALSE298:%.*]]
|
|
// SIMD-ONLY0: cond.true296:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV297:%.*]] = zext i16 [[TMP137]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END300:%.*]]
|
|
// SIMD-ONLY0: cond.false298:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV299:%.*]] = zext i16 [[TMP138]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END300]]
|
|
// SIMD-ONLY0: cond.end300:
|
|
// SIMD-ONLY0-NEXT: [[COND301:%.*]] = phi i32 [ [[CONV297]], [[COND_TRUE296]] ], [ [[CONV299]], [[COND_FALSE298]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV302:%.*]] = trunc i32 [[COND301]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV302]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP139]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV303:%.*]] = zext i16 [[TMP140]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV304:%.*]] = zext i16 [[TMP141]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP305:%.*]] = icmp slt i32 [[CONV303]], [[CONV304]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP305]], label [[COND_TRUE307:%.*]], label [[COND_FALSE309:%.*]]
|
|
// SIMD-ONLY0: cond.true307:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV308:%.*]] = zext i16 [[TMP142]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END311:%.*]]
|
|
// SIMD-ONLY0: cond.false309:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV310:%.*]] = zext i16 [[TMP143]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END311]]
|
|
// SIMD-ONLY0: cond.end311:
|
|
// SIMD-ONLY0-NEXT: [[COND312:%.*]] = phi i32 [ [[CONV308]], [[COND_TRUE307]] ], [ [[CONV310]], [[COND_FALSE309]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV313:%.*]] = trunc i32 [[COND312]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV313]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP144]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV314:%.*]] = zext i16 [[TMP145]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV315:%.*]] = zext i16 [[TMP146]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP316:%.*]] = icmp eq i32 [[CONV314]], [[CONV315]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP316]], label [[COND_TRUE318:%.*]], label [[COND_FALSE320:%.*]]
|
|
// SIMD-ONLY0: cond.true318:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV319:%.*]] = zext i16 [[TMP147]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END322:%.*]]
|
|
// SIMD-ONLY0: cond.false320:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV321:%.*]] = zext i16 [[TMP148]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END322]]
|
|
// SIMD-ONLY0: cond.end322:
|
|
// SIMD-ONLY0-NEXT: [[COND323:%.*]] = phi i32 [ [[CONV319]], [[COND_TRUE318]] ], [ [[CONV321]], [[COND_FALSE320]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV324:%.*]] = trunc i32 [[COND323]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV324]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP149]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP150]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV325:%.*]] = zext i16 [[TMP151]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV326:%.*]] = zext i16 [[TMP152]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP327:%.*]] = icmp sgt i32 [[CONV325]], [[CONV326]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP327]], label [[COND_TRUE329:%.*]], label [[COND_FALSE331:%.*]]
|
|
// SIMD-ONLY0: cond.true329:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV330:%.*]] = zext i16 [[TMP153]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END333:%.*]]
|
|
// SIMD-ONLY0: cond.false331:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV332:%.*]] = zext i16 [[TMP154]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END333]]
|
|
// SIMD-ONLY0: cond.end333:
|
|
// SIMD-ONLY0-NEXT: [[COND334:%.*]] = phi i32 [ [[CONV330]], [[COND_TRUE329]] ], [ [[CONV332]], [[COND_FALSE331]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV335:%.*]] = trunc i32 [[COND334]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV335]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP155]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV336:%.*]] = zext i16 [[TMP156]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV337:%.*]] = zext i16 [[TMP157]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP338:%.*]] = icmp slt i32 [[CONV336]], [[CONV337]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP338]], label [[COND_TRUE340:%.*]], label [[COND_FALSE342:%.*]]
|
|
// SIMD-ONLY0: cond.true340:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV341:%.*]] = zext i16 [[TMP158]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END344:%.*]]
|
|
// SIMD-ONLY0: cond.false342:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV343:%.*]] = zext i16 [[TMP159]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END344]]
|
|
// SIMD-ONLY0: cond.end344:
|
|
// SIMD-ONLY0-NEXT: [[COND345:%.*]] = phi i32 [ [[CONV341]], [[COND_TRUE340]] ], [ [[CONV343]], [[COND_FALSE342]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV346:%.*]] = trunc i32 [[COND345]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV346]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP160]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV347:%.*]] = zext i16 [[TMP161]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV348:%.*]] = zext i16 [[TMP162]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP349:%.*]] = icmp eq i32 [[CONV347]], [[CONV348]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP349]], label [[COND_TRUE351:%.*]], label [[COND_FALSE353:%.*]]
|
|
// SIMD-ONLY0: cond.true351:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV352:%.*]] = zext i16 [[TMP163]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END355:%.*]]
|
|
// SIMD-ONLY0: cond.false353:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV354:%.*]] = zext i16 [[TMP164]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END355]]
|
|
// SIMD-ONLY0: cond.end355:
|
|
// SIMD-ONLY0-NEXT: [[COND356:%.*]] = phi i32 [ [[CONV352]], [[COND_TRUE351]] ], [ [[CONV354]], [[COND_FALSE353]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV357:%.*]] = trunc i32 [[COND356]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV357]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV358:%.*]] = zext i16 [[TMP165]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV359:%.*]] = zext i16 [[TMP166]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP360:%.*]] = icmp sgt i32 [[CONV358]], [[CONV359]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP360]], label [[COND_TRUE362:%.*]], label [[COND_FALSE364:%.*]]
|
|
// SIMD-ONLY0: cond.true362:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV363:%.*]] = zext i16 [[TMP167]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END366:%.*]]
|
|
// SIMD-ONLY0: cond.false364:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV365:%.*]] = zext i16 [[TMP168]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END366]]
|
|
// SIMD-ONLY0: cond.end366:
|
|
// SIMD-ONLY0-NEXT: [[COND367:%.*]] = phi i32 [ [[CONV363]], [[COND_TRUE362]] ], [ [[CONV365]], [[COND_FALSE364]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV368:%.*]] = trunc i32 [[COND367]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV368]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP169]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV369:%.*]] = zext i16 [[TMP170]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV370:%.*]] = zext i16 [[TMP171]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP371:%.*]] = icmp slt i32 [[CONV369]], [[CONV370]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP371]], label [[COND_TRUE373:%.*]], label [[COND_FALSE375:%.*]]
|
|
// SIMD-ONLY0: cond.true373:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV374:%.*]] = zext i16 [[TMP172]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END377:%.*]]
|
|
// SIMD-ONLY0: cond.false375:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV376:%.*]] = zext i16 [[TMP173]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END377]]
|
|
// SIMD-ONLY0: cond.end377:
|
|
// SIMD-ONLY0-NEXT: [[COND378:%.*]] = phi i32 [ [[CONV374]], [[COND_TRUE373]] ], [ [[CONV376]], [[COND_FALSE375]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV379:%.*]] = trunc i32 [[COND378]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV379]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP174]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV380:%.*]] = zext i16 [[TMP175]] to i32
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i16, ptr [[USE]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV381:%.*]] = zext i16 [[TMP176]] to i32
|
|
// SIMD-ONLY0-NEXT: [[CMP382:%.*]] = icmp eq i32 [[CONV380]], [[CONV381]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP382]], label [[COND_TRUE384:%.*]], label [[COND_FALSE386:%.*]]
|
|
// SIMD-ONLY0: cond.true384:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i16, ptr [[USD]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV385:%.*]] = zext i16 [[TMP177]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END388:%.*]]
|
|
// SIMD-ONLY0: cond.false386:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[CONV387:%.*]] = zext i16 [[TMP178]] to i32
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END388]]
|
|
// SIMD-ONLY0: cond.end388:
|
|
// SIMD-ONLY0-NEXT: [[COND389:%.*]] = phi i32 [ [[CONV385]], [[COND_TRUE384]] ], [ [[CONV387]], [[COND_FALSE386]] ]
|
|
// SIMD-ONLY0-NEXT: [[CONV390:%.*]] = trunc i32 [[COND389]] to i16
|
|
// SIMD-ONLY0-NEXT: store i16 [[CONV390]], ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i16, ptr [[USX]], align 2
|
|
// SIMD-ONLY0-NEXT: store i16 [[TMP179]], ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i16, ptr [[USV]], align 2
|
|
// SIMD-ONLY0-NEXT: ret i16 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @ixevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[IX:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[IV:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[IE:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[ID:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP0]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], [[TMP2]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i32 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP5]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
|
|
// SIMD-ONLY0: cond.true2:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4:%.*]]
|
|
// SIMD-ONLY0: cond.false3:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4]]
|
|
// SIMD-ONLY0: cond.end4:
|
|
// SIMD-ONLY0-NEXT: [[COND5:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND5]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP10]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6:%.*]] = icmp eq i32 [[TMP11]], [[TMP12]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
|
|
// SIMD-ONLY0: cond.true7:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9:%.*]]
|
|
// SIMD-ONLY0: cond.false8:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9]]
|
|
// SIMD-ONLY0: cond.end9:
|
|
// SIMD-ONLY0-NEXT: [[COND10:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND10]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP15]], [[TMP16]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
|
|
// SIMD-ONLY0: cond.true12:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false13:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND15]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP19]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP20]], [[TMP21]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
|
|
// SIMD-ONLY0: cond.true17:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19:%.*]]
|
|
// SIMD-ONLY0: cond.false18:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19]]
|
|
// SIMD-ONLY0: cond.end19:
|
|
// SIMD-ONLY0-NEXT: [[COND20:%.*]] = phi i32 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND20]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP24]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP21:%.*]] = icmp eq i32 [[TMP25]], [[TMP26]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true22:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24]]
|
|
// SIMD-ONLY0: cond.end24:
|
|
// SIMD-ONLY0-NEXT: [[COND25:%.*]] = phi i32 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND25]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP29]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP30]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP26:%.*]] = icmp sgt i32 [[TMP31]], [[TMP32]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
|
|
// SIMD-ONLY0: cond.true27:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29:%.*]]
|
|
// SIMD-ONLY0: cond.false28:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29]]
|
|
// SIMD-ONLY0: cond.end29:
|
|
// SIMD-ONLY0-NEXT: [[COND30:%.*]] = phi i32 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND30]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP35]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP31:%.*]] = icmp slt i32 [[TMP36]], [[TMP37]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34:%.*]]
|
|
// SIMD-ONLY0: cond.false33:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34]]
|
|
// SIMD-ONLY0: cond.end34:
|
|
// SIMD-ONLY0-NEXT: [[COND35:%.*]] = phi i32 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND35]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP40]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP36:%.*]] = icmp eq i32 [[TMP41]], [[TMP42]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
|
|
// SIMD-ONLY0: cond.true37:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39:%.*]]
|
|
// SIMD-ONLY0: cond.false38:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39]]
|
|
// SIMD-ONLY0: cond.end39:
|
|
// SIMD-ONLY0-NEXT: [[COND40:%.*]] = phi i32 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND40]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp sgt i32 [[TMP45]], [[TMP46]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
|
|
// SIMD-ONLY0: cond.true42:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44:%.*]]
|
|
// SIMD-ONLY0: cond.false43:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44]]
|
|
// SIMD-ONLY0: cond.end44:
|
|
// SIMD-ONLY0-NEXT: [[COND45:%.*]] = phi i32 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND45]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP49]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP46:%.*]] = icmp slt i32 [[TMP50]], [[TMP51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
|
|
// SIMD-ONLY0: cond.true47:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49:%.*]]
|
|
// SIMD-ONLY0: cond.false48:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49]]
|
|
// SIMD-ONLY0: cond.end49:
|
|
// SIMD-ONLY0-NEXT: [[COND50:%.*]] = phi i32 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND50]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP54]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP51:%.*]] = icmp eq i32 [[TMP55]], [[TMP56]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
|
|
// SIMD-ONLY0: cond.true52:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54:%.*]]
|
|
// SIMD-ONLY0: cond.false53:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54]]
|
|
// SIMD-ONLY0: cond.end54:
|
|
// SIMD-ONLY0-NEXT: [[COND55:%.*]] = phi i32 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND55]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP59]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP60]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP56:%.*]] = icmp sgt i32 [[TMP61]], [[TMP62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
|
|
// SIMD-ONLY0: cond.true57:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59:%.*]]
|
|
// SIMD-ONLY0: cond.false58:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59]]
|
|
// SIMD-ONLY0: cond.end59:
|
|
// SIMD-ONLY0-NEXT: [[COND60:%.*]] = phi i32 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND60]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP65]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP61:%.*]] = icmp slt i32 [[TMP66]], [[TMP67]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
|
|
// SIMD-ONLY0: cond.true62:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64:%.*]]
|
|
// SIMD-ONLY0: cond.false63:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64]]
|
|
// SIMD-ONLY0: cond.end64:
|
|
// SIMD-ONLY0-NEXT: [[COND65:%.*]] = phi i32 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND65]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP70]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP66:%.*]] = icmp eq i32 [[TMP71]], [[TMP72]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
|
|
// SIMD-ONLY0: cond.true67:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false68:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i32 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND70]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP71:%.*]] = icmp sgt i32 [[TMP75]], [[TMP76]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
|
|
// SIMD-ONLY0: cond.true72:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74:%.*]]
|
|
// SIMD-ONLY0: cond.false73:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74]]
|
|
// SIMD-ONLY0: cond.end74:
|
|
// SIMD-ONLY0-NEXT: [[COND75:%.*]] = phi i32 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND75]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP79]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP76:%.*]] = icmp slt i32 [[TMP80]], [[TMP81]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true77:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79]]
|
|
// SIMD-ONLY0: cond.end79:
|
|
// SIMD-ONLY0-NEXT: [[COND80:%.*]] = phi i32 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND80]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP84]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP81:%.*]] = icmp eq i32 [[TMP85]], [[TMP86]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
|
|
// SIMD-ONLY0: cond.true82:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84:%.*]]
|
|
// SIMD-ONLY0: cond.false83:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84]]
|
|
// SIMD-ONLY0: cond.end84:
|
|
// SIMD-ONLY0-NEXT: [[COND85:%.*]] = phi i32 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND85]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP89]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP90]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP86:%.*]] = icmp sgt i32 [[TMP91]], [[TMP92]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89:%.*]]
|
|
// SIMD-ONLY0: cond.false88:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89]]
|
|
// SIMD-ONLY0: cond.end89:
|
|
// SIMD-ONLY0-NEXT: [[COND90:%.*]] = phi i32 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND90]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP95]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = icmp slt i32 [[TMP96]], [[TMP97]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
|
|
// SIMD-ONLY0: cond.true92:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94:%.*]]
|
|
// SIMD-ONLY0: cond.false93:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94]]
|
|
// SIMD-ONLY0: cond.end94:
|
|
// SIMD-ONLY0-NEXT: [[COND95:%.*]] = phi i32 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND95]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP100]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp eq i32 [[TMP101]], [[TMP102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
|
|
// SIMD-ONLY0: cond.true97:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99:%.*]]
|
|
// SIMD-ONLY0: cond.false98:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99]]
|
|
// SIMD-ONLY0: cond.end99:
|
|
// SIMD-ONLY0-NEXT: [[COND100:%.*]] = phi i32 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND100]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP101:%.*]] = icmp sgt i32 [[TMP105]], [[TMP106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
|
|
// SIMD-ONLY0: cond.true102:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104:%.*]]
|
|
// SIMD-ONLY0: cond.false103:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104]]
|
|
// SIMD-ONLY0: cond.end104:
|
|
// SIMD-ONLY0-NEXT: [[COND105:%.*]] = phi i32 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND105]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP109]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP106:%.*]] = icmp slt i32 [[TMP110]], [[TMP111]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
|
|
// SIMD-ONLY0: cond.true107:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109:%.*]]
|
|
// SIMD-ONLY0: cond.false108:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109]]
|
|
// SIMD-ONLY0: cond.end109:
|
|
// SIMD-ONLY0-NEXT: [[COND110:%.*]] = phi i32 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND110]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP114]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP111:%.*]] = icmp eq i32 [[TMP115]], [[TMP116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
|
|
// SIMD-ONLY0: cond.true112:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114:%.*]]
|
|
// SIMD-ONLY0: cond.false113:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114]]
|
|
// SIMD-ONLY0: cond.end114:
|
|
// SIMD-ONLY0-NEXT: [[COND115:%.*]] = phi i32 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND115]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP119]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP120]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP116:%.*]] = icmp sgt i32 [[TMP121]], [[TMP122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
|
|
// SIMD-ONLY0: cond.true117:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119:%.*]]
|
|
// SIMD-ONLY0: cond.false118:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119]]
|
|
// SIMD-ONLY0: cond.end119:
|
|
// SIMD-ONLY0-NEXT: [[COND120:%.*]] = phi i32 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND120]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP125]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP121:%.*]] = icmp slt i32 [[TMP126]], [[TMP127]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
|
|
// SIMD-ONLY0: cond.true122:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false123:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i32 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND125]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP130]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP126:%.*]] = icmp eq i32 [[TMP131]], [[TMP132]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
|
|
// SIMD-ONLY0: cond.true127:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129:%.*]]
|
|
// SIMD-ONLY0: cond.false128:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129]]
|
|
// SIMD-ONLY0: cond.end129:
|
|
// SIMD-ONLY0-NEXT: [[COND130:%.*]] = phi i32 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND130]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP131:%.*]] = icmp sgt i32 [[TMP135]], [[TMP136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true132:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134]]
|
|
// SIMD-ONLY0: cond.end134:
|
|
// SIMD-ONLY0-NEXT: [[COND135:%.*]] = phi i32 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND135]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP139]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP136:%.*]] = icmp slt i32 [[TMP140]], [[TMP141]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
|
|
// SIMD-ONLY0: cond.true137:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139:%.*]]
|
|
// SIMD-ONLY0: cond.false138:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139]]
|
|
// SIMD-ONLY0: cond.end139:
|
|
// SIMD-ONLY0-NEXT: [[COND140:%.*]] = phi i32 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND140]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP144]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = icmp eq i32 [[TMP145]], [[TMP146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144:%.*]]
|
|
// SIMD-ONLY0: cond.false143:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144]]
|
|
// SIMD-ONLY0: cond.end144:
|
|
// SIMD-ONLY0-NEXT: [[COND145:%.*]] = phi i32 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND145]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP149]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP150]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP146:%.*]] = icmp sgt i32 [[TMP151]], [[TMP152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
|
|
// SIMD-ONLY0: cond.true147:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149:%.*]]
|
|
// SIMD-ONLY0: cond.false148:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149]]
|
|
// SIMD-ONLY0: cond.end149:
|
|
// SIMD-ONLY0-NEXT: [[COND150:%.*]] = phi i32 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND150]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP155]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp slt i32 [[TMP156]], [[TMP157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
|
|
// SIMD-ONLY0: cond.true152:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154:%.*]]
|
|
// SIMD-ONLY0: cond.false153:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154]]
|
|
// SIMD-ONLY0: cond.end154:
|
|
// SIMD-ONLY0-NEXT: [[COND155:%.*]] = phi i32 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND155]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP160]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP156:%.*]] = icmp eq i32 [[TMP161]], [[TMP162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
|
|
// SIMD-ONLY0: cond.true157:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159:%.*]]
|
|
// SIMD-ONLY0: cond.false158:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159]]
|
|
// SIMD-ONLY0: cond.end159:
|
|
// SIMD-ONLY0-NEXT: [[COND160:%.*]] = phi i32 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND160]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP161:%.*]] = icmp sgt i32 [[TMP165]], [[TMP166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
|
|
// SIMD-ONLY0: cond.true162:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164:%.*]]
|
|
// SIMD-ONLY0: cond.false163:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164]]
|
|
// SIMD-ONLY0: cond.end164:
|
|
// SIMD-ONLY0-NEXT: [[COND165:%.*]] = phi i32 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND165]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP169]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP166:%.*]] = icmp slt i32 [[TMP170]], [[TMP171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
|
|
// SIMD-ONLY0: cond.true167:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169:%.*]]
|
|
// SIMD-ONLY0: cond.false168:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169]]
|
|
// SIMD-ONLY0: cond.end169:
|
|
// SIMD-ONLY0-NEXT: [[COND170:%.*]] = phi i32 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND170]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP174]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i32, ptr [[IE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP171:%.*]] = icmp eq i32 [[TMP175]], [[TMP176]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
|
|
// SIMD-ONLY0: cond.true172:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i32, ptr [[ID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174:%.*]]
|
|
// SIMD-ONLY0: cond.false173:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174]]
|
|
// SIMD-ONLY0: cond.end174:
|
|
// SIMD-ONLY0-NEXT: [[COND175:%.*]] = phi i32 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND175]], ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i32, ptr [[IX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP179]], ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i32, ptr [[IV]], align 4
|
|
// SIMD-ONLY0-NEXT: ret i32 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @uixevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[UIX:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UIV:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UIE:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[UID:%.*]] = alloca i32, align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP0]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP1]], [[TMP2]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i32 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP5]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP1:%.*]] = icmp ult i32 [[TMP6]], [[TMP7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
|
|
// SIMD-ONLY0: cond.true2:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4:%.*]]
|
|
// SIMD-ONLY0: cond.false3:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4]]
|
|
// SIMD-ONLY0: cond.end4:
|
|
// SIMD-ONLY0-NEXT: [[COND5:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND5]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP10]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6:%.*]] = icmp eq i32 [[TMP11]], [[TMP12]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
|
|
// SIMD-ONLY0: cond.true7:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9:%.*]]
|
|
// SIMD-ONLY0: cond.false8:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9]]
|
|
// SIMD-ONLY0: cond.end9:
|
|
// SIMD-ONLY0-NEXT: [[COND10:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND10]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP11:%.*]] = icmp ugt i32 [[TMP15]], [[TMP16]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
|
|
// SIMD-ONLY0: cond.true12:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false13:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND15]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP19]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP16:%.*]] = icmp ult i32 [[TMP20]], [[TMP21]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
|
|
// SIMD-ONLY0: cond.true17:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19:%.*]]
|
|
// SIMD-ONLY0: cond.false18:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19]]
|
|
// SIMD-ONLY0: cond.end19:
|
|
// SIMD-ONLY0-NEXT: [[COND20:%.*]] = phi i32 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND20]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP24]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP21:%.*]] = icmp eq i32 [[TMP25]], [[TMP26]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true22:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24]]
|
|
// SIMD-ONLY0: cond.end24:
|
|
// SIMD-ONLY0-NEXT: [[COND25:%.*]] = phi i32 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND25]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP29]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP30]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP26:%.*]] = icmp ugt i32 [[TMP31]], [[TMP32]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
|
|
// SIMD-ONLY0: cond.true27:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29:%.*]]
|
|
// SIMD-ONLY0: cond.false28:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29]]
|
|
// SIMD-ONLY0: cond.end29:
|
|
// SIMD-ONLY0-NEXT: [[COND30:%.*]] = phi i32 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND30]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP35]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP36]], [[TMP37]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34:%.*]]
|
|
// SIMD-ONLY0: cond.false33:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34]]
|
|
// SIMD-ONLY0: cond.end34:
|
|
// SIMD-ONLY0-NEXT: [[COND35:%.*]] = phi i32 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND35]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP40]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP36:%.*]] = icmp eq i32 [[TMP41]], [[TMP42]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
|
|
// SIMD-ONLY0: cond.true37:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39:%.*]]
|
|
// SIMD-ONLY0: cond.false38:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39]]
|
|
// SIMD-ONLY0: cond.end39:
|
|
// SIMD-ONLY0-NEXT: [[COND40:%.*]] = phi i32 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND40]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp ugt i32 [[TMP45]], [[TMP46]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
|
|
// SIMD-ONLY0: cond.true42:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44:%.*]]
|
|
// SIMD-ONLY0: cond.false43:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44]]
|
|
// SIMD-ONLY0: cond.end44:
|
|
// SIMD-ONLY0-NEXT: [[COND45:%.*]] = phi i32 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND45]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP49]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP46:%.*]] = icmp ult i32 [[TMP50]], [[TMP51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
|
|
// SIMD-ONLY0: cond.true47:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49:%.*]]
|
|
// SIMD-ONLY0: cond.false48:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49]]
|
|
// SIMD-ONLY0: cond.end49:
|
|
// SIMD-ONLY0-NEXT: [[COND50:%.*]] = phi i32 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND50]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP54]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP51:%.*]] = icmp eq i32 [[TMP55]], [[TMP56]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
|
|
// SIMD-ONLY0: cond.true52:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54:%.*]]
|
|
// SIMD-ONLY0: cond.false53:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54]]
|
|
// SIMD-ONLY0: cond.end54:
|
|
// SIMD-ONLY0-NEXT: [[COND55:%.*]] = phi i32 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND55]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP59]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP60]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP56:%.*]] = icmp ugt i32 [[TMP61]], [[TMP62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
|
|
// SIMD-ONLY0: cond.true57:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59:%.*]]
|
|
// SIMD-ONLY0: cond.false58:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59]]
|
|
// SIMD-ONLY0: cond.end59:
|
|
// SIMD-ONLY0-NEXT: [[COND60:%.*]] = phi i32 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND60]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP65]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP61:%.*]] = icmp ult i32 [[TMP66]], [[TMP67]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
|
|
// SIMD-ONLY0: cond.true62:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64:%.*]]
|
|
// SIMD-ONLY0: cond.false63:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64]]
|
|
// SIMD-ONLY0: cond.end64:
|
|
// SIMD-ONLY0-NEXT: [[COND65:%.*]] = phi i32 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND65]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP70]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP66:%.*]] = icmp eq i32 [[TMP71]], [[TMP72]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
|
|
// SIMD-ONLY0: cond.true67:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false68:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i32 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND70]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP71:%.*]] = icmp ugt i32 [[TMP75]], [[TMP76]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
|
|
// SIMD-ONLY0: cond.true72:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74:%.*]]
|
|
// SIMD-ONLY0: cond.false73:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74]]
|
|
// SIMD-ONLY0: cond.end74:
|
|
// SIMD-ONLY0-NEXT: [[COND75:%.*]] = phi i32 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND75]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP79]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP76:%.*]] = icmp ult i32 [[TMP80]], [[TMP81]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true77:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79]]
|
|
// SIMD-ONLY0: cond.end79:
|
|
// SIMD-ONLY0-NEXT: [[COND80:%.*]] = phi i32 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND80]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP84]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP81:%.*]] = icmp eq i32 [[TMP85]], [[TMP86]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
|
|
// SIMD-ONLY0: cond.true82:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84:%.*]]
|
|
// SIMD-ONLY0: cond.false83:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84]]
|
|
// SIMD-ONLY0: cond.end84:
|
|
// SIMD-ONLY0-NEXT: [[COND85:%.*]] = phi i32 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND85]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP89]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP90]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP86:%.*]] = icmp ugt i32 [[TMP91]], [[TMP92]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89:%.*]]
|
|
// SIMD-ONLY0: cond.false88:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89]]
|
|
// SIMD-ONLY0: cond.end89:
|
|
// SIMD-ONLY0-NEXT: [[COND90:%.*]] = phi i32 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND90]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP95]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = icmp ult i32 [[TMP96]], [[TMP97]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
|
|
// SIMD-ONLY0: cond.true92:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94:%.*]]
|
|
// SIMD-ONLY0: cond.false93:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94]]
|
|
// SIMD-ONLY0: cond.end94:
|
|
// SIMD-ONLY0-NEXT: [[COND95:%.*]] = phi i32 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND95]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP100]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp eq i32 [[TMP101]], [[TMP102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
|
|
// SIMD-ONLY0: cond.true97:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99:%.*]]
|
|
// SIMD-ONLY0: cond.false98:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99]]
|
|
// SIMD-ONLY0: cond.end99:
|
|
// SIMD-ONLY0-NEXT: [[COND100:%.*]] = phi i32 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND100]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP101:%.*]] = icmp ugt i32 [[TMP105]], [[TMP106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
|
|
// SIMD-ONLY0: cond.true102:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104:%.*]]
|
|
// SIMD-ONLY0: cond.false103:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104]]
|
|
// SIMD-ONLY0: cond.end104:
|
|
// SIMD-ONLY0-NEXT: [[COND105:%.*]] = phi i32 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND105]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP109]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP106:%.*]] = icmp ult i32 [[TMP110]], [[TMP111]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
|
|
// SIMD-ONLY0: cond.true107:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109:%.*]]
|
|
// SIMD-ONLY0: cond.false108:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109]]
|
|
// SIMD-ONLY0: cond.end109:
|
|
// SIMD-ONLY0-NEXT: [[COND110:%.*]] = phi i32 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND110]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP114]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP111:%.*]] = icmp eq i32 [[TMP115]], [[TMP116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
|
|
// SIMD-ONLY0: cond.true112:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114:%.*]]
|
|
// SIMD-ONLY0: cond.false113:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114]]
|
|
// SIMD-ONLY0: cond.end114:
|
|
// SIMD-ONLY0-NEXT: [[COND115:%.*]] = phi i32 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND115]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP119]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP120]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP116:%.*]] = icmp ugt i32 [[TMP121]], [[TMP122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
|
|
// SIMD-ONLY0: cond.true117:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119:%.*]]
|
|
// SIMD-ONLY0: cond.false118:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119]]
|
|
// SIMD-ONLY0: cond.end119:
|
|
// SIMD-ONLY0-NEXT: [[COND120:%.*]] = phi i32 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND120]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP125]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP121:%.*]] = icmp ult i32 [[TMP126]], [[TMP127]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
|
|
// SIMD-ONLY0: cond.true122:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false123:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i32 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND125]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP130]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP126:%.*]] = icmp eq i32 [[TMP131]], [[TMP132]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
|
|
// SIMD-ONLY0: cond.true127:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129:%.*]]
|
|
// SIMD-ONLY0: cond.false128:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129]]
|
|
// SIMD-ONLY0: cond.end129:
|
|
// SIMD-ONLY0-NEXT: [[COND130:%.*]] = phi i32 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND130]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP131:%.*]] = icmp ugt i32 [[TMP135]], [[TMP136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true132:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134]]
|
|
// SIMD-ONLY0: cond.end134:
|
|
// SIMD-ONLY0-NEXT: [[COND135:%.*]] = phi i32 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND135]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP139]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP136:%.*]] = icmp ult i32 [[TMP140]], [[TMP141]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
|
|
// SIMD-ONLY0: cond.true137:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139:%.*]]
|
|
// SIMD-ONLY0: cond.false138:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139]]
|
|
// SIMD-ONLY0: cond.end139:
|
|
// SIMD-ONLY0-NEXT: [[COND140:%.*]] = phi i32 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND140]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP144]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = icmp eq i32 [[TMP145]], [[TMP146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144:%.*]]
|
|
// SIMD-ONLY0: cond.false143:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144]]
|
|
// SIMD-ONLY0: cond.end144:
|
|
// SIMD-ONLY0-NEXT: [[COND145:%.*]] = phi i32 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND145]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP149]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP150]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP146:%.*]] = icmp ugt i32 [[TMP151]], [[TMP152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
|
|
// SIMD-ONLY0: cond.true147:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149:%.*]]
|
|
// SIMD-ONLY0: cond.false148:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149]]
|
|
// SIMD-ONLY0: cond.end149:
|
|
// SIMD-ONLY0-NEXT: [[COND150:%.*]] = phi i32 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND150]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP155]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp ult i32 [[TMP156]], [[TMP157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
|
|
// SIMD-ONLY0: cond.true152:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154:%.*]]
|
|
// SIMD-ONLY0: cond.false153:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154]]
|
|
// SIMD-ONLY0: cond.end154:
|
|
// SIMD-ONLY0-NEXT: [[COND155:%.*]] = phi i32 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND155]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP160]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP156:%.*]] = icmp eq i32 [[TMP161]], [[TMP162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
|
|
// SIMD-ONLY0: cond.true157:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159:%.*]]
|
|
// SIMD-ONLY0: cond.false158:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159]]
|
|
// SIMD-ONLY0: cond.end159:
|
|
// SIMD-ONLY0-NEXT: [[COND160:%.*]] = phi i32 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND160]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP161:%.*]] = icmp ugt i32 [[TMP165]], [[TMP166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
|
|
// SIMD-ONLY0: cond.true162:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164:%.*]]
|
|
// SIMD-ONLY0: cond.false163:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164]]
|
|
// SIMD-ONLY0: cond.end164:
|
|
// SIMD-ONLY0-NEXT: [[COND165:%.*]] = phi i32 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND165]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP169]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP166:%.*]] = icmp ult i32 [[TMP170]], [[TMP171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
|
|
// SIMD-ONLY0: cond.true167:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169:%.*]]
|
|
// SIMD-ONLY0: cond.false168:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169]]
|
|
// SIMD-ONLY0: cond.end169:
|
|
// SIMD-ONLY0-NEXT: [[COND170:%.*]] = phi i32 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND170]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP174]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i32, ptr [[UIE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP171:%.*]] = icmp eq i32 [[TMP175]], [[TMP176]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
|
|
// SIMD-ONLY0: cond.true172:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i32, ptr [[UID]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174:%.*]]
|
|
// SIMD-ONLY0: cond.false173:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174]]
|
|
// SIMD-ONLY0: cond.end174:
|
|
// SIMD-ONLY0-NEXT: [[COND175:%.*]] = phi i32 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
|
|
// SIMD-ONLY0-NEXT: store i32 [[COND175]], ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i32, ptr [[UIX]], align 4
|
|
// SIMD-ONLY0-NEXT: store i32 [[TMP179]], ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i32, ptr [[UIV]], align 4
|
|
// SIMD-ONLY0-NEXT: ret i32 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @lxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[LX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LV:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP0]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP1]], [[TMP2]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i64 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP5]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP1:%.*]] = icmp slt i64 [[TMP6]], [[TMP7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
|
|
// SIMD-ONLY0: cond.true2:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4:%.*]]
|
|
// SIMD-ONLY0: cond.false3:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4]]
|
|
// SIMD-ONLY0: cond.end4:
|
|
// SIMD-ONLY0-NEXT: [[COND5:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND5]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP10]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6:%.*]] = icmp eq i64 [[TMP11]], [[TMP12]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
|
|
// SIMD-ONLY0: cond.true7:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9:%.*]]
|
|
// SIMD-ONLY0: cond.false8:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9]]
|
|
// SIMD-ONLY0: cond.end9:
|
|
// SIMD-ONLY0-NEXT: [[COND10:%.*]] = phi i64 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND10]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP11:%.*]] = icmp sgt i64 [[TMP15]], [[TMP16]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
|
|
// SIMD-ONLY0: cond.true12:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false13:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND15]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP19]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP16:%.*]] = icmp slt i64 [[TMP20]], [[TMP21]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
|
|
// SIMD-ONLY0: cond.true17:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19:%.*]]
|
|
// SIMD-ONLY0: cond.false18:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19]]
|
|
// SIMD-ONLY0: cond.end19:
|
|
// SIMD-ONLY0-NEXT: [[COND20:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND20]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP24]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP21:%.*]] = icmp eq i64 [[TMP25]], [[TMP26]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true22:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24]]
|
|
// SIMD-ONLY0: cond.end24:
|
|
// SIMD-ONLY0-NEXT: [[COND25:%.*]] = phi i64 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND25]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP29]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP30]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP26:%.*]] = icmp sgt i64 [[TMP31]], [[TMP32]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
|
|
// SIMD-ONLY0: cond.true27:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29:%.*]]
|
|
// SIMD-ONLY0: cond.false28:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29]]
|
|
// SIMD-ONLY0: cond.end29:
|
|
// SIMD-ONLY0-NEXT: [[COND30:%.*]] = phi i64 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND30]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP35]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP31:%.*]] = icmp slt i64 [[TMP36]], [[TMP37]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34:%.*]]
|
|
// SIMD-ONLY0: cond.false33:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34]]
|
|
// SIMD-ONLY0: cond.end34:
|
|
// SIMD-ONLY0-NEXT: [[COND35:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND35]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP40]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP36:%.*]] = icmp eq i64 [[TMP41]], [[TMP42]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
|
|
// SIMD-ONLY0: cond.true37:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39:%.*]]
|
|
// SIMD-ONLY0: cond.false38:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39]]
|
|
// SIMD-ONLY0: cond.end39:
|
|
// SIMD-ONLY0-NEXT: [[COND40:%.*]] = phi i64 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND40]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp sgt i64 [[TMP45]], [[TMP46]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
|
|
// SIMD-ONLY0: cond.true42:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44:%.*]]
|
|
// SIMD-ONLY0: cond.false43:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44]]
|
|
// SIMD-ONLY0: cond.end44:
|
|
// SIMD-ONLY0-NEXT: [[COND45:%.*]] = phi i64 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND45]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP49]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP46:%.*]] = icmp slt i64 [[TMP50]], [[TMP51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
|
|
// SIMD-ONLY0: cond.true47:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49:%.*]]
|
|
// SIMD-ONLY0: cond.false48:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49]]
|
|
// SIMD-ONLY0: cond.end49:
|
|
// SIMD-ONLY0-NEXT: [[COND50:%.*]] = phi i64 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND50]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP54]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP51:%.*]] = icmp eq i64 [[TMP55]], [[TMP56]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
|
|
// SIMD-ONLY0: cond.true52:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54:%.*]]
|
|
// SIMD-ONLY0: cond.false53:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54]]
|
|
// SIMD-ONLY0: cond.end54:
|
|
// SIMD-ONLY0-NEXT: [[COND55:%.*]] = phi i64 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND55]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP59]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP60]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP56:%.*]] = icmp sgt i64 [[TMP61]], [[TMP62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
|
|
// SIMD-ONLY0: cond.true57:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59:%.*]]
|
|
// SIMD-ONLY0: cond.false58:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59]]
|
|
// SIMD-ONLY0: cond.end59:
|
|
// SIMD-ONLY0-NEXT: [[COND60:%.*]] = phi i64 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND60]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP65]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP61:%.*]] = icmp slt i64 [[TMP66]], [[TMP67]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
|
|
// SIMD-ONLY0: cond.true62:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64:%.*]]
|
|
// SIMD-ONLY0: cond.false63:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64]]
|
|
// SIMD-ONLY0: cond.end64:
|
|
// SIMD-ONLY0-NEXT: [[COND65:%.*]] = phi i64 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND65]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP70]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP66:%.*]] = icmp eq i64 [[TMP71]], [[TMP72]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
|
|
// SIMD-ONLY0: cond.true67:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false68:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i64 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND70]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP71:%.*]] = icmp sgt i64 [[TMP75]], [[TMP76]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
|
|
// SIMD-ONLY0: cond.true72:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74:%.*]]
|
|
// SIMD-ONLY0: cond.false73:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74]]
|
|
// SIMD-ONLY0: cond.end74:
|
|
// SIMD-ONLY0-NEXT: [[COND75:%.*]] = phi i64 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND75]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP79]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP76:%.*]] = icmp slt i64 [[TMP80]], [[TMP81]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true77:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79]]
|
|
// SIMD-ONLY0: cond.end79:
|
|
// SIMD-ONLY0-NEXT: [[COND80:%.*]] = phi i64 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND80]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP84]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP81:%.*]] = icmp eq i64 [[TMP85]], [[TMP86]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
|
|
// SIMD-ONLY0: cond.true82:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84:%.*]]
|
|
// SIMD-ONLY0: cond.false83:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84]]
|
|
// SIMD-ONLY0: cond.end84:
|
|
// SIMD-ONLY0-NEXT: [[COND85:%.*]] = phi i64 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND85]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP89]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP90]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP86:%.*]] = icmp sgt i64 [[TMP91]], [[TMP92]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89:%.*]]
|
|
// SIMD-ONLY0: cond.false88:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89]]
|
|
// SIMD-ONLY0: cond.end89:
|
|
// SIMD-ONLY0-NEXT: [[COND90:%.*]] = phi i64 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND90]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP95]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = icmp slt i64 [[TMP96]], [[TMP97]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
|
|
// SIMD-ONLY0: cond.true92:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94:%.*]]
|
|
// SIMD-ONLY0: cond.false93:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94]]
|
|
// SIMD-ONLY0: cond.end94:
|
|
// SIMD-ONLY0-NEXT: [[COND95:%.*]] = phi i64 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND95]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP100]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp eq i64 [[TMP101]], [[TMP102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
|
|
// SIMD-ONLY0: cond.true97:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99:%.*]]
|
|
// SIMD-ONLY0: cond.false98:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99]]
|
|
// SIMD-ONLY0: cond.end99:
|
|
// SIMD-ONLY0-NEXT: [[COND100:%.*]] = phi i64 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND100]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP101:%.*]] = icmp sgt i64 [[TMP105]], [[TMP106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
|
|
// SIMD-ONLY0: cond.true102:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104:%.*]]
|
|
// SIMD-ONLY0: cond.false103:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104]]
|
|
// SIMD-ONLY0: cond.end104:
|
|
// SIMD-ONLY0-NEXT: [[COND105:%.*]] = phi i64 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND105]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP109]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP106:%.*]] = icmp slt i64 [[TMP110]], [[TMP111]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
|
|
// SIMD-ONLY0: cond.true107:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109:%.*]]
|
|
// SIMD-ONLY0: cond.false108:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109]]
|
|
// SIMD-ONLY0: cond.end109:
|
|
// SIMD-ONLY0-NEXT: [[COND110:%.*]] = phi i64 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND110]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP114]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP111:%.*]] = icmp eq i64 [[TMP115]], [[TMP116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
|
|
// SIMD-ONLY0: cond.true112:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114:%.*]]
|
|
// SIMD-ONLY0: cond.false113:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114]]
|
|
// SIMD-ONLY0: cond.end114:
|
|
// SIMD-ONLY0-NEXT: [[COND115:%.*]] = phi i64 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND115]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP119]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP120]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP116:%.*]] = icmp sgt i64 [[TMP121]], [[TMP122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
|
|
// SIMD-ONLY0: cond.true117:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119:%.*]]
|
|
// SIMD-ONLY0: cond.false118:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119]]
|
|
// SIMD-ONLY0: cond.end119:
|
|
// SIMD-ONLY0-NEXT: [[COND120:%.*]] = phi i64 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND120]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP125]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP121:%.*]] = icmp slt i64 [[TMP126]], [[TMP127]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
|
|
// SIMD-ONLY0: cond.true122:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false123:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i64 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND125]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP130]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP126:%.*]] = icmp eq i64 [[TMP131]], [[TMP132]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
|
|
// SIMD-ONLY0: cond.true127:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129:%.*]]
|
|
// SIMD-ONLY0: cond.false128:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129]]
|
|
// SIMD-ONLY0: cond.end129:
|
|
// SIMD-ONLY0-NEXT: [[COND130:%.*]] = phi i64 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND130]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP131:%.*]] = icmp sgt i64 [[TMP135]], [[TMP136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true132:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134]]
|
|
// SIMD-ONLY0: cond.end134:
|
|
// SIMD-ONLY0-NEXT: [[COND135:%.*]] = phi i64 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND135]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP139]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP136:%.*]] = icmp slt i64 [[TMP140]], [[TMP141]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
|
|
// SIMD-ONLY0: cond.true137:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139:%.*]]
|
|
// SIMD-ONLY0: cond.false138:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139]]
|
|
// SIMD-ONLY0: cond.end139:
|
|
// SIMD-ONLY0-NEXT: [[COND140:%.*]] = phi i64 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND140]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP144]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = icmp eq i64 [[TMP145]], [[TMP146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144:%.*]]
|
|
// SIMD-ONLY0: cond.false143:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144]]
|
|
// SIMD-ONLY0: cond.end144:
|
|
// SIMD-ONLY0-NEXT: [[COND145:%.*]] = phi i64 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND145]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP149]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP150]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP146:%.*]] = icmp sgt i64 [[TMP151]], [[TMP152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
|
|
// SIMD-ONLY0: cond.true147:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149:%.*]]
|
|
// SIMD-ONLY0: cond.false148:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149]]
|
|
// SIMD-ONLY0: cond.end149:
|
|
// SIMD-ONLY0-NEXT: [[COND150:%.*]] = phi i64 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND150]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP155]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp slt i64 [[TMP156]], [[TMP157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
|
|
// SIMD-ONLY0: cond.true152:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154:%.*]]
|
|
// SIMD-ONLY0: cond.false153:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154]]
|
|
// SIMD-ONLY0: cond.end154:
|
|
// SIMD-ONLY0-NEXT: [[COND155:%.*]] = phi i64 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND155]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP160]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP156:%.*]] = icmp eq i64 [[TMP161]], [[TMP162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
|
|
// SIMD-ONLY0: cond.true157:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159:%.*]]
|
|
// SIMD-ONLY0: cond.false158:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159]]
|
|
// SIMD-ONLY0: cond.end159:
|
|
// SIMD-ONLY0-NEXT: [[COND160:%.*]] = phi i64 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND160]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP161:%.*]] = icmp sgt i64 [[TMP165]], [[TMP166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
|
|
// SIMD-ONLY0: cond.true162:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164:%.*]]
|
|
// SIMD-ONLY0: cond.false163:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164]]
|
|
// SIMD-ONLY0: cond.end164:
|
|
// SIMD-ONLY0-NEXT: [[COND165:%.*]] = phi i64 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND165]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP169]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP166:%.*]] = icmp slt i64 [[TMP170]], [[TMP171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
|
|
// SIMD-ONLY0: cond.true167:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169:%.*]]
|
|
// SIMD-ONLY0: cond.false168:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169]]
|
|
// SIMD-ONLY0: cond.end169:
|
|
// SIMD-ONLY0-NEXT: [[COND170:%.*]] = phi i64 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND170]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP174]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i64, ptr [[LE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP171:%.*]] = icmp eq i64 [[TMP175]], [[TMP176]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
|
|
// SIMD-ONLY0: cond.true172:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i64, ptr [[LD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174:%.*]]
|
|
// SIMD-ONLY0: cond.false173:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174]]
|
|
// SIMD-ONLY0: cond.end174:
|
|
// SIMD-ONLY0-NEXT: [[COND175:%.*]] = phi i64 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND175]], ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i64, ptr [[LX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP179]], ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i64, ptr [[LV]], align 8
|
|
// SIMD-ONLY0-NEXT: ret i64 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @ulxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[ULX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULV:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP0]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP1]], [[TMP2]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i64 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP5]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP1:%.*]] = icmp ult i64 [[TMP6]], [[TMP7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
|
|
// SIMD-ONLY0: cond.true2:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4:%.*]]
|
|
// SIMD-ONLY0: cond.false3:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4]]
|
|
// SIMD-ONLY0: cond.end4:
|
|
// SIMD-ONLY0-NEXT: [[COND5:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND5]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP10]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6:%.*]] = icmp eq i64 [[TMP11]], [[TMP12]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
|
|
// SIMD-ONLY0: cond.true7:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9:%.*]]
|
|
// SIMD-ONLY0: cond.false8:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9]]
|
|
// SIMD-ONLY0: cond.end9:
|
|
// SIMD-ONLY0-NEXT: [[COND10:%.*]] = phi i64 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND10]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP11:%.*]] = icmp ugt i64 [[TMP15]], [[TMP16]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
|
|
// SIMD-ONLY0: cond.true12:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false13:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND15]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP19]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP16:%.*]] = icmp ult i64 [[TMP20]], [[TMP21]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
|
|
// SIMD-ONLY0: cond.true17:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19:%.*]]
|
|
// SIMD-ONLY0: cond.false18:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19]]
|
|
// SIMD-ONLY0: cond.end19:
|
|
// SIMD-ONLY0-NEXT: [[COND20:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND20]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP24]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP21:%.*]] = icmp eq i64 [[TMP25]], [[TMP26]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true22:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24]]
|
|
// SIMD-ONLY0: cond.end24:
|
|
// SIMD-ONLY0-NEXT: [[COND25:%.*]] = phi i64 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND25]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP29]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP30]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP26:%.*]] = icmp ugt i64 [[TMP31]], [[TMP32]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
|
|
// SIMD-ONLY0: cond.true27:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29:%.*]]
|
|
// SIMD-ONLY0: cond.false28:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29]]
|
|
// SIMD-ONLY0: cond.end29:
|
|
// SIMD-ONLY0-NEXT: [[COND30:%.*]] = phi i64 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND30]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP35]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP31:%.*]] = icmp ult i64 [[TMP36]], [[TMP37]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34:%.*]]
|
|
// SIMD-ONLY0: cond.false33:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34]]
|
|
// SIMD-ONLY0: cond.end34:
|
|
// SIMD-ONLY0-NEXT: [[COND35:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND35]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP40]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP36:%.*]] = icmp eq i64 [[TMP41]], [[TMP42]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
|
|
// SIMD-ONLY0: cond.true37:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39:%.*]]
|
|
// SIMD-ONLY0: cond.false38:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39]]
|
|
// SIMD-ONLY0: cond.end39:
|
|
// SIMD-ONLY0-NEXT: [[COND40:%.*]] = phi i64 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND40]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp ugt i64 [[TMP45]], [[TMP46]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
|
|
// SIMD-ONLY0: cond.true42:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44:%.*]]
|
|
// SIMD-ONLY0: cond.false43:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44]]
|
|
// SIMD-ONLY0: cond.end44:
|
|
// SIMD-ONLY0-NEXT: [[COND45:%.*]] = phi i64 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND45]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP49]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP46:%.*]] = icmp ult i64 [[TMP50]], [[TMP51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
|
|
// SIMD-ONLY0: cond.true47:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49:%.*]]
|
|
// SIMD-ONLY0: cond.false48:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49]]
|
|
// SIMD-ONLY0: cond.end49:
|
|
// SIMD-ONLY0-NEXT: [[COND50:%.*]] = phi i64 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND50]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP54]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP51:%.*]] = icmp eq i64 [[TMP55]], [[TMP56]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
|
|
// SIMD-ONLY0: cond.true52:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54:%.*]]
|
|
// SIMD-ONLY0: cond.false53:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54]]
|
|
// SIMD-ONLY0: cond.end54:
|
|
// SIMD-ONLY0-NEXT: [[COND55:%.*]] = phi i64 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND55]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP59]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP60]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP56:%.*]] = icmp ugt i64 [[TMP61]], [[TMP62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
|
|
// SIMD-ONLY0: cond.true57:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59:%.*]]
|
|
// SIMD-ONLY0: cond.false58:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59]]
|
|
// SIMD-ONLY0: cond.end59:
|
|
// SIMD-ONLY0-NEXT: [[COND60:%.*]] = phi i64 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND60]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP65]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP61:%.*]] = icmp ult i64 [[TMP66]], [[TMP67]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
|
|
// SIMD-ONLY0: cond.true62:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64:%.*]]
|
|
// SIMD-ONLY0: cond.false63:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64]]
|
|
// SIMD-ONLY0: cond.end64:
|
|
// SIMD-ONLY0-NEXT: [[COND65:%.*]] = phi i64 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND65]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP70]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP66:%.*]] = icmp eq i64 [[TMP71]], [[TMP72]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
|
|
// SIMD-ONLY0: cond.true67:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false68:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i64 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND70]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP71:%.*]] = icmp ugt i64 [[TMP75]], [[TMP76]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
|
|
// SIMD-ONLY0: cond.true72:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74:%.*]]
|
|
// SIMD-ONLY0: cond.false73:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74]]
|
|
// SIMD-ONLY0: cond.end74:
|
|
// SIMD-ONLY0-NEXT: [[COND75:%.*]] = phi i64 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND75]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP79]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP76:%.*]] = icmp ult i64 [[TMP80]], [[TMP81]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true77:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79]]
|
|
// SIMD-ONLY0: cond.end79:
|
|
// SIMD-ONLY0-NEXT: [[COND80:%.*]] = phi i64 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND80]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP84]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP81:%.*]] = icmp eq i64 [[TMP85]], [[TMP86]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
|
|
// SIMD-ONLY0: cond.true82:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84:%.*]]
|
|
// SIMD-ONLY0: cond.false83:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84]]
|
|
// SIMD-ONLY0: cond.end84:
|
|
// SIMD-ONLY0-NEXT: [[COND85:%.*]] = phi i64 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND85]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP89]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP90]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP86:%.*]] = icmp ugt i64 [[TMP91]], [[TMP92]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89:%.*]]
|
|
// SIMD-ONLY0: cond.false88:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89]]
|
|
// SIMD-ONLY0: cond.end89:
|
|
// SIMD-ONLY0-NEXT: [[COND90:%.*]] = phi i64 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND90]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP95]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = icmp ult i64 [[TMP96]], [[TMP97]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
|
|
// SIMD-ONLY0: cond.true92:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94:%.*]]
|
|
// SIMD-ONLY0: cond.false93:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94]]
|
|
// SIMD-ONLY0: cond.end94:
|
|
// SIMD-ONLY0-NEXT: [[COND95:%.*]] = phi i64 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND95]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP100]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp eq i64 [[TMP101]], [[TMP102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
|
|
// SIMD-ONLY0: cond.true97:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99:%.*]]
|
|
// SIMD-ONLY0: cond.false98:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99]]
|
|
// SIMD-ONLY0: cond.end99:
|
|
// SIMD-ONLY0-NEXT: [[COND100:%.*]] = phi i64 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND100]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP101:%.*]] = icmp ugt i64 [[TMP105]], [[TMP106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
|
|
// SIMD-ONLY0: cond.true102:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104:%.*]]
|
|
// SIMD-ONLY0: cond.false103:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104]]
|
|
// SIMD-ONLY0: cond.end104:
|
|
// SIMD-ONLY0-NEXT: [[COND105:%.*]] = phi i64 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND105]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP109]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP106:%.*]] = icmp ult i64 [[TMP110]], [[TMP111]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
|
|
// SIMD-ONLY0: cond.true107:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109:%.*]]
|
|
// SIMD-ONLY0: cond.false108:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109]]
|
|
// SIMD-ONLY0: cond.end109:
|
|
// SIMD-ONLY0-NEXT: [[COND110:%.*]] = phi i64 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND110]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP114]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP111:%.*]] = icmp eq i64 [[TMP115]], [[TMP116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
|
|
// SIMD-ONLY0: cond.true112:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114:%.*]]
|
|
// SIMD-ONLY0: cond.false113:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114]]
|
|
// SIMD-ONLY0: cond.end114:
|
|
// SIMD-ONLY0-NEXT: [[COND115:%.*]] = phi i64 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND115]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP119]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP120]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP116:%.*]] = icmp ugt i64 [[TMP121]], [[TMP122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
|
|
// SIMD-ONLY0: cond.true117:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119:%.*]]
|
|
// SIMD-ONLY0: cond.false118:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119]]
|
|
// SIMD-ONLY0: cond.end119:
|
|
// SIMD-ONLY0-NEXT: [[COND120:%.*]] = phi i64 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND120]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP125]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP121:%.*]] = icmp ult i64 [[TMP126]], [[TMP127]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
|
|
// SIMD-ONLY0: cond.true122:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false123:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i64 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND125]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP130]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP126:%.*]] = icmp eq i64 [[TMP131]], [[TMP132]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
|
|
// SIMD-ONLY0: cond.true127:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129:%.*]]
|
|
// SIMD-ONLY0: cond.false128:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129]]
|
|
// SIMD-ONLY0: cond.end129:
|
|
// SIMD-ONLY0-NEXT: [[COND130:%.*]] = phi i64 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND130]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP131:%.*]] = icmp ugt i64 [[TMP135]], [[TMP136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true132:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134]]
|
|
// SIMD-ONLY0: cond.end134:
|
|
// SIMD-ONLY0-NEXT: [[COND135:%.*]] = phi i64 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND135]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP139]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP136:%.*]] = icmp ult i64 [[TMP140]], [[TMP141]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
|
|
// SIMD-ONLY0: cond.true137:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139:%.*]]
|
|
// SIMD-ONLY0: cond.false138:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139]]
|
|
// SIMD-ONLY0: cond.end139:
|
|
// SIMD-ONLY0-NEXT: [[COND140:%.*]] = phi i64 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND140]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP144]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = icmp eq i64 [[TMP145]], [[TMP146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144:%.*]]
|
|
// SIMD-ONLY0: cond.false143:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144]]
|
|
// SIMD-ONLY0: cond.end144:
|
|
// SIMD-ONLY0-NEXT: [[COND145:%.*]] = phi i64 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND145]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP149]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP150]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP146:%.*]] = icmp ugt i64 [[TMP151]], [[TMP152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
|
|
// SIMD-ONLY0: cond.true147:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149:%.*]]
|
|
// SIMD-ONLY0: cond.false148:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149]]
|
|
// SIMD-ONLY0: cond.end149:
|
|
// SIMD-ONLY0-NEXT: [[COND150:%.*]] = phi i64 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND150]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP155]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp ult i64 [[TMP156]], [[TMP157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
|
|
// SIMD-ONLY0: cond.true152:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154:%.*]]
|
|
// SIMD-ONLY0: cond.false153:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154]]
|
|
// SIMD-ONLY0: cond.end154:
|
|
// SIMD-ONLY0-NEXT: [[COND155:%.*]] = phi i64 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND155]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP160]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP156:%.*]] = icmp eq i64 [[TMP161]], [[TMP162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
|
|
// SIMD-ONLY0: cond.true157:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159:%.*]]
|
|
// SIMD-ONLY0: cond.false158:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159]]
|
|
// SIMD-ONLY0: cond.end159:
|
|
// SIMD-ONLY0-NEXT: [[COND160:%.*]] = phi i64 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND160]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP161:%.*]] = icmp ugt i64 [[TMP165]], [[TMP166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
|
|
// SIMD-ONLY0: cond.true162:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164:%.*]]
|
|
// SIMD-ONLY0: cond.false163:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164]]
|
|
// SIMD-ONLY0: cond.end164:
|
|
// SIMD-ONLY0-NEXT: [[COND165:%.*]] = phi i64 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND165]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP169]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP166:%.*]] = icmp ult i64 [[TMP170]], [[TMP171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
|
|
// SIMD-ONLY0: cond.true167:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169:%.*]]
|
|
// SIMD-ONLY0: cond.false168:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169]]
|
|
// SIMD-ONLY0: cond.end169:
|
|
// SIMD-ONLY0-NEXT: [[COND170:%.*]] = phi i64 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND170]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP174]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i64, ptr [[ULE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP171:%.*]] = icmp eq i64 [[TMP175]], [[TMP176]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
|
|
// SIMD-ONLY0: cond.true172:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i64, ptr [[ULD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174:%.*]]
|
|
// SIMD-ONLY0: cond.false173:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174]]
|
|
// SIMD-ONLY0: cond.end174:
|
|
// SIMD-ONLY0-NEXT: [[COND175:%.*]] = phi i64 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND175]], ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i64, ptr [[ULX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP179]], ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i64, ptr [[ULV]], align 8
|
|
// SIMD-ONLY0-NEXT: ret i64 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @llxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[LLX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLV:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[LLD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP0]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP1]], [[TMP2]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i64 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP5]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP1:%.*]] = icmp slt i64 [[TMP6]], [[TMP7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
|
|
// SIMD-ONLY0: cond.true2:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4:%.*]]
|
|
// SIMD-ONLY0: cond.false3:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4]]
|
|
// SIMD-ONLY0: cond.end4:
|
|
// SIMD-ONLY0-NEXT: [[COND5:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND5]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP10]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6:%.*]] = icmp eq i64 [[TMP11]], [[TMP12]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
|
|
// SIMD-ONLY0: cond.true7:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9:%.*]]
|
|
// SIMD-ONLY0: cond.false8:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9]]
|
|
// SIMD-ONLY0: cond.end9:
|
|
// SIMD-ONLY0-NEXT: [[COND10:%.*]] = phi i64 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND10]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP11:%.*]] = icmp sgt i64 [[TMP15]], [[TMP16]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
|
|
// SIMD-ONLY0: cond.true12:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false13:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND15]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP19]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP16:%.*]] = icmp slt i64 [[TMP20]], [[TMP21]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
|
|
// SIMD-ONLY0: cond.true17:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19:%.*]]
|
|
// SIMD-ONLY0: cond.false18:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19]]
|
|
// SIMD-ONLY0: cond.end19:
|
|
// SIMD-ONLY0-NEXT: [[COND20:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND20]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP24]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP21:%.*]] = icmp eq i64 [[TMP25]], [[TMP26]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true22:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24]]
|
|
// SIMD-ONLY0: cond.end24:
|
|
// SIMD-ONLY0-NEXT: [[COND25:%.*]] = phi i64 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND25]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP29]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP30]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP26:%.*]] = icmp sgt i64 [[TMP31]], [[TMP32]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
|
|
// SIMD-ONLY0: cond.true27:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29:%.*]]
|
|
// SIMD-ONLY0: cond.false28:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29]]
|
|
// SIMD-ONLY0: cond.end29:
|
|
// SIMD-ONLY0-NEXT: [[COND30:%.*]] = phi i64 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND30]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP35]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP31:%.*]] = icmp slt i64 [[TMP36]], [[TMP37]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34:%.*]]
|
|
// SIMD-ONLY0: cond.false33:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34]]
|
|
// SIMD-ONLY0: cond.end34:
|
|
// SIMD-ONLY0-NEXT: [[COND35:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND35]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP40]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP36:%.*]] = icmp eq i64 [[TMP41]], [[TMP42]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
|
|
// SIMD-ONLY0: cond.true37:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39:%.*]]
|
|
// SIMD-ONLY0: cond.false38:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39]]
|
|
// SIMD-ONLY0: cond.end39:
|
|
// SIMD-ONLY0-NEXT: [[COND40:%.*]] = phi i64 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND40]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp sgt i64 [[TMP45]], [[TMP46]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
|
|
// SIMD-ONLY0: cond.true42:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44:%.*]]
|
|
// SIMD-ONLY0: cond.false43:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44]]
|
|
// SIMD-ONLY0: cond.end44:
|
|
// SIMD-ONLY0-NEXT: [[COND45:%.*]] = phi i64 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND45]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP49]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP46:%.*]] = icmp slt i64 [[TMP50]], [[TMP51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
|
|
// SIMD-ONLY0: cond.true47:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49:%.*]]
|
|
// SIMD-ONLY0: cond.false48:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49]]
|
|
// SIMD-ONLY0: cond.end49:
|
|
// SIMD-ONLY0-NEXT: [[COND50:%.*]] = phi i64 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND50]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP54]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP51:%.*]] = icmp eq i64 [[TMP55]], [[TMP56]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
|
|
// SIMD-ONLY0: cond.true52:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54:%.*]]
|
|
// SIMD-ONLY0: cond.false53:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54]]
|
|
// SIMD-ONLY0: cond.end54:
|
|
// SIMD-ONLY0-NEXT: [[COND55:%.*]] = phi i64 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND55]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP59]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP60]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP56:%.*]] = icmp sgt i64 [[TMP61]], [[TMP62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
|
|
// SIMD-ONLY0: cond.true57:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59:%.*]]
|
|
// SIMD-ONLY0: cond.false58:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59]]
|
|
// SIMD-ONLY0: cond.end59:
|
|
// SIMD-ONLY0-NEXT: [[COND60:%.*]] = phi i64 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND60]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP65]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP61:%.*]] = icmp slt i64 [[TMP66]], [[TMP67]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
|
|
// SIMD-ONLY0: cond.true62:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64:%.*]]
|
|
// SIMD-ONLY0: cond.false63:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64]]
|
|
// SIMD-ONLY0: cond.end64:
|
|
// SIMD-ONLY0-NEXT: [[COND65:%.*]] = phi i64 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND65]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP70]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP66:%.*]] = icmp eq i64 [[TMP71]], [[TMP72]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
|
|
// SIMD-ONLY0: cond.true67:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false68:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i64 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND70]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP71:%.*]] = icmp sgt i64 [[TMP75]], [[TMP76]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
|
|
// SIMD-ONLY0: cond.true72:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74:%.*]]
|
|
// SIMD-ONLY0: cond.false73:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74]]
|
|
// SIMD-ONLY0: cond.end74:
|
|
// SIMD-ONLY0-NEXT: [[COND75:%.*]] = phi i64 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND75]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP79]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP76:%.*]] = icmp slt i64 [[TMP80]], [[TMP81]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true77:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79]]
|
|
// SIMD-ONLY0: cond.end79:
|
|
// SIMD-ONLY0-NEXT: [[COND80:%.*]] = phi i64 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND80]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP84]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP81:%.*]] = icmp eq i64 [[TMP85]], [[TMP86]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
|
|
// SIMD-ONLY0: cond.true82:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84:%.*]]
|
|
// SIMD-ONLY0: cond.false83:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84]]
|
|
// SIMD-ONLY0: cond.end84:
|
|
// SIMD-ONLY0-NEXT: [[COND85:%.*]] = phi i64 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND85]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP89]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP90]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP86:%.*]] = icmp sgt i64 [[TMP91]], [[TMP92]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89:%.*]]
|
|
// SIMD-ONLY0: cond.false88:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89]]
|
|
// SIMD-ONLY0: cond.end89:
|
|
// SIMD-ONLY0-NEXT: [[COND90:%.*]] = phi i64 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND90]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP95]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = icmp slt i64 [[TMP96]], [[TMP97]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
|
|
// SIMD-ONLY0: cond.true92:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94:%.*]]
|
|
// SIMD-ONLY0: cond.false93:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94]]
|
|
// SIMD-ONLY0: cond.end94:
|
|
// SIMD-ONLY0-NEXT: [[COND95:%.*]] = phi i64 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND95]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP100]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp eq i64 [[TMP101]], [[TMP102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
|
|
// SIMD-ONLY0: cond.true97:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99:%.*]]
|
|
// SIMD-ONLY0: cond.false98:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99]]
|
|
// SIMD-ONLY0: cond.end99:
|
|
// SIMD-ONLY0-NEXT: [[COND100:%.*]] = phi i64 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND100]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP101:%.*]] = icmp sgt i64 [[TMP105]], [[TMP106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
|
|
// SIMD-ONLY0: cond.true102:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104:%.*]]
|
|
// SIMD-ONLY0: cond.false103:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104]]
|
|
// SIMD-ONLY0: cond.end104:
|
|
// SIMD-ONLY0-NEXT: [[COND105:%.*]] = phi i64 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND105]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP109]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP106:%.*]] = icmp slt i64 [[TMP110]], [[TMP111]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
|
|
// SIMD-ONLY0: cond.true107:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109:%.*]]
|
|
// SIMD-ONLY0: cond.false108:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109]]
|
|
// SIMD-ONLY0: cond.end109:
|
|
// SIMD-ONLY0-NEXT: [[COND110:%.*]] = phi i64 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND110]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP114]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP111:%.*]] = icmp eq i64 [[TMP115]], [[TMP116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
|
|
// SIMD-ONLY0: cond.true112:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114:%.*]]
|
|
// SIMD-ONLY0: cond.false113:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114]]
|
|
// SIMD-ONLY0: cond.end114:
|
|
// SIMD-ONLY0-NEXT: [[COND115:%.*]] = phi i64 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND115]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP119]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP120]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP116:%.*]] = icmp sgt i64 [[TMP121]], [[TMP122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
|
|
// SIMD-ONLY0: cond.true117:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119:%.*]]
|
|
// SIMD-ONLY0: cond.false118:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119]]
|
|
// SIMD-ONLY0: cond.end119:
|
|
// SIMD-ONLY0-NEXT: [[COND120:%.*]] = phi i64 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND120]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP125]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP121:%.*]] = icmp slt i64 [[TMP126]], [[TMP127]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
|
|
// SIMD-ONLY0: cond.true122:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false123:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i64 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND125]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP130]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP126:%.*]] = icmp eq i64 [[TMP131]], [[TMP132]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
|
|
// SIMD-ONLY0: cond.true127:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129:%.*]]
|
|
// SIMD-ONLY0: cond.false128:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129]]
|
|
// SIMD-ONLY0: cond.end129:
|
|
// SIMD-ONLY0-NEXT: [[COND130:%.*]] = phi i64 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND130]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP131:%.*]] = icmp sgt i64 [[TMP135]], [[TMP136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true132:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134]]
|
|
// SIMD-ONLY0: cond.end134:
|
|
// SIMD-ONLY0-NEXT: [[COND135:%.*]] = phi i64 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND135]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP139]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP136:%.*]] = icmp slt i64 [[TMP140]], [[TMP141]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
|
|
// SIMD-ONLY0: cond.true137:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139:%.*]]
|
|
// SIMD-ONLY0: cond.false138:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139]]
|
|
// SIMD-ONLY0: cond.end139:
|
|
// SIMD-ONLY0-NEXT: [[COND140:%.*]] = phi i64 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND140]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP144]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = icmp eq i64 [[TMP145]], [[TMP146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144:%.*]]
|
|
// SIMD-ONLY0: cond.false143:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144]]
|
|
// SIMD-ONLY0: cond.end144:
|
|
// SIMD-ONLY0-NEXT: [[COND145:%.*]] = phi i64 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND145]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP149]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP150]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP146:%.*]] = icmp sgt i64 [[TMP151]], [[TMP152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
|
|
// SIMD-ONLY0: cond.true147:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149:%.*]]
|
|
// SIMD-ONLY0: cond.false148:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149]]
|
|
// SIMD-ONLY0: cond.end149:
|
|
// SIMD-ONLY0-NEXT: [[COND150:%.*]] = phi i64 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND150]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP155]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp slt i64 [[TMP156]], [[TMP157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
|
|
// SIMD-ONLY0: cond.true152:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154:%.*]]
|
|
// SIMD-ONLY0: cond.false153:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154]]
|
|
// SIMD-ONLY0: cond.end154:
|
|
// SIMD-ONLY0-NEXT: [[COND155:%.*]] = phi i64 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND155]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP160]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP156:%.*]] = icmp eq i64 [[TMP161]], [[TMP162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
|
|
// SIMD-ONLY0: cond.true157:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159:%.*]]
|
|
// SIMD-ONLY0: cond.false158:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159]]
|
|
// SIMD-ONLY0: cond.end159:
|
|
// SIMD-ONLY0-NEXT: [[COND160:%.*]] = phi i64 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND160]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP161:%.*]] = icmp sgt i64 [[TMP165]], [[TMP166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
|
|
// SIMD-ONLY0: cond.true162:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164:%.*]]
|
|
// SIMD-ONLY0: cond.false163:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164]]
|
|
// SIMD-ONLY0: cond.end164:
|
|
// SIMD-ONLY0-NEXT: [[COND165:%.*]] = phi i64 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND165]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP169]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP166:%.*]] = icmp slt i64 [[TMP170]], [[TMP171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
|
|
// SIMD-ONLY0: cond.true167:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169:%.*]]
|
|
// SIMD-ONLY0: cond.false168:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169]]
|
|
// SIMD-ONLY0: cond.end169:
|
|
// SIMD-ONLY0-NEXT: [[COND170:%.*]] = phi i64 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND170]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP174]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i64, ptr [[LLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP171:%.*]] = icmp eq i64 [[TMP175]], [[TMP176]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
|
|
// SIMD-ONLY0: cond.true172:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i64, ptr [[LLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174:%.*]]
|
|
// SIMD-ONLY0: cond.false173:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174]]
|
|
// SIMD-ONLY0: cond.end174:
|
|
// SIMD-ONLY0-NEXT: [[COND175:%.*]] = phi i64 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND175]], ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i64, ptr [[LLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP179]], ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i64, ptr [[LLV]], align 8
|
|
// SIMD-ONLY0-NEXT: ret i64 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @ullxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[ULLX:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLV:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLE:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[ULLD:%.*]] = alloca i64, align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP0]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP1]], [[TMP2]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi i64 [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP5]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP1:%.*]] = icmp ult i64 [[TMP6]], [[TMP7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
|
|
// SIMD-ONLY0: cond.true2:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4:%.*]]
|
|
// SIMD-ONLY0: cond.false3:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4]]
|
|
// SIMD-ONLY0: cond.end4:
|
|
// SIMD-ONLY0-NEXT: [[COND5:%.*]] = phi i64 [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND5]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP10]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6:%.*]] = icmp eq i64 [[TMP11]], [[TMP12]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
|
|
// SIMD-ONLY0: cond.true7:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9:%.*]]
|
|
// SIMD-ONLY0: cond.false8:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9]]
|
|
// SIMD-ONLY0: cond.end9:
|
|
// SIMD-ONLY0-NEXT: [[COND10:%.*]] = phi i64 [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND10]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP11:%.*]] = icmp ugt i64 [[TMP15]], [[TMP16]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
|
|
// SIMD-ONLY0: cond.true12:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false13:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND15]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP19]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP16:%.*]] = icmp ult i64 [[TMP20]], [[TMP21]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
|
|
// SIMD-ONLY0: cond.true17:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19:%.*]]
|
|
// SIMD-ONLY0: cond.false18:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19]]
|
|
// SIMD-ONLY0: cond.end19:
|
|
// SIMD-ONLY0-NEXT: [[COND20:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND20]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP24]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP21:%.*]] = icmp eq i64 [[TMP25]], [[TMP26]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true22:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24]]
|
|
// SIMD-ONLY0: cond.end24:
|
|
// SIMD-ONLY0-NEXT: [[COND25:%.*]] = phi i64 [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND25]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP29]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP30]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP26:%.*]] = icmp ugt i64 [[TMP31]], [[TMP32]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
|
|
// SIMD-ONLY0: cond.true27:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29:%.*]]
|
|
// SIMD-ONLY0: cond.false28:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29]]
|
|
// SIMD-ONLY0: cond.end29:
|
|
// SIMD-ONLY0-NEXT: [[COND30:%.*]] = phi i64 [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND30]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP35]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP31:%.*]] = icmp ult i64 [[TMP36]], [[TMP37]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34:%.*]]
|
|
// SIMD-ONLY0: cond.false33:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34]]
|
|
// SIMD-ONLY0: cond.end34:
|
|
// SIMD-ONLY0-NEXT: [[COND35:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND35]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP40]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP36:%.*]] = icmp eq i64 [[TMP41]], [[TMP42]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
|
|
// SIMD-ONLY0: cond.true37:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39:%.*]]
|
|
// SIMD-ONLY0: cond.false38:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39]]
|
|
// SIMD-ONLY0: cond.end39:
|
|
// SIMD-ONLY0-NEXT: [[COND40:%.*]] = phi i64 [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND40]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = icmp ugt i64 [[TMP45]], [[TMP46]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
|
|
// SIMD-ONLY0: cond.true42:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44:%.*]]
|
|
// SIMD-ONLY0: cond.false43:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44]]
|
|
// SIMD-ONLY0: cond.end44:
|
|
// SIMD-ONLY0-NEXT: [[COND45:%.*]] = phi i64 [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND45]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP49]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP46:%.*]] = icmp ult i64 [[TMP50]], [[TMP51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
|
|
// SIMD-ONLY0: cond.true47:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49:%.*]]
|
|
// SIMD-ONLY0: cond.false48:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49]]
|
|
// SIMD-ONLY0: cond.end49:
|
|
// SIMD-ONLY0-NEXT: [[COND50:%.*]] = phi i64 [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND50]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP54]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP51:%.*]] = icmp eq i64 [[TMP55]], [[TMP56]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
|
|
// SIMD-ONLY0: cond.true52:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54:%.*]]
|
|
// SIMD-ONLY0: cond.false53:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54]]
|
|
// SIMD-ONLY0: cond.end54:
|
|
// SIMD-ONLY0-NEXT: [[COND55:%.*]] = phi i64 [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND55]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP59]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP60]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP56:%.*]] = icmp ugt i64 [[TMP61]], [[TMP62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
|
|
// SIMD-ONLY0: cond.true57:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59:%.*]]
|
|
// SIMD-ONLY0: cond.false58:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59]]
|
|
// SIMD-ONLY0: cond.end59:
|
|
// SIMD-ONLY0-NEXT: [[COND60:%.*]] = phi i64 [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND60]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP65]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP61:%.*]] = icmp ult i64 [[TMP66]], [[TMP67]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
|
|
// SIMD-ONLY0: cond.true62:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64:%.*]]
|
|
// SIMD-ONLY0: cond.false63:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64]]
|
|
// SIMD-ONLY0: cond.end64:
|
|
// SIMD-ONLY0-NEXT: [[COND65:%.*]] = phi i64 [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND65]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP70]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP66:%.*]] = icmp eq i64 [[TMP71]], [[TMP72]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
|
|
// SIMD-ONLY0: cond.true67:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false68:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi i64 [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND70]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP71:%.*]] = icmp ugt i64 [[TMP75]], [[TMP76]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
|
|
// SIMD-ONLY0: cond.true72:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74:%.*]]
|
|
// SIMD-ONLY0: cond.false73:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74]]
|
|
// SIMD-ONLY0: cond.end74:
|
|
// SIMD-ONLY0-NEXT: [[COND75:%.*]] = phi i64 [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND75]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP79]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP76:%.*]] = icmp ult i64 [[TMP80]], [[TMP81]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true77:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79]]
|
|
// SIMD-ONLY0: cond.end79:
|
|
// SIMD-ONLY0-NEXT: [[COND80:%.*]] = phi i64 [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND80]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP84]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP81:%.*]] = icmp eq i64 [[TMP85]], [[TMP86]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
|
|
// SIMD-ONLY0: cond.true82:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84:%.*]]
|
|
// SIMD-ONLY0: cond.false83:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84]]
|
|
// SIMD-ONLY0: cond.end84:
|
|
// SIMD-ONLY0-NEXT: [[COND85:%.*]] = phi i64 [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND85]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP89]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP90]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP86:%.*]] = icmp ugt i64 [[TMP91]], [[TMP92]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89:%.*]]
|
|
// SIMD-ONLY0: cond.false88:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89]]
|
|
// SIMD-ONLY0: cond.end89:
|
|
// SIMD-ONLY0-NEXT: [[COND90:%.*]] = phi i64 [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND90]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP95]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = icmp ult i64 [[TMP96]], [[TMP97]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
|
|
// SIMD-ONLY0: cond.true92:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94:%.*]]
|
|
// SIMD-ONLY0: cond.false93:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94]]
|
|
// SIMD-ONLY0: cond.end94:
|
|
// SIMD-ONLY0-NEXT: [[COND95:%.*]] = phi i64 [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND95]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP100]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = icmp eq i64 [[TMP101]], [[TMP102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
|
|
// SIMD-ONLY0: cond.true97:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99:%.*]]
|
|
// SIMD-ONLY0: cond.false98:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99]]
|
|
// SIMD-ONLY0: cond.end99:
|
|
// SIMD-ONLY0-NEXT: [[COND100:%.*]] = phi i64 [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND100]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP101:%.*]] = icmp ugt i64 [[TMP105]], [[TMP106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
|
|
// SIMD-ONLY0: cond.true102:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104:%.*]]
|
|
// SIMD-ONLY0: cond.false103:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104]]
|
|
// SIMD-ONLY0: cond.end104:
|
|
// SIMD-ONLY0-NEXT: [[COND105:%.*]] = phi i64 [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND105]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP109]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP106:%.*]] = icmp ult i64 [[TMP110]], [[TMP111]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
|
|
// SIMD-ONLY0: cond.true107:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109:%.*]]
|
|
// SIMD-ONLY0: cond.false108:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109]]
|
|
// SIMD-ONLY0: cond.end109:
|
|
// SIMD-ONLY0-NEXT: [[COND110:%.*]] = phi i64 [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND110]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP114]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP111:%.*]] = icmp eq i64 [[TMP115]], [[TMP116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
|
|
// SIMD-ONLY0: cond.true112:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114:%.*]]
|
|
// SIMD-ONLY0: cond.false113:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114]]
|
|
// SIMD-ONLY0: cond.end114:
|
|
// SIMD-ONLY0-NEXT: [[COND115:%.*]] = phi i64 [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND115]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP119]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP120]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP116:%.*]] = icmp ugt i64 [[TMP121]], [[TMP122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
|
|
// SIMD-ONLY0: cond.true117:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119:%.*]]
|
|
// SIMD-ONLY0: cond.false118:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119]]
|
|
// SIMD-ONLY0: cond.end119:
|
|
// SIMD-ONLY0-NEXT: [[COND120:%.*]] = phi i64 [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND120]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP125]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP121:%.*]] = icmp ult i64 [[TMP126]], [[TMP127]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
|
|
// SIMD-ONLY0: cond.true122:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false123:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi i64 [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND125]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP130]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP126:%.*]] = icmp eq i64 [[TMP131]], [[TMP132]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
|
|
// SIMD-ONLY0: cond.true127:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129:%.*]]
|
|
// SIMD-ONLY0: cond.false128:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129]]
|
|
// SIMD-ONLY0: cond.end129:
|
|
// SIMD-ONLY0-NEXT: [[COND130:%.*]] = phi i64 [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND130]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP131:%.*]] = icmp ugt i64 [[TMP135]], [[TMP136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true132:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134]]
|
|
// SIMD-ONLY0: cond.end134:
|
|
// SIMD-ONLY0-NEXT: [[COND135:%.*]] = phi i64 [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND135]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP139]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP136:%.*]] = icmp ult i64 [[TMP140]], [[TMP141]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
|
|
// SIMD-ONLY0: cond.true137:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139:%.*]]
|
|
// SIMD-ONLY0: cond.false138:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139]]
|
|
// SIMD-ONLY0: cond.end139:
|
|
// SIMD-ONLY0-NEXT: [[COND140:%.*]] = phi i64 [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND140]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP144]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = icmp eq i64 [[TMP145]], [[TMP146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144:%.*]]
|
|
// SIMD-ONLY0: cond.false143:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144]]
|
|
// SIMD-ONLY0: cond.end144:
|
|
// SIMD-ONLY0-NEXT: [[COND145:%.*]] = phi i64 [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND145]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP149]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP150]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP146:%.*]] = icmp ugt i64 [[TMP151]], [[TMP152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
|
|
// SIMD-ONLY0: cond.true147:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149:%.*]]
|
|
// SIMD-ONLY0: cond.false148:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149]]
|
|
// SIMD-ONLY0: cond.end149:
|
|
// SIMD-ONLY0-NEXT: [[COND150:%.*]] = phi i64 [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND150]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP155]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = icmp ult i64 [[TMP156]], [[TMP157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
|
|
// SIMD-ONLY0: cond.true152:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154:%.*]]
|
|
// SIMD-ONLY0: cond.false153:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154]]
|
|
// SIMD-ONLY0: cond.end154:
|
|
// SIMD-ONLY0-NEXT: [[COND155:%.*]] = phi i64 [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND155]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP160]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP156:%.*]] = icmp eq i64 [[TMP161]], [[TMP162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
|
|
// SIMD-ONLY0: cond.true157:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159:%.*]]
|
|
// SIMD-ONLY0: cond.false158:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159]]
|
|
// SIMD-ONLY0: cond.end159:
|
|
// SIMD-ONLY0-NEXT: [[COND160:%.*]] = phi i64 [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND160]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP161:%.*]] = icmp ugt i64 [[TMP165]], [[TMP166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
|
|
// SIMD-ONLY0: cond.true162:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164:%.*]]
|
|
// SIMD-ONLY0: cond.false163:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164]]
|
|
// SIMD-ONLY0: cond.end164:
|
|
// SIMD-ONLY0-NEXT: [[COND165:%.*]] = phi i64 [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND165]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP169]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP166:%.*]] = icmp ult i64 [[TMP170]], [[TMP171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
|
|
// SIMD-ONLY0: cond.true167:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169:%.*]]
|
|
// SIMD-ONLY0: cond.false168:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169]]
|
|
// SIMD-ONLY0: cond.end169:
|
|
// SIMD-ONLY0-NEXT: [[COND170:%.*]] = phi i64 [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND170]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP174]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load i64, ptr [[ULLE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP171:%.*]] = icmp eq i64 [[TMP175]], [[TMP176]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
|
|
// SIMD-ONLY0: cond.true172:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load i64, ptr [[ULLD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174:%.*]]
|
|
// SIMD-ONLY0: cond.false173:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174]]
|
|
// SIMD-ONLY0: cond.end174:
|
|
// SIMD-ONLY0-NEXT: [[COND175:%.*]] = phi i64 [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
|
|
// SIMD-ONLY0-NEXT: store i64 [[COND175]], ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load i64, ptr [[ULLX]], align 8
|
|
// SIMD-ONLY0-NEXT: store i64 [[TMP179]], ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load i64, ptr [[ULLV]], align 8
|
|
// SIMD-ONLY0-NEXT: ret i64 [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @fxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[FX:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[FV:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[FE:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[FD:%.*]] = alloca float, align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP0]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = fcmp ogt float [[TMP1]], [[TMP2]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi float [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP5]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP1:%.*]] = fcmp olt float [[TMP6]], [[TMP7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
|
|
// SIMD-ONLY0: cond.true2:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4:%.*]]
|
|
// SIMD-ONLY0: cond.false3:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4]]
|
|
// SIMD-ONLY0: cond.end4:
|
|
// SIMD-ONLY0-NEXT: [[COND5:%.*]] = phi float [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND5]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP10]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP6:%.*]] = fcmp oeq float [[TMP11]], [[TMP12]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
|
|
// SIMD-ONLY0: cond.true7:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9:%.*]]
|
|
// SIMD-ONLY0: cond.false8:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9]]
|
|
// SIMD-ONLY0: cond.end9:
|
|
// SIMD-ONLY0-NEXT: [[COND10:%.*]] = phi float [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND10]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP11:%.*]] = fcmp ogt float [[TMP15]], [[TMP16]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
|
|
// SIMD-ONLY0: cond.true12:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false13:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi float [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND15]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP19]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP16:%.*]] = fcmp olt float [[TMP20]], [[TMP21]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
|
|
// SIMD-ONLY0: cond.true17:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19:%.*]]
|
|
// SIMD-ONLY0: cond.false18:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19]]
|
|
// SIMD-ONLY0: cond.end19:
|
|
// SIMD-ONLY0-NEXT: [[COND20:%.*]] = phi float [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND20]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP24]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP21:%.*]] = fcmp oeq float [[TMP25]], [[TMP26]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true22:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24]]
|
|
// SIMD-ONLY0: cond.end24:
|
|
// SIMD-ONLY0-NEXT: [[COND25:%.*]] = phi float [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND25]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP29]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP30]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP26:%.*]] = fcmp ogt float [[TMP31]], [[TMP32]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
|
|
// SIMD-ONLY0: cond.true27:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29:%.*]]
|
|
// SIMD-ONLY0: cond.false28:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29]]
|
|
// SIMD-ONLY0: cond.end29:
|
|
// SIMD-ONLY0-NEXT: [[COND30:%.*]] = phi float [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND30]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP35]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP31:%.*]] = fcmp olt float [[TMP36]], [[TMP37]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34:%.*]]
|
|
// SIMD-ONLY0: cond.false33:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34]]
|
|
// SIMD-ONLY0: cond.end34:
|
|
// SIMD-ONLY0-NEXT: [[COND35:%.*]] = phi float [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND35]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP40]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP36:%.*]] = fcmp oeq float [[TMP41]], [[TMP42]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
|
|
// SIMD-ONLY0: cond.true37:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39:%.*]]
|
|
// SIMD-ONLY0: cond.false38:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39]]
|
|
// SIMD-ONLY0: cond.end39:
|
|
// SIMD-ONLY0-NEXT: [[COND40:%.*]] = phi float [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND40]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = fcmp ogt float [[TMP45]], [[TMP46]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
|
|
// SIMD-ONLY0: cond.true42:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44:%.*]]
|
|
// SIMD-ONLY0: cond.false43:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44]]
|
|
// SIMD-ONLY0: cond.end44:
|
|
// SIMD-ONLY0-NEXT: [[COND45:%.*]] = phi float [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND45]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP49]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP46:%.*]] = fcmp olt float [[TMP50]], [[TMP51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
|
|
// SIMD-ONLY0: cond.true47:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49:%.*]]
|
|
// SIMD-ONLY0: cond.false48:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49]]
|
|
// SIMD-ONLY0: cond.end49:
|
|
// SIMD-ONLY0-NEXT: [[COND50:%.*]] = phi float [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND50]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP54]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP51:%.*]] = fcmp oeq float [[TMP55]], [[TMP56]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
|
|
// SIMD-ONLY0: cond.true52:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54:%.*]]
|
|
// SIMD-ONLY0: cond.false53:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54]]
|
|
// SIMD-ONLY0: cond.end54:
|
|
// SIMD-ONLY0-NEXT: [[COND55:%.*]] = phi float [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND55]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP59]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP60]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP56:%.*]] = fcmp ogt float [[TMP61]], [[TMP62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
|
|
// SIMD-ONLY0: cond.true57:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59:%.*]]
|
|
// SIMD-ONLY0: cond.false58:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59]]
|
|
// SIMD-ONLY0: cond.end59:
|
|
// SIMD-ONLY0-NEXT: [[COND60:%.*]] = phi float [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND60]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP65]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP61:%.*]] = fcmp olt float [[TMP66]], [[TMP67]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
|
|
// SIMD-ONLY0: cond.true62:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64:%.*]]
|
|
// SIMD-ONLY0: cond.false63:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64]]
|
|
// SIMD-ONLY0: cond.end64:
|
|
// SIMD-ONLY0-NEXT: [[COND65:%.*]] = phi float [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND65]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP70]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP66:%.*]] = fcmp oeq float [[TMP71]], [[TMP72]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
|
|
// SIMD-ONLY0: cond.true67:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false68:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi float [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND70]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP71:%.*]] = fcmp ogt float [[TMP75]], [[TMP76]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
|
|
// SIMD-ONLY0: cond.true72:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74:%.*]]
|
|
// SIMD-ONLY0: cond.false73:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74]]
|
|
// SIMD-ONLY0: cond.end74:
|
|
// SIMD-ONLY0-NEXT: [[COND75:%.*]] = phi float [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND75]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP79]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP76:%.*]] = fcmp olt float [[TMP80]], [[TMP81]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true77:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79]]
|
|
// SIMD-ONLY0: cond.end79:
|
|
// SIMD-ONLY0-NEXT: [[COND80:%.*]] = phi float [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND80]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP84]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP81:%.*]] = fcmp oeq float [[TMP85]], [[TMP86]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
|
|
// SIMD-ONLY0: cond.true82:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84:%.*]]
|
|
// SIMD-ONLY0: cond.false83:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84]]
|
|
// SIMD-ONLY0: cond.end84:
|
|
// SIMD-ONLY0-NEXT: [[COND85:%.*]] = phi float [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND85]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP89]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP90]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP86:%.*]] = fcmp ogt float [[TMP91]], [[TMP92]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89:%.*]]
|
|
// SIMD-ONLY0: cond.false88:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89]]
|
|
// SIMD-ONLY0: cond.end89:
|
|
// SIMD-ONLY0-NEXT: [[COND90:%.*]] = phi float [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND90]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP95]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = fcmp olt float [[TMP96]], [[TMP97]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
|
|
// SIMD-ONLY0: cond.true92:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94:%.*]]
|
|
// SIMD-ONLY0: cond.false93:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94]]
|
|
// SIMD-ONLY0: cond.end94:
|
|
// SIMD-ONLY0-NEXT: [[COND95:%.*]] = phi float [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND95]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP100]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = fcmp oeq float [[TMP101]], [[TMP102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
|
|
// SIMD-ONLY0: cond.true97:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99:%.*]]
|
|
// SIMD-ONLY0: cond.false98:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99]]
|
|
// SIMD-ONLY0: cond.end99:
|
|
// SIMD-ONLY0-NEXT: [[COND100:%.*]] = phi float [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND100]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP101:%.*]] = fcmp ogt float [[TMP105]], [[TMP106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
|
|
// SIMD-ONLY0: cond.true102:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104:%.*]]
|
|
// SIMD-ONLY0: cond.false103:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104]]
|
|
// SIMD-ONLY0: cond.end104:
|
|
// SIMD-ONLY0-NEXT: [[COND105:%.*]] = phi float [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND105]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP109]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP106:%.*]] = fcmp olt float [[TMP110]], [[TMP111]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
|
|
// SIMD-ONLY0: cond.true107:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109:%.*]]
|
|
// SIMD-ONLY0: cond.false108:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109]]
|
|
// SIMD-ONLY0: cond.end109:
|
|
// SIMD-ONLY0-NEXT: [[COND110:%.*]] = phi float [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND110]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP114]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP111:%.*]] = fcmp oeq float [[TMP115]], [[TMP116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
|
|
// SIMD-ONLY0: cond.true112:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114:%.*]]
|
|
// SIMD-ONLY0: cond.false113:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114]]
|
|
// SIMD-ONLY0: cond.end114:
|
|
// SIMD-ONLY0-NEXT: [[COND115:%.*]] = phi float [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND115]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP119]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP120]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP116:%.*]] = fcmp ogt float [[TMP121]], [[TMP122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
|
|
// SIMD-ONLY0: cond.true117:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119:%.*]]
|
|
// SIMD-ONLY0: cond.false118:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119]]
|
|
// SIMD-ONLY0: cond.end119:
|
|
// SIMD-ONLY0-NEXT: [[COND120:%.*]] = phi float [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND120]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP125]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP121:%.*]] = fcmp olt float [[TMP126]], [[TMP127]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
|
|
// SIMD-ONLY0: cond.true122:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false123:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi float [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND125]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP130]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP126:%.*]] = fcmp oeq float [[TMP131]], [[TMP132]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
|
|
// SIMD-ONLY0: cond.true127:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129:%.*]]
|
|
// SIMD-ONLY0: cond.false128:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129]]
|
|
// SIMD-ONLY0: cond.end129:
|
|
// SIMD-ONLY0-NEXT: [[COND130:%.*]] = phi float [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND130]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP131:%.*]] = fcmp ogt float [[TMP135]], [[TMP136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true132:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134]]
|
|
// SIMD-ONLY0: cond.end134:
|
|
// SIMD-ONLY0-NEXT: [[COND135:%.*]] = phi float [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND135]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP139]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP136:%.*]] = fcmp olt float [[TMP140]], [[TMP141]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
|
|
// SIMD-ONLY0: cond.true137:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139:%.*]]
|
|
// SIMD-ONLY0: cond.false138:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139]]
|
|
// SIMD-ONLY0: cond.end139:
|
|
// SIMD-ONLY0-NEXT: [[COND140:%.*]] = phi float [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND140]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP144]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = fcmp oeq float [[TMP145]], [[TMP146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144:%.*]]
|
|
// SIMD-ONLY0: cond.false143:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144]]
|
|
// SIMD-ONLY0: cond.end144:
|
|
// SIMD-ONLY0-NEXT: [[COND145:%.*]] = phi float [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND145]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP149]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP150]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP146:%.*]] = fcmp ogt float [[TMP151]], [[TMP152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
|
|
// SIMD-ONLY0: cond.true147:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149:%.*]]
|
|
// SIMD-ONLY0: cond.false148:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149]]
|
|
// SIMD-ONLY0: cond.end149:
|
|
// SIMD-ONLY0-NEXT: [[COND150:%.*]] = phi float [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND150]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP155]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = fcmp olt float [[TMP156]], [[TMP157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
|
|
// SIMD-ONLY0: cond.true152:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154:%.*]]
|
|
// SIMD-ONLY0: cond.false153:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154]]
|
|
// SIMD-ONLY0: cond.end154:
|
|
// SIMD-ONLY0-NEXT: [[COND155:%.*]] = phi float [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND155]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP160]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP156:%.*]] = fcmp oeq float [[TMP161]], [[TMP162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
|
|
// SIMD-ONLY0: cond.true157:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159:%.*]]
|
|
// SIMD-ONLY0: cond.false158:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159]]
|
|
// SIMD-ONLY0: cond.end159:
|
|
// SIMD-ONLY0-NEXT: [[COND160:%.*]] = phi float [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND160]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP161:%.*]] = fcmp ogt float [[TMP165]], [[TMP166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
|
|
// SIMD-ONLY0: cond.true162:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164:%.*]]
|
|
// SIMD-ONLY0: cond.false163:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164]]
|
|
// SIMD-ONLY0: cond.end164:
|
|
// SIMD-ONLY0-NEXT: [[COND165:%.*]] = phi float [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND165]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP169]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP166:%.*]] = fcmp olt float [[TMP170]], [[TMP171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
|
|
// SIMD-ONLY0: cond.true167:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169:%.*]]
|
|
// SIMD-ONLY0: cond.false168:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169]]
|
|
// SIMD-ONLY0: cond.end169:
|
|
// SIMD-ONLY0-NEXT: [[COND170:%.*]] = phi float [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND170]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP174]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load float, ptr [[FE]], align 4
|
|
// SIMD-ONLY0-NEXT: [[CMP171:%.*]] = fcmp oeq float [[TMP175]], [[TMP176]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
|
|
// SIMD-ONLY0: cond.true172:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load float, ptr [[FD]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174:%.*]]
|
|
// SIMD-ONLY0: cond.false173:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174]]
|
|
// SIMD-ONLY0: cond.end174:
|
|
// SIMD-ONLY0-NEXT: [[COND175:%.*]] = phi float [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
|
|
// SIMD-ONLY0-NEXT: store float [[COND175]], ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load float, ptr [[FX]], align 4
|
|
// SIMD-ONLY0-NEXT: store float [[TMP179]], ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load float, ptr [[FV]], align 4
|
|
// SIMD-ONLY0-NEXT: ret float [[TMP180]]
|
|
//
|
|
//
|
|
// SIMD-ONLY0-LABEL: @dxevd(
|
|
// SIMD-ONLY0-NEXT: entry:
|
|
// SIMD-ONLY0-NEXT: [[DX:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[DV:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[DE:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[DD:%.*]] = alloca double, align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP0]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP1]], [[TMP2]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// SIMD-ONLY0: cond.true:
|
|
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
|
|
// SIMD-ONLY0: cond.false:
|
|
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END]]
|
|
// SIMD-ONLY0: cond.end:
|
|
// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi double [ [[TMP3]], [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP5]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP1:%.*]] = fcmp olt double [[TMP6]], [[TMP7]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP1]], label [[COND_TRUE2:%.*]], label [[COND_FALSE3:%.*]]
|
|
// SIMD-ONLY0: cond.true2:
|
|
// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4:%.*]]
|
|
// SIMD-ONLY0: cond.false3:
|
|
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END4]]
|
|
// SIMD-ONLY0: cond.end4:
|
|
// SIMD-ONLY0-NEXT: [[COND5:%.*]] = phi double [ [[TMP8]], [[COND_TRUE2]] ], [ [[TMP9]], [[COND_FALSE3]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND5]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP10]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP6:%.*]] = fcmp oeq double [[TMP11]], [[TMP12]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
|
|
// SIMD-ONLY0: cond.true7:
|
|
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9:%.*]]
|
|
// SIMD-ONLY0: cond.false8:
|
|
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END9]]
|
|
// SIMD-ONLY0: cond.end9:
|
|
// SIMD-ONLY0-NEXT: [[COND10:%.*]] = phi double [ [[TMP13]], [[COND_TRUE7]] ], [ [[TMP14]], [[COND_FALSE8]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND10]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP11:%.*]] = fcmp ogt double [[TMP15]], [[TMP16]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
|
|
// SIMD-ONLY0: cond.true12:
|
|
// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14:%.*]]
|
|
// SIMD-ONLY0: cond.false13:
|
|
// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END14]]
|
|
// SIMD-ONLY0: cond.end14:
|
|
// SIMD-ONLY0-NEXT: [[COND15:%.*]] = phi double [ [[TMP17]], [[COND_TRUE12]] ], [ [[TMP18]], [[COND_FALSE13]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND15]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP19]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP16:%.*]] = fcmp olt double [[TMP20]], [[TMP21]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP16]], label [[COND_TRUE17:%.*]], label [[COND_FALSE18:%.*]]
|
|
// SIMD-ONLY0: cond.true17:
|
|
// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19:%.*]]
|
|
// SIMD-ONLY0: cond.false18:
|
|
// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END19]]
|
|
// SIMD-ONLY0: cond.end19:
|
|
// SIMD-ONLY0-NEXT: [[COND20:%.*]] = phi double [ [[TMP22]], [[COND_TRUE17]] ], [ [[TMP23]], [[COND_FALSE18]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND20]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP24]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP21:%.*]] = fcmp oeq double [[TMP25]], [[TMP26]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP21]], label [[COND_TRUE22:%.*]], label [[COND_FALSE23:%.*]]
|
|
// SIMD-ONLY0: cond.true22:
|
|
// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24:%.*]]
|
|
// SIMD-ONLY0: cond.false23:
|
|
// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END24]]
|
|
// SIMD-ONLY0: cond.end24:
|
|
// SIMD-ONLY0-NEXT: [[COND25:%.*]] = phi double [ [[TMP27]], [[COND_TRUE22]] ], [ [[TMP28]], [[COND_FALSE23]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND25]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP29]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP30]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP26:%.*]] = fcmp ogt double [[TMP31]], [[TMP32]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP26]], label [[COND_TRUE27:%.*]], label [[COND_FALSE28:%.*]]
|
|
// SIMD-ONLY0: cond.true27:
|
|
// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29:%.*]]
|
|
// SIMD-ONLY0: cond.false28:
|
|
// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END29]]
|
|
// SIMD-ONLY0: cond.end29:
|
|
// SIMD-ONLY0-NEXT: [[COND30:%.*]] = phi double [ [[TMP33]], [[COND_TRUE27]] ], [ [[TMP34]], [[COND_FALSE28]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND30]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP35]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP31:%.*]] = fcmp olt double [[TMP36]], [[TMP37]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP31]], label [[COND_TRUE32:%.*]], label [[COND_FALSE33:%.*]]
|
|
// SIMD-ONLY0: cond.true32:
|
|
// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34:%.*]]
|
|
// SIMD-ONLY0: cond.false33:
|
|
// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END34]]
|
|
// SIMD-ONLY0: cond.end34:
|
|
// SIMD-ONLY0-NEXT: [[COND35:%.*]] = phi double [ [[TMP38]], [[COND_TRUE32]] ], [ [[TMP39]], [[COND_FALSE33]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND35]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP40]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP36:%.*]] = fcmp oeq double [[TMP41]], [[TMP42]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP36]], label [[COND_TRUE37:%.*]], label [[COND_FALSE38:%.*]]
|
|
// SIMD-ONLY0: cond.true37:
|
|
// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39:%.*]]
|
|
// SIMD-ONLY0: cond.false38:
|
|
// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END39]]
|
|
// SIMD-ONLY0: cond.end39:
|
|
// SIMD-ONLY0-NEXT: [[COND40:%.*]] = phi double [ [[TMP43]], [[COND_TRUE37]] ], [ [[TMP44]], [[COND_FALSE38]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND40]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = fcmp ogt double [[TMP45]], [[TMP46]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[COND_TRUE42:%.*]], label [[COND_FALSE43:%.*]]
|
|
// SIMD-ONLY0: cond.true42:
|
|
// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44:%.*]]
|
|
// SIMD-ONLY0: cond.false43:
|
|
// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END44]]
|
|
// SIMD-ONLY0: cond.end44:
|
|
// SIMD-ONLY0-NEXT: [[COND45:%.*]] = phi double [ [[TMP47]], [[COND_TRUE42]] ], [ [[TMP48]], [[COND_FALSE43]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND45]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP49]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP46:%.*]] = fcmp olt double [[TMP50]], [[TMP51]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP46]], label [[COND_TRUE47:%.*]], label [[COND_FALSE48:%.*]]
|
|
// SIMD-ONLY0: cond.true47:
|
|
// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49:%.*]]
|
|
// SIMD-ONLY0: cond.false48:
|
|
// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END49]]
|
|
// SIMD-ONLY0: cond.end49:
|
|
// SIMD-ONLY0-NEXT: [[COND50:%.*]] = phi double [ [[TMP52]], [[COND_TRUE47]] ], [ [[TMP53]], [[COND_FALSE48]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND50]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP54]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP51:%.*]] = fcmp oeq double [[TMP55]], [[TMP56]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP51]], label [[COND_TRUE52:%.*]], label [[COND_FALSE53:%.*]]
|
|
// SIMD-ONLY0: cond.true52:
|
|
// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54:%.*]]
|
|
// SIMD-ONLY0: cond.false53:
|
|
// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END54]]
|
|
// SIMD-ONLY0: cond.end54:
|
|
// SIMD-ONLY0-NEXT: [[COND55:%.*]] = phi double [ [[TMP57]], [[COND_TRUE52]] ], [ [[TMP58]], [[COND_FALSE53]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND55]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP59]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP60]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP56:%.*]] = fcmp ogt double [[TMP61]], [[TMP62]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP56]], label [[COND_TRUE57:%.*]], label [[COND_FALSE58:%.*]]
|
|
// SIMD-ONLY0: cond.true57:
|
|
// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59:%.*]]
|
|
// SIMD-ONLY0: cond.false58:
|
|
// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END59]]
|
|
// SIMD-ONLY0: cond.end59:
|
|
// SIMD-ONLY0-NEXT: [[COND60:%.*]] = phi double [ [[TMP63]], [[COND_TRUE57]] ], [ [[TMP64]], [[COND_FALSE58]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND60]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP65]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP61:%.*]] = fcmp olt double [[TMP66]], [[TMP67]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP61]], label [[COND_TRUE62:%.*]], label [[COND_FALSE63:%.*]]
|
|
// SIMD-ONLY0: cond.true62:
|
|
// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64:%.*]]
|
|
// SIMD-ONLY0: cond.false63:
|
|
// SIMD-ONLY0-NEXT: [[TMP69:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END64]]
|
|
// SIMD-ONLY0: cond.end64:
|
|
// SIMD-ONLY0-NEXT: [[COND65:%.*]] = phi double [ [[TMP68]], [[COND_TRUE62]] ], [ [[TMP69]], [[COND_FALSE63]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND65]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP70:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP70]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP71:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP72:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP66:%.*]] = fcmp oeq double [[TMP71]], [[TMP72]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP66]], label [[COND_TRUE67:%.*]], label [[COND_FALSE68:%.*]]
|
|
// SIMD-ONLY0: cond.true67:
|
|
// SIMD-ONLY0-NEXT: [[TMP73:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69:%.*]]
|
|
// SIMD-ONLY0: cond.false68:
|
|
// SIMD-ONLY0-NEXT: [[TMP74:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END69]]
|
|
// SIMD-ONLY0: cond.end69:
|
|
// SIMD-ONLY0-NEXT: [[COND70:%.*]] = phi double [ [[TMP73]], [[COND_TRUE67]] ], [ [[TMP74]], [[COND_FALSE68]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND70]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP75:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP76:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP71:%.*]] = fcmp ogt double [[TMP75]], [[TMP76]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP71]], label [[COND_TRUE72:%.*]], label [[COND_FALSE73:%.*]]
|
|
// SIMD-ONLY0: cond.true72:
|
|
// SIMD-ONLY0-NEXT: [[TMP77:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74:%.*]]
|
|
// SIMD-ONLY0: cond.false73:
|
|
// SIMD-ONLY0-NEXT: [[TMP78:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END74]]
|
|
// SIMD-ONLY0: cond.end74:
|
|
// SIMD-ONLY0-NEXT: [[COND75:%.*]] = phi double [ [[TMP77]], [[COND_TRUE72]] ], [ [[TMP78]], [[COND_FALSE73]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND75]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP79:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP79]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP80:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP81:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP76:%.*]] = fcmp olt double [[TMP80]], [[TMP81]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP76]], label [[COND_TRUE77:%.*]], label [[COND_FALSE78:%.*]]
|
|
// SIMD-ONLY0: cond.true77:
|
|
// SIMD-ONLY0-NEXT: [[TMP82:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79:%.*]]
|
|
// SIMD-ONLY0: cond.false78:
|
|
// SIMD-ONLY0-NEXT: [[TMP83:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END79]]
|
|
// SIMD-ONLY0: cond.end79:
|
|
// SIMD-ONLY0-NEXT: [[COND80:%.*]] = phi double [ [[TMP82]], [[COND_TRUE77]] ], [ [[TMP83]], [[COND_FALSE78]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND80]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP84:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP84]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP85:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP86:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP81:%.*]] = fcmp oeq double [[TMP85]], [[TMP86]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP81]], label [[COND_TRUE82:%.*]], label [[COND_FALSE83:%.*]]
|
|
// SIMD-ONLY0: cond.true82:
|
|
// SIMD-ONLY0-NEXT: [[TMP87:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84:%.*]]
|
|
// SIMD-ONLY0: cond.false83:
|
|
// SIMD-ONLY0-NEXT: [[TMP88:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END84]]
|
|
// SIMD-ONLY0: cond.end84:
|
|
// SIMD-ONLY0-NEXT: [[COND85:%.*]] = phi double [ [[TMP87]], [[COND_TRUE82]] ], [ [[TMP88]], [[COND_FALSE83]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND85]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP89:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP89]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP90:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP90]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP91:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP92:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP86:%.*]] = fcmp ogt double [[TMP91]], [[TMP92]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP86]], label [[COND_TRUE87:%.*]], label [[COND_FALSE88:%.*]]
|
|
// SIMD-ONLY0: cond.true87:
|
|
// SIMD-ONLY0-NEXT: [[TMP93:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89:%.*]]
|
|
// SIMD-ONLY0: cond.false88:
|
|
// SIMD-ONLY0-NEXT: [[TMP94:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END89]]
|
|
// SIMD-ONLY0: cond.end89:
|
|
// SIMD-ONLY0-NEXT: [[COND90:%.*]] = phi double [ [[TMP93]], [[COND_TRUE87]] ], [ [[TMP94]], [[COND_FALSE88]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND90]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP95:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP95]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP96:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP97:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP91:%.*]] = fcmp olt double [[TMP96]], [[TMP97]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP91]], label [[COND_TRUE92:%.*]], label [[COND_FALSE93:%.*]]
|
|
// SIMD-ONLY0: cond.true92:
|
|
// SIMD-ONLY0-NEXT: [[TMP98:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94:%.*]]
|
|
// SIMD-ONLY0: cond.false93:
|
|
// SIMD-ONLY0-NEXT: [[TMP99:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END94]]
|
|
// SIMD-ONLY0: cond.end94:
|
|
// SIMD-ONLY0-NEXT: [[COND95:%.*]] = phi double [ [[TMP98]], [[COND_TRUE92]] ], [ [[TMP99]], [[COND_FALSE93]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND95]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP100:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP100]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP101:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP102:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP96:%.*]] = fcmp oeq double [[TMP101]], [[TMP102]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP96]], label [[COND_TRUE97:%.*]], label [[COND_FALSE98:%.*]]
|
|
// SIMD-ONLY0: cond.true97:
|
|
// SIMD-ONLY0-NEXT: [[TMP103:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99:%.*]]
|
|
// SIMD-ONLY0: cond.false98:
|
|
// SIMD-ONLY0-NEXT: [[TMP104:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END99]]
|
|
// SIMD-ONLY0: cond.end99:
|
|
// SIMD-ONLY0-NEXT: [[COND100:%.*]] = phi double [ [[TMP103]], [[COND_TRUE97]] ], [ [[TMP104]], [[COND_FALSE98]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND100]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP105:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP106:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP101:%.*]] = fcmp ogt double [[TMP105]], [[TMP106]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP101]], label [[COND_TRUE102:%.*]], label [[COND_FALSE103:%.*]]
|
|
// SIMD-ONLY0: cond.true102:
|
|
// SIMD-ONLY0-NEXT: [[TMP107:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104:%.*]]
|
|
// SIMD-ONLY0: cond.false103:
|
|
// SIMD-ONLY0-NEXT: [[TMP108:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END104]]
|
|
// SIMD-ONLY0: cond.end104:
|
|
// SIMD-ONLY0-NEXT: [[COND105:%.*]] = phi double [ [[TMP107]], [[COND_TRUE102]] ], [ [[TMP108]], [[COND_FALSE103]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND105]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP109:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP109]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP110:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP111:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP106:%.*]] = fcmp olt double [[TMP110]], [[TMP111]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP106]], label [[COND_TRUE107:%.*]], label [[COND_FALSE108:%.*]]
|
|
// SIMD-ONLY0: cond.true107:
|
|
// SIMD-ONLY0-NEXT: [[TMP112:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109:%.*]]
|
|
// SIMD-ONLY0: cond.false108:
|
|
// SIMD-ONLY0-NEXT: [[TMP113:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END109]]
|
|
// SIMD-ONLY0: cond.end109:
|
|
// SIMD-ONLY0-NEXT: [[COND110:%.*]] = phi double [ [[TMP112]], [[COND_TRUE107]] ], [ [[TMP113]], [[COND_FALSE108]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND110]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP114:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP114]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP115:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP116:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP111:%.*]] = fcmp oeq double [[TMP115]], [[TMP116]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP111]], label [[COND_TRUE112:%.*]], label [[COND_FALSE113:%.*]]
|
|
// SIMD-ONLY0: cond.true112:
|
|
// SIMD-ONLY0-NEXT: [[TMP117:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114:%.*]]
|
|
// SIMD-ONLY0: cond.false113:
|
|
// SIMD-ONLY0-NEXT: [[TMP118:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END114]]
|
|
// SIMD-ONLY0: cond.end114:
|
|
// SIMD-ONLY0-NEXT: [[COND115:%.*]] = phi double [ [[TMP117]], [[COND_TRUE112]] ], [ [[TMP118]], [[COND_FALSE113]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND115]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP119:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP119]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP120:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP120]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP121:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP122:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP116:%.*]] = fcmp ogt double [[TMP121]], [[TMP122]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP116]], label [[COND_TRUE117:%.*]], label [[COND_FALSE118:%.*]]
|
|
// SIMD-ONLY0: cond.true117:
|
|
// SIMD-ONLY0-NEXT: [[TMP123:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119:%.*]]
|
|
// SIMD-ONLY0: cond.false118:
|
|
// SIMD-ONLY0-NEXT: [[TMP124:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END119]]
|
|
// SIMD-ONLY0: cond.end119:
|
|
// SIMD-ONLY0-NEXT: [[COND120:%.*]] = phi double [ [[TMP123]], [[COND_TRUE117]] ], [ [[TMP124]], [[COND_FALSE118]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND120]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP125:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP125]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP126:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP127:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP121:%.*]] = fcmp olt double [[TMP126]], [[TMP127]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP121]], label [[COND_TRUE122:%.*]], label [[COND_FALSE123:%.*]]
|
|
// SIMD-ONLY0: cond.true122:
|
|
// SIMD-ONLY0-NEXT: [[TMP128:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124:%.*]]
|
|
// SIMD-ONLY0: cond.false123:
|
|
// SIMD-ONLY0-NEXT: [[TMP129:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END124]]
|
|
// SIMD-ONLY0: cond.end124:
|
|
// SIMD-ONLY0-NEXT: [[COND125:%.*]] = phi double [ [[TMP128]], [[COND_TRUE122]] ], [ [[TMP129]], [[COND_FALSE123]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND125]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP130:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP130]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP131:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP132:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP126:%.*]] = fcmp oeq double [[TMP131]], [[TMP132]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP126]], label [[COND_TRUE127:%.*]], label [[COND_FALSE128:%.*]]
|
|
// SIMD-ONLY0: cond.true127:
|
|
// SIMD-ONLY0-NEXT: [[TMP133:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129:%.*]]
|
|
// SIMD-ONLY0: cond.false128:
|
|
// SIMD-ONLY0-NEXT: [[TMP134:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END129]]
|
|
// SIMD-ONLY0: cond.end129:
|
|
// SIMD-ONLY0-NEXT: [[COND130:%.*]] = phi double [ [[TMP133]], [[COND_TRUE127]] ], [ [[TMP134]], [[COND_FALSE128]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND130]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP135:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP136:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP131:%.*]] = fcmp ogt double [[TMP135]], [[TMP136]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP131]], label [[COND_TRUE132:%.*]], label [[COND_FALSE133:%.*]]
|
|
// SIMD-ONLY0: cond.true132:
|
|
// SIMD-ONLY0-NEXT: [[TMP137:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134:%.*]]
|
|
// SIMD-ONLY0: cond.false133:
|
|
// SIMD-ONLY0-NEXT: [[TMP138:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END134]]
|
|
// SIMD-ONLY0: cond.end134:
|
|
// SIMD-ONLY0-NEXT: [[COND135:%.*]] = phi double [ [[TMP137]], [[COND_TRUE132]] ], [ [[TMP138]], [[COND_FALSE133]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND135]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP139:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP139]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP140:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP141:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP136:%.*]] = fcmp olt double [[TMP140]], [[TMP141]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP136]], label [[COND_TRUE137:%.*]], label [[COND_FALSE138:%.*]]
|
|
// SIMD-ONLY0: cond.true137:
|
|
// SIMD-ONLY0-NEXT: [[TMP142:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139:%.*]]
|
|
// SIMD-ONLY0: cond.false138:
|
|
// SIMD-ONLY0-NEXT: [[TMP143:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END139]]
|
|
// SIMD-ONLY0: cond.end139:
|
|
// SIMD-ONLY0-NEXT: [[COND140:%.*]] = phi double [ [[TMP142]], [[COND_TRUE137]] ], [ [[TMP143]], [[COND_FALSE138]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND140]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP144:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP144]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP145:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP146:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP141:%.*]] = fcmp oeq double [[TMP145]], [[TMP146]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP141]], label [[COND_TRUE142:%.*]], label [[COND_FALSE143:%.*]]
|
|
// SIMD-ONLY0: cond.true142:
|
|
// SIMD-ONLY0-NEXT: [[TMP147:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144:%.*]]
|
|
// SIMD-ONLY0: cond.false143:
|
|
// SIMD-ONLY0-NEXT: [[TMP148:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END144]]
|
|
// SIMD-ONLY0: cond.end144:
|
|
// SIMD-ONLY0-NEXT: [[COND145:%.*]] = phi double [ [[TMP147]], [[COND_TRUE142]] ], [ [[TMP148]], [[COND_FALSE143]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND145]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP149:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP149]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP150:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP150]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP151:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP152:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP146:%.*]] = fcmp ogt double [[TMP151]], [[TMP152]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP146]], label [[COND_TRUE147:%.*]], label [[COND_FALSE148:%.*]]
|
|
// SIMD-ONLY0: cond.true147:
|
|
// SIMD-ONLY0-NEXT: [[TMP153:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149:%.*]]
|
|
// SIMD-ONLY0: cond.false148:
|
|
// SIMD-ONLY0-NEXT: [[TMP154:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END149]]
|
|
// SIMD-ONLY0: cond.end149:
|
|
// SIMD-ONLY0-NEXT: [[COND150:%.*]] = phi double [ [[TMP153]], [[COND_TRUE147]] ], [ [[TMP154]], [[COND_FALSE148]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND150]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP155:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP155]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP156:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP157:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP151:%.*]] = fcmp olt double [[TMP156]], [[TMP157]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP151]], label [[COND_TRUE152:%.*]], label [[COND_FALSE153:%.*]]
|
|
// SIMD-ONLY0: cond.true152:
|
|
// SIMD-ONLY0-NEXT: [[TMP158:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154:%.*]]
|
|
// SIMD-ONLY0: cond.false153:
|
|
// SIMD-ONLY0-NEXT: [[TMP159:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END154]]
|
|
// SIMD-ONLY0: cond.end154:
|
|
// SIMD-ONLY0-NEXT: [[COND155:%.*]] = phi double [ [[TMP158]], [[COND_TRUE152]] ], [ [[TMP159]], [[COND_FALSE153]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND155]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP160:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP160]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP161:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP162:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP156:%.*]] = fcmp oeq double [[TMP161]], [[TMP162]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP156]], label [[COND_TRUE157:%.*]], label [[COND_FALSE158:%.*]]
|
|
// SIMD-ONLY0: cond.true157:
|
|
// SIMD-ONLY0-NEXT: [[TMP163:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159:%.*]]
|
|
// SIMD-ONLY0: cond.false158:
|
|
// SIMD-ONLY0-NEXT: [[TMP164:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END159]]
|
|
// SIMD-ONLY0: cond.end159:
|
|
// SIMD-ONLY0-NEXT: [[COND160:%.*]] = phi double [ [[TMP163]], [[COND_TRUE157]] ], [ [[TMP164]], [[COND_FALSE158]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND160]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP165:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP166:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP161:%.*]] = fcmp ogt double [[TMP165]], [[TMP166]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP161]], label [[COND_TRUE162:%.*]], label [[COND_FALSE163:%.*]]
|
|
// SIMD-ONLY0: cond.true162:
|
|
// SIMD-ONLY0-NEXT: [[TMP167:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164:%.*]]
|
|
// SIMD-ONLY0: cond.false163:
|
|
// SIMD-ONLY0-NEXT: [[TMP168:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END164]]
|
|
// SIMD-ONLY0: cond.end164:
|
|
// SIMD-ONLY0-NEXT: [[COND165:%.*]] = phi double [ [[TMP167]], [[COND_TRUE162]] ], [ [[TMP168]], [[COND_FALSE163]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND165]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP169:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP169]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP170:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP171:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP166:%.*]] = fcmp olt double [[TMP170]], [[TMP171]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP166]], label [[COND_TRUE167:%.*]], label [[COND_FALSE168:%.*]]
|
|
// SIMD-ONLY0: cond.true167:
|
|
// SIMD-ONLY0-NEXT: [[TMP172:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169:%.*]]
|
|
// SIMD-ONLY0: cond.false168:
|
|
// SIMD-ONLY0-NEXT: [[TMP173:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END169]]
|
|
// SIMD-ONLY0: cond.end169:
|
|
// SIMD-ONLY0-NEXT: [[COND170:%.*]] = phi double [ [[TMP172]], [[COND_TRUE167]] ], [ [[TMP173]], [[COND_FALSE168]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND170]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP174:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP174]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP175:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP176:%.*]] = load double, ptr [[DE]], align 8
|
|
// SIMD-ONLY0-NEXT: [[CMP171:%.*]] = fcmp oeq double [[TMP175]], [[TMP176]]
|
|
// SIMD-ONLY0-NEXT: br i1 [[CMP171]], label [[COND_TRUE172:%.*]], label [[COND_FALSE173:%.*]]
|
|
// SIMD-ONLY0: cond.true172:
|
|
// SIMD-ONLY0-NEXT: [[TMP177:%.*]] = load double, ptr [[DD]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174:%.*]]
|
|
// SIMD-ONLY0: cond.false173:
|
|
// SIMD-ONLY0-NEXT: [[TMP178:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: br label [[COND_END174]]
|
|
// SIMD-ONLY0: cond.end174:
|
|
// SIMD-ONLY0-NEXT: [[COND175:%.*]] = phi double [ [[TMP177]], [[COND_TRUE172]] ], [ [[TMP178]], [[COND_FALSE173]] ]
|
|
// SIMD-ONLY0-NEXT: store double [[COND175]], ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP179:%.*]] = load double, ptr [[DX]], align 8
|
|
// SIMD-ONLY0-NEXT: store double [[TMP179]], ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load double, ptr [[DV]], align 8
|
|
// SIMD-ONLY0-NEXT: ret double [[TMP180]]
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//
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