39 lines
1.2 KiB
C++
39 lines
1.2 KiB
C++
//===-- RISCVTargetParser - Parser for target features ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features
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// for RISC-V CPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGETPARSER_RISCVTARGETPARSER_H
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#define LLVM_TARGETPARSER_RISCVTARGETPARSER_H
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#include "llvm/ADT/StringRef.h"
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namespace llvm {
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class Triple;
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namespace RISCV {
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// We use 64 bits as the known part in the scalable vector types.
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static constexpr unsigned RVVBitsPerBlock = 64;
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bool parseCPU(StringRef CPU, bool IsRV64);
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bool parseTuneCPU(StringRef CPU, bool IsRV64);
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StringRef getMArchFromMcpu(StringRef CPU);
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
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void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
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bool hasFastUnalignedAccess(StringRef CPU);
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} // namespace RISCV
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} // namespace llvm
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#endif
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