6892c175c5
Add empty AMDGPUGlobalISelDivergenceLowering pass. This pass will implement - selection of divergent i1 phis as lane mask phis, requires lane mask merging in some cases - lower uses of divergent i1 values outside of the cycle using lane mask merging - lowering of all cases of temporal divergence: - lower uses of uniform i1 values outside of the cycle using lane mask merging - lower uses of uniform non-i1 values outside of the cycle using a copy to vgpr inside of the cycle Add very detailed set of regression tests for cases mentioned above. patch 1 from: https://github.com/llvm/llvm-project/pull/73337
69 lines
2.2 KiB
C++
69 lines
2.2 KiB
C++
//===-- AMDGPUGlobalISelDivergenceLowering.cpp ----------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// GlobalISel pass that selects divergent i1 phis as lane mask phis.
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/// Lane mask merging uses same algorithm as SDAG in SILowerI1Copies.
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/// Handles all cases of temporal divergence.
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/// For divergent non-phi i1 and uniform i1 uses outside of the cycle this pass
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/// currently depends on LCSSA to insert phis with one incoming.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#define DEBUG_TYPE "amdgpu-global-isel-divergence-lowering"
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using namespace llvm;
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namespace {
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class AMDGPUGlobalISelDivergenceLowering : public MachineFunctionPass {
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public:
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static char ID;
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public:
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AMDGPUGlobalISelDivergenceLowering() : MachineFunctionPass(ID) {
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initializeAMDGPUGlobalISelDivergenceLoweringPass(
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*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "AMDGPU GlobalISel divergence lowering";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(AMDGPUGlobalISelDivergenceLowering, DEBUG_TYPE,
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"AMDGPU GlobalISel divergence lowering", false, false)
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INITIALIZE_PASS_END(AMDGPUGlobalISelDivergenceLowering, DEBUG_TYPE,
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"AMDGPU GlobalISel divergence lowering", false, false)
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char AMDGPUGlobalISelDivergenceLowering::ID = 0;
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char &llvm::AMDGPUGlobalISelDivergenceLoweringID =
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AMDGPUGlobalISelDivergenceLowering::ID;
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FunctionPass *llvm::createAMDGPUGlobalISelDivergenceLoweringPass() {
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return new AMDGPUGlobalISelDivergenceLowering();
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}
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bool AMDGPUGlobalISelDivergenceLowering::runOnMachineFunction(
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MachineFunction &MF) {
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return false;
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}
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