In [1], a few new insns are proposed to expand BPF ISA to
. fixing the limitation of existing insn (e.g., 16bit jmp offset)
. adding new insns which may improve code quality
(sign_ext_ld, sign_ext_mov, st)
. feature complete (sdiv, smod)
. better user experience (bswap)
This patch implemented insn encoding for
. sign-extended load
. sign-extended mov
. sdiv/smod
. bswap insns
. unconditional jump with 32bit offset
The new bswap insns are generated under cpu=v4 for __builtin_bswap.
For cpu=v3 or earlier, for __builtin_bswap, be or le insns are generated
which is not intuitive for the user.
To support 32-bit branch offset, a 32-bit ja (JMPL) insn is implemented.
For conditional branch which is beyond 16-bit offset, llvm will do
some transformation 'cond_jmp' -> 'cond_jmp + jmpl' to simulate 32bit
conditional jmp. See BPFMIPeephole.cpp for details. The algorithm is
hueristic based. I have tested bpf selftest pyperf600 with unroll account
600 which can indeed generate 32-bit jump insn, e.g.,
13: 06 00 00 00 9b cd 00 00 gotol +0xcd9b <LBB0_6619>
Eduard is working on to add 'st' insn to cpu=v4.
A list of llc flags:
disable-ldsx, disable-movsx, disable-bswap,
disable-sdiv-smod, disable-gotol
can be used to disable a particular insn for cpu v4.
For example, user can do:
llc -march=bpf -mcpu=v4 -disable-movsx t.ll
to enable cpu v4 without movsx insns.
References:
[1] https://lore.kernel.org/bpf/4bfe98be-5333-1c7e-2f6d-42486c8ec039@meta.com/
Differential Revision: https://reviews.llvm.org/D144829
155 lines
5.4 KiB
C++
155 lines
5.4 KiB
C++
//===-- BPFMCTargetDesc.cpp - BPF Target Descriptions ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides BPF specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/BPFMCTargetDesc.h"
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#include "MCTargetDesc/BPFInstPrinter.h"
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#include "MCTargetDesc/BPFMCAsmInfo.h"
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#include "TargetInfo/BPFTargetInfo.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/TargetParser/Host.h"
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#define GET_INSTRINFO_MC_DESC
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#define ENABLE_INSTR_PREDICATE_VERIFIER
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#include "BPFGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "BPFGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "BPFGenRegisterInfo.inc"
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using namespace llvm;
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static MCInstrInfo *createBPFMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitBPFMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createBPFMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */);
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return X;
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}
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static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT,
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StringRef CPU, StringRef FS) {
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return createBPFMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
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}
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static MCStreamer *createBPFMCStreamer(const Triple &T, MCContext &Ctx,
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std::unique_ptr<MCAsmBackend> &&MAB,
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std::unique_ptr<MCObjectWriter> &&OW,
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std::unique_ptr<MCCodeEmitter> &&Emitter,
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bool RelaxAll) {
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return createELFStreamer(Ctx, std::move(MAB), std::move(OW), std::move(Emitter),
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RelaxAll);
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}
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static MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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if (SyntaxVariant == 0)
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return new BPFInstPrinter(MAI, MII, MRI);
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return nullptr;
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}
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namespace {
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class BPFMCInstrAnalysis : public MCInstrAnalysis {
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public:
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explicit BPFMCInstrAnalysis(const MCInstrInfo *Info)
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: MCInstrAnalysis(Info) {}
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bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
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uint64_t &Target) const override {
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// The target is the 3rd operand of cond inst and the 1st of uncond inst.
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int32_t Imm;
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if (isConditionalBranch(Inst)) {
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Imm = (short)Inst.getOperand(2).getImm();
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} else if (isUnconditionalBranch(Inst)) {
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if (Inst.getOpcode() == BPF::JMP)
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Imm = (short)Inst.getOperand(0).getImm();
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else
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Imm = (int)Inst.getOperand(0).getImm();
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} else
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return false;
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Target = Addr + Size + Imm * Size;
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return true;
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}
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};
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} // end anonymous namespace
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static MCInstrAnalysis *createBPFInstrAnalysis(const MCInstrInfo *Info) {
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return new BPFMCInstrAnalysis(Info);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFTargetMC() {
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for (Target *T :
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{&getTheBPFleTarget(), &getTheBPFbeTarget(), &getTheBPFTarget()}) {
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// Register the MC asm info.
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RegisterMCAsmInfo<BPFMCAsmInfo> X(*T);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(*T, createBPFMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(*T, createBPFMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(*T,
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createBPFMCSubtargetInfo);
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// Register the object streamer
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TargetRegistry::RegisterELFStreamer(*T, createBPFMCStreamer);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(*T, createBPFMCInstPrinter);
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// Register the MC instruction analyzer.
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TargetRegistry::RegisterMCInstrAnalysis(*T, createBPFInstrAnalysis);
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}
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// Register the MC code emitter
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TargetRegistry::RegisterMCCodeEmitter(getTheBPFleTarget(),
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createBPFMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(getTheBPFbeTarget(),
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createBPFbeMCCodeEmitter);
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// Register the ASM Backend
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TargetRegistry::RegisterMCAsmBackend(getTheBPFleTarget(),
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createBPFAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(getTheBPFbeTarget(),
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createBPFbeAsmBackend);
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if (sys::IsLittleEndianHost) {
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TargetRegistry::RegisterMCCodeEmitter(getTheBPFTarget(),
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createBPFMCCodeEmitter);
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TargetRegistry::RegisterMCAsmBackend(getTheBPFTarget(),
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createBPFAsmBackend);
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} else {
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TargetRegistry::RegisterMCCodeEmitter(getTheBPFTarget(),
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createBPFbeMCCodeEmitter);
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TargetRegistry::RegisterMCAsmBackend(getTheBPFTarget(),
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createBPFbeAsmBackend);
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}
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}
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