0a2aaab5ab
There is no log10 instruction in the GLSL Extended Instruction Set so to
implement the HLSL log10 intrinsic when targeting Vulkan this change
adds the logic to derive the result using the following formula:
```
log10(x) = log2(x) * (1 / log2(10))
= log2(x) * 0.30103
```
320 lines
12 KiB
C++
320 lines
12 KiB
C++
//===- SPIRVLegalizerInfo.cpp --- SPIR-V Legalization Rules ------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the targeting of the Machinelegalizer class for SPIR-V.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVLegalizerInfo.h"
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#include "SPIRV.h"
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRVSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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using namespace llvm;
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using namespace llvm::LegalizeActions;
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using namespace llvm::LegalityPredicates;
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static const std::set<unsigned> TypeFoldingSupportingOpcs = {
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TargetOpcode::G_ADD,
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TargetOpcode::G_FADD,
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TargetOpcode::G_SUB,
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TargetOpcode::G_FSUB,
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TargetOpcode::G_MUL,
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TargetOpcode::G_FMUL,
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TargetOpcode::G_SDIV,
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TargetOpcode::G_UDIV,
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TargetOpcode::G_FDIV,
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TargetOpcode::G_SREM,
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TargetOpcode::G_UREM,
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TargetOpcode::G_FREM,
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TargetOpcode::G_FNEG,
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TargetOpcode::G_CONSTANT,
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TargetOpcode::G_FCONSTANT,
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TargetOpcode::G_AND,
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TargetOpcode::G_OR,
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TargetOpcode::G_XOR,
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TargetOpcode::G_SHL,
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TargetOpcode::G_ASHR,
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TargetOpcode::G_LSHR,
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TargetOpcode::G_SELECT,
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TargetOpcode::G_EXTRACT_VECTOR_ELT,
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};
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bool isTypeFoldingSupported(unsigned Opcode) {
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return TypeFoldingSupportingOpcs.count(Opcode) > 0;
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}
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SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
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using namespace TargetOpcode;
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this->ST = &ST;
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GR = ST.getSPIRVGlobalRegistry();
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const LLT s1 = LLT::scalar(1);
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const LLT s8 = LLT::scalar(8);
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const LLT s16 = LLT::scalar(16);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT v16s64 = LLT::fixed_vector(16, 64);
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const LLT v16s32 = LLT::fixed_vector(16, 32);
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const LLT v16s16 = LLT::fixed_vector(16, 16);
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const LLT v16s8 = LLT::fixed_vector(16, 8);
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const LLT v16s1 = LLT::fixed_vector(16, 1);
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const LLT v8s64 = LLT::fixed_vector(8, 64);
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const LLT v8s32 = LLT::fixed_vector(8, 32);
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const LLT v8s16 = LLT::fixed_vector(8, 16);
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const LLT v8s8 = LLT::fixed_vector(8, 8);
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const LLT v8s1 = LLT::fixed_vector(8, 1);
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const LLT v4s64 = LLT::fixed_vector(4, 64);
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const LLT v4s32 = LLT::fixed_vector(4, 32);
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const LLT v4s16 = LLT::fixed_vector(4, 16);
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const LLT v4s8 = LLT::fixed_vector(4, 8);
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const LLT v4s1 = LLT::fixed_vector(4, 1);
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const LLT v3s64 = LLT::fixed_vector(3, 64);
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const LLT v3s32 = LLT::fixed_vector(3, 32);
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const LLT v3s16 = LLT::fixed_vector(3, 16);
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const LLT v3s8 = LLT::fixed_vector(3, 8);
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const LLT v3s1 = LLT::fixed_vector(3, 1);
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const LLT v2s64 = LLT::fixed_vector(2, 64);
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const LLT v2s32 = LLT::fixed_vector(2, 32);
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const LLT v2s16 = LLT::fixed_vector(2, 16);
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const LLT v2s8 = LLT::fixed_vector(2, 8);
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const LLT v2s1 = LLT::fixed_vector(2, 1);
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const unsigned PSize = ST.getPointerSize();
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const LLT p0 = LLT::pointer(0, PSize); // Function
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const LLT p1 = LLT::pointer(1, PSize); // CrossWorkgroup
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const LLT p2 = LLT::pointer(2, PSize); // UniformConstant
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const LLT p3 = LLT::pointer(3, PSize); // Workgroup
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const LLT p4 = LLT::pointer(4, PSize); // Generic
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const LLT p5 = LLT::pointer(5, PSize); // Input
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// TODO: remove copy-pasting here by using concatenation in some way.
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auto allPtrsScalarsAndVectors = {
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p0, p1, p2, p3, p4, p5, s1, s8, s16,
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s32, s64, v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8,
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v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64, v8s1,
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v8s8, v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
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auto allScalarsAndVectors = {
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s1, s8, s16, s32, s64, v2s1, v2s8, v2s16, v2s32, v2s64,
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v3s1, v3s8, v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64,
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v8s1, v8s8, v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
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auto allIntScalarsAndVectors = {s8, s16, s32, s64, v2s8, v2s16,
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v2s32, v2s64, v3s8, v3s16, v3s32, v3s64,
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v4s8, v4s16, v4s32, v4s64, v8s8, v8s16,
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v8s32, v8s64, v16s8, v16s16, v16s32, v16s64};
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auto allBoolScalarsAndVectors = {s1, v2s1, v3s1, v4s1, v8s1, v16s1};
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auto allIntScalars = {s8, s16, s32, s64};
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auto allFloatScalarsAndVectors = {
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s16, s32, s64, v2s16, v2s32, v2s64, v3s16, v3s32, v3s64,
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v4s16, v4s32, v4s64, v8s16, v8s32, v8s64, v16s16, v16s32, v16s64};
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auto allFloatAndIntScalars = allIntScalars;
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auto allPtrs = {p0, p1, p2, p3, p4, p5};
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auto allWritablePtrs = {p0, p1, p3, p4};
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for (auto Opc : TypeFoldingSupportingOpcs)
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getActionDefinitionsBuilder(Opc).custom();
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getActionDefinitionsBuilder(G_GLOBAL_VALUE).alwaysLegal();
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// TODO: add proper rules for vectors legalization.
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getActionDefinitionsBuilder({G_BUILD_VECTOR, G_SHUFFLE_VECTOR}).alwaysLegal();
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getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE})
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.legalIf(all(typeInSet(0, allWritablePtrs), typeInSet(1, allPtrs)));
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getActionDefinitionsBuilder(G_MEMSET).legalIf(
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all(typeInSet(0, allWritablePtrs), typeInSet(1, allIntScalars)));
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getActionDefinitionsBuilder(G_ADDRSPACE_CAST)
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.legalForCartesianProduct(allPtrs, allPtrs);
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getActionDefinitionsBuilder({G_LOAD, G_STORE}).legalIf(typeInSet(1, allPtrs));
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getActionDefinitionsBuilder(G_BITREVERSE).legalFor(allFloatScalarsAndVectors);
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getActionDefinitionsBuilder(G_FMA).legalFor(allFloatScalarsAndVectors);
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getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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.legalForCartesianProduct(allIntScalarsAndVectors,
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allFloatScalarsAndVectors);
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getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
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.legalForCartesianProduct(allFloatScalarsAndVectors,
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allScalarsAndVectors);
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getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX, G_ABS})
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.legalFor(allIntScalarsAndVectors);
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getActionDefinitionsBuilder(G_CTPOP).legalForCartesianProduct(
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allIntScalarsAndVectors, allIntScalarsAndVectors);
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getActionDefinitionsBuilder(G_PHI).legalFor(allPtrsScalarsAndVectors);
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getActionDefinitionsBuilder(G_BITCAST).legalIf(all(
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typeInSet(0, allPtrsScalarsAndVectors),
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typeInSet(1, allPtrsScalarsAndVectors),
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LegalityPredicate(([=](const LegalityQuery &Query) {
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return Query.Types[0].getSizeInBits() == Query.Types[1].getSizeInBits();
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}))));
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getActionDefinitionsBuilder(G_IMPLICIT_DEF).alwaysLegal();
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getActionDefinitionsBuilder(G_INTTOPTR)
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.legalForCartesianProduct(allPtrs, allIntScalars);
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getActionDefinitionsBuilder(G_PTRTOINT)
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.legalForCartesianProduct(allIntScalars, allPtrs);
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getActionDefinitionsBuilder(G_PTR_ADD).legalForCartesianProduct(
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allPtrs, allIntScalars);
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// ST.canDirectlyComparePointers() for pointer args is supported in
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// legalizeCustom().
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getActionDefinitionsBuilder(G_ICMP).customIf(
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all(typeInSet(0, allBoolScalarsAndVectors),
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typeInSet(1, allPtrsScalarsAndVectors)));
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getActionDefinitionsBuilder(G_FCMP).legalIf(
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all(typeInSet(0, allBoolScalarsAndVectors),
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typeInSet(1, allFloatScalarsAndVectors)));
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getActionDefinitionsBuilder({G_ATOMICRMW_OR, G_ATOMICRMW_ADD, G_ATOMICRMW_AND,
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G_ATOMICRMW_MAX, G_ATOMICRMW_MIN,
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G_ATOMICRMW_SUB, G_ATOMICRMW_XOR,
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G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN})
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.legalForCartesianProduct(allIntScalars, allWritablePtrs);
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getActionDefinitionsBuilder(G_ATOMICRMW_XCHG)
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.legalForCartesianProduct(allFloatAndIntScalars, allWritablePtrs);
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getActionDefinitionsBuilder(G_ATOMIC_CMPXCHG_WITH_SUCCESS).lower();
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// TODO: add proper legalization rules.
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getActionDefinitionsBuilder(G_ATOMIC_CMPXCHG).alwaysLegal();
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getActionDefinitionsBuilder({G_UADDO, G_USUBO, G_SMULO, G_UMULO})
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.alwaysLegal();
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// Extensions.
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getActionDefinitionsBuilder({G_TRUNC, G_ZEXT, G_SEXT, G_ANYEXT})
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.legalForCartesianProduct(allScalarsAndVectors);
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// FP conversions.
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getActionDefinitionsBuilder({G_FPTRUNC, G_FPEXT})
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.legalForCartesianProduct(allFloatScalarsAndVectors);
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// Pointer-handling.
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getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
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// Control-flow. In some cases (e.g. constants) s1 may be promoted to s32.
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getActionDefinitionsBuilder(G_BRCOND).legalFor({s1, s32});
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// TODO: Review the target OpenCL and GLSL Extended Instruction Set specs to
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// tighten these requirements. Many of these math functions are only legal on
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// specific bitwidths, so they are not selectable for
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// allFloatScalarsAndVectors.
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getActionDefinitionsBuilder({G_FPOW,
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G_FEXP,
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G_FEXP2,
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G_FLOG,
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G_FLOG2,
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G_FLOG10,
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G_FABS,
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G_FMINNUM,
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G_FMAXNUM,
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G_FCEIL,
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G_FCOS,
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G_FSIN,
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G_FSQRT,
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G_FFLOOR,
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G_FRINT,
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G_FNEARBYINT,
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G_INTRINSIC_ROUND,
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G_INTRINSIC_TRUNC,
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G_FMINIMUM,
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G_FMAXIMUM,
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G_INTRINSIC_ROUNDEVEN})
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.legalFor(allFloatScalarsAndVectors);
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getActionDefinitionsBuilder(G_FCOPYSIGN)
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.legalForCartesianProduct(allFloatScalarsAndVectors,
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allFloatScalarsAndVectors);
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getActionDefinitionsBuilder(G_FPOWI).legalForCartesianProduct(
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allFloatScalarsAndVectors, allIntScalarsAndVectors);
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if (ST.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
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getActionDefinitionsBuilder(
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{G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTLZ, G_CTLZ_ZERO_UNDEF})
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.legalForCartesianProduct(allIntScalarsAndVectors,
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allIntScalarsAndVectors);
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// Struct return types become a single scalar, so cannot easily legalize.
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getActionDefinitionsBuilder({G_SMULH, G_UMULH}).alwaysLegal();
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}
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getLegacyLegalizerInfo().computeTables();
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verify(*ST.getInstrInfo());
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}
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static Register convertPtrToInt(Register Reg, LLT ConvTy, SPIRVType *SpirvType,
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LegalizerHelper &Helper,
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MachineRegisterInfo &MRI,
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SPIRVGlobalRegistry *GR) {
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Register ConvReg = MRI.createGenericVirtualRegister(ConvTy);
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GR->assignSPIRVTypeToVReg(SpirvType, ConvReg, Helper.MIRBuilder.getMF());
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Helper.MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
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.addDef(ConvReg)
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.addUse(Reg);
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return ConvReg;
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}
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bool SPIRVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
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MachineInstr &MI) const {
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auto Opc = MI.getOpcode();
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MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
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if (!isTypeFoldingSupported(Opc)) {
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assert(Opc == TargetOpcode::G_ICMP);
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assert(GR->getSPIRVTypeForVReg(MI.getOperand(0).getReg()));
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auto &Op0 = MI.getOperand(2);
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auto &Op1 = MI.getOperand(3);
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Register Reg0 = Op0.getReg();
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Register Reg1 = Op1.getReg();
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CmpInst::Predicate Cond =
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static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
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if ((!ST->canDirectlyComparePointers() ||
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(Cond != CmpInst::ICMP_EQ && Cond != CmpInst::ICMP_NE)) &&
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MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) {
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LLT ConvT = LLT::scalar(ST->getPointerSize());
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Type *LLVMTy = IntegerType::get(MI.getMF()->getFunction().getContext(),
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ST->getPointerSize());
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SPIRVType *SpirvTy = GR->getOrCreateSPIRVType(LLVMTy, Helper.MIRBuilder);
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Op0.setReg(convertPtrToInt(Reg0, ConvT, SpirvTy, Helper, MRI, GR));
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Op1.setReg(convertPtrToInt(Reg1, ConvT, SpirvTy, Helper, MRI, GR));
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}
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return true;
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}
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// TODO: implement legalization for other opcodes.
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return true;
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}
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