e39f6c1844
There are many tests that specify a target triple/CPU flags but no DataLayout which can lead to IR being generated that has unusual behaviour. This commit attempts to use the default DataLayout based on the relevant flags if there is no explicit override on the command line or in the IR file. One thing that is not currently possible to differentiate from a missing datalayout `target datalayout = ""` in the IR file since the current APIs don't allow detecting this case. If it is considered useful to support this case (instead of passing "-data-layout=" on the command line), I can change IR parsers to track whether they have seen such a directive and change the callback type. Differential Revision: https://reviews.llvm.org/D141060
49 lines
2.6 KiB
LLVM
49 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -atomic-expand -S -mtriple=powerpc64-unknown-unknown \
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; RUN: -mcpu=pwr8 %s | FileCheck %s
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; RUN: opt -atomic-expand -S -mtriple=powerpc64-unknown-unknown \
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; RUN: -mcpu=pwr7 %s | FileCheck --check-prefix=PWR7 %s
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define i1 @test_cmpxchg_seq_cst(ptr %addr, i128 %desire, i128 %new) {
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; CHECK-LABEL: @test_cmpxchg_seq_cst(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP_LO:%.*]] = trunc i128 [[DESIRE:%.*]] to i64
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; CHECK-NEXT: [[TMP0:%.*]] = lshr i128 [[DESIRE]], 64
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; CHECK-NEXT: [[CMP_HI:%.*]] = trunc i128 [[TMP0]] to i64
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; CHECK-NEXT: [[NEW_LO:%.*]] = trunc i128 [[NEW:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i128 [[NEW]], 64
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; CHECK-NEXT: [[NEW_HI:%.*]] = trunc i128 [[TMP1]] to i64
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; CHECK-NEXT: call void @llvm.ppc.sync()
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; CHECK-NEXT: [[TMP2:%.*]] = call { i64, i64 } @llvm.ppc.cmpxchg.i128(ptr [[ADDR:%.*]], i64 [[CMP_LO]], i64 [[CMP_HI]], i64 [[NEW_LO]], i64 [[NEW_HI]])
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; CHECK-NEXT: call void @llvm.ppc.lwsync()
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; CHECK-NEXT: [[LO:%.*]] = extractvalue { i64, i64 } [[TMP2]], 0
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; CHECK-NEXT: [[HI:%.*]] = extractvalue { i64, i64 } [[TMP2]], 1
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; CHECK-NEXT: [[LO64:%.*]] = zext i64 [[LO]] to i128
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; CHECK-NEXT: [[HI64:%.*]] = zext i64 [[HI]] to i128
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; CHECK-NEXT: [[TMP3:%.*]] = shl i128 [[HI64]], 64
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; CHECK-NEXT: [[VAL64:%.*]] = or i128 [[LO64]], [[TMP3]]
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; CHECK-NEXT: [[TMP4:%.*]] = insertvalue { i128, i1 } poison, i128 [[VAL64]], 0
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; CHECK-NEXT: [[SUCCESS:%.*]] = icmp eq i128 [[DESIRE]], [[VAL64]]
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; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i128, i1 } [[TMP4]], i1 [[SUCCESS]], 1
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; CHECK-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP5]], 1
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; CHECK-NEXT: ret i1 [[SUCC]]
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;
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; PWR7-LABEL: @test_cmpxchg_seq_cst(
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; PWR7-NEXT: entry:
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; PWR7-NEXT: [[TMP0:%.*]] = alloca i128, align 8
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; PWR7-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[TMP0]])
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; PWR7-NEXT: store i128 [[DESIRE:%.*]], ptr [[TMP0]], align 8
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; PWR7-NEXT: [[TMP1:%.*]] = call zeroext i1 @__atomic_compare_exchange_16(ptr [[ADDR:%.*]], ptr [[TMP0]], i128 [[NEW:%.*]], i32 5, i32 5)
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; PWR7-NEXT: [[TMP2:%.*]] = load i128, ptr [[TMP0]], align 8
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; PWR7-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[TMP0]])
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; PWR7-NEXT: [[TMP3:%.*]] = insertvalue { i128, i1 } poison, i128 [[TMP2]], 0
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; PWR7-NEXT: [[TMP4:%.*]] = insertvalue { i128, i1 } [[TMP3]], i1 [[TMP1]], 1
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; PWR7-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP4]], 1
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; PWR7-NEXT: ret i1 [[SUCC]]
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;
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entry:
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%pair = cmpxchg weak ptr %addr, i128 %desire, i128 %new seq_cst seq_cst
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%succ = extractvalue {i128, i1} %pair, 1
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ret i1 %succ
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}
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