2a859b2014
The cost of vector instructions has always been high under AArch64, in order to add a high cost for inserts/extracts, shuffles and scalarization. This is a conservative approach to limit the scope of unusual SLP vectorization where the codegen ends up being quite poor, but has always been higher than the correct costs would be for any specific core. This relaxes that, reducing the vector insert/extract cost from 3 to 2. It is a generalization of D142359 to all AArch64 cpus. The ScalarizationOverhead is also overridden for integer vector at the same time, to remove the effect of lane 0 being considered free for integer vectors (something that should only be true for float when scalarizing). The lower insert/extract cost will reduce the cost of insert, extracts, shuffling and scalarization. The adjustments of ScalaizationOverhead will increase the cost on integer, especially for small vectors. The end result will be lower cost for float and long-integer types, some higher cost for some smaller vectors. This, along with the raw insert/extract cost being lower, will generally mean more vectorization from the Loop and SLP vectorizer. We may end up regretting this, as that vectorization is not always profitable. In all the benchmarking I have done this is generally an improvement in the overall performance, and I've attempted to address the places where it wasn't with other costmodel adjustments. Differential Revision: https://reviews.llvm.org/D155459
87 lines
4.3 KiB
LLVM
87 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; REQUIRES: asserts
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; RUN: opt < %s -passes=loop-vectorize -disable-output -debug-only=loop-vectorize 2>&1 | FileCheck %s --check-prefix=COST
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; RUN: opt < %s -passes=loop-vectorize,instcombine,simplifycfg -force-vector-width=2 -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--linux-gnu"
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; This test checks that we correctly compute the scalarized operands for a
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; user-specified vectorization factor when interleaving is disabled. We use the
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; "optsize" attribute to disable all interleaving calculations. A cost of 4
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; for %var4 indicates that we would scalarize it's operand (%var3), giving
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; %var4 a lower scalarization overhead.
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;
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; COST-LABEL: predicated_udiv_scalarized_operand
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; COST: LV: Found an estimated cost of 5 for VF 2 For instruction: %var4 = udiv i64 %var2, %var3
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;
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;
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define i64 @predicated_udiv_scalarized_operand(ptr %a, i64 %x) optsize {
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; CHECK-LABEL: @predicated_udiv_scalarized_operand(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_UDIV_CONTINUE2:%.*]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, [[ENTRY]] ], [ [[TMP17:%.*]], [[PRED_UDIV_CONTINUE2]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[INDEX]]
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP0]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <2 x i64> [[WIDE_LOAD]], zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i64 0
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; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_UDIV_IF:%.*]], label [[PRED_UDIV_CONTINUE:%.*]]
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; CHECK: pred.udiv.if:
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i64 0
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; CHECK-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP4]], [[X:%.*]]
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i64 0
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; CHECK-NEXT: [[TMP7:%.*]] = udiv i64 [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[TMP7]], i64 0
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; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE]]
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; CHECK: pred.udiv.continue:
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; CHECK-NEXT: [[TMP9:%.*]] = phi <2 x i64> [ poison, [[VECTOR_BODY]] ], [ [[TMP8]], [[PRED_UDIV_IF]] ]
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; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP2]], i64 1
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; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_UDIV_IF1:%.*]], label [[PRED_UDIV_CONTINUE2]]
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; CHECK: pred.udiv.if1:
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; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i64 1
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; CHECK-NEXT: [[TMP12:%.*]] = add nsw i64 [[TMP11]], [[X]]
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; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i64 1
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; CHECK-NEXT: [[TMP14:%.*]] = udiv i64 [[TMP13]], [[TMP12]]
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; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x i64> [[TMP9]], i64 [[TMP14]], i64 1
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; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE2]]
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; CHECK: pred.udiv.continue2:
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; CHECK-NEXT: [[TMP16:%.*]] = phi <2 x i64> [ [[TMP9]], [[PRED_UDIV_CONTINUE]] ], [ [[TMP15]], [[PRED_UDIV_IF1]] ]
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; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP2]], <2 x i64> [[TMP16]], <2 x i64> [[WIDE_LOAD]]
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; CHECK-NEXT: [[TMP17]] = add <2 x i64> [[VEC_PHI]], [[PREDPHI]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[TMP17]])
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; CHECK-NEXT: ret i64 [[TMP19]]
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;
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
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%r = phi i64 [ 0, %entry ], [ %var6, %for.inc ]
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%var0 = getelementptr inbounds i64, ptr %a, i64 %i
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%var2 = load i64, ptr %var0, align 4
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%cond0 = icmp sgt i64 %var2, 0
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br i1 %cond0, label %if.then, label %for.inc
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if.then:
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%var3 = add nsw i64 %var2, %x
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%var4 = udiv i64 %var2, %var3
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br label %for.inc
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for.inc:
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%var5 = phi i64 [ %var2, %for.body ], [ %var4, %if.then]
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%var6 = add i64 %r, %var5
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%i.next = add nuw nsw i64 %i, 1
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%cond1 = icmp slt i64 %i.next, 100
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br i1 %cond1, label %for.body, label %for.end
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for.end:
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%var7 = phi i64 [ %var6, %for.inc ]
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ret i64 %var7
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}
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