eecb99c5f6
These tests rely on SCEV looking recognizing an "or" with no common bits as an "add". Add the disjoint flag to relevant or instructions in preparation for switching SCEV to use the flag instead of the ValueTracking query. The IR with disjoint flag matches what InstCombine would produce.
81 lines
3.5 KiB
LLVM
81 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=slp-vectorizer -S -mcpu=corei7-avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.8.0"
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define i32 @foo(ptr nocapture %A, i32 %n) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP62:%.*]] = icmp sgt i32 [[N:%.*]], 0
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; CHECK-NEXT: br i1 [[CMP62]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[N]], i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = add nsw <8 x i32> [[TMP0]], [[TMP2]]
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; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 8
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[N]]
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]]
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; CHECK: for.end:
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; CHECK-NEXT: ret i32 undef
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;
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entry:
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%cmp62 = icmp sgt i32 %n, 0
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br i1 %cmp62, label %for.body, label %for.end
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for.body:
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
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%0 = load i32, ptr %arrayidx, align 4
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%add1 = add nsw i32 %0, %n
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store i32 %add1, ptr %arrayidx, align 4
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%1 = or disjoint i64 %indvars.iv, 1
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%arrayidx4 = getelementptr inbounds i32, ptr %A, i64 %1
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%2 = load i32, ptr %arrayidx4, align 4
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%add5 = add nsw i32 %2, %n
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store i32 %add5, ptr %arrayidx4, align 4
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%3 = or disjoint i64 %indvars.iv, 2
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%arrayidx8 = getelementptr inbounds i32, ptr %A, i64 %3
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%4 = load i32, ptr %arrayidx8, align 4
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%add9 = add nsw i32 %4, %n
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store i32 %add9, ptr %arrayidx8, align 4
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%5 = or disjoint i64 %indvars.iv, 3
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%arrayidx12 = getelementptr inbounds i32, ptr %A, i64 %5
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%6 = load i32, ptr %arrayidx12, align 4
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%add13 = add nsw i32 %6, %n
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store i32 %add13, ptr %arrayidx12, align 4
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%7 = or disjoint i64 %indvars.iv, 4
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%arrayidx16 = getelementptr inbounds i32, ptr %A, i64 %7
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%8 = load i32, ptr %arrayidx16, align 4
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%add17 = add nsw i32 %8, %n
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store i32 %add17, ptr %arrayidx16, align 4
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%9 = or disjoint i64 %indvars.iv, 5
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%arrayidx20 = getelementptr inbounds i32, ptr %A, i64 %9
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%10 = load i32, ptr %arrayidx20, align 4
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%add21 = add nsw i32 %10, %n
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store i32 %add21, ptr %arrayidx20, align 4
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%11 = or disjoint i64 %indvars.iv, 6
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%arrayidx24 = getelementptr inbounds i32, ptr %A, i64 %11
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%12 = load i32, ptr %arrayidx24, align 4
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%add25 = add nsw i32 %12, %n
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store i32 %add25, ptr %arrayidx24, align 4
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%13 = or disjoint i64 %indvars.iv, 7
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%arrayidx28 = getelementptr inbounds i32, ptr %A, i64 %13
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%14 = load i32, ptr %arrayidx28, align 4
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%add29 = add nsw i32 %14, %n
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store i32 %add29, ptr %arrayidx28, align 4
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%indvars.iv.next = add i64 %indvars.iv, 8
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%15 = trunc i64 %indvars.iv.next to i32
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%cmp = icmp slt i32 %15, %n
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret i32 undef
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}
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