85e3875ad7
D150312 added a TODO: TODO: consider renaming the field `StartAtCycle` and `Cycles` to `AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the fact that resource allocation is now represented as an interval, relatively to the issue cycle of the instruction. This patch implements that TODO. This naming clarifies how to use these fields in the scheduler. In addition it was confusing that `StartAtCycle` was singular but `Cycles` was plural. This renaming fixes this inconsistency. This commit as previously reverted since it missed renaming that came down after rebasing. This version of the commit fixes those problems. Differential Revision: https://reviews.llvm.org/D158568
645 lines
22 KiB
C++
645 lines
22 KiB
C++
//===--------------------- BottleneckAnalysis.cpp ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements the functionalities used by the BottleneckAnalysis
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/// to report bottleneck info.
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///
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//===----------------------------------------------------------------------===//
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#include "Views/BottleneckAnalysis.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MCA/Support.h"
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#include "llvm/Support/Format.h"
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namespace llvm {
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namespace mca {
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#define DEBUG_TYPE "llvm-mca"
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PressureTracker::PressureTracker(const MCSchedModel &Model)
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: SM(Model),
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ResourcePressureDistribution(Model.getNumProcResourceKinds(), 0),
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ProcResID2Mask(Model.getNumProcResourceKinds(), 0),
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ResIdx2ProcResID(Model.getNumProcResourceKinds(), 0),
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ProcResID2ResourceUsersIndex(Model.getNumProcResourceKinds(), 0) {
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computeProcResourceMasks(SM, ProcResID2Mask);
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// Ignore the invalid resource at index zero.
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unsigned NextResourceUsersIdx = 0;
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for (unsigned I = 1, E = Model.getNumProcResourceKinds(); I < E; ++I) {
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const MCProcResourceDesc &ProcResource = *SM.getProcResource(I);
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ProcResID2ResourceUsersIndex[I] = NextResourceUsersIdx;
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NextResourceUsersIdx += ProcResource.NumUnits;
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uint64_t ResourceMask = ProcResID2Mask[I];
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ResIdx2ProcResID[getResourceStateIndex(ResourceMask)] = I;
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}
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ResourceUsers.resize(NextResourceUsersIdx);
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std::fill(ResourceUsers.begin(), ResourceUsers.end(),
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std::make_pair<unsigned, unsigned>(~0U, 0U));
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}
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void PressureTracker::getResourceUsers(uint64_t ResourceMask,
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SmallVectorImpl<User> &Users) const {
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unsigned Index = getResourceStateIndex(ResourceMask);
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unsigned ProcResID = ResIdx2ProcResID[Index];
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const MCProcResourceDesc &PRDesc = *SM.getProcResource(ProcResID);
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for (unsigned I = 0, E = PRDesc.NumUnits; I < E; ++I) {
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const User U = getResourceUser(ProcResID, I);
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if (U.second && IPI.contains(U.first))
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Users.emplace_back(U);
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}
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}
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void PressureTracker::onInstructionDispatched(unsigned IID) {
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IPI.insert(std::make_pair(IID, InstructionPressureInfo()));
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}
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void PressureTracker::onInstructionExecuted(unsigned IID) { IPI.erase(IID); }
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void PressureTracker::handleInstructionIssuedEvent(
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const HWInstructionIssuedEvent &Event) {
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unsigned IID = Event.IR.getSourceIndex();
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for (const ResourceUse &Use : Event.UsedResources) {
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const ResourceRef &RR = Use.first;
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unsigned Index = ProcResID2ResourceUsersIndex[RR.first];
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Index += llvm::countr_zero(RR.second);
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ResourceUsers[Index] = std::make_pair(IID, Use.second.getNumerator());
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}
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}
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void PressureTracker::updateResourcePressureDistribution(
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uint64_t CumulativeMask) {
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while (CumulativeMask) {
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uint64_t Current = CumulativeMask & (-CumulativeMask);
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unsigned ResIdx = getResourceStateIndex(Current);
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unsigned ProcResID = ResIdx2ProcResID[ResIdx];
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uint64_t Mask = ProcResID2Mask[ProcResID];
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if (Mask == Current) {
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ResourcePressureDistribution[ProcResID]++;
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CumulativeMask ^= Current;
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continue;
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}
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Mask ^= Current;
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while (Mask) {
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uint64_t SubUnit = Mask & (-Mask);
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ResIdx = getResourceStateIndex(SubUnit);
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ProcResID = ResIdx2ProcResID[ResIdx];
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ResourcePressureDistribution[ProcResID]++;
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Mask ^= SubUnit;
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}
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CumulativeMask ^= Current;
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}
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}
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void PressureTracker::handlePressureEvent(const HWPressureEvent &Event) {
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assert(Event.Reason != HWPressureEvent::INVALID &&
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"Unexpected invalid event!");
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switch (Event.Reason) {
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default:
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break;
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case HWPressureEvent::RESOURCES: {
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const uint64_t ResourceMask = Event.ResourceMask;
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updateResourcePressureDistribution(Event.ResourceMask);
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for (const InstRef &IR : Event.AffectedInstructions) {
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const Instruction &IS = *IR.getInstruction();
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unsigned BusyResources = IS.getCriticalResourceMask() & ResourceMask;
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if (!BusyResources)
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continue;
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unsigned IID = IR.getSourceIndex();
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IPI[IID].ResourcePressureCycles++;
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}
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break;
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}
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case HWPressureEvent::REGISTER_DEPS:
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for (const InstRef &IR : Event.AffectedInstructions) {
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unsigned IID = IR.getSourceIndex();
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IPI[IID].RegisterPressureCycles++;
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}
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break;
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case HWPressureEvent::MEMORY_DEPS:
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for (const InstRef &IR : Event.AffectedInstructions) {
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unsigned IID = IR.getSourceIndex();
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IPI[IID].MemoryPressureCycles++;
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}
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}
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}
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#ifndef NDEBUG
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void DependencyGraph::dumpDependencyEdge(raw_ostream &OS,
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const DependencyEdge &DepEdge,
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MCInstPrinter &MCIP) const {
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unsigned FromIID = DepEdge.FromIID;
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unsigned ToIID = DepEdge.ToIID;
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assert(FromIID < ToIID && "Graph should be acyclic!");
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const DependencyEdge::Dependency &DE = DepEdge.Dep;
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assert(DE.Type != DependencyEdge::DT_INVALID && "Unexpected invalid edge!");
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OS << " FROM: " << FromIID << " TO: " << ToIID << " ";
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if (DE.Type == DependencyEdge::DT_REGISTER) {
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OS << " - REGISTER: ";
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MCIP.printRegName(OS, DE.ResourceOrRegID);
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} else if (DE.Type == DependencyEdge::DT_MEMORY) {
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OS << " - MEMORY";
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} else {
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assert(DE.Type == DependencyEdge::DT_RESOURCE &&
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"Unsupported dependency type!");
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OS << " - RESOURCE MASK: " << DE.ResourceOrRegID;
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}
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OS << " - COST: " << DE.Cost << '\n';
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}
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#endif // NDEBUG
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void DependencyGraph::pruneEdges(unsigned Iterations) {
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for (DGNode &N : Nodes) {
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unsigned NumPruned = 0;
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const unsigned Size = N.OutgoingEdges.size();
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// Use a cut-off threshold to prune edges with a low frequency.
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for (unsigned I = 0, E = Size; I < E; ++I) {
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DependencyEdge &Edge = N.OutgoingEdges[I];
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if (Edge.Frequency == Iterations)
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continue;
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double Factor = (double)Edge.Frequency / Iterations;
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if (0.10 < Factor)
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continue;
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Nodes[Edge.ToIID].NumPredecessors--;
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std::swap(Edge, N.OutgoingEdges[E - 1]);
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--E;
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++NumPruned;
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}
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if (NumPruned)
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N.OutgoingEdges.resize(Size - NumPruned);
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}
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}
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void DependencyGraph::initializeRootSet(
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SmallVectorImpl<unsigned> &RootSet) const {
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for (unsigned I = 0, E = Nodes.size(); I < E; ++I) {
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const DGNode &N = Nodes[I];
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if (N.NumPredecessors == 0 && !N.OutgoingEdges.empty())
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RootSet.emplace_back(I);
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}
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}
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void DependencyGraph::propagateThroughEdges(SmallVectorImpl<unsigned> &RootSet,
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unsigned Iterations) {
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SmallVector<unsigned, 8> ToVisit;
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// A critical sequence is computed as the longest path from a node of the
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// RootSet to a leaf node (i.e. a node with no successors). The RootSet is
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// composed of nodes with at least one successor, and no predecessors.
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//
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// Each node of the graph starts with an initial default cost of zero. The
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// cost of a node is a measure of criticality: the higher the cost, the bigger
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// is the performance impact.
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// For register and memory dependencies, the cost is a function of the write
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// latency as well as the actual delay (in cycles) caused to users.
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// For processor resource dependencies, the cost is a function of the resource
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// pressure. Resource interferences with low frequency values are ignored.
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//
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// This algorithm is very similar to a (reverse) Dijkstra. Every iteration of
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// the inner loop selects (i.e. visits) a node N from a set of `unvisited
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// nodes`, and then propagates the cost of N to all its neighbors.
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//
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// The `unvisited nodes` set initially contains all the nodes from the
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// RootSet. A node N is added to the `unvisited nodes` if all its
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// predecessors have been visited already.
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//
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// For simplicity, every node tracks the number of unvisited incoming edges in
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// field `NumVisitedPredecessors`. When the value of that field drops to
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// zero, then the corresponding node is added to a `ToVisit` set.
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//
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// At the end of every iteration of the outer loop, set `ToVisit` becomes our
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// new `unvisited nodes` set.
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//
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// The algorithm terminates when the set of unvisited nodes (i.e. our RootSet)
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// is empty. This algorithm works under the assumption that the graph is
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// acyclic.
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do {
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for (unsigned IID : RootSet) {
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const DGNode &N = Nodes[IID];
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for (const DependencyEdge &DepEdge : N.OutgoingEdges) {
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unsigned ToIID = DepEdge.ToIID;
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DGNode &To = Nodes[ToIID];
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uint64_t Cost = N.Cost + DepEdge.Dep.Cost;
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// Check if this is the most expensive incoming edge seen so far. In
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// case, update the total cost of the destination node (ToIID), as well
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// its field `CriticalPredecessor`.
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if (Cost > To.Cost) {
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To.CriticalPredecessor = DepEdge;
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To.Cost = Cost;
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To.Depth = N.Depth + 1;
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}
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To.NumVisitedPredecessors++;
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if (To.NumVisitedPredecessors == To.NumPredecessors)
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ToVisit.emplace_back(ToIID);
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}
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}
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std::swap(RootSet, ToVisit);
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ToVisit.clear();
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} while (!RootSet.empty());
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}
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void DependencyGraph::getCriticalSequence(
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SmallVectorImpl<const DependencyEdge *> &Seq) const {
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// At this stage, nodes of the graph have been already visited, and costs have
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// been propagated through the edges (see method `propagateThroughEdges()`).
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// Identify the node N with the highest cost in the graph. By construction,
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// that node is the last instruction of our critical sequence.
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// Field N.Depth would tell us the total length of the sequence.
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//
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// To obtain the sequence of critical edges, we simply follow the chain of
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// critical predecessors starting from node N (field
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// DGNode::CriticalPredecessor).
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const auto It = std::max_element(
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Nodes.begin(), Nodes.end(),
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[](const DGNode &Lhs, const DGNode &Rhs) { return Lhs.Cost < Rhs.Cost; });
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unsigned IID = std::distance(Nodes.begin(), It);
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Seq.resize(Nodes[IID].Depth);
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for (const DependencyEdge *&DE : llvm::reverse(Seq)) {
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const DGNode &N = Nodes[IID];
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DE = &N.CriticalPredecessor;
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IID = N.CriticalPredecessor.FromIID;
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}
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}
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void BottleneckAnalysis::printInstruction(formatted_raw_ostream &FOS,
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const MCInst &MCI,
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bool UseDifferentColor) const {
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FOS.PadToColumn(14);
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if (UseDifferentColor)
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FOS.changeColor(raw_ostream::CYAN, true, false);
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FOS << printInstructionString(MCI);
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if (UseDifferentColor)
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FOS.resetColor();
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}
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void BottleneckAnalysis::printCriticalSequence(raw_ostream &OS) const {
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// Early exit if no bottlenecks were found during the simulation.
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if (!SeenStallCycles || !BPI.PressureIncreaseCycles)
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return;
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SmallVector<const DependencyEdge *, 16> Seq;
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DG.getCriticalSequence(Seq);
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if (Seq.empty())
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return;
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OS << "\nCritical sequence based on the simulation:\n\n";
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const DependencyEdge &FirstEdge = *Seq[0];
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ArrayRef<llvm::MCInst> Source = getSource();
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unsigned FromIID = FirstEdge.FromIID % Source.size();
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unsigned ToIID = FirstEdge.ToIID % Source.size();
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bool IsLoopCarried = FromIID >= ToIID;
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formatted_raw_ostream FOS(OS);
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FOS.PadToColumn(14);
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FOS << "Instruction";
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FOS.PadToColumn(58);
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FOS << "Dependency Information";
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bool HasColors = FOS.has_colors();
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unsigned CurrentIID = 0;
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if (IsLoopCarried) {
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FOS << "\n +----< " << FromIID << ".";
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printInstruction(FOS, Source[FromIID], HasColors);
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FOS << "\n |\n | < loop carried > \n |";
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} else {
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while (CurrentIID < FromIID) {
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FOS << "\n " << CurrentIID << ".";
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printInstruction(FOS, Source[CurrentIID]);
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CurrentIID++;
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}
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FOS << "\n +----< " << CurrentIID << ".";
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printInstruction(FOS, Source[CurrentIID], HasColors);
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CurrentIID++;
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}
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for (const DependencyEdge *&DE : Seq) {
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ToIID = DE->ToIID % Source.size();
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unsigned LastIID = CurrentIID > ToIID ? Source.size() : ToIID;
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while (CurrentIID < LastIID) {
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FOS << "\n | " << CurrentIID << ".";
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printInstruction(FOS, Source[CurrentIID]);
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CurrentIID++;
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}
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if (CurrentIID == ToIID) {
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FOS << "\n +----> " << ToIID << ".";
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printInstruction(FOS, Source[CurrentIID], HasColors);
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} else {
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FOS << "\n |\n | < loop carried > \n |"
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<< "\n +----> " << ToIID << ".";
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printInstruction(FOS, Source[ToIID], HasColors);
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}
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FOS.PadToColumn(58);
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const DependencyEdge::Dependency &Dep = DE->Dep;
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if (HasColors)
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FOS.changeColor(raw_ostream::SAVEDCOLOR, true, false);
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if (Dep.Type == DependencyEdge::DT_REGISTER) {
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FOS << "## REGISTER dependency: ";
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if (HasColors)
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FOS.changeColor(raw_ostream::MAGENTA, true, false);
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getInstPrinter().printRegName(FOS, Dep.ResourceOrRegID);
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} else if (Dep.Type == DependencyEdge::DT_MEMORY) {
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FOS << "## MEMORY dependency.";
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} else {
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assert(Dep.Type == DependencyEdge::DT_RESOURCE &&
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"Unsupported dependency type!");
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FOS << "## RESOURCE interference: ";
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if (HasColors)
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FOS.changeColor(raw_ostream::MAGENTA, true, false);
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FOS << Tracker.resolveResourceName(Dep.ResourceOrRegID);
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if (HasColors) {
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FOS.resetColor();
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FOS.changeColor(raw_ostream::SAVEDCOLOR, true, false);
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}
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FOS << " [ probability: " << ((DE->Frequency * 100) / Iterations)
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<< "% ]";
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}
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if (HasColors)
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FOS.resetColor();
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++CurrentIID;
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}
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while (CurrentIID < Source.size()) {
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FOS << "\n " << CurrentIID << ".";
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printInstruction(FOS, Source[CurrentIID]);
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CurrentIID++;
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}
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FOS << '\n';
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FOS.flush();
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}
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#ifndef NDEBUG
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void DependencyGraph::dump(raw_ostream &OS, MCInstPrinter &MCIP) const {
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OS << "\nREG DEPS\n";
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for (const DGNode &Node : Nodes)
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for (const DependencyEdge &DE : Node.OutgoingEdges)
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if (DE.Dep.Type == DependencyEdge::DT_REGISTER)
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dumpDependencyEdge(OS, DE, MCIP);
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OS << "\nMEM DEPS\n";
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for (const DGNode &Node : Nodes)
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for (const DependencyEdge &DE : Node.OutgoingEdges)
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if (DE.Dep.Type == DependencyEdge::DT_MEMORY)
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dumpDependencyEdge(OS, DE, MCIP);
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OS << "\nRESOURCE DEPS\n";
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for (const DGNode &Node : Nodes)
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for (const DependencyEdge &DE : Node.OutgoingEdges)
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if (DE.Dep.Type == DependencyEdge::DT_RESOURCE)
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dumpDependencyEdge(OS, DE, MCIP);
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}
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#endif // NDEBUG
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void DependencyGraph::addDependency(unsigned From, unsigned To,
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DependencyEdge::Dependency &&Dep) {
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DGNode &NodeFrom = Nodes[From];
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DGNode &NodeTo = Nodes[To];
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SmallVectorImpl<DependencyEdge> &Vec = NodeFrom.OutgoingEdges;
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auto It = find_if(Vec, [To, Dep](DependencyEdge &DE) {
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return DE.ToIID == To && DE.Dep.ResourceOrRegID == Dep.ResourceOrRegID;
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});
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if (It != Vec.end()) {
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It->Dep.Cost += Dep.Cost;
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It->Frequency++;
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return;
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}
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DependencyEdge DE = {Dep, From, To, 1};
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Vec.emplace_back(DE);
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NodeTo.NumPredecessors++;
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}
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BottleneckAnalysis::BottleneckAnalysis(const MCSubtargetInfo &sti,
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MCInstPrinter &Printer,
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ArrayRef<MCInst> S, unsigned NumIter)
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: InstructionView(sti, Printer, S), Tracker(sti.getSchedModel()),
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DG(S.size() * 3), Iterations(NumIter), TotalCycles(0),
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PressureIncreasedBecauseOfResources(false),
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PressureIncreasedBecauseOfRegisterDependencies(false),
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PressureIncreasedBecauseOfMemoryDependencies(false),
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SeenStallCycles(false), BPI() {}
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void BottleneckAnalysis::addRegisterDep(unsigned From, unsigned To,
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unsigned RegID, unsigned Cost) {
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bool IsLoopCarried = From >= To;
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unsigned SourceSize = getSource().size();
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if (IsLoopCarried) {
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DG.addRegisterDep(From, To + SourceSize, RegID, Cost);
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DG.addRegisterDep(From + SourceSize, To + (SourceSize * 2), RegID, Cost);
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return;
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}
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DG.addRegisterDep(From + SourceSize, To + SourceSize, RegID, Cost);
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}
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void BottleneckAnalysis::addMemoryDep(unsigned From, unsigned To,
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unsigned Cost) {
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bool IsLoopCarried = From >= To;
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unsigned SourceSize = getSource().size();
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if (IsLoopCarried) {
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DG.addMemoryDep(From, To + SourceSize, Cost);
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DG.addMemoryDep(From + SourceSize, To + (SourceSize * 2), Cost);
|
|
return;
|
|
}
|
|
DG.addMemoryDep(From + SourceSize, To + SourceSize, Cost);
|
|
}
|
|
|
|
void BottleneckAnalysis::addResourceDep(unsigned From, unsigned To,
|
|
uint64_t Mask, unsigned Cost) {
|
|
bool IsLoopCarried = From >= To;
|
|
unsigned SourceSize = getSource().size();
|
|
if (IsLoopCarried) {
|
|
DG.addResourceDep(From, To + SourceSize, Mask, Cost);
|
|
DG.addResourceDep(From + SourceSize, To + (SourceSize * 2), Mask, Cost);
|
|
return;
|
|
}
|
|
DG.addResourceDep(From + SourceSize, To + SourceSize, Mask, Cost);
|
|
}
|
|
|
|
void BottleneckAnalysis::onEvent(const HWInstructionEvent &Event) {
|
|
const unsigned IID = Event.IR.getSourceIndex();
|
|
if (Event.Type == HWInstructionEvent::Dispatched) {
|
|
Tracker.onInstructionDispatched(IID);
|
|
return;
|
|
}
|
|
if (Event.Type == HWInstructionEvent::Executed) {
|
|
Tracker.onInstructionExecuted(IID);
|
|
return;
|
|
}
|
|
|
|
if (Event.Type != HWInstructionEvent::Issued)
|
|
return;
|
|
|
|
ArrayRef<llvm::MCInst> Source = getSource();
|
|
const Instruction &IS = *Event.IR.getInstruction();
|
|
unsigned To = IID % Source.size();
|
|
|
|
unsigned Cycles = 2 * Tracker.getResourcePressureCycles(IID);
|
|
uint64_t ResourceMask = IS.getCriticalResourceMask();
|
|
SmallVector<std::pair<unsigned, unsigned>, 4> Users;
|
|
while (ResourceMask) {
|
|
uint64_t Current = ResourceMask & (-ResourceMask);
|
|
Tracker.getResourceUsers(Current, Users);
|
|
for (const std::pair<unsigned, unsigned> &U : Users)
|
|
addResourceDep(U.first % Source.size(), To, Current, U.second + Cycles);
|
|
Users.clear();
|
|
ResourceMask ^= Current;
|
|
}
|
|
|
|
const CriticalDependency &RegDep = IS.getCriticalRegDep();
|
|
if (RegDep.Cycles) {
|
|
Cycles = RegDep.Cycles + 2 * Tracker.getRegisterPressureCycles(IID);
|
|
unsigned From = RegDep.IID % Source.size();
|
|
addRegisterDep(From, To, RegDep.RegID, Cycles);
|
|
}
|
|
|
|
const CriticalDependency &MemDep = IS.getCriticalMemDep();
|
|
if (MemDep.Cycles) {
|
|
Cycles = MemDep.Cycles + 2 * Tracker.getMemoryPressureCycles(IID);
|
|
unsigned From = MemDep.IID % Source.size();
|
|
addMemoryDep(From, To, Cycles);
|
|
}
|
|
|
|
Tracker.handleInstructionIssuedEvent(
|
|
static_cast<const HWInstructionIssuedEvent &>(Event));
|
|
|
|
// Check if this is the last simulated instruction.
|
|
if (IID == ((Iterations * Source.size()) - 1))
|
|
DG.finalizeGraph(Iterations);
|
|
}
|
|
|
|
void BottleneckAnalysis::onEvent(const HWPressureEvent &Event) {
|
|
assert(Event.Reason != HWPressureEvent::INVALID &&
|
|
"Unexpected invalid event!");
|
|
|
|
Tracker.handlePressureEvent(Event);
|
|
|
|
switch (Event.Reason) {
|
|
default:
|
|
break;
|
|
|
|
case HWPressureEvent::RESOURCES:
|
|
PressureIncreasedBecauseOfResources = true;
|
|
break;
|
|
case HWPressureEvent::REGISTER_DEPS:
|
|
PressureIncreasedBecauseOfRegisterDependencies = true;
|
|
break;
|
|
case HWPressureEvent::MEMORY_DEPS:
|
|
PressureIncreasedBecauseOfMemoryDependencies = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void BottleneckAnalysis::onCycleEnd() {
|
|
++TotalCycles;
|
|
|
|
bool PressureIncreasedBecauseOfDataDependencies =
|
|
PressureIncreasedBecauseOfRegisterDependencies ||
|
|
PressureIncreasedBecauseOfMemoryDependencies;
|
|
if (!PressureIncreasedBecauseOfResources &&
|
|
!PressureIncreasedBecauseOfDataDependencies)
|
|
return;
|
|
|
|
++BPI.PressureIncreaseCycles;
|
|
if (PressureIncreasedBecauseOfRegisterDependencies)
|
|
++BPI.RegisterDependencyCycles;
|
|
if (PressureIncreasedBecauseOfMemoryDependencies)
|
|
++BPI.MemoryDependencyCycles;
|
|
if (PressureIncreasedBecauseOfDataDependencies)
|
|
++BPI.DataDependencyCycles;
|
|
if (PressureIncreasedBecauseOfResources)
|
|
++BPI.ResourcePressureCycles;
|
|
PressureIncreasedBecauseOfResources = false;
|
|
PressureIncreasedBecauseOfRegisterDependencies = false;
|
|
PressureIncreasedBecauseOfMemoryDependencies = false;
|
|
}
|
|
|
|
void BottleneckAnalysis::printBottleneckHints(raw_ostream &OS) const {
|
|
if (!SeenStallCycles || !BPI.PressureIncreaseCycles) {
|
|
OS << "\n\nNo resource or data dependency bottlenecks discovered.\n";
|
|
return;
|
|
}
|
|
|
|
double PressurePerCycle =
|
|
(double)BPI.PressureIncreaseCycles * 100 / TotalCycles;
|
|
double ResourcePressurePerCycle =
|
|
(double)BPI.ResourcePressureCycles * 100 / TotalCycles;
|
|
double DDPerCycle = (double)BPI.DataDependencyCycles * 100 / TotalCycles;
|
|
double RegDepPressurePerCycle =
|
|
(double)BPI.RegisterDependencyCycles * 100 / TotalCycles;
|
|
double MemDepPressurePerCycle =
|
|
(double)BPI.MemoryDependencyCycles * 100 / TotalCycles;
|
|
|
|
OS << "\n\nCycles with backend pressure increase [ "
|
|
<< format("%.2f", floor((PressurePerCycle * 100) + 0.5) / 100) << "% ]";
|
|
|
|
OS << "\nThroughput Bottlenecks: "
|
|
<< "\n Resource Pressure [ "
|
|
<< format("%.2f", floor((ResourcePressurePerCycle * 100) + 0.5) / 100)
|
|
<< "% ]";
|
|
|
|
if (BPI.PressureIncreaseCycles) {
|
|
ArrayRef<unsigned> Distribution = Tracker.getResourcePressureDistribution();
|
|
const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
|
|
for (unsigned I = 0, E = Distribution.size(); I < E; ++I) {
|
|
unsigned ReleaseAtCycles = Distribution[I];
|
|
if (ReleaseAtCycles) {
|
|
double Frequency = (double)ReleaseAtCycles * 100 / TotalCycles;
|
|
const MCProcResourceDesc &PRDesc = *SM.getProcResource(I);
|
|
OS << "\n - " << PRDesc.Name << " [ "
|
|
<< format("%.2f", floor((Frequency * 100) + 0.5) / 100) << "% ]";
|
|
}
|
|
}
|
|
}
|
|
|
|
OS << "\n Data Dependencies: [ "
|
|
<< format("%.2f", floor((DDPerCycle * 100) + 0.5) / 100) << "% ]";
|
|
OS << "\n - Register Dependencies [ "
|
|
<< format("%.2f", floor((RegDepPressurePerCycle * 100) + 0.5) / 100)
|
|
<< "% ]";
|
|
OS << "\n - Memory Dependencies [ "
|
|
<< format("%.2f", floor((MemDepPressurePerCycle * 100) + 0.5) / 100)
|
|
<< "% ]\n";
|
|
}
|
|
|
|
void BottleneckAnalysis::printView(raw_ostream &OS) const {
|
|
std::string Buffer;
|
|
raw_string_ostream TempStream(Buffer);
|
|
printBottleneckHints(TempStream);
|
|
TempStream.flush();
|
|
OS << Buffer;
|
|
printCriticalSequence(OS);
|
|
}
|
|
|
|
} // namespace mca.
|
|
} // namespace llvm
|