560564f51c
This is to avoid confusion when dealing with reduction/combining kinds. For example, see a recent PR comment: https://github.com/llvm/llvm-project/pull/75846#discussion_r1430722175. Previously, they were picked to mostly mirror the names of the llvm vector reduction intrinsics: https://llvm.org/docs/LangRef.html#llvm-vector-reduce-fmin-intrinsic. In isolation, it was not clear if `<maxf>` has `arith.maxnumf` or `arith.maximumf` semantics. The new reduction kind names map 1:1 to arith ops, which makes it easier to tell/look up their semantics. Because both the vector and the gpu dialect depend on the arith dialect, it's more natural to align names with those in arith than with the lowering to llvm intrinsics. Issue: https://github.com/llvm/llvm-project/issues/72354
395 lines
17 KiB
C++
395 lines
17 KiB
C++
//===- LowerGpuOpsToNVVMOps.cpp - MLIR GPU to NVVM lowering passes --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass to generate NVVMIR operations for higher-level
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// GPU operations.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h"
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#include "mlir/Conversion/ArithToLLVM/ArithToLLVM.h"
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#include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h"
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#include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h"
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#include "mlir/Conversion/GPUCommon/GPUCommonPass.h"
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#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
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#include "mlir/Conversion/LLVMCommon/LoweringOptions.h"
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#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
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#include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h"
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#include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h"
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#include "mlir/Dialect/ControlFlow/IR/ControlFlow.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/GPU/Transforms/Passes.h"
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/Dialect/Math/IR/Math.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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#include "../GPUCommon/GPUOpsLowering.h"
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#include "../GPUCommon/IndexIntrinsicsOpLowering.h"
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#include "../GPUCommon/OpToFuncCallLowering.h"
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#include <optional>
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namespace mlir {
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#define GEN_PASS_DEF_CONVERTGPUOPSTONVVMOPS
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#include "mlir/Conversion/Passes.h.inc"
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} // namespace mlir
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using namespace mlir;
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namespace {
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/// Convert gpu dialect shfl mode enum to the equivalent nvvm one.
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static NVVM::ShflKind convertShflKind(gpu::ShuffleMode mode) {
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switch (mode) {
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case gpu::ShuffleMode::XOR:
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return NVVM::ShflKind::bfly;
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case gpu::ShuffleMode::UP:
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return NVVM::ShflKind::up;
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case gpu::ShuffleMode::DOWN:
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return NVVM::ShflKind::down;
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case gpu::ShuffleMode::IDX:
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return NVVM::ShflKind::idx;
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}
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llvm_unreachable("unknown shuffle mode");
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}
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static std::optional<NVVM::ReduxKind>
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convertReduxKind(gpu::AllReduceOperation mode) {
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switch (mode) {
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case gpu::AllReduceOperation::ADD:
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return NVVM::ReduxKind::ADD;
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case gpu::AllReduceOperation::MUL:
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return std::nullopt;
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case gpu::AllReduceOperation::MINSI:
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return NVVM::ReduxKind::MIN;
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case gpu::AllReduceOperation::MINUI:
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return std::nullopt;
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case gpu::AllReduceOperation::MINNUMF:
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return NVVM::ReduxKind::MIN;
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case gpu::AllReduceOperation::MAXSI:
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return NVVM::ReduxKind::MAX;
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case gpu::AllReduceOperation::MAXUI:
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return std::nullopt;
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case gpu::AllReduceOperation::MAXNUMF:
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return NVVM::ReduxKind::MAX;
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case gpu::AllReduceOperation::AND:
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return NVVM::ReduxKind::AND;
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case gpu::AllReduceOperation::OR:
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return NVVM::ReduxKind::OR;
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case gpu::AllReduceOperation::XOR:
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return NVVM::ReduxKind::XOR;
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case gpu::AllReduceOperation::MINIMUMF:
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case gpu::AllReduceOperation::MAXIMUMF:
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return std::nullopt;
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}
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return std::nullopt;
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}
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/// This pass lowers gpu.subgroup_reduce op into to the nvvm.redux op. The op
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/// must be run by the entire subgroup, otherwise it is undefined behaviour.
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struct GPUSubgroupReduceOpLowering
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: public ConvertOpToLLVMPattern<gpu::SubgroupReduceOp> {
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using ConvertOpToLLVMPattern<gpu::SubgroupReduceOp>::ConvertOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(gpu::SubgroupReduceOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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if (!op.getUniform())
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return rewriter.notifyMatchFailure(
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op, "cannot be lowered to redux as the op must be run "
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"uniformly (entire subgroup).");
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if (!op.getValue().getType().isInteger(32))
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return rewriter.notifyMatchFailure(op, "unsupported data type");
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std::optional<NVVM::ReduxKind> mode = convertReduxKind(op.getOp());
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if (!mode.has_value())
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return rewriter.notifyMatchFailure(
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op, "unsupported reduction mode for redux");
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Location loc = op->getLoc();
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auto int32Type = IntegerType::get(rewriter.getContext(), 32);
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Value offset = rewriter.create<LLVM::ConstantOp>(loc, int32Type, -1);
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auto reduxOp = rewriter.create<NVVM::ReduxOp>(loc, int32Type, op.getValue(),
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mode.value(), offset);
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rewriter.replaceOp(op, reduxOp->getResult(0));
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return success();
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}
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};
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struct GPUShuffleOpLowering : public ConvertOpToLLVMPattern<gpu::ShuffleOp> {
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using ConvertOpToLLVMPattern<gpu::ShuffleOp>::ConvertOpToLLVMPattern;
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/// Lowers a shuffle to the corresponding NVVM op.
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///
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/// Convert the `width` argument into an activeMask (a bitmask which specifies
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/// which threads participate in the shuffle) and a maskAndClamp (specifying
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/// the highest lane which participates in the shuffle).
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///
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/// %one = llvm.constant(1 : i32) : i32
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/// %minus_one = llvm.constant(-1 : i32) : i32
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/// %thirty_two = llvm.constant(32 : i32) : i32
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/// %num_lanes = llvm.sub %thirty_two, %width : i32
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/// %active_mask = llvm.lshr %minus_one, %num_lanes : i32
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/// %mask_and_clamp = llvm.sub %width, %one : i32
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/// %shfl = nvvm.shfl.sync.bfly %active_mask, %value, %offset,
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/// %mask_and_clamp : !llvm<"{ float, i1 }">
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/// %shfl_value = llvm.extractvalue %shfl[0] :
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/// !llvm<"{ float, i1 }">
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/// %shfl_pred = llvm.extractvalue %shfl[1] :
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/// !llvm<"{ float, i1 }">
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LogicalResult
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matchAndRewrite(gpu::ShuffleOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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auto valueTy = adaptor.getValue().getType();
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auto int32Type = IntegerType::get(rewriter.getContext(), 32);
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auto predTy = IntegerType::get(rewriter.getContext(), 1);
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auto resultTy = LLVM::LLVMStructType::getLiteral(rewriter.getContext(),
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{valueTy, predTy});
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Value one = rewriter.create<LLVM::ConstantOp>(loc, int32Type, 1);
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Value minusOne = rewriter.create<LLVM::ConstantOp>(loc, int32Type, -1);
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Value thirtyTwo = rewriter.create<LLVM::ConstantOp>(loc, int32Type, 32);
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Value numLeadInactiveLane = rewriter.create<LLVM::SubOp>(
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loc, int32Type, thirtyTwo, adaptor.getWidth());
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// Bit mask of active lanes: `(-1) >> (32 - activeWidth)`.
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Value activeMask = rewriter.create<LLVM::LShrOp>(loc, int32Type, minusOne,
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numLeadInactiveLane);
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Value maskAndClamp;
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if (op.getMode() == gpu::ShuffleMode::UP) {
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// Clamp lane: `32 - activeWidth`
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maskAndClamp = numLeadInactiveLane;
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} else {
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// Clamp lane: `activeWidth - 1`
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maskAndClamp =
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rewriter.create<LLVM::SubOp>(loc, int32Type, adaptor.getWidth(), one);
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}
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auto returnValueAndIsValidAttr = rewriter.getUnitAttr();
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Value shfl = rewriter.create<NVVM::ShflOp>(
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loc, resultTy, activeMask, adaptor.getValue(), adaptor.getOffset(),
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maskAndClamp, convertShflKind(op.getMode()), returnValueAndIsValidAttr);
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Value shflValue = rewriter.create<LLVM::ExtractValueOp>(loc, shfl, 0);
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Value isActiveSrcLane = rewriter.create<LLVM::ExtractValueOp>(loc, shfl, 1);
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rewriter.replaceOp(op, {shflValue, isActiveSrcLane});
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return success();
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}
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};
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struct GPULaneIdOpToNVVM : ConvertOpToLLVMPattern<gpu::LaneIdOp> {
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using ConvertOpToLLVMPattern<gpu::LaneIdOp>::ConvertOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(gpu::LaneIdOp op, gpu::LaneIdOp::Adaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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auto loc = op->getLoc();
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MLIRContext *context = rewriter.getContext();
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Value newOp = rewriter.create<NVVM::LaneIdOp>(loc, rewriter.getI32Type());
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// Truncate or extend the result depending on the index bitwidth specified
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// by the LLVMTypeConverter options.
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const unsigned indexBitwidth = getTypeConverter()->getIndexTypeBitwidth();
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if (indexBitwidth > 32) {
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newOp = rewriter.create<LLVM::SExtOp>(
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loc, IntegerType::get(context, indexBitwidth), newOp);
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} else if (indexBitwidth < 32) {
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newOp = rewriter.create<LLVM::TruncOp>(
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loc, IntegerType::get(context, indexBitwidth), newOp);
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}
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rewriter.replaceOp(op, {newOp});
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return success();
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}
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};
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/// Import the GPU Ops to NVVM Patterns.
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#include "GPUToNVVM.cpp.inc"
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/// A pass that replaces all occurrences of GPU device operations with their
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/// corresponding NVVM equivalent.
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///
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/// This pass only handles device code and is not meant to be run on GPU host
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/// code.
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struct LowerGpuOpsToNVVMOpsPass
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: public impl::ConvertGpuOpsToNVVMOpsBase<LowerGpuOpsToNVVMOpsPass> {
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using Base::Base;
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void runOnOperation() override {
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gpu::GPUModuleOp m = getOperation();
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// Request C wrapper emission.
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for (auto func : m.getOps<func::FuncOp>()) {
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func->setAttr(LLVM::LLVMDialect::getEmitCWrapperAttrName(),
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UnitAttr::get(&getContext()));
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}
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// Customize the bitwidth used for the device side index computations.
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LowerToLLVMOptions options(
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m.getContext(),
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DataLayout(cast<DataLayoutOpInterface>(m.getOperation())));
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if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout)
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options.overrideIndexBitwidth(indexBitwidth);
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options.useBarePtrCallConv = useBarePtrCallConv;
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// Apply in-dialect lowering. In-dialect lowering will replace
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// ops which need to be lowered further, which is not supported by a
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// single conversion pass.
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{
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RewritePatternSet patterns(m.getContext());
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populateGpuRewritePatterns(patterns);
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if (failed(applyPatternsAndFoldGreedily(m, std::move(patterns))))
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return signalPassFailure();
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}
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LLVMTypeConverter converter(m.getContext(), options);
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// NVVM uses alloca in the default address space to represent private
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// memory allocations, so drop private annotations. NVVM uses address
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// space 3 for shared memory. NVVM uses the default address space to
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// represent global memory.
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populateGpuMemorySpaceAttributeConversions(
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converter, [](gpu::AddressSpace space) -> unsigned {
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switch (space) {
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case gpu::AddressSpace::Global:
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return static_cast<unsigned>(
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NVVM::NVVMMemorySpace::kGlobalMemorySpace);
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case gpu::AddressSpace::Workgroup:
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return static_cast<unsigned>(
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NVVM::NVVMMemorySpace::kSharedMemorySpace);
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case gpu::AddressSpace::Private:
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return 0;
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}
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llvm_unreachable("unknown address space enum value");
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return 0;
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});
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// Lowering for MMAMatrixType.
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converter.addConversion([&](gpu::MMAMatrixType type) -> Type {
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return convertMMAToLLVMType(type);
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});
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RewritePatternSet llvmPatterns(m.getContext());
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arith::populateArithToLLVMConversionPatterns(converter, llvmPatterns);
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cf::populateControlFlowToLLVMConversionPatterns(converter, llvmPatterns);
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populateFuncToLLVMConversionPatterns(converter, llvmPatterns);
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populateFinalizeMemRefToLLVMConversionPatterns(converter, llvmPatterns);
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populateGpuToNVVMConversionPatterns(converter, llvmPatterns);
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populateGpuWMMAToNVVMConversionPatterns(converter, llvmPatterns);
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populateVectorToLLVMConversionPatterns(converter, llvmPatterns);
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if (this->hasRedux)
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populateGpuSubgroupReduceOpLoweringPattern(converter, llvmPatterns);
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LLVMConversionTarget target(getContext());
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configureGpuToNVVMConversionLegality(target);
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if (failed(applyPartialConversion(m, target, std::move(llvmPatterns))))
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signalPassFailure();
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}
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};
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} // namespace
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void mlir::configureGpuToNVVMConversionLegality(ConversionTarget &target) {
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target.addIllegalOp<func::FuncOp>();
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target.addLegalDialect<::mlir::LLVM::LLVMDialect>();
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target.addLegalDialect<::mlir::NVVM::NVVMDialect>();
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target.addIllegalDialect<gpu::GPUDialect>();
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target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp,
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LLVM::FCeilOp, LLVM::FFloorOp, LLVM::FRemOp, LLVM::LogOp,
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LLVM::Log10Op, LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp,
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LLVM::SqrtOp>();
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// TODO: Remove once we support replacing non-root ops.
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target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>();
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}
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template <typename OpTy>
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static void populateOpPatterns(LLVMTypeConverter &converter,
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RewritePatternSet &patterns, StringRef f32Func,
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StringRef f64Func) {
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patterns.add<ScalarizeVectorOpLowering<OpTy>>(converter);
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patterns.add<OpToFuncCallLowering<OpTy>>(converter, f32Func, f64Func);
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}
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void mlir::populateGpuSubgroupReduceOpLoweringPattern(
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LLVMTypeConverter &converter, RewritePatternSet &patterns) {
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patterns.add<GPUSubgroupReduceOpLowering>(converter);
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}
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void mlir::populateGpuToNVVMConversionPatterns(LLVMTypeConverter &converter,
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RewritePatternSet &patterns) {
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populateWithGenerated(patterns);
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patterns.add<GPUPrintfOpToVPrintfLowering>(converter);
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patterns.add<
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GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, NVVM::ThreadIdXOp,
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NVVM::ThreadIdYOp, NVVM::ThreadIdZOp>,
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GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, NVVM::BlockDimXOp,
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NVVM::BlockDimYOp, NVVM::BlockDimZOp>,
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GPUIndexIntrinsicOpLowering<gpu::ClusterIdOp, NVVM::ClusterIdXOp,
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NVVM::ClusterIdYOp, NVVM::ClusterIdZOp>,
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GPUIndexIntrinsicOpLowering<gpu::ClusterDimOp, NVVM::ClusterDimXOp,
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NVVM::ClusterDimYOp, NVVM::ClusterDimZOp>,
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GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, NVVM::BlockIdXOp,
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NVVM::BlockIdYOp, NVVM::BlockIdZOp>,
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GPUIndexIntrinsicOpLowering<gpu::GridDimOp, NVVM::GridDimXOp,
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NVVM::GridDimYOp, NVVM::GridDimZOp>,
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GPULaneIdOpToNVVM, GPUShuffleOpLowering, GPUReturnOpLowering>(converter);
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patterns.add<GPUDynamicSharedMemoryOpLowering>(
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converter, NVVM::kSharedMemoryAlignmentBit);
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// Explicitly drop memory space when lowering private memory
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// attributions since NVVM models it as `alloca`s in the default
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// memory space and does not support `alloca`s with addrspace(5).
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patterns.add<GPUFuncOpLowering>(
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converter, /*allocaAddrSpace=*/0,
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/*workgroupAddrSpace=*/
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static_cast<unsigned>(NVVM::NVVMMemorySpace::kSharedMemorySpace),
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StringAttr::get(&converter.getContext(),
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NVVM::NVVMDialect::getKernelFuncAttrName()));
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populateOpPatterns<math::AbsFOp>(converter, patterns, "__nv_fabsf",
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"__nv_fabs");
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populateOpPatterns<math::AtanOp>(converter, patterns, "__nv_atanf",
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"__nv_atan");
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populateOpPatterns<math::Atan2Op>(converter, patterns, "__nv_atan2f",
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"__nv_atan2");
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populateOpPatterns<math::CbrtOp>(converter, patterns, "__nv_cbrtf",
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"__nv_cbrt");
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populateOpPatterns<math::CeilOp>(converter, patterns, "__nv_ceilf",
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"__nv_ceil");
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populateOpPatterns<math::CosOp>(converter, patterns, "__nv_cosf", "__nv_cos");
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populateOpPatterns<math::ExpOp>(converter, patterns, "__nv_expf", "__nv_exp");
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populateOpPatterns<math::Exp2Op>(converter, patterns, "__nv_exp2f",
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"__nv_exp2");
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populateOpPatterns<math::ExpM1Op>(converter, patterns, "__nv_expm1f",
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"__nv_expm1");
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populateOpPatterns<math::FloorOp>(converter, patterns, "__nv_floorf",
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"__nv_floor");
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populateOpPatterns<arith::RemFOp>(converter, patterns, "__nv_fmodf",
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"__nv_fmod");
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populateOpPatterns<math::LogOp>(converter, patterns, "__nv_logf", "__nv_log");
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populateOpPatterns<math::Log1pOp>(converter, patterns, "__nv_log1pf",
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"__nv_log1p");
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populateOpPatterns<math::Log10Op>(converter, patterns, "__nv_log10f",
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"__nv_log10");
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populateOpPatterns<math::Log2Op>(converter, patterns, "__nv_log2f",
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"__nv_log2");
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populateOpPatterns<math::PowFOp>(converter, patterns, "__nv_powf",
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"__nv_pow");
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populateOpPatterns<math::RsqrtOp>(converter, patterns, "__nv_rsqrtf",
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"__nv_rsqrt");
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populateOpPatterns<math::SinOp>(converter, patterns, "__nv_sinf", "__nv_sin");
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populateOpPatterns<math::SqrtOp>(converter, patterns, "__nv_sqrtf",
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"__nv_sqrt");
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populateOpPatterns<math::TanhOp>(converter, patterns, "__nv_tanhf",
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"__nv_tanh");
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populateOpPatterns<math::TanOp>(converter, patterns, "__nv_tanf", "__nv_tan");
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}
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