44bd807512
Make the stack alignment register (AP) reserved in the given function. This will make it available everywhere in the function, and allow aligned access to vector register spill slots.
91 lines
3.3 KiB
C++
91 lines
3.3 KiB
C++
//=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
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#include "llvm/CodeGen/MachineFunction.h"
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#include <map>
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namespace llvm {
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namespace Hexagon {
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const unsigned int StartPacket = 0x1;
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const unsigned int EndPacket = 0x2;
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} // end namespace Hexagon
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/// Hexagon target-specific information for each MachineFunction.
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class HexagonMachineFunctionInfo : public MachineFunctionInfo {
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// SRetReturnReg - Some subtargets require that sret lowering includes
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// returning the value of the returned struct in a register. This field
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// holds the virtual register into which the sret argument is passed.
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unsigned SRetReturnReg = 0;
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Register StackAlignBaseReg = 0; // Aligned-stack base register
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int VarArgsFrameIndex;
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int RegSavedAreaStartFrameIndex;
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int FirstNamedArgFrameIndex;
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int LastNamedArgFrameIndex;
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bool HasClobberLR = false;
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bool HasEHReturn = false;
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std::map<const MachineInstr*, unsigned> PacketInfo;
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virtual void anchor();
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public:
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HexagonMachineFunctionInfo() = default;
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HexagonMachineFunctionInfo(MachineFunction &MF) {}
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MachineFunctionInfo *
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clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
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const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
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const override;
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unsigned getSRetReturnReg() const { return SRetReturnReg; }
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void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
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void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
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int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
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void setRegSavedAreaStartFrameIndex(int v) { RegSavedAreaStartFrameIndex = v;}
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int getRegSavedAreaStartFrameIndex() { return RegSavedAreaStartFrameIndex; }
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void setFirstNamedArgFrameIndex(int v) { FirstNamedArgFrameIndex = v; }
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int getFirstNamedArgFrameIndex() { return FirstNamedArgFrameIndex; }
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void setLastNamedArgFrameIndex(int v) { LastNamedArgFrameIndex = v; }
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int getLastNamedArgFrameIndex() { return LastNamedArgFrameIndex; }
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void setStartPacket(MachineInstr* MI) {
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PacketInfo[MI] |= Hexagon::StartPacket;
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}
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void setEndPacket(MachineInstr* MI) {
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PacketInfo[MI] |= Hexagon::EndPacket;
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}
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bool isStartPacket(const MachineInstr* MI) const {
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return (PacketInfo.count(MI) &&
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(PacketInfo.find(MI)->second & Hexagon::StartPacket));
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}
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bool isEndPacket(const MachineInstr* MI) const {
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return (PacketInfo.count(MI) &&
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(PacketInfo.find(MI)->second & Hexagon::EndPacket));
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}
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void setHasClobberLR(bool v) { HasClobberLR = v; }
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bool hasClobberLR() const { return HasClobberLR; }
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bool hasEHReturn() const { return HasEHReturn; };
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void setHasEHReturn(bool H = true) { HasEHReturn = H; };
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void setStackAlignBaseReg(Register R) { StackAlignBaseReg = R; }
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Register getStackAlignBaseReg() const { return StackAlignBaseReg; }
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
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