cc5a1b3dd9
MIR support is totally unusable for AMDGPU without this, since the set of reserved registers is set from fields here. Add a clone method to MachineFunctionInfo. This is a subtle variant of the copy constructor that is required if there are any MIR constructs that use pointers. Specifically, at minimum fields that reference MachineBasicBlocks or the MachineFunction need to be adjusted to the values in the new function.
58 lines
2.1 KiB
C++
58 lines
2.1 KiB
C++
//===- LanaiMachineFuctionInfo.h - Lanai machine func info -------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares Lanai-specific per-machine-function information.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_LANAI_LANAIMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_LANAI_LANAIMACHINEFUNCTIONINFO_H
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#include "LanaiRegisterInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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namespace llvm {
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// LanaiMachineFunctionInfo - This class is derived from MachineFunction and
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// contains private Lanai target-specific information for each MachineFunction.
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class LanaiMachineFunctionInfo : public MachineFunctionInfo {
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virtual void anchor();
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// SRetReturnReg - Lanai ABI require that sret lowering includes
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// returning the value of the returned struct in a register. This field
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// holds the virtual register into which the sret argument is passed.
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Register SRetReturnReg;
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// GlobalBaseReg - keeps track of the virtual register initialized for
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// use as the global base register. This is used for PIC in some PIC
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// relocation models.
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Register GlobalBaseReg;
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// VarArgsFrameIndex - FrameIndex for start of varargs area.
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int VarArgsFrameIndex;
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public:
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explicit LanaiMachineFunctionInfo(MachineFunction &MF)
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: VarArgsFrameIndex(0) {}
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MachineFunctionInfo *
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clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
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const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
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const override;
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Register getSRetReturnReg() const { return SRetReturnReg; }
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void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; }
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int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
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void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_LANAI_LANAIMACHINEFUNCTIONINFO_H
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