454758ab69
Some PowerPC CPU may have slow MFLR instruction, so we need to schedule the MFLR and its store in function prologue away to hidden the long latency for slow MFLR instruction. This patch adds a new feature fastMFLR and the new feature will be used in https://reviews.llvm.org/D137423. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137612
461 lines
15 KiB
C++
461 lines
15 KiB
C++
//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
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#define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
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#include "PPCFrameLowering.h"
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#include "PPCISelLowering.h"
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#include "PPCInstrInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/RegisterBankInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "PPCGenSubtargetInfo.inc"
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// GCC #defines PPC on Linux but we use it as our namespace name
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#undef PPC
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namespace llvm {
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class StringRef;
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namespace PPC {
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// -m directive values.
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enum {
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DIR_NONE,
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DIR_32,
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DIR_440,
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DIR_601,
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DIR_602,
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DIR_603,
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DIR_7400,
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DIR_750,
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DIR_970,
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DIR_A2,
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DIR_E500,
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DIR_E500mc,
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DIR_E5500,
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DIR_PWR3,
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DIR_PWR4,
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DIR_PWR5,
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DIR_PWR5X,
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DIR_PWR6,
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DIR_PWR6X,
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DIR_PWR7,
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DIR_PWR8,
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DIR_PWR9,
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DIR_PWR10,
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DIR_PWR_FUTURE,
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DIR_64
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};
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}
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class GlobalValue;
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class PPCSubtarget : public PPCGenSubtargetInfo {
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public:
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enum POPCNTDKind {
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POPCNTD_Unavailable,
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POPCNTD_Slow,
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POPCNTD_Fast
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};
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protected:
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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Align StackAlignment;
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/// Selected instruction itineraries (one entry per itinerary class.)
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InstrItineraryData InstrItins;
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/// Which cpu directive was used.
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unsigned CPUDirective;
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/// Used by the ISel to turn in optimizations for POWER4-derived architectures
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bool HasMFOCRF;
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bool Has64BitSupport;
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bool Use64BitRegs;
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bool UseCRBits;
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bool HasHardFloat;
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bool IsPPC64;
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bool HasAltivec;
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bool HasFPU;
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bool HasSPE;
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bool HasEFPU2;
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bool HasVSX;
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bool NeedsTwoConstNR;
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bool HasP8Vector;
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bool HasP8Altivec;
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bool HasP8Crypto;
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bool HasP9Vector;
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bool HasP9Altivec;
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bool HasP10Vector;
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bool HasPrefixInstrs;
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bool HasPCRelativeMemops;
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bool HasMMA;
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bool HasROPProtect;
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bool HasPrivileged;
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bool HasFCPSGN;
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bool HasFSQRT;
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bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
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bool HasRecipPrec;
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bool HasSTFIWX;
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bool HasLFIWAX;
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bool HasFPRND;
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bool HasFPCVT;
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bool HasISEL;
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bool HasBPERMD;
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bool HasExtDiv;
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bool HasCMPB;
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bool HasLDBRX;
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bool IsBookE;
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bool HasOnlyMSYNC;
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bool IsE500;
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bool IsPPC4xx;
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bool IsPPC6xx;
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bool FeatureMFTB;
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bool AllowsUnalignedFPAccess;
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bool DeprecatedDST;
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bool IsLittleEndian;
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bool HasICBT;
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bool HasInvariantFunctionDescriptors;
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bool HasPartwordAtomics;
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bool HasQuadwordAtomics;
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bool HasDirectMove;
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bool HasHTM;
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bool HasFloat128;
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bool HasFusion;
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bool HasStoreFusion;
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bool HasAddiLoadFusion;
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bool HasAddisLoadFusion;
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bool HasArithAddFusion;
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bool HasAddLogicalFusion;
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bool HasLogicalAddFusion;
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bool HasLogicalFusion;
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bool HasSha3Fusion;
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bool HasCompareFusion;
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bool HasWideImmFusion;
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bool HasZeroMoveFusion;
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bool HasBack2BackFusion;
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bool IsISA2_06;
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bool IsISA2_07;
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bool IsISA3_0;
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bool IsISA3_1;
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bool IsISAFuture;
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bool UseLongCalls;
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bool SecurePlt;
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bool VectorsUseTwoUnits;
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bool UsePPCPreRASchedStrategy;
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bool UsePPCPostRASchedStrategy;
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bool PairedVectorMemops;
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bool PredictableSelectIsExpensive;
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bool HasFastMFLR;
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bool HasModernAIXAs;
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bool IsAIX;
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POPCNTDKind HasPOPCNTD;
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const PPCTargetMachine &TM;
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PPCFrameLowering FrameLowering;
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PPCInstrInfo InstrInfo;
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PPCTargetLowering TLInfo;
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SelectionDAGTargetInfo TSInfo;
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/// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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///
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PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
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const PPCTargetMachine &TM);
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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Align getStackAlignment() const { return StackAlignment; }
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/// getCPUDirective - Returns the -m directive specified for the cpu.
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///
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unsigned getCPUDirective() const { return CPUDirective; }
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/// getInstrItins - Return the instruction itineraries based on subtarget
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/// selection.
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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const PPCFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const PPCTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const PPCRegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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const PPCTargetMachine &getTargetMachine() const { return TM; }
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/// initializeSubtargetDependencies - Initializes using a CPU and feature string
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/// so that we can use initializer lists for subtarget initialization.
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PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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private:
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void initializeEnvironment();
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void initSubtargetFeatures(StringRef CPU, StringRef FS);
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public:
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/// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
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///
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bool isPPC64() const;
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/// has64BitSupport - Return true if the selected CPU supports 64-bit
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/// instructions, regardless of whether we are in 32-bit or 64-bit mode.
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bool has64BitSupport() const { return Has64BitSupport; }
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// useSoftFloat - Return true if soft-float option is turned on.
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bool useSoftFloat() const {
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if (isAIXABI() && !HasHardFloat)
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report_fatal_error("soft-float is not yet supported on AIX.");
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return !HasHardFloat;
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}
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/// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
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/// registers in 32-bit mode when possible. This can only true if
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/// has64BitSupport() returns true.
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bool use64BitRegs() const { return Use64BitRegs; }
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/// useCRBits - Return true if we should store and manipulate i1 values in
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/// the individual condition register bits.
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bool useCRBits() const { return UseCRBits; }
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// isLittleEndian - True if generating little-endian code
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bool isLittleEndian() const { return IsLittleEndian; }
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// Specific obvious features.
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bool hasFCPSGN() const { return HasFCPSGN; }
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bool hasFSQRT() const { return HasFSQRT; }
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bool hasFRE() const { return HasFRE; }
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bool hasFRES() const { return HasFRES; }
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bool hasFRSQRTE() const { return HasFRSQRTE; }
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bool hasFRSQRTES() const { return HasFRSQRTES; }
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bool hasRecipPrec() const { return HasRecipPrec; }
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bool hasSTFIWX() const { return HasSTFIWX; }
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bool hasLFIWAX() const { return HasLFIWAX; }
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bool hasFPRND() const { return HasFPRND; }
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bool hasFPCVT() const { return HasFPCVT; }
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bool hasAltivec() const { return HasAltivec; }
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bool hasSPE() const { return HasSPE; }
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bool hasEFPU2() const { return HasEFPU2; }
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bool hasFPU() const { return HasFPU; }
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bool hasVSX() const { return HasVSX; }
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bool needsTwoConstNR() const { return NeedsTwoConstNR; }
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bool hasP8Vector() const { return HasP8Vector; }
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bool hasP8Altivec() const { return HasP8Altivec; }
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bool hasP8Crypto() const { return HasP8Crypto; }
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bool hasP9Vector() const { return HasP9Vector; }
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bool hasP9Altivec() const { return HasP9Altivec; }
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bool hasP10Vector() const { return HasP10Vector; }
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bool hasPrefixInstrs() const { return HasPrefixInstrs; }
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bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
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bool hasMMA() const { return HasMMA; }
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bool hasROPProtect() const { return HasROPProtect; }
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bool hasPrivileged() const { return HasPrivileged; }
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bool pairedVectorMemops() const { return PairedVectorMemops; }
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bool hasMFOCRF() const { return HasMFOCRF; }
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bool hasISEL() const { return HasISEL; }
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bool hasBPERMD() const { return HasBPERMD; }
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bool hasExtDiv() const { return HasExtDiv; }
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bool hasCMPB() const { return HasCMPB; }
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bool hasLDBRX() const { return HasLDBRX; }
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bool isBookE() const { return IsBookE; }
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bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
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bool isPPC4xx() const { return IsPPC4xx; }
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bool isPPC6xx() const { return IsPPC6xx; }
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bool isSecurePlt() const {return SecurePlt; }
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bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
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bool isE500() const { return IsE500; }
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bool isFeatureMFTB() const { return FeatureMFTB; }
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bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
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bool isDeprecatedDST() const { return DeprecatedDST; }
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bool hasICBT() const { return HasICBT; }
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bool hasInvariantFunctionDescriptors() const {
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return HasInvariantFunctionDescriptors;
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}
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bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
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bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
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bool hasPartwordAtomics() const { return HasPartwordAtomics; }
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bool hasQuadwordAtomics() const { return HasQuadwordAtomics; }
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bool hasDirectMove() const { return HasDirectMove; }
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bool hasFastMFLR() const { return HasFastMFLR; }
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Align getPlatformStackAlignment() const {
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return Align(16);
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}
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unsigned getRedZoneSize() const {
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if (isPPC64())
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// 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
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return 288;
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// AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
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// PPC32 SVR4ABI has no redzone.
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return isAIXABI() ? 220 : 0;
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}
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bool hasHTM() const { return HasHTM; }
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bool hasFloat128() const { return HasFloat128; }
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bool isISA2_06() const { return IsISA2_06; }
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bool isISA2_07() const { return IsISA2_07; }
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bool isISA3_0() const { return IsISA3_0; }
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bool isISA3_1() const { return IsISA3_1; }
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bool isISAFuture() const { return IsISAFuture; }
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bool useLongCalls() const { return UseLongCalls; }
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bool hasFusion() const { return HasFusion; }
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bool hasStoreFusion() const { return HasStoreFusion; }
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bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
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bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
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bool hasArithAddFusion() const { return HasArithAddFusion; }
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bool hasAddLogicalFusion() const { return HasAddLogicalFusion; }
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bool hasLogicalAddFusion() const { return HasLogicalAddFusion; }
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bool hasLogicalFusion() const { return HasLogicalFusion; }
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bool hasCompareFusion() const { return HasCompareFusion; }
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bool hasWideImmFusion() const { return HasWideImmFusion; }
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bool hasSha3Fusion() const { return HasSha3Fusion; }
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bool hasZeroMoveFusion() const { return HasZeroMoveFusion; }
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bool hasBack2BackFusion() const { return HasBack2BackFusion; }
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bool needsSwapsForVSXMemOps() const {
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return hasVSX() && isLittleEndian() && !hasP9Vector();
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}
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POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isAIXABI() const { return TargetTriple.isOSAIX(); }
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bool isSVR4ABI() const { return !isAIXABI(); }
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bool isELFv2ABI() const;
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bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
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bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
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bool isUsingPCRelativeCalls() const;
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/// Originally, this function return hasISEL(). Now we always enable it,
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/// but may expand the ISEL instruction later.
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bool enableEarlyIfConversion() const override { return true; }
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/// Scheduling customization.
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bool enableMachineScheduler() const override;
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/// Pipeliner customization.
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bool enableMachinePipeliner() const override;
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/// Machine Pipeliner customization
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bool useDFAforSMS() const override;
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/// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
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bool enablePostRAScheduler() const override;
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AntiDepBreakMode getAntiDepBreakMode() const override;
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void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
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void overrideSchedPolicy(MachineSchedPolicy &Policy,
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unsigned NumRegionInstrs) const override;
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bool useAA() const override;
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bool enableSubRegLiveness() const override;
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/// True if the GV will be accessed via an indirect symbol.
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bool isGVIndirectSymbol(const GlobalValue *GV) const;
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/// True if the ABI is descriptor based.
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bool usesFunctionDescriptors() const {
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// Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
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// v1 ABI uses descriptors.
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return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
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}
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unsigned descriptorTOCAnchorOffset() const {
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assert(usesFunctionDescriptors() &&
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"Should only be called when the target uses descriptors.");
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return IsPPC64 ? 8 : 4;
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}
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unsigned descriptorEnvironmentPointerOffset() const {
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assert(usesFunctionDescriptors() &&
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"Should only be called when the target uses descriptors.");
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return IsPPC64 ? 16 : 8;
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}
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MCRegister getEnvironmentPointerRegister() const {
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assert(usesFunctionDescriptors() &&
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"Should only be called when the target uses descriptors.");
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return IsPPC64 ? PPC::X11 : PPC::R11;
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}
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MCRegister getTOCPointerRegister() const {
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assert((is64BitELFABI() || isAIXABI()) &&
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"Should only be called when the target is a TOC based ABI.");
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return IsPPC64 ? PPC::X2 : PPC::R2;
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}
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MCRegister getStackPointerRegister() const {
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return IsPPC64 ? PPC::X1 : PPC::R1;
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}
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bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
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bool isPredictableSelectIsExpensive() const {
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return PredictableSelectIsExpensive;
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}
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// Select allocation orders of GPRC and G8RC. It should be strictly consistent
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// with corresponding AltOrders in PPCRegisterInfo.td.
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unsigned getGPRAllocationOrderIdx() const {
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if (is64BitELFABI())
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return 1;
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if (isAIXABI())
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return 2;
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return 0;
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}
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// GlobalISEL
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const CallLowering *getCallLowering() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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InstructionSelector *getInstructionSelector() const override;
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};
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} // End llvm namespace
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#endif
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