6c85668d28
arm64_32 guarantees the high 32 bits of pointer parameters are passed as 0, and this is modelled in the IR by inserting an AssertZExt after the CopyFromReg. The function deciding whether registers that need to be preserved actually are wasn't expecting this so it banned perfectly legitimate tail calls.
96 lines
3.4 KiB
LLVM
96 lines
3.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios -o - %s | FileCheck --check-prefix=CHECK --check-prefix=OPT --check-prefix=OPTAARCH64 %s
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; RUN: llc -O0 -fast-isel -verify-machineinstrs -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck --check-prefix=CHECK --check-prefix=OPT --check-prefix=OPTAARCH64 %s
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; RUN: llc -verify-machineinstrs -mtriple=arm64_32-apple-ios -o - %s | FileCheck --check-prefix=CHECK --check-prefix=OPT --check-prefix=OPTARM64_32 %s
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; Parameter with swiftself should be allocated to x20.
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; CHECK-LABEL: swiftself_param:
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; CHECK: mov x0, x20
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; CHECK-NEXT: ret
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define i8* @swiftself_param(i8* swiftself %addr0) {
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ret i8 *%addr0
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}
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; Check that x20 is used to pass a swiftself argument.
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; CHECK-LABEL: call_swiftself:
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; CHECK: mov x20, x0
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; CHECK: bl {{_?}}swiftself_param
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; CHECK: ret
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define i8 *@call_swiftself(i8* %arg) {
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%res = call i8 *@swiftself_param(i8* swiftself %arg)
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ret i8 *%res
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}
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; x20 should be saved by the callee even if used for swiftself
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; CHECK-LABEL: swiftself_clobber:
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; CHECK: {{stp|str}} {{.*}}x20{{.*}}sp
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; ...
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; CHECK: {{ldp|ldr}} {{.*}}x20{{.*}}sp
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; CHECK: ret
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define i8 *@swiftself_clobber(i8* swiftself %addr0) {
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call void asm sideeffect "", "~{x20}"()
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ret i8 *%addr0
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}
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; Demonstrate that we do not need any movs when calling multiple functions
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; with swiftself argument.
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; CHECK-LABEL: swiftself_passthrough:
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; OPT-NOT: mov{{.*}}x20
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; OPT: bl {{_?}}swiftself_param
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; OPT-NOT: mov{{.*}}x20
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; OPT-NEXT: bl {{_?}}swiftself_param
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; OPT: ret
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define void @swiftself_passthrough(i8* swiftself %addr0) {
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call i8 *@swiftself_param(i8* swiftself %addr0)
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call i8 *@swiftself_param(i8* swiftself %addr0)
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ret void
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}
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; We can use a tail call if the callee swiftself is the same as the caller one.
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; This should also work with fast-isel.
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; CHECK-LABEL: swiftself_tail:
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; OPTAARCH64: b {{_?}}swiftself_param
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; OPTAARCH64-NOT: ret
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; OPTARM64_32: b {{_?}}swiftself_param
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define i8* @swiftself_tail(i8* swiftself %addr0) {
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call void asm sideeffect "", "~{x20}"()
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%res = musttail call i8* @swiftself_param(i8* swiftself %addr0)
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ret i8* %res
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}
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; We can not use a tail call if the callee swiftself is not the same as the
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; caller one.
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; CHECK-LABEL: swiftself_notail:
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; CHECK: mov x20, x0
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; CHECK: bl {{_?}}swiftself_param
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; CHECK: ret
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define i8* @swiftself_notail(i8* swiftself %addr0, i8* %addr1) nounwind {
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%res = tail call i8* @swiftself_param(i8* swiftself %addr1)
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ret i8* %res
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}
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; We cannot pretend that 'x0' is alive across the thisreturn_attribute call as
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; we normally would. We marked the first parameter with swiftself which means it
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; will no longer be passed in x0.
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declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself)
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; OPTAARCH64-LABEL: swiftself_nothisreturn:
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; OPTAARCH64-DAG: ldr x20, [x20]
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; OPTAARCH64-DAG: mov [[CSREG:x[1-9].*]], x8
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; OPTAARCH64: bl {{_?}}thisreturn_attribute
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; OPTAARCH64: str x0, [[[CSREG]]
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; OPTAARCH64: ret
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; OPTARM64_32-LABEL: swiftself_nothisreturn:
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; OPTARM64_32-DAG: ldr w20, [x20]
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; OPTARM64_32-DAG: mov [[CSREG:x[1-9].*]], x8
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; OPTARM64_32: bl {{_?}}thisreturn_attribute
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; OPTARM64_32: str w0, [[[CSREG]]
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; OPTARM64_32: ret
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define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8*), i8** noalias nocapture readonly swiftself) {
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entry:
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%2 = load i8*, i8** %1, align 8
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%3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2)
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store i8* %3, i8** %0, align 8
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ret void
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}
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