fbdea5a2e9
This patch contains changes necessary to carry physical condition register (SCC) dependencies through the SDNode scheduler. It adds the edge in the SDNodeScheduler dependency graph instead of inserting the SCC copy between each definition and use. This approach lets the scheduler place instructions in an optimal way placing the copy only when the dependency cannot be resolved. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D133593
311 lines
12 KiB
LLVM
311 lines
12 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; GCN-LABEL: {{^}}select_and1:
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; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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; GCN-NOT: v_and_b32
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; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @select_and1(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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%c = icmp slt i32 %x, 11
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%s = select i1 %c, i32 0, i32 -1
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%a = and i32 %y, %s
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store i32 %a, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}select_and2:
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; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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; GCN-NOT: v_and_b32
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; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @select_and2(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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%c = icmp slt i32 %x, 11
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%s = select i1 %c, i32 0, i32 -1
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%a = and i32 %s, %y
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store i32 %a, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}select_and3:
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; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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; GCN-NOT: v_and_b32
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; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @select_and3(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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%c = icmp slt i32 %x, 11
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%s = select i1 %c, i32 -1, i32 0
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%a = and i32 %y, %s
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store i32 %a, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}select_and_v4:
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; GCN: s_cselect_b32 s[[SEL0:[0-9]+]], s{{[0-9]+}}, 0
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; GCN: s_cselect_b32 s[[SEL1:[0-9]+]], s{{[0-9]+}}, 0
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; GCN: s_cselect_b32 s[[SEL2:[0-9]+]], s{{[0-9]+}}, 0
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; GCN: s_cselect_b32 s[[SEL3:[0-9]+]], s{{[0-9]+}}, 0
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; GCN: v_mov_b32_e32 v[[V0:[0-9]+]], s[[SEL3]]
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; GCN: v_mov_b32_e32 v[[V1:[0-9]+]], s[[SEL2]]
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; GCN: v_mov_b32_e32 v[[V2:[0-9]+]], s[[SEL1]]
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; GCN: v_mov_b32_e32 v[[V3:[0-9]+]], s[[SEL0]]
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; GCN-NOT: v_and_b32
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; GCN: global_store_dwordx4 v{{[0-9]+}}, v[[[V0]]:[[V3]]]
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define amdgpu_kernel void @select_and_v4(<4 x i32> addrspace(1)* %p, i32 %x, <4 x i32> %y) {
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%c = icmp slt i32 %x, 11
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%s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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%a = and <4 x i32> %s, %y
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store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32
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ret void
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}
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; GCN-LABEL: {{^}}select_or1:
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; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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; GCN-NOT: v_or_b32
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; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @select_or1(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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%c = icmp slt i32 %x, 11
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%s = select i1 %c, i32 0, i32 -1
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%a = or i32 %y, %s
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store i32 %a, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}select_or2:
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; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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; GCN-NOT: v_or_b32
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; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @select_or2(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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%c = icmp slt i32 %x, 11
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%s = select i1 %c, i32 0, i32 -1
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%a = or i32 %s, %y
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store i32 %a, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}select_or3:
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; GCN: s_cselect_b32 [[SEL:s[0-9]+]], s{{[0-9]+}},
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; GCN: v_mov_b32_e32 [[VSEL:v[0-9]+]], [[SEL]]
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; GCN-NOT: v_or_b32
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; GCN: store_dword v{{[0-9]+}}, [[VSEL]], s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @select_or3(i32 addrspace(1)* %p, i32 %x, i32 %y) {
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%c = icmp slt i32 %x, 11
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%s = select i1 %c, i32 -1, i32 0
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%a = or i32 %y, %s
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store i32 %a, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}select_or_v4:
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; GCN: s_cselect_b32 s[[SEL0:[0-9]+]], s{{[0-9]+}}, -1
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; GCN: s_cselect_b32 s[[SEL1:[0-9]+]], s{{[0-9]+}}, -1
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; GCN: s_cselect_b32 s[[SEL2:[0-9]+]], s{{[0-9]+}}, -1
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; GCN: s_cselect_b32 s[[SEL3:[0-9]+]], s{{[0-9]+}}, -1
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; GCN-NOT: v_or_b32
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; GCN: v_mov_b32_e32 v[[V0:[0-9]+]], s[[SEL3]]
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; GCN: v_mov_b32_e32 v[[V1:[0-9]+]], s[[SEL2]]
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; GCN: v_mov_b32_e32 v[[V2:[0-9]+]], s[[SEL1]]
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; GCN: v_mov_b32_e32 v[[V3:[0-9]+]], s[[SEL0]]
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; GCN: global_store_dwordx4 v{{[0-9]+}}, v[[[V0]]:[[V3]]]
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define amdgpu_kernel void @select_or_v4(<4 x i32> addrspace(1)* %p, i32 %x, <4 x i32> %y) {
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%c = icmp slt i32 %x, 11
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%s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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%a = or <4 x i32> %s, %y
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store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32
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ret void
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}
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; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 9, 2
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define amdgpu_kernel void @sel_constants_sub_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i32 -4, i32 3
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%bo = sub i32 5, %sel
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store i32 %bo, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_i16:
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9,
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define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16(i16 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i16 -4, i16 3
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%bo = sub i16 5, %sel
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store i16 %bo, i16 addrspace(1)* %p, align 2
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ret void
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}
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; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_i16_neg:
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; GCN: v_mov_b32_e32 [[F:v[0-9]+]], 0xfffff449
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, [[F]], -3,
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define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16_neg(i16 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i16 4, i16 3000
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%bo = sub i16 1, %sel
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store i16 %bo, i16 addrspace(1)* %p, align 2
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ret void
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}
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; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_v2i16:
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; GCN-DAG: s_mov_b32 [[T:s[0-9]+]], 0x50009
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; GCN: s_cselect_b32 s{{[0-9]+}}, [[T]], 0x60002
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define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v2i16(<2 x i16> addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, <2 x i16> <i16 -4, i16 2>, <2 x i16> <i16 3, i16 1>
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%bo = sub <2 x i16> <i16 5, i16 7>, %sel
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store <2 x i16> %bo, <2 x i16> addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_v4i32:
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; GCN: s_cselect_b32 s[[SEL0:[0-9]+]], 7, 14
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; GCN: s_cselect_b32 s[[SEL1:[0-9]+]], 6, 10
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; GCN: s_cselect_b32 s[[SEL2:[0-9]+]], 5, 6
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; GCN: s_cselect_b32 s[[SEL3:[0-9]+]], 9, 2
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; GCN: v_mov_b32_e32 v[[V0:[0-9]+]], s[[SEL3]]
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; GCN: v_mov_b32_e32 v[[V1:[0-9]+]], s[[SEL2]]
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; GCN: v_mov_b32_e32 v[[V2:[0-9]+]], s[[SEL1]]
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; GCN: v_mov_b32_e32 v[[V3:[0-9]+]], s[[SEL0]]
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; GCN: global_store_dwordx4 v{{[0-9]+}}, v[[[V0]]:[[V3]]]
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define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v4i32(<4 x i32> addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, <4 x i32> <i32 -4, i32 2, i32 3, i32 4>, <4 x i32> <i32 3, i32 1, i32 -1, i32 -3>
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%bo = sub <4 x i32> <i32 5, i32 7, i32 9, i32 11>, %sel
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store <4 x i32> %bo, <4 x i32> addrspace(1)* %p, align 32
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ret void
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}
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; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i64:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 0, 5
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define amdgpu_kernel void @sdiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i64 121, i64 23
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%bo = sdiv i64 120, %sel
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store i64 %bo, i64 addrspace(1)* %p, align 8
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ret void
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}
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; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i32:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 26, 8
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define amdgpu_kernel void @sdiv_constant_sel_constants_i32(i32 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i32 7, i32 23
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%bo = sdiv i32 184, %sel
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store i32 %bo, i32 addrspace(1)* %p, align 8
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ret void
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}
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; GCN-LABEL: {{^}}udiv_constant_sel_constants_i64:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 0, 5
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define amdgpu_kernel void @udiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i64 -4, i64 23
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%bo = udiv i64 120, %sel
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store i64 %bo, i64 addrspace(1)* %p, align 8
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ret void
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}
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; GCN-LABEL: {{^}}srem_constant_sel_constants:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 33, 3
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define amdgpu_kernel void @srem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i64 34, i64 15
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%bo = srem i64 33, %sel
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store i64 %bo, i64 addrspace(1)* %p, align 8
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ret void
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}
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; GCN-LABEL: {{^}}urem_constant_sel_constants:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 33, 3
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define amdgpu_kernel void @urem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i64 34, i64 15
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%bo = urem i64 33, %sel
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store i64 %bo, i64 addrspace(1)* %p, align 8
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ret void
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}
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; GCN-LABEL: {{^}}shl_constant_sel_constants:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 4, 8
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define amdgpu_kernel void @shl_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i32 2, i32 3
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%bo = shl i32 1, %sel
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store i32 %bo, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}lshr_constant_sel_constants:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 16, 8
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define amdgpu_kernel void @lshr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i32 2, i32 3
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%bo = lshr i32 64, %sel
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store i32 %bo, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}ashr_constant_sel_constants:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 32, 16
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define amdgpu_kernel void @ashr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, i32 2, i32 3
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%bo = ashr i32 128, %sel
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store i32 %bo, i32 addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}fsub_constant_sel_constants:
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, -4.0, 1.0,
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define amdgpu_kernel void @fsub_constant_sel_constants(float addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, float -2.0, float 3.0
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%bo = fsub float -1.0, %sel
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store float %bo, float addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}fsub_constant_sel_constants_f16:
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; TODO: it shall be possible to fold constants with OpSel
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; GCN-DAG: v_mov_b32_e32 [[T:v[0-9]+]], 0x3c00
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; GCN-DAG: v_mov_b32_e32 [[F:v[0-9]+]], 0xc400
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, [[F]], [[T]],
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define amdgpu_kernel void @fsub_constant_sel_constants_f16(half addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, half -2.0, half 3.0
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%bo = fsub half -1.0, %sel
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store half %bo, half addrspace(1)* %p, align 2
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ret void
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}
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; GCN-LABEL: {{^}}fsub_constant_sel_constants_v2f16:
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; GCN: s_cselect_b32 s{{[0-9]+}}, 0x45003c00, -2.0
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define amdgpu_kernel void @fsub_constant_sel_constants_v2f16(<2 x half> addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, <2 x half> <half -2.0, half -3.0>, <2 x half> <half -1.0, half 4.0>
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%bo = fsub <2 x half> <half -1.0, half 2.0>, %sel
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store <2 x half> %bo, <2 x half> addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}fsub_constant_sel_constants_v4f32:
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; GCN: s_mov_b32 [[T0:s[0-9]+]], 0x41500000
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; GCN: s_cselect_b32 s[[SEL0:[0-9]+]], [[T0]], 0x40c00000
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; GCN: s_cselect_b32 s[[SEL1:[0-9]+]], 0x41100000, 4.0
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; GCN: s_cselect_b32 s[[SEL2:[0-9]+]], 0x40a00000, 2.0
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; GCN: s_cselect_b32 s[[SEL3:[0-9]+]], 1.0, 0
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; GCN: v_mov_b32_e32 v[[V0:[0-9]+]], s[[SEL3]]
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; GCN: v_mov_b32_e32 v[[V1:[0-9]+]], s[[SEL2]]
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; GCN: v_mov_b32_e32 v[[V2:[0-9]+]], s[[SEL1]]
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; GCN: v_mov_b32_e32 v[[V3:[0-9]+]], s[[SEL0]]
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; GCN: global_store_dwordx4 v{{[0-9]+}}, v[[[V0]]:[[V3]]]
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define amdgpu_kernel void @fsub_constant_sel_constants_v4f32(<4 x float> addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, <4 x float> <float -2.0, float -3.0, float -4.0, float -5.0>, <4 x float> <float -1.0, float 0.0, float 1.0, float 2.0>
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%bo = fsub <4 x float> <float -1.0, float 2.0, float 5.0, float 8.0>, %sel
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store <4 x float> %bo, <4 x float> addrspace(1)* %p, align 32
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ret void
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}
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; GCN-LABEL: {{^}}fdiv_constant_sel_constants:
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 4.0, -2.0,
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define amdgpu_kernel void @fdiv_constant_sel_constants(float addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, float -4.0, float 2.0
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%bo = fdiv float 8.0, %sel
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store float %bo, float addrspace(1)* %p, align 4
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ret void
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}
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; GCN-LABEL: {{^}}frem_constant_sel_constants:
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0,
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define amdgpu_kernel void @frem_constant_sel_constants(float addrspace(1)* %p, i1 %cond) {
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%sel = select i1 %cond, float -4.0, float 3.0
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%bo = frem float 5.0, %sel
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store float %bo, float addrspace(1)* %p, align 4
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ret void
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}
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