d77ae7f251
Renames the current lowering scheme to "module" and introduces two new ones, "kernel" and "table", plus a "hybrid" that chooses between those three on a per-variable basis. Unit tests are set up to pass with the default lowering of "module" or "hybrid" with this patch defaulting to "module", which will be a less dramatic codegen change relative to the current. This reflects the sparsity of test coverage for the table lowering method. Hybrid is better than module in every respect and will be default in a subsequent patch. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D139433
87 lines
3.9 KiB
LLVM
87 lines
3.9 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=HSA %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-flat-for-global --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=HSA-CI %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=HSA %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=HSA-VI %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj --amdhsa-code-object-version=2 --amdgpu-lower-module-lds-strategy=module | llvm-readobj -S --sd --syms - | FileCheck --check-prefix=ELF %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 --amdgpu-lower-module-lds-strategy=module | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck %s --check-prefix=ELF
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
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; The SHT_NOTE section contains the output from the .hsa_code_object_*
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; directives.
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; ELF: Section {
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; ELF: Name: .text
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; ELF: Type: SHT_PROGBITS (0x1)
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; ELF: Flags [ (0x6)
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; ELF: SHF_ALLOC (0x2)
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; ELF: SHF_EXECINSTR (0x4)
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; ELF: }
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; ELF: SHT_NOTE
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; ELF: Flags [ (0x2)
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; ELF: SHF_ALLOC (0x2)
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; ELF: ]
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; ELF: SectionData (
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; ELF: 0000: 04000000 08000000 01000000 414D4400
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; ELF: 0010: 02000000 01000000 04000000 1B000000
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; ELF: 0020: 03000000 414D4400 04000700 07000000
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; ELF: 0030: 00000000 00000000 414D4400 414D4447
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; ELF: 0040: 50550000
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; ELF: )
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; ELF: Symbol {
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; ELF: Name: simple
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; ELF: Size: 288
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; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
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; ELF: }
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; HSA-NOT: .AMDGPU.config
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; HSA: .text
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; HSA: .hsa_code_object_version 2,1
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; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
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; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
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; HSA-LABEL: .amdgpu_hsa_kernel simple
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; HSA: {{^}}simple:
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; HSA: .amd_kernel_code_t
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; PRE-GFX10: enable_wavefront_size32 = 0
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; GFX10-W32: .amdhsa_wavefront_size32 1
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; GFX10-W64: .amdhsa_wavefront_size32 0
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; PRE-GFX10: wavefront_size = 6
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; HSA: call_convention = -1
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; HSA: .end_amd_kernel_code_t
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; HSA: s_load_{{dwordx2|b64}} s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
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; Make sure we are setting the ATC bit:
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; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
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; On VI+ we also need to set MTYPE = 2
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; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
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; Make sure we generate flat store for HSA
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; PRE-GFX10: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
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; GFX10: global_store_{{dword|b32}} v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off
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; HSA: .Lfunc_end0:
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; HSA: .size simple, .Lfunc_end0-simple
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define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; HSA-LABEL: .amdgpu_hsa_kernel simple_no_kernargs
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; HSA: enable_sgpr_kernarg_segment_ptr = 0
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define amdgpu_kernel void @simple_no_kernargs() {
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entry:
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store volatile i32 0, i32 addrspace(1)* undef
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ret void
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}
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