b982ba2a6e
Due to the encoding changes in GFX11, we had a hack in place that
disables the use of VGPRs above 128. This patch removes the need for
that hack.
We introduce a new register class VGPR_32_Lo128 which is used for 16-bit
operands of VOP1, VOP2, and VOPC instructions. This register class only has the
low 128 VGPRs, but is otherwise identical to VGPR_32. Therefore, 16-bit VOP1,
VOP2, and VOPC instructions are correctly limited to use the first 128
VGPRs, while the other instructions can freely use all 256.
We introduce new pseduo-instructions used on GFX11 which have the suffix
t16 (True 16) to use the VGPR_32_Lo128 register class.
Reviewed By: foad, rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D133723
61 lines
3.2 KiB
LLVM
61 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stop-after=finalize-isel -o - %s | FileCheck -check-prefix=GFX908 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stop-after=finalize-isel -o - %s | FileCheck -check-prefix=GFX90A %s
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; Make sure we only use one 128-bit register instead of 2 for i128 asm
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; constraints
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define amdgpu_kernel void @s_input_output_i128() {
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; GFX908-LABEL: name: s_input_output_i128
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; GFX908: bb.0 (%ir-block.0):
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; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6881290 /* regdef:SGPR_128 */, def %4
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; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %4
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; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6881289 /* reguse:SGPR_128 */, [[COPY]]
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; GFX908-NEXT: S_ENDPGM 0
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; GFX90A-LABEL: name: s_input_output_i128
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; GFX90A: bb.0 (%ir-block.0):
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; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6881290 /* regdef:SGPR_128 */, def %4
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; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %4
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; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6881289 /* reguse:SGPR_128 */, [[COPY]]
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; GFX90A-NEXT: S_ENDPGM 0
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%val = tail call i128 asm sideeffect "; def $0", "=s"()
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call void asm sideeffect "; use $0", "s"(i128 %val)
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ret void
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}
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define amdgpu_kernel void @v_input_output_i128() {
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; GFX908-LABEL: name: v_input_output_i128
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; GFX908: bb.0 (%ir-block.0):
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; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 5832714 /* regdef:VReg_128 */, def %4
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; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY %4
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; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 5832713 /* reguse:VReg_128 */, [[COPY]]
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; GFX908-NEXT: S_ENDPGM 0
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; GFX90A-LABEL: name: v_input_output_i128
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; GFX90A: bb.0 (%ir-block.0):
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; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6160394 /* regdef:VReg_128_Align2 */, def %4
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; GFX90A-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY %4
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; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6160393 /* reguse:VReg_128_Align2 */, [[COPY]]
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; GFX90A-NEXT: S_ENDPGM 0
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%val = tail call i128 asm sideeffect "; def $0", "=v"()
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call void asm sideeffect "; use $0", "v"(i128 %val)
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ret void
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}
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define amdgpu_kernel void @a_input_output_i128() {
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; GFX908-LABEL: name: a_input_output_i128
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; GFX908: bb.0 (%ir-block.0):
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; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 5767178 /* regdef:AReg_128 */, def %4
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; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY %4
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; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 5767177 /* reguse:AReg_128 */, [[COPY]]
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; GFX908-NEXT: S_ENDPGM 0
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; GFX90A-LABEL: name: a_input_output_i128
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; GFX90A: bb.0 (%ir-block.0):
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; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6029322 /* regdef:AReg_128_Align2 */, def %4
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; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY %4
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; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6029321 /* reguse:AReg_128_Align2 */, [[COPY]]
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; GFX90A-NEXT: S_ENDPGM 0
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%val = call i128 asm sideeffect "; def $0", "=a"()
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call void asm sideeffect "; use $0", "a"(i128 %val)
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ret void
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}
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