d77ae7f251
Renames the current lowering scheme to "module" and introduces two new ones, "kernel" and "table", plus a "hybrid" that chooses between those three on a per-variable basis. Unit tests are set up to pass with the default lowering of "module" or "hybrid" with this patch defaulting to "module", which will be a less dramatic codegen change relative to the current. This reflects the sparsity of test coverage for the table lowering method. Hybrid is better than module in every respect and will be default in a subsequent patch. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D139433
53 lines
3.0 KiB
LLVM
53 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -check-prefix=OPT %s
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; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -check-prefix=GCN %s
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; Check that module LDS is allocated at address 0 and kernel starts its
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; allocation past module LDS when a call is present.
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@lds.size.1.align.1 = internal unnamed_addr addrspace(3) global [1 x i8] undef, align 1
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@lds.size.16.align.16 = internal unnamed_addr addrspace(3) global [16 x i8] undef, align 16
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; GCN-LABEL: {{^}}k0:
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; GCN-DAG: v_mov_b32_e32 [[NULL:v[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
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; GCN: ds_write_b8 [[NULL]], [[ONE]]
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; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
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; GCN: ds_write_b8 [[NULL]], [[TWO]] offset:16
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define amdgpu_kernel void @k0() {
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; OPT-LABEL: @k0(
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; OPT-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_MODULE_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.module.lds) ]
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; OPT-NEXT: [[LDS_SIZE_1_ALIGN_1_BC:%.*]] = bitcast [1 x i8] addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0) to i8 addrspace(3)*
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; OPT-NEXT: store i8 1, i8 addrspace(3)* [[LDS_SIZE_1_ALIGN_1_BC]], align 1
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; OPT-NEXT: [[LDS_SIZE_16_ALIGN_16_BC:%.*]] = bitcast [16 x i8] addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_LDS_T:%.*]], [[LLVM_AMDGCN_KERNEL_K0_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0.lds, i32 0, i32 0) to i8 addrspace(3)*
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; OPT-NEXT: store i8 2, i8 addrspace(3)* [[LDS_SIZE_16_ALIGN_16_BC]], align 16
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; OPT-NEXT: call void @f0()
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; OPT-NEXT: ret void
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;
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%lds.size.1.align.1.bc = bitcast [1 x i8] addrspace(3)* @lds.size.1.align.1 to i8 addrspace(3)*
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store i8 1, i8 addrspace(3)* %lds.size.1.align.1.bc, align 1
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%lds.size.16.align.16.bc = bitcast [16 x i8] addrspace(3)* @lds.size.16.align.16 to i8 addrspace(3)*
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store i8 2, i8 addrspace(3)* %lds.size.16.align.16.bc, align 16
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call void @f0()
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ret void
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}
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; GCN-LABEL: {{^}}f0:
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; GCN-DAG: v_mov_b32_e32 [[NULL:v[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[TREE:v[0-9]+]], 3
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; GCN: ds_write_b8 [[NULL]], [[TREE]]
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define void @f0() {
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; OPT-LABEL: @f0() {
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; OPT-NEXT: [[LDS_SIZE_1_ALIGN_1_BC:%.*]] = bitcast [1 x i8] addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T:%.*]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0) to i8 addrspace(3)*
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; OPT-NEXT: store i8 3, i8 addrspace(3)* [[LDS_SIZE_1_ALIGN_1_BC]], align 1
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; OPT-NEXT: ret void
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;
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%lds.size.1.align.1.bc = bitcast [1 x i8] addrspace(3)* @lds.size.1.align.1 to i8 addrspace(3)*
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store i8 3, i8 addrspace(3)* %lds.size.1.align.1.bc, align 1
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ret void
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}
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attributes #0 = { "amdgpu-elide-module-lds" }
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; CHECK: attributes #0 = { "amdgpu-elide-module-lds" }
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