5ecd363295
This reverts commit 122efef8ee.
- Patch fixed to not reuse definitions from predecessors in EH landing pads.
- Late review suggestions (by MaskRay) have been addressed.
- M68k/pipeline.ll test updated.
- Init captures added in processBlock() to avoid capturing structured bindings.
- RISCV has this disabled for now.
Original commit message:
A new pass MachineLateInstrsCleanup is added to be run after PEI.
This is a simple pass that removes redundant and identical instructions
whenever found by scanning the MF once while keeping track of register
definitions in a map. These instructions are typically immediate loads
resulting from rematerialization, and address loads emitted by target in
eliminateFrameInde().
This is enabled by default, but a target could easily disable it by means of
'disablePass(&MachineLateInstrsCleanupID);'.
This late cleanup is naturally not "optimal" in removing instructions as it
is done by looking at phys-regs, but still quite effective. It would be
desirable to improve other parts of CodeGen and avoid these redundant
instructions in the first place, but there are no ideas for this yet.
Differential Revision: https://reviews.llvm.org/D123394
Reviewed By: RKSimon, foad, craig.topper, arsenm, asb
253 lines
11 KiB
LLVM
253 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Ensure two if.break calls, for both the inner and outer loops
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; FIXME: duplicate comparison
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define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) {
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; OPT-LABEL: @multi_else_break(
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; OPT-NEXT: main_body:
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; OPT-NEXT: br label [[LOOP_OUTER:%.*]]
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; OPT: LOOP.outer:
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; OPT-NEXT: [[PHI_BROKEN2:%.*]] = phi i64 [ [[TMP8:%.*]], [[FLOW1:%.*]] ], [ 0, [[MAIN_BODY:%.*]] ]
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; OPT-NEXT: [[TMP43:%.*]] = phi i32 [ 0, [[MAIN_BODY]] ], [ [[TMP3:%.*]], [[FLOW1]] ]
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; OPT-NEXT: br label [[LOOP:%.*]]
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; OPT: LOOP:
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; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP6:%.*]], [[FLOW:%.*]] ], [ 0, [[LOOP_OUTER]] ]
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; OPT-NEXT: [[TMP45:%.*]] = phi i32 [ [[TMP43]], [[LOOP_OUTER]] ], [ [[TMP3]], [[FLOW]] ]
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; OPT-NEXT: [[TMP48:%.*]] = icmp slt i32 [[TMP45]], [[UB:%.*]]
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; OPT-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP48]])
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; OPT-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0
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; OPT-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1
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; OPT-NEXT: br i1 [[TMP1]], label [[ENDIF:%.*]], label [[FLOW]]
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; OPT: Flow:
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; OPT-NEXT: [[TMP3]] = phi i32 [ [[TMP47:%.*]], [[ENDIF]] ], [ undef, [[LOOP]] ]
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; OPT-NEXT: [[TMP4:%.*]] = phi i1 [ [[TMP51:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
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; OPT-NEXT: [[TMP5:%.*]] = phi i1 [ [[TMP51_INV:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ]
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
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; OPT-NEXT: [[TMP6]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP5]], i64 [[PHI_BROKEN]])
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; OPT-NEXT: [[TMP7:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP6]])
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; OPT-NEXT: [[TMP8]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN2]])
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; OPT-NEXT: br i1 [[TMP7]], label [[FLOW1]], label [[LOOP]]
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; OPT: Flow1:
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP6]])
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; OPT-NEXT: [[TMP9:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP8]])
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; OPT-NEXT: br i1 [[TMP9]], label [[IF:%.*]], label [[LOOP_OUTER]]
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; OPT: IF:
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP8]])
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; OPT-NEXT: ret void
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; OPT: ENDIF:
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; OPT-NEXT: [[TMP47]] = add i32 [[TMP45]], 1
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; OPT-NEXT: [[TMP51]] = icmp eq i32 [[TMP47]], [[CONT:%.*]]
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; OPT-NEXT: [[TMP51_INV]] = xor i1 [[TMP51]], true
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; OPT-NEXT: br label [[FLOW]]
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;
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; GCN-LABEL: multi_else_break:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b64 s[0:1], 0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_branch .LBB0_2
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; GCN-NEXT: .LBB0_1: ; %loop.exit.guard
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
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; GCN-NEXT: s_and_b64 s[2:3], exec, s[2:3]
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; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
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; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
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; GCN-NEXT: s_cbranch_execz .LBB0_6
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; GCN-NEXT: .LBB0_2: ; %LOOP.outer
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; GCN-NEXT: ; =>This Loop Header: Depth=1
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; GCN-NEXT: ; Child Loop BB0_4 Depth 2
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; GCN-NEXT: ; implicit-def: $sgpr6_sgpr7
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; GCN-NEXT: ; implicit-def: $sgpr2_sgpr3
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; GCN-NEXT: s_mov_b64 s[4:5], 0
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; GCN-NEXT: s_branch .LBB0_4
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; GCN-NEXT: .LBB0_3: ; %Flow
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; GCN-NEXT: ; in Loop: Header=BB0_4 Depth=2
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; GCN-NEXT: s_or_b64 exec, exec, s[8:9]
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; GCN-NEXT: s_and_b64 s[8:9], exec, s[6:7]
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; GCN-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
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; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
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; GCN-NEXT: s_cbranch_execz .LBB0_1
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; GCN-NEXT: .LBB0_4: ; %LOOP
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; GCN-NEXT: ; Parent Loop BB0_2 Depth=1
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; GCN-NEXT: ; => This Inner Loop Header: Depth=2
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; GCN-NEXT: v_cmp_lt_i32_e32 vcc, v0, v4
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; GCN-NEXT: s_or_b64 s[2:3], s[2:3], exec
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; GCN-NEXT: s_or_b64 s[6:7], s[6:7], exec
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; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc
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; GCN-NEXT: s_cbranch_execz .LBB0_3
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; GCN-NEXT: ; %bb.5: ; %ENDIF
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; GCN-NEXT: ; in Loop: Header=BB0_4 Depth=2
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; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v0
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; GCN-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, v5, v0
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; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec
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; GCN-NEXT: s_and_b64 s[10:11], vcc, exec
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; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
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; GCN-NEXT: s_branch .LBB0_3
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; GCN-NEXT: .LBB0_6: ; %IF
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; GCN-NEXT: s_endpgm
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main_body:
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br label %LOOP.outer
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LOOP.outer: ; preds = %ENDIF, %main_body
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%tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ]
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br label %LOOP
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LOOP: ; preds = %ENDIF, %LOOP.outer
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%tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ]
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%tmp48 = icmp slt i32 %tmp45, %ub
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br i1 %tmp48, label %ENDIF, label %IF
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IF: ; preds = %LOOP
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ret void
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ENDIF: ; preds = %LOOP
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%tmp47 = add i32 %tmp45, 1
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%tmp51 = icmp eq i32 %tmp47, %cont
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br i1 %tmp51, label %LOOP, label %LOOP.outer
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}
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define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
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; OPT-LABEL: @multi_if_break_loop(
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; OPT-NEXT: bb:
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; OPT-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; OPT-NEXT: [[TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]]
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; OPT-NEXT: br label [[BB1:%.*]]
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; OPT: bb1:
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; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP4:%.*]], [[FLOW4:%.*]] ], [ 0, [[BB:%.*]] ]
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; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[TMP2:%.*]], [[FLOW4]] ]
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; OPT-NEXT: [[LSR_IV_NEXT:%.*]] = add i32 [[LSR_IV]], 1
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; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0
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; OPT-NEXT: [[LOAD0:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: br label [[NODEBLOCK:%.*]]
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; OPT: NodeBlock:
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; OPT-NEXT: [[PIVOT:%.*]] = icmp sge i32 [[LOAD0]], 1
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; OPT-NEXT: br i1 [[PIVOT]], label [[LEAFBLOCK1:%.*]], label [[FLOW:%.*]]
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; OPT: LeafBlock1:
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; OPT-NEXT: [[SWITCHLEAF2:%.*]] = icmp eq i32 [[LOAD0]], 1
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; OPT-NEXT: br i1 [[SWITCHLEAF2]], label [[CASE1:%.*]], label [[FLOW3:%.*]]
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; OPT: Flow3:
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; OPT-NEXT: [[TMP0:%.*]] = phi i32 [ [[LSR_IV_NEXT]], [[CASE1]] ], [ undef, [[LEAFBLOCK1]] ]
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; OPT-NEXT: [[TMP1:%.*]] = phi i1 [ [[CMP2:%.*]], [[CASE1]] ], [ true, [[LEAFBLOCK1]] ]
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; OPT-NEXT: br label [[FLOW]]
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; OPT: LeafBlock:
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; OPT-NEXT: [[SWITCHLEAF:%.*]] = icmp eq i32 [[LOAD0]], 0
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; OPT-NEXT: br i1 [[SWITCHLEAF]], label [[CASE0:%.*]], label [[FLOW5:%.*]]
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; OPT: Flow4:
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; OPT-NEXT: [[TMP2]] = phi i32 [ [[TMP9:%.*]], [[FLOW5]] ], [ [[TMP6:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[TMP3:%.*]] = phi i1 [ [[TMP10:%.*]], [[FLOW5]] ], [ [[TMP7:%.*]], [[FLOW]] ]
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; OPT-NEXT: [[TMP4]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP3]], i64 [[PHI_BROKEN]])
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; OPT-NEXT: [[TMP5:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP4]])
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; OPT-NEXT: br i1 [[TMP5]], label [[BB9:%.*]], label [[BB1]]
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; OPT: case0:
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; OPT-NEXT: [[LOAD1:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: [[CMP1:%.*]] = icmp sge i32 [[TMP]], [[LOAD1]]
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; OPT-NEXT: br label [[FLOW5]]
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; OPT: Flow:
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; OPT-NEXT: [[TMP6]] = phi i32 [ [[TMP0]], [[FLOW3]] ], [ undef, [[NODEBLOCK]] ]
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; OPT-NEXT: [[TMP7]] = phi i1 [ [[TMP1]], [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
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; OPT-NEXT: [[TMP8:%.*]] = phi i1 [ false, [[FLOW3]] ], [ true, [[NODEBLOCK]] ]
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; OPT-NEXT: br i1 [[TMP8]], label [[LEAFBLOCK:%.*]], label [[FLOW4]]
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; OPT: case1:
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; OPT-NEXT: [[LOAD2:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4
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; OPT-NEXT: [[CMP2]] = icmp sge i32 [[TMP]], [[LOAD2]]
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; OPT-NEXT: br label [[FLOW3]]
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; OPT: Flow5:
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; OPT-NEXT: [[TMP9]] = phi i32 [ [[LSR_IV_NEXT]], [[CASE0]] ], [ undef, [[LEAFBLOCK]] ]
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; OPT-NEXT: [[TMP10]] = phi i1 [ [[CMP1]], [[CASE0]] ], [ [[TMP7]], [[LEAFBLOCK]] ]
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; OPT-NEXT: br label [[FLOW4]]
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; OPT: bb9:
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP4]])
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; OPT-NEXT: ret void
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;
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; GCN-LABEL: multi_if_break_loop:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dword s2, s[0:1], 0x9
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; GCN-NEXT: s_mov_b64 s[0:1], 0
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_branch .LBB1_2
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; GCN-NEXT: .LBB1_1: ; %Flow4
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_and_b64 s[4:5], exec, s[4:5]
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; GCN-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
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; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1]
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; GCN-NEXT: s_cbranch_execz .LBB1_9
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; GCN-NEXT: .LBB1_2: ; %bb1
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 s8, v1
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; GCN-NEXT: s_mov_b64 s[4:5], -1
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; GCN-NEXT: s_cmp_lt_i32 s8, 1
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; GCN-NEXT: s_mov_b64 s[6:7], -1
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; GCN-NEXT: s_cbranch_scc1 .LBB1_6
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; GCN-NEXT: ; %bb.3: ; %LeafBlock1
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_cmp_eq_u32 s8, 1
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; GCN-NEXT: s_cbranch_scc0 .LBB1_5
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; GCN-NEXT: ; %bb.4: ; %case1
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
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; GCN-NEXT: s_orn2_b64 s[4:5], vcc, exec
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; GCN-NEXT: .LBB1_5: ; %Flow3
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_mov_b64 s[6:7], 0
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; GCN-NEXT: .LBB1_6: ; %Flow
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_and_b64 vcc, exec, s[6:7]
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; GCN-NEXT: s_cbranch_vccz .LBB1_1
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; GCN-NEXT: ; %bb.7: ; %LeafBlock
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: s_cmp_eq_u32 s8, 0
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; GCN-NEXT: s_cbranch_scc0 .LBB1_1
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; GCN-NEXT: ; %bb.8: ; %case0
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; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
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; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
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; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
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; GCN-NEXT: s_and_b64 s[6:7], vcc, exec
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; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
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; GCN-NEXT: s_branch .LBB1_1
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; GCN-NEXT: .LBB1_9: ; %bb9
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; GCN-NEXT: s_endpgm
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1:
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%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %case0 ], [ %lsr.iv.next, %case1 ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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%load0 = load volatile i32, i32 addrspace(1)* undef, align 4
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switch i32 %load0, label %bb9 [
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i32 0, label %case0
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i32 1, label %case1
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]
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case0:
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%load1 = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp slt i32 %tmp, %load1
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br i1 %cmp1, label %bb1, label %bb9
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case1:
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%load2 = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp2 = icmp slt i32 %tmp, %load2
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br i1 %cmp2, label %bb1, label %bb9
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bb9:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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