9fa425c1ab
AMDGPUPerfHintAnalysis doesn't set the memory bound attribute if FuncInfo::InstCost outweighs MemInstCost even if we have a basic block with relatively high global memory access. GCNSchedStrategy could revert optimal scheduling in favour of occupancy which seems to degrade performance for some kernels. This change introduces the HasDenseGlobalMemAcc metric in the heuristic that makes the analysis more conservative in these cases. This fixes SWDEV-334259/SWDEV-343932 Differential Revision: https://reviews.llvm.org/D129759
174 lines
7.5 KiB
LLVM
174 lines
7.5 KiB
LLVM
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_membound:
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; GCN: MemoryBound: 1
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; GCN: WaveLimiterHint : 1
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define amdgpu_kernel void @test_membound(<4 x i32> addrspace(1)* nocapture readonly %arg, <4 x i32> addrspace(1)* nocapture %arg1) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = zext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
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%tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
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%tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
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%tmp6 = add nuw nsw i64 %tmp2, 1
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%tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
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%tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
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%tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
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store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
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ret void
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}
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; GCN-LABEL: {{^}}test_membound_1:
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; GCN: MemoryBound: 1
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define amdgpu_kernel void @test_membound_1(<2 x double> addrspace(1)* nocapture readonly %ptr.0,
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<2 x double> addrspace(1)* nocapture %ptr.1,
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<2 x double> %arg.0, i32 %arg.1, <4 x double> %arg.2) {
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bb.entry:
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%id.32 = tail call i32 @llvm.amdgcn.workitem.id.x()
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%id.0 = zext i32 %id.32 to i64
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%gep.0 = getelementptr inbounds <2 x double>, <2 x double> addrspace(1)* %ptr.0, i64 %id.0
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%ld.0 = load <2 x double>, <2 x double> addrspace(1)* %gep.0, align 16
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%add.0 = fadd <2 x double> %arg.0, %ld.0
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%id.1 = add nuw nsw i64 %id.0, 1
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%gep.1 = getelementptr inbounds <2 x double>, <2 x double> addrspace(1)* %ptr.0, i64 %id.1
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%ld.1 = load <2 x double>, <2 x double> addrspace(1)* %gep.1, align 16
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%add.1 = fadd <2 x double> %add.0, %ld.1
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%id.2 = add nuw nsw i64 %id.0, 2
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%gep.2 = getelementptr inbounds <2 x double>, <2 x double> addrspace(1)* %ptr.0, i64 %id.2
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%ld.2 = load <2 x double>, <2 x double> addrspace(1)* %gep.2, align 16
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%add.2 = fadd <2 x double> %add.1, %ld.2
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%id.3 = add nuw nsw i64 %id.0, 3
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%gep.3= getelementptr inbounds <2 x double>, <2 x double> addrspace(1)* %ptr.0, i64 %id.3
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%ld.3 = load <2 x double>, <2 x double> addrspace(1)* %gep.3, align 16
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%add.3 = fadd <2 x double> %add.2, %ld.3
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%id.4 = add nuw nsw i64 %id.0, 4
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%gep.4= getelementptr inbounds <2 x double>, <2 x double> addrspace(1)* %ptr.0, i64 %id.4
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%ld.4 = load <2 x double>, <2 x double> addrspace(1)* %gep.4, align 16
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%add.4 = fadd <2 x double> %add.3, %ld.4
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store <2 x double> %add.4, <2 x double> addrspace(1)* %ptr.1, align 16
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%cond = icmp eq i32 %arg.1, 0
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br i1 %cond, label %bb.true, label %bb.ret
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bb.true:
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%i0.arg.0 = extractelement <2 x double> %arg.0, i32 0
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%i1.arg.0 = extractelement <2 x double> %arg.0, i32 1
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%add.1.0 = fadd double %i0.arg.0, %i1.arg.0
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%i0.arg.2 = extractelement <4 x double> %arg.2, i32 0
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%i1.arg.2 = extractelement <4 x double> %arg.2, i32 1
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%add.1.1 = fadd double %i0.arg.2, %i1.arg.2
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%add.1.2 = fadd double %add.1.0, %add.1.1
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%i2.arg.2 = extractelement <4 x double> %arg.2, i32 2
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%i3.arg.2 = extractelement <4 x double> %arg.2, i32 3
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%add.1.3 = fadd double %i2.arg.2, %i3.arg.2
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%add.1.4 = fadd double %add.1.2, %add.1.3
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%i0.add.0 = extractelement <2 x double> %add.0, i32 0
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%i1.add.0 = extractelement <2 x double> %add.0, i32 1
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%add.1.5 = fadd double %i0.add.0, %i1.add.0
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%add.1.6 = fadd double %add.1.4, %add.1.5
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%i0.add.1 = extractelement <2 x double> %add.1, i32 0
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%i1.add.1 = extractelement <2 x double> %add.1, i32 1
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%add.1.7 = fadd double %i0.add.1, %i1.add.1
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%add.1.8 = fadd double %add.1.6, %add.1.7
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%i0.add.2 = extractelement <2 x double> %add.2, i32 0
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%i1.add.2 = extractelement <2 x double> %add.2, i32 1
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%add.1.9 = fadd double %i0.add.2, %i1.add.2
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%add.1.10 = fadd double %add.1.8, %add.1.9
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%ptr.1.bc = bitcast <2 x double> addrspace(1)* %ptr.1 to double addrspace(1)*
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store double %add.1.8, double addrspace(1)* %ptr.1.bc, align 8
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br label %bb.ret
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bb.ret:
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ret void
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}
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; GCN-LABEL: {{^}}test_large_stride:
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; GCN: MemoryBound: 0
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; GCN: WaveLimiterHint : 1
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define amdgpu_kernel void @test_large_stride(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 4096
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%tmp1 = load i32, i32 addrspace(1)* %tmp, align 4
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%mul1 = mul i32 %tmp1, %tmp1
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%tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
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store i32 %mul1, i32 addrspace(1)* %tmp2, align 4
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%tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 8192
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%tmp4 = load i32, i32 addrspace(1)* %tmp3, align 4
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%mul4 = mul i32 %tmp4, %tmp4
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
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store i32 %mul4, i32 addrspace(1)* %tmp5, align 4
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%tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 12288
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%tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4
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%mul7 = mul i32 %tmp7, %tmp7
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%tmp8 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 3
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store i32 %mul7, i32 addrspace(1)* %tmp8, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_indirect:
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; GCN: MemoryBound: 0
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; GCN: WaveLimiterHint : 1
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define amdgpu_kernel void @test_indirect(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
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%tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 3
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%tmp3 = bitcast i32 addrspace(1)* %arg to <4 x i32> addrspace(1)*
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%tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 4
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%tmp5 = extractelement <4 x i32> %tmp4, i32 0
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%tmp6 = sext i32 %tmp5 to i64
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%tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp6
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%tmp8 = load i32, i32 addrspace(1)* %tmp7, align 4
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store i32 %tmp8, i32 addrspace(1)* %arg, align 4
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%tmp9 = extractelement <4 x i32> %tmp4, i32 1
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%tmp10 = sext i32 %tmp9 to i64
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%tmp11 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp10
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%tmp12 = load i32, i32 addrspace(1)* %tmp11, align 4
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store i32 %tmp12, i32 addrspace(1)* %tmp, align 4
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%tmp13 = extractelement <4 x i32> %tmp4, i32 2
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%tmp14 = sext i32 %tmp13 to i64
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%tmp15 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp14
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%tmp16 = load i32, i32 addrspace(1)* %tmp15, align 4
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store i32 %tmp16, i32 addrspace(1)* %tmp1, align 4
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%tmp17 = extractelement <4 x i32> %tmp4, i32 3
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%tmp18 = sext i32 %tmp17 to i64
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%tmp19 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp18
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%tmp20 = load i32, i32 addrspace(1)* %tmp19, align 4
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store i32 %tmp20, i32 addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_indirect_through_phi:
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; GCN: MemoryBound: 0
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; GCN: WaveLimiterHint : 0
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define amdgpu_kernel void @test_indirect_through_phi(float addrspace(1)* %arg) {
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bb:
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%load = load float, float addrspace(1)* %arg, align 8
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%load.f = bitcast float %load to i32
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%n = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1: ; preds = %bb1, %bb
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%phi = phi i32 [ %load.f, %bb ], [ %and2, %bb1 ]
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%ind = phi i32 [ 0, %bb ], [ %inc2, %bb1 ]
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%and1 = and i32 %phi, %n
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%gep = getelementptr inbounds float, float addrspace(1)* %arg, i32 %and1
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store float %load, float addrspace(1)* %gep, align 4
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%inc1 = add nsw i32 %phi, 1310720
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%and2 = and i32 %inc1, %n
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%inc2 = add nuw nsw i32 %ind, 1
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%cmp = icmp eq i32 %inc2, 1024
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br i1 %cmp, label %bb2, label %bb1
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bb2: ; preds = %bb1
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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