68901fdbeb
The instruction is used to modify wave priority with the intent to affect VALU execution and currently we can reschedule VALU around it since that VALU does not have side effects. Differential Revision: https://reviews.llvm.org/D130654
21 lines
902 B
LLVM
21 lines
902 B
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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declare void @llvm.amdgcn.s.setprio(i16)
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declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float, float, <4 x float>, i32, i32, i32)
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; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32:
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; GCN: s_setprio 1
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; GCN: v_mfma
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; GCN: v_mfma
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; GCN: s_setprio 0
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define amdgpu_kernel void @test_mfma_f32_4x4x1f32(<4 x float> addrspace(1)* %arg) #0 {
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bb:
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%in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg
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call void @llvm.amdgcn.s.setprio(i16 1)
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%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 2.0, <4 x float> %in.1, i32 0, i32 0, i32 0)
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%mai.2 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 3.0, float 4.0, <4 x float> %mai.1, i32 0, i32 0, i32 0)
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call void @llvm.amdgcn.s.setprio(i16 0)
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store <4 x float> %mai.2, <4 x float> addrspace(1)* %arg
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ret void
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}
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