fbdea5a2e9
This patch contains changes necessary to carry physical condition register (SCC) dependencies through the SDNode scheduler. It adds the edge in the SDNodeScheduler dependency graph instead of inserting the SCC copy between each definition and use. This approach lets the scheduler place instructions in an optimal way placing the copy only when the dependency cannot be resolved. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D133593
65 lines
2.3 KiB
LLVM
65 lines
2.3 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck -check-prefix=GCN %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}select0:
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; i64 select should be split into two i32 selects, and we shouldn't need
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; to use a shfit to extract the hi dword of the input.
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; GCN-NOT: s_lshr_b64
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; GCN: s_cselect_b32
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; GCN: s_cselect_b32
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define amdgpu_kernel void @select0(i64 addrspace(1)* %out, i32 %cond, i64 %in) {
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entry:
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%0 = icmp ugt i32 %cond, 5
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%1 = select i1 %0, i64 0, i64 %in
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}select_trunc_i64:
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; GCN: s_cselect_b32
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; GCN-NOT: s_cselect_b32
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define amdgpu_kernel void @select_trunc_i64(i32 addrspace(1)* %out, i32 %cond, i64 %in) nounwind {
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%cmp = icmp ugt i32 %cond, 5
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%sel = select i1 %cmp, i64 0, i64 %in
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%trunc = trunc i64 %sel to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}select_trunc_i64_2:
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; GCN: s_cselect_b32
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; GCN-NOT: s_cselect_b32
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define amdgpu_kernel void @select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 %a, i64 %b) nounwind {
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%cmp = icmp ugt i32 %cond, 5
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%sel = select i1 %cmp, i64 %a, i64 %b
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%trunc = trunc i64 %sel to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_select_trunc_i64_2:
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; GCN: s_cselect_b32
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; GCN-NOT: s_cselect_b32
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define amdgpu_kernel void @v_select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
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%cmp = icmp ugt i32 %cond, 5
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%b = load i64, i64 addrspace(1)* %bptr, align 8
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%sel = select i1 %cmp, i64 %a, i64 %b
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%trunc = trunc i64 %sel to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_select_i64_split_imm:
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; GCN-DAG: s_cselect_b32
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; GCN-DAG: s_cselect_b32
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; GCN: s_endpgm
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define amdgpu_kernel void @v_select_i64_split_imm(i64 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
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%cmp = icmp ugt i32 %cond, 5
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%b = load i64, i64 addrspace(1)* %bptr, align 8
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%sel = select i1 %cmp, i64 %a, i64 270582939648 ; 63 << 32
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store i64 %sel, i64 addrspace(1)* %out, align 8
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ret void
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}
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