fbdea5a2e9
This patch contains changes necessary to carry physical condition register (SCC) dependencies through the SDNode scheduler. It adds the edge in the SDNodeScheduler dependency graph instead of inserting the SCC copy between each definition and use. This approach lets the scheduler place instructions in an optimal way placing the copy only when the dependency cannot be resolved. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D133593
21 lines
764 B
LLVM
21 lines
764 B
LLVM
; RUN: llc -verify-machineinstrs -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI -check-prefix=FUNC %s
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; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}selectcc_i64:
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; EG: XOR_INT
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; EG: XOR_INT
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; EG: OR_INT
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; EG: CNDE_INT
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; EG: CNDE_INT
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; SI: v_cmp_eq_u64
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; VI: s_cmp_eq_u64
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; GCN: s_cselect_b32
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define amdgpu_kernel void @selectcc_i64(i64 addrspace(1) * %out, i64 %lhs, i64 %rhs, i64 %true, i64 %false) {
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entry:
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%0 = icmp eq i64 %lhs, %rhs
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%1 = select i1 %0, i64 %true, i64 %false
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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