11e86868c1
Ignorable operands don't impact instruction's behavior, we can safely do CSE on
the instruction.
It is split from D130919. It has big impact to some AMDGPU test cases.
For example in atomic_optimizations_raw_buffer.ll, when trying to check if the
following instruction can be CSEed
%37:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
Function isCallerPreservedOrConstPhysReg is called on operand "implicit $exec",
this function is implemented as
- return TRI.isCallerPreservedPhysReg(Reg, MF) ||
+ return TRI.isCallerPreservedPhysReg(Reg, MF) || TII.isIgnorableUse(MO) ||
(MRI.reservedRegsFrozen() && MRI.isConstantPhysReg(Reg));
Both TRI.isCallerPreservedPhysReg and MRI.isConstantPhysReg return false on this
operand, so isCallerPreservedOrConstPhysReg is also false, it causes LLVM failed
to CSE this instruction.
With this patch TII.isIgnorableUse returns true for the operand $exec, so
isCallerPreservedOrConstPhysReg also returns true, it causes this instruction to
be CSEed with previous instruction
%14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
So I got different result from here. AMDGPU's implementation of isIgnorableUse
is
bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {
// Any implicit use of exec by VALU is not a real register read.
return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
isVALU(*MO.getParent()) && !resultDependsOnExec(*MO.getParent());
}
Since the operand $exec is not a real register read, my understanding is it's
reasonable to do CSE on such instructions.
Because more instructions are CSEed, so I get less instructions generated for
these tests.
Differential Revision: https://reviews.llvm.org/D137222
228 lines
7.3 KiB
LLVM
228 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
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;
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; Most SALU instructions ignore control flow, so we need to make sure
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; they don't overwrite values from other blocks.
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; If the branch decision is made based on a value in an SGPR then all
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; threads will execute the same code paths, so we don't need to worry
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; about instructions in different blocks overwriting each other.
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define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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; SI-LABEL: sgpr_if_else_salu_br:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
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; SI-NEXT: s_load_dword s2, s[0:1], 0xf
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_cmp_lg_u32 s4, 0
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; SI-NEXT: s_cbranch_scc0 .LBB0_4
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; SI-NEXT: ; %bb.1: ; %else
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; SI-NEXT: s_add_i32 s7, s7, s2
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; SI-NEXT: s_cbranch_execnz .LBB0_3
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; SI-NEXT: .LBB0_2: ; %if
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; SI-NEXT: s_sub_i32 s7, s5, s6
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; SI-NEXT: .LBB0_3: ; %endif
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; SI-NEXT: s_add_i32 s4, s7, s4
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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; SI-NEXT: .LBB0_4:
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; SI-NEXT: ; implicit-def: $sgpr7
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; SI-NEXT: s_branch .LBB0_2
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entry:
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%0 = icmp eq i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = sub i32 %b, %c
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br label %endif
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else:
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%2 = add i32 %d, %e
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br label %endif
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endif:
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%3 = phi i32 [%1, %if], [%2, %else]
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%4 = add i32 %3, %a
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store i32 %4, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
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; SI-LABEL: sgpr_if_else_salu_br_opt:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dword s4, s[0:1], 0x13
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_cmp_lg_u32 s4, 0
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; SI-NEXT: s_cbranch_scc0 .LBB1_4
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; SI-NEXT: ; %bb.1: ; %else
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; SI-NEXT: s_load_dword s2, s[0:1], 0x2e
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; SI-NEXT: s_load_dword s3, s[0:1], 0x37
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_add_i32 s5, s2, s3
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; SI-NEXT: s_cbranch_execnz .LBB1_3
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; SI-NEXT: .LBB1_2: ; %if
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; SI-NEXT: s_load_dword s2, s[0:1], 0x1c
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; SI-NEXT: s_load_dword s3, s[0:1], 0x25
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_add_i32 s5, s2, s3
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; SI-NEXT: .LBB1_3: ; %endif
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; SI-NEXT: s_add_i32 s4, s5, s4
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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; SI-NEXT: .LBB1_4:
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; SI-NEXT: ; implicit-def: $sgpr5
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; SI-NEXT: s_branch .LBB1_2
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entry:
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%cmp0 = icmp eq i32 %a, 0
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br i1 %cmp0, label %if, label %else
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if:
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%add0 = add i32 %b, %c
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br label %endif
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else:
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%add1 = add i32 %d, %e
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br label %endif
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endif:
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%phi = phi i32 [%add0, %if], [%add1, %else]
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%add2 = add i32 %phi, %a
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store i32 %add2, i32 addrspace(1)* %out
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ret void
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}
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; The two S_ADD instructions should write to different registers, since
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; different threads will take different control flow paths.
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define amdgpu_kernel void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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; SI-LABEL: sgpr_if_else_valu_br:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xc
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; SI-NEXT: v_cvt_f32_u32_e32 v0, v0
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; SI-NEXT: ; implicit-def: $sgpr8
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; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0
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; SI-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; SI-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
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; SI-NEXT: s_cbranch_execz .LBB2_2
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; SI-NEXT: ; %bb.1: ; %else
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_add_i32 s8, s6, s7
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; SI-NEXT: .LBB2_2: ; %Flow
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; SI-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]
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; SI-NEXT: v_mov_b32_e32 v0, s8
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; SI-NEXT: s_xor_b64 exec, exec, s[2:3]
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; SI-NEXT: s_cbranch_execz .LBB2_4
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; SI-NEXT: ; %bb.3: ; %if
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_add_i32 s4, s4, s5
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: .LBB2_4: ; %endif
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; SI-NEXT: s_or_b64 exec, exec, s[2:3]
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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%tid_f = uitofp i32 %tid to float
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%tmp1 = fcmp ueq float %tid_f, 0.0
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br i1 %tmp1, label %if, label %else
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if:
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%tmp2 = add i32 %b, %c
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br label %endif
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else:
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%tmp3 = add i32 %d, %e
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br label %endif
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endif:
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%tmp4 = phi i32 [%tmp2, %if], [%tmp3, %else]
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store i32 %tmp4, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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; SI-LABEL: sgpr_if_else_valu_cmp_phi_br:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
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; SI-NEXT: s_mov_b32 s2, 0
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; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; SI-NEXT: ; implicit-def: $sgpr8_sgpr9
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; SI-NEXT: s_and_saveexec_b64 s[10:11], vcc
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; SI-NEXT: s_xor_b64 s[10:11], exec, s[10:11]
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; SI-NEXT: s_cbranch_execz .LBB3_2
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; SI-NEXT: ; %bb.1: ; %else
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
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; SI-NEXT: s_and_b64 s[8:9], vcc, exec
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; SI-NEXT: ; implicit-def: $vgpr0
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; SI-NEXT: .LBB3_2: ; %Flow
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_andn2_saveexec_b64 s[0:1], s[10:11]
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; SI-NEXT: s_cbranch_execz .LBB3_4
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; SI-NEXT: ; %bb.3: ; %if
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; SI-NEXT: s_mov_b32 s15, 0xf000
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; SI-NEXT: s_mov_b32 s14, 0
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; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
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; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], exec
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
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; SI-NEXT: s_and_b64 s[6:7], vcc, exec
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; SI-NEXT: s_or_b64 s[8:9], s[2:3], s[6:7]
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; SI-NEXT: .LBB3_4: ; %endif
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; SI-NEXT: s_or_b64 exec, exec, s[0:1]
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[8:9]
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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%tmp1 = icmp eq i32 %tid, 0
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br i1 %tmp1, label %if, label %else
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if:
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%gep.if = getelementptr i32, i32 addrspace(1)* %a, i32 %tid
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%a.val = load i32, i32 addrspace(1)* %gep.if
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%cmp.if = icmp eq i32 %a.val, 0
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br label %endif
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else:
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%gep.else = getelementptr i32, i32 addrspace(1)* %b, i32 %tid
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%b.val = load i32, i32 addrspace(1)* %gep.else
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%cmp.else = icmp slt i32 %b.val, 0
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br label %endif
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endif:
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%tmp4 = phi i1 [%cmp.if, %if], [%cmp.else, %else]
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%ext = sext i1 %tmp4 to i32
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { readnone }
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