2e29b0138c
Since the divergence-driven instruction selection has been enabled for AMDGPU, all the uniform instructions are expected to be selected to SALU form, except those not having one. VGPR to SGPR copies appear in MIR to connect values producers and consumers. This change implements an algorithm that evolves a reasonable tradeoff between the profit achieved from keeping the uniform instructions in SALU form and overhead introduced by the data transfer between the VGPRs and SGPRs. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D128252
95 lines
3.6 KiB
LLVM
95 lines
3.6 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; The code generated by urem is long and complex and may frequently
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; change. The goal of this test is to make sure the ISel doesn't fail
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; when it gets a v2i32/v4i32 urem
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; FUNC-LABEL: {{^}}test_urem_i32:
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; SI: s_endpgm
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; EG: CF_END
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define amdgpu_kernel void @test_urem_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
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%a = load i32, i32 addrspace(1)* %in
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%b = load i32, i32 addrspace(1)* %b_ptr
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%result = urem i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_urem_i32_7:
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; SI: s_mov_b32 [[MAGIC:s[0-9]+]], 0x24924925
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; SI: v_mul_hi_u32 {{v[0-9]+}}, {{v[0-9]+}}, [[MAGIC]]
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; SI: v_sub_{{[iu]}}32
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; SI: v_mul_lo_u32
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; SI: v_subrev_{{[iu]}}32
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; SI: buffer_store_dword
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; SI: s_endpgm
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define amdgpu_kernel void @test_urem_i32_7(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%num = load i32, i32 addrspace(1) * %in
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%result = urem i32 %num, 7
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_urem_v2i32:
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; SI: s_endpgm
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; EG: CF_END
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define amdgpu_kernel void @test_urem_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1)* %in
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%b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
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%result = urem <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_urem_v4i32:
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; SI: s_endpgm
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; EG: CF_END
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define amdgpu_kernel void @test_urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1)* %in
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%b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
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%result = urem <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_urem_i64:
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; SI: s_endpgm
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; EG: CF_END
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define amdgpu_kernel void @test_urem_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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%b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
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%a = load i64, i64 addrspace(1)* %in
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%b = load i64, i64 addrspace(1)* %b_ptr
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%result = urem i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_urem_v2i64:
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; SI: s_endpgm
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; EG: CF_END
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define amdgpu_kernel void @test_urem_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
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%a = load <2 x i64>, <2 x i64> addrspace(1)* %in
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%b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
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%result = urem <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_urem_v4i64:
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; SI: s_endpgm
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; EG: CF_END
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define amdgpu_kernel void @test_urem_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
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%a = load <4 x i64>, <4 x i64> addrspace(1)* %in
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%b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
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%result = urem <4 x i64> %a, %b
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store <4 x i64> %result, <4 x i64> addrspace(1)* %out
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ret void
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}
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