7a84624079
Surprisingly these were getting legalized to something zero initialized. This fixes an infinite loop when combining some vector types. Also fixes zero initializing some undef values. SimplifyDemandedVectorElts / SimplifyDemandedBits are not checking for the legality of the output undefs they are replacing unused operations with. This resulted in turning vectors into undefs that were later re-legalized back into zero vectors.
23 lines
1.0 KiB
LLVM
23 lines
1.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck %s
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declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16(<16 x half>, <16 x half>, <4 x float>)
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; Make sure we don't crash when trying to select modifiers in SelectVOP3PMods.
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define amdgpu_cs void @xyz () {
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; CHECK-LABEL: xyz:
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; CHECK: v_wmma_f32_16x16x16_f16 v[0:3], v[0:7], v[0:7], v[0:3]
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.entry:
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br label %loop
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loop:
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%ld = load <8 x float>, <8 x float> addrspace(5)* null, align 32
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%in_shuffle = shufflevector <8 x float> %ld, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%wmma = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16(<16 x half> undef, <16 x half> undef, <4 x float> %in_shuffle)
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%out_shuffle = shufflevector <4 x float> %wmma, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x float> %out_shuffle, <8 x float> addrspace(5)* null, align 32
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br i1 false, label %.exit, label %loop
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.exit:
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ret void
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}
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