3eb2281bc0
Previously SIFoldOperands::foldInstOperand would only fold a non-inlinable immediate into a single user, so as not to increase code size by adding the same 32-bit literal operand to many instructions. This patch removes that restriction, so that a non-inlinable immediate will be folded into any number of users. The rationale is: - It reduces the number of registers used for holding constant values, which might increase occupancy. (On the other hand, many of these registers are SGPRs which no longer affect occupancy on GFX10+.) - It reduces ALU stalls between the instruction that loads a constant into a register, and the instruction that uses it. - The above benefits are expected to outweigh any increase in code size. Differential Revision: https://reviews.llvm.org/D114643
252 lines
9.2 KiB
LLVM
252 lines
9.2 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}xor_v2i32:
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_xor_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_xor_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in0
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %in1
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%result = xor <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}xor_v4i32:
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in0
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %in1
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%result = xor <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}xor_i1:
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; EG: XOR_INT {{\** *}}{{T[0-9]+\.[XYZW]}}, {{PS|PV\.[XYZW]}}, {{PS|PV\.[XYZW]}}
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; SI-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}}
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; SI-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, {{v[0-9]+}}
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; SI: s_xor_b64 [[XOR:vcc]], [[CMP1]], [[CMP0]]
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; SI: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define amdgpu_kernel void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
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%a = load float, float addrspace(1) * %in0
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%b = load float, float addrspace(1) * %in1
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%acmp = fcmp oge float %a, 0.000000e+00
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%bcmp = fcmp oge float %b, 1.000000e+00
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%xor = xor i1 %acmp, %bcmp
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%result = select i1 %xor, float %a, float %b
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store float %result, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_xor_i1:
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; SI: buffer_load_ubyte [[B:v[0-9]+]]
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; SI: buffer_load_ubyte [[A:v[0-9]+]]
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; SI: v_xor_b32_e32 [[XOR:v[0-9]+]], [[B]], [[A]]
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; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[XOR]]
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; SI: buffer_store_byte [[RESULT]]
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define amdgpu_kernel void @v_xor_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
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%a = load volatile i1, i1 addrspace(1)* %in0
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%b = load volatile i1, i1 addrspace(1)* %in1
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%xor = xor i1 %a, %b
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store i1 %xor, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_xor_i32:
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; SI: v_xor_b32_e32
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define amdgpu_kernel void @vector_xor_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
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%a = load i32, i32 addrspace(1)* %in0
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%b = load i32, i32 addrspace(1)* %in1
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%result = xor i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_xor_i32:
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; SI: s_xor_b32
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define amdgpu_kernel void @scalar_xor_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%result = xor i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_not_i32:
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; SI: s_not_b32
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define amdgpu_kernel void @scalar_not_i32(i32 addrspace(1)* %out, i32 %a) {
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%result = xor i32 %a, -1
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_not_i32:
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; SI: v_not_b32
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define amdgpu_kernel void @vector_not_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
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%a = load i32, i32 addrspace(1)* %in0
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%b = load i32, i32 addrspace(1)* %in1
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%result = xor i32 %a, -1
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_xor_i64:
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; SI: v_xor_b32_e32
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; SI: v_xor_b32_e32
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; SI: s_endpgm
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define amdgpu_kernel void @vector_xor_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) {
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%a = load i64, i64 addrspace(1)* %in0
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%b = load i64, i64 addrspace(1)* %in1
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%result = xor i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_xor_i64:
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; SI: s_xor_b64
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; SI: s_endpgm
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define amdgpu_kernel void @scalar_xor_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%result = xor i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_not_i64:
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; SI: s_not_b64
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define amdgpu_kernel void @scalar_not_i64(i64 addrspace(1)* %out, i64 %a) {
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%result = xor i64 %a, -1
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_not_i64:
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; SI: v_not_b32
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; SI: v_not_b32
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define amdgpu_kernel void @vector_not_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) {
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%a = load i64, i64 addrspace(1)* %in0
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%b = load i64, i64 addrspace(1)* %in1
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%result = xor i64 %a, -1
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; Test that we have a pattern to match xor inside a branch.
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; Note that in the future the backend may be smart enough to
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; use an SALU instruction for this.
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; FUNC-LABEL: {{^}}xor_cf:
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; SI: s_xor_b64
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define amdgpu_kernel void @xor_cf(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b) {
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entry:
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%0 = icmp eq i64 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = xor i64 %a, %b
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br label %endif
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else:
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%2 = load i64, i64 addrspace(1)* %in
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br label %endif
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endif:
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%3 = phi i64 [%1, %if], [%2, %else]
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store i64 %3, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_xor_literal_i64:
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; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}
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; SI-DAG: s_xor_b32 s[[RES_HI:[0-9]+]], s{{[0-9]+}}, 0xf237b
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; SI-DAG: s_xor_b32 s[[RES_LO:[0-9]+]], s{{[0-9]+}}, 0x3039
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; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_LO]]
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; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_HI]]
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define amdgpu_kernel void @scalar_xor_literal_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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%or = xor i64 %a, 4261135838621753
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_xor_literal_multi_use_i64:
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; SI: s_load_dwordx4 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xf237b
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; SI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x3039
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; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]
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; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x3039
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; SI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0xf237b
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define amdgpu_kernel void @scalar_xor_literal_multi_use_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a, i64 %b) {
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%or = xor i64 %a, 4261135838621753
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store i64 %or, i64 addrspace(1)* %out
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%foo = add i64 %b, 4261135838621753
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store volatile i64 %foo, i64 addrspace(1)* undef
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_xor_inline_imm_i64:
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; SI: s_load_dwordx2 s[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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; SI-NOT: xor_b32
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; SI: s_xor_b32 s[[VAL_LO]], s{{[0-9]+}}, 63
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; SI-NOT: xor_b32
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; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s{{[0-9]+}}
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; SI-NOT: xor_b32
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; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s{{[0-9]+}}
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; SI-NOT: xor_b32
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; SI: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
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define amdgpu_kernel void @scalar_xor_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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%or = xor i64 %a, 63
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_xor_neg_inline_imm_i64:
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; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -8
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define amdgpu_kernel void @scalar_xor_neg_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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%or = xor i64 %a, -8
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_xor_i64_neg_inline_imm:
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; SI: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
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; SI: v_xor_b32_e32 {{v[0-9]+}}, -8, v[[LO_VREG]]
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; SI: v_xor_b32_e32 {{v[0-9]+}}, -1, {{.*}}
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; SI: s_endpgm
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define amdgpu_kernel void @vector_xor_i64_neg_inline_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%or = xor i64 %loada, -8
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_xor_literal_i64:
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; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
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; SI-DAG: v_xor_b32_e32 {{v[0-9]+}}, 0xdf77987f, v[[LO_VREG]]
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; SI-DAG: v_xor_b32_e32 {{v[0-9]+}}, 0x146f, v[[HI_VREG]]
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; SI: s_endpgm
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define amdgpu_kernel void @vector_xor_literal_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%or = xor i64 %loada, 22470723082367
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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