88ac25b357
Currently MachineCSE forbids PRE when the instruction reads a physical register. Relax this so that it's allowed when the value being read is the same as what would be read in the place the instruction would be hoisted to. This is being done in preparation for adding FPCR handling to the AArch64 backend, in order to prevent it to from worsening the generated code, but for targets that already have a similar register it should improve things. This patch affects code generation in several tests. The new code looks better except for in Thumb2/LowOverheadLoops/memcall.ll where we perform PRE but the LowOverheadLoops transformation then undoes it. Also in AMDGPU/selectcc-opt.ll the CHECK makes things look worse, but actually the function as a whole is better (as a MOV is PRE'd). Differential Revision: https://reviews.llvm.org/D136675
121 lines
2.9 KiB
LLVM
121 lines
2.9 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
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;rdar://8003725
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declare void @llvm.trap()
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@G1 = external global i32
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@G2 = external global i32
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define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) {
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entry:
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; CHECK-LABEL: f1:
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; CHECK: cmp
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; CHECK: moveq
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; CHECK-NOT: cmp
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; CHECK: mov{{eq|ne}}
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%tmp1 = icmp eq i32 %cond1, 0
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%tmp2 = select i1 %tmp1, i32 %x1, i32 %x2
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%tmp3 = select i1 %tmp1, i32 %x2, i32 %x3
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%tmp4 = add i32 %tmp2, %tmp3
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ret i32 %tmp4
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}
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@foo = external global i32
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@bar = external global [250 x i8], align 1
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; CSE of cmp across BB boundary
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; rdar://10660865
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define void @f2() nounwind ssp {
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entry:
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; CHECK-LABEL: f2:
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; CHECK: cmp
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; CHECK: bxlt
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; CHECK-NOT: cmp
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; CHECK: movle
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%0 = load i32, i32* @foo, align 4
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%cmp28 = icmp sgt i32 %0, 0
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br i1 %cmp28, label %for.body.lr.ph, label %for.cond1.preheader
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for.body.lr.ph: ; preds = %entry
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%1 = icmp sgt i32 %0, 1
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%smax = select i1 %1, i32 %0, i32 1
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call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([250 x i8], [250 x i8]* @bar, i32 0, i32 0), i8 0, i32 %smax, i1 false)
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call void @llvm.trap()
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unreachable
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for.cond1.preheader: ; preds = %entry
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ret void
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}
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declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
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; rdar://12462006
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define i8* @f3(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
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entry:
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; CHECK-LABEL: f3:
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; CHECK-NOT: sub
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; CHECK: cmp
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; CHECK: blt
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%0 = load i32, i32* %offset, align 4
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%cmp = icmp slt i32 %0, %size
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%s = sub nsw i32 %0, %size
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%size2 = sub nsw i32 %size, 0
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br i1 %cmp, label %return, label %if.end
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if.end:
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; We are checking cse between %sub here and %s in entry block.
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%sub = sub nsw i32 %0, %size2
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%s2 = sub nsw i32 %s, %size
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%s3 = sub nsw i32 %sub, %s2
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; CHECK: sub [[R1:r[0-9]+]], [[R2:r[0-9]+]], r2
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; CHECK: sub [[R3:r[0-9]+]], r2, [[R1]]
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; CHECK: add [[R4:r[0-9]+]], [[R1]], [[R3]]
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; CHECK-NOT: sub
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; CHECK: str
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store i32 %s3, i32* %offset, align 4
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%add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub
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br label %return
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return:
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%retval.0 = phi i8* [ %add.ptr, %if.end ], [ null, %entry ]
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ret i8* %retval.0
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}
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; The cmp of %val should not be hoisted above the preceding conditional branch
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define void @f4(i32** %ptr1, i64* %ptr2, i64 %val) {
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entry:
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; CHECK-LABEL: f4:
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; CHECK: cmp
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; CHECK: movne
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; CHECK: strne
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; CHECK: orrs
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; CHECK-NOT: subs
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; CHECK-NOT: sbcs
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; CHECK: beq
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%tobool.not = icmp eq i32** %ptr1, null
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br i1 %tobool.not, label %if.end, label %if.then
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if.then:
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store i32* null, i32** %ptr1, align 4
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br label %if.end
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if.end:
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; CHECK: subs
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; CHECK: sbcs
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; CHECK: bxlt lr
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%tobool1 = icmp ne i64 %val, 0
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%cmp = icmp slt i64 %val, 10
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%or.cond = and i1 %tobool1, %cmp
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br i1 %or.cond, label %cleanup, label %if.end3
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if.end3:
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; CHECK: subs
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; CHECK: sbc
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%sub = add nsw i64 %val, -10
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store i64 %sub, i64* %ptr2, align 8
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br label %cleanup
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cleanup:
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ret void
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}
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