9fc347aa4e
PromoteIntRes_BUILD_VECTOR currently always ANY_EXTENDs build vector operands, but if this is a constant boolean vector we're losing the useful ability to keep the vector matching the BooleanContents mode used by the target. This patch extends constant boolean vectors according to target BooleanContents, allowing a number of additional all-bits folds (notable XOR -> NOT conversions) to occur. Differential Revision: https://reviews.llvm.org/D129641
542 lines
12 KiB
LLVM
542 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-- -mcpu=cortex-a8 | FileCheck %s -check-prefixes=CHECK,ARM
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; RUN: llc < %s -mtriple=thumb-- -mcpu=cortex-a8 | FileCheck %s -check-prefixes=CHECK,T2
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; rdar://8662825
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define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
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; ARM-LABEL: t1:
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; ARM: @ %bb.0:
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; ARM-NEXT: mov r0, r1
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; ARM-NEXT: cmp r2, #10
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; ARM-NEXT: suble r0, r0, #-2147483647
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t1:
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; T2: @ %bb.0:
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; T2-NEXT: mov r0, r1
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; T2-NEXT: mvn r1, #-2147483648
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; T2-NEXT: cmp r2, #10
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; T2-NEXT: it le
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; T2-NEXT: addle r0, r1
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; T2-NEXT: bx lr
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
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%tmp3 = add i32 %tmp2, %b
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ret i32 %tmp3
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; ARM-LABEL: t2:
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; ARM: @ %bb.0:
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; ARM-NEXT: mov r0, r1
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; ARM-NEXT: cmp r2, #10
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; ARM-NEXT: suble r0, r0, #10
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t2:
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; T2: @ %bb.0:
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; T2-NEXT: mov r0, r1
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; T2-NEXT: cmp r2, #10
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; T2-NEXT: it le
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; T2-NEXT: suble r0, #10
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; T2-NEXT: bx lr
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 10
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%tmp3 = sub i32 %b, %tmp2
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ret i32 %tmp3
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}
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define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
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; ARM-LABEL: t3:
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; ARM: @ %bb.0:
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: andge r3, r3, r2
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; ARM-NEXT: mov r0, r3
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t3:
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; T2: @ %bb.0:
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it ge
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; T2-NEXT: andge r3, r2
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; T2-NEXT: mov r0, r3
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; T2-NEXT: bx lr
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%cond = icmp slt i32 %a, %b
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%z = select i1 %cond, i32 -1, i32 %x
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%s = and i32 %z, %y
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ret i32 %s
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}
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define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
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; ARM-LABEL: t4:
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; ARM: @ %bb.0:
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: orrge r3, r3, r2
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; ARM-NEXT: mov r0, r3
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t4:
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; T2: @ %bb.0:
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it ge
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; T2-NEXT: orrge r3, r2
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; T2-NEXT: mov r0, r3
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; T2-NEXT: bx lr
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%cond = icmp slt i32 %a, %b
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%z = select i1 %cond, i32 0, i32 %x
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%s = or i32 %z, %y
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ret i32 %s
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}
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define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
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; ARM-LABEL: t5:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: orreq r2, r2, #1
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; ARM-NEXT: mov r0, r2
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t5:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it eq
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; T2-NEXT: orreq r2, r2, #1
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; T2-NEXT: mov r0, r2
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; T2-NEXT: bx lr
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entry:
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%tmp1 = icmp eq i32 %a, %b
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%tmp2 = zext i1 %tmp1 to i32
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%tmp3 = or i32 %tmp2, %c
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ret i32 %tmp3
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}
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define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; ARM-LABEL: t6:
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; ARM: @ %bb.0:
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: eorlt r3, r3, r2
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; ARM-NEXT: mov r0, r3
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t6:
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; T2: @ %bb.0:
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it lt
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; T2-NEXT: eorlt r3, r2
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; T2-NEXT: mov r0, r3
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; T2-NEXT: bx lr
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %c, i32 0
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%tmp2 = xor i32 %tmp1, %d
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ret i32 %tmp2
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}
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define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
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; ARM-LABEL: t7:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: andeq r2, r2, r2, lsl #1
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; ARM-NEXT: mov r0, r2
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t7:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it eq
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; T2-NEXT: andeq.w r2, r2, r2, lsl #1
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; T2-NEXT: mov r0, r2
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; T2-NEXT: bx lr
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entry:
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%tmp1 = shl i32 %c, 1
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%cond = icmp eq i32 %a, %b
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%tmp2 = select i1 %cond, i32 %tmp1, i32 -1
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%tmp3 = and i32 %c, %tmp2
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ret i32 %tmp3
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}
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; Fold ORRri into movcc.
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define i32 @t8(i32 %a, i32 %b) nounwind {
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; ARM-LABEL: t8:
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; ARM: @ %bb.0:
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: orrge r0, r1, #1
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t8:
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; T2: @ %bb.0:
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it ge
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; T2-NEXT: orrge r0, r1, #1
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; T2-NEXT: bx lr
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%x = or i32 %b, 1
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Fold ANDrr into movcc.
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define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
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; ARM-LABEL: t9:
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; ARM: @ %bb.0:
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: andge r0, r1, r2
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t9:
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; T2: @ %bb.0:
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it ge
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; T2-NEXT: andge.w r0, r1, r2
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; T2-NEXT: bx lr
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%x = and i32 %b, %c
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Fold EORrs into movcc.
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define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; ARM-LABEL: t10:
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; ARM: @ %bb.0:
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: eorge r0, r1, r2, lsl #7
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t10:
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; T2: @ %bb.0:
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it ge
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; T2-NEXT: eorge.w r0, r1, r2, lsl #7
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; T2-NEXT: bx lr
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%s = shl i32 %c, 7
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%x = xor i32 %b, %s
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Fold ORRri into movcc, reversing the condition.
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define i32 @t11(i32 %a, i32 %b) nounwind {
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; ARM-LABEL: t11:
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; ARM: @ %bb.0:
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: orrlt r0, r1, #1
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t11:
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; T2: @ %bb.0:
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it lt
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; T2-NEXT: orrlt r0, r1, #1
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; T2-NEXT: bx lr
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%x = or i32 %b, 1
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %x, i32 %a
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ret i32 %tmp1
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}
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; Fold ADDri12 into movcc
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define i32 @t12(i32 %a, i32 %b) nounwind {
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; ARM-LABEL: t12:
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; ARM: @ %bb.0:
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; ARM-NEXT: cmp r0, r1
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; ARM-NEXT: movw r2, #3000
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; ARM-NEXT: addge r0, r1, r2
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t12:
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; T2: @ %bb.0:
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; T2-NEXT: cmp r0, r1
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; T2-NEXT: it ge
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; T2-NEXT: addwge r0, r1, #3000
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; T2-NEXT: bx lr
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%x = add i32 %b, 3000
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Handle frame index operands.
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define void @pr13628() nounwind uwtable align 2 {
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; ARM-LABEL: pr13628:
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; ARM: @ %bb.0:
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; ARM-NEXT: push {r11, lr}
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; ARM-NEXT: sub sp, sp, #256
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; ARM-NEXT: ldrb r1, [r0]
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; ARM-NEXT: mov r0, sp
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; ARM-NEXT: cmp r1, #0
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; ARM-NEXT: moveq r0, r1
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; ARM-NEXT: bl bar
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; ARM-NEXT: add sp, sp, #256
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; ARM-NEXT: pop {r11, pc}
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;
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; T2-LABEL: pr13628:
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; T2: @ %bb.0:
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; T2-NEXT: push {r7, lr}
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; T2-NEXT: sub sp, #256
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; T2-NEXT: ldrb r1, [r0]
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; T2-NEXT: mov r0, sp
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; T2-NEXT: cmp r1, #0
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; T2-NEXT: it eq
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; T2-NEXT: moveq r0, r1
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; T2-NEXT: bl bar
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; T2-NEXT: add sp, #256
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; T2-NEXT: pop {r7, pc}
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%x3 = alloca i8, i32 256, align 8
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%x4 = load i8, i8* undef, align 1
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%x5 = icmp ne i8 %x4, 0
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%x6 = select i1 %x5, i8* %x3, i8* null
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call void @bar(i8* %x6) nounwind
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ret void
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}
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declare void @bar(i8*)
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; Fold zext i1 into predicated add
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define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {
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; ARM-LABEL: t13:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: cmp r1, #10
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; ARM-NEXT: addgt r0, r0, #1
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t13:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: cmp r1, #10
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; T2-NEXT: it gt
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; T2-NEXT: addgt r0, #1
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; T2-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 10
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%conv = zext i1 %cmp to i32
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%add = add i32 %conv, %c
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ret i32 %add
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}
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; Fold sext i1 into predicated sub
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define i32 @t14(i32 %c, i32 %a) nounwind readnone ssp {
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; ARM-LABEL: t14:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: cmp r1, #10
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; ARM-NEXT: subgt r0, r0, #1
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t14:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: cmp r1, #10
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; T2-NEXT: it gt
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; T2-NEXT: subgt r0, #1
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; T2-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, 10
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%conv = sext i1 %cmp to i32
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%add = add i32 %conv, %c
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ret i32 %add
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}
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; Fold the xor into the select.
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define i32 @t15(i32 %p) {
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; ARM-LABEL: t15:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: mov r1, #3
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; ARM-NEXT: cmp r0, #8
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; ARM-NEXT: movwgt r1, #0
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; ARM-NEXT: mov r0, r1
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t15:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: movs r1, #3
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; T2-NEXT: cmp r0, #8
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; T2-NEXT: it gt
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; T2-NEXT: movgt r1, #0
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; T2-NEXT: mov r0, r1
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; T2-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %p, 8
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%a = select i1 %cmp, i32 1, i32 2
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%xor = xor i32 %a, 1
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ret i32 %xor
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}
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define i32 @t16(i32 %x, i32 %y) {
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; ARM-LABEL: t16:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: cmp r0, #0
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; ARM-NEXT: mov r2, #2
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; ARM-NEXT: movweq r2, #5
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; ARM-NEXT: mov r0, #4
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; ARM-NEXT: cmp r1, #0
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; ARM-NEXT: movweq r0, #3
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; ARM-NEXT: and r0, r0, r2
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t16:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: cmp r0, #0
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; T2-NEXT: mov.w r2, #2
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; T2-NEXT: mov.w r0, #4
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; T2-NEXT: it eq
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; T2-NEXT: moveq r2, #5
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; T2-NEXT: cmp r1, #0
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; T2-NEXT: it eq
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; T2-NEXT: moveq r0, #3
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; T2-NEXT: ands r0, r2
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; T2-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %x, 0
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp eq i32 %y, 0
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%and = and i32 %cond2, %cond
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ret i32 %and
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}
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define i32 @t17(i32 %x, i32 %y) #0 {
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; ARM-LABEL: t17:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: cmn r0, #1
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; ARM-NEXT: mov r2, #2
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; ARM-NEXT: movweq r2, #5
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; ARM-NEXT: mov r0, #4
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; ARM-NEXT: cmn r1, #1
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; ARM-NEXT: movweq r0, #3
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; ARM-NEXT: and r0, r0, r2
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; ARM-NEXT: bx lr
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;
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; T2-LABEL: t17:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: adds r0, #1
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; T2-NEXT: mov.w r0, #2
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; T2-NEXT: it eq
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; T2-NEXT: moveq r0, #5
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; T2-NEXT: adds r1, #1
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; T2-NEXT: mov.w r1, #4
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; T2-NEXT: it eq
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; T2-NEXT: moveq r1, #3
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; T2-NEXT: ands r0, r1
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; T2-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %x, -1
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp eq i32 %y, -1
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%and = and i32 %cond2, %cond
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ret i32 %and
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}
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define i32 @t18(i32 %x, i32 %y) #0 {
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; ARM-LABEL: t18:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: mov r1, #2
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; ARM-NEXT: cmp r0, #0
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; ARM-NEXT: movwne r1, #5
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; ARM-NEXT: mov r2, #4
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; ARM-NEXT: cmn r0, #1
|
|
; ARM-NEXT: movwne r2, #3
|
|
; ARM-NEXT: and r0, r2, r1
|
|
; ARM-NEXT: bx lr
|
|
;
|
|
; T2-LABEL: t18:
|
|
; T2: @ %bb.0: @ %entry
|
|
; T2-NEXT: movs r1, #2
|
|
; T2-NEXT: cmp r0, #0
|
|
; T2-NEXT: it ne
|
|
; T2-NEXT: movne r1, #5
|
|
; T2-NEXT: adds r0, #1
|
|
; T2-NEXT: mov.w r0, #4
|
|
; T2-NEXT: it ne
|
|
; T2-NEXT: movne r0, #3
|
|
; T2-NEXT: ands r0, r1
|
|
; T2-NEXT: bx lr
|
|
entry:
|
|
%cmp = icmp ne i32 %x, 0
|
|
%cond = select i1 %cmp, i32 5, i32 2
|
|
%cmp1 = icmp ne i32 %x, -1
|
|
%cond2 = select i1 %cmp1, i32 3, i32 4
|
|
%and = and i32 %cond2, %cond
|
|
ret i32 %and
|
|
}
|
|
|
|
define i32 @t19(i32 %x, i32 %y) #0 {
|
|
; ARM-LABEL: t19:
|
|
; ARM: @ %bb.0: @ %entry
|
|
; ARM-NEXT: cmp r0, #0
|
|
; ARM-NEXT: mov r2, #2
|
|
; ARM-NEXT: movwne r2, #5
|
|
; ARM-NEXT: mov r0, #4
|
|
; ARM-NEXT: cmp r1, #0
|
|
; ARM-NEXT: movwne r0, #3
|
|
; ARM-NEXT: orr r0, r0, r2
|
|
; ARM-NEXT: bx lr
|
|
;
|
|
; T2-LABEL: t19:
|
|
; T2: @ %bb.0: @ %entry
|
|
; T2-NEXT: cmp r0, #0
|
|
; T2-NEXT: mov.w r2, #2
|
|
; T2-NEXT: mov.w r0, #4
|
|
; T2-NEXT: it ne
|
|
; T2-NEXT: movne r2, #5
|
|
; T2-NEXT: cmp r1, #0
|
|
; T2-NEXT: it ne
|
|
; T2-NEXT: movne r0, #3
|
|
; T2-NEXT: orrs r0, r2
|
|
; T2-NEXT: bx lr
|
|
entry:
|
|
%cmp = icmp ne i32 %x, 0
|
|
%cond = select i1 %cmp, i32 5, i32 2
|
|
%cmp1 = icmp ne i32 %y, 0
|
|
%cond2 = select i1 %cmp1, i32 3, i32 4
|
|
%or = or i32 %cond2, %cond
|
|
ret i32 %or
|
|
}
|
|
|
|
define i32 @t20(i32 %x, i32 %y) #0 {
|
|
; ARM-LABEL: t20:
|
|
; ARM: @ %bb.0: @ %entry
|
|
; ARM-NEXT: cmn r0, #1
|
|
; ARM-NEXT: mov r2, #2
|
|
; ARM-NEXT: movwne r2, #5
|
|
; ARM-NEXT: mov r0, #4
|
|
; ARM-NEXT: cmn r1, #1
|
|
; ARM-NEXT: movwne r0, #3
|
|
; ARM-NEXT: orr r0, r0, r2
|
|
; ARM-NEXT: bx lr
|
|
;
|
|
; T2-LABEL: t20:
|
|
; T2: @ %bb.0: @ %entry
|
|
; T2-NEXT: adds r0, #1
|
|
; T2-NEXT: mov.w r0, #2
|
|
; T2-NEXT: it ne
|
|
; T2-NEXT: movne r0, #5
|
|
; T2-NEXT: adds r1, #1
|
|
; T2-NEXT: mov.w r1, #4
|
|
; T2-NEXT: it ne
|
|
; T2-NEXT: movne r1, #3
|
|
; T2-NEXT: orrs r0, r1
|
|
; T2-NEXT: bx lr
|
|
entry:
|
|
%cmp = icmp ne i32 %x, -1
|
|
%cond = select i1 %cmp, i32 5, i32 2
|
|
%cmp1 = icmp ne i32 %y, -1
|
|
%cond2 = select i1 %cmp1, i32 3, i32 4
|
|
%or = or i32 %cond2, %cond
|
|
ret i32 %or
|
|
}
|
|
|
|
define <2 x i32> @t21(<2 x i32> %lhs, <2 x i32> %rhs) {
|
|
; CHECK-LABEL: t21:
|
|
; CHECK: @ %bb.0:
|
|
; CHECK-NEXT: vmov d16, r2, r3
|
|
; CHECK-NEXT: vmov d17, r0, r1
|
|
; CHECK-NEXT: vceq.i32 d16, d17, d16
|
|
; CHECK-NEXT: vmvn d16, d16
|
|
; CHECK-NEXT: vshl.i32 d16, d16, #31
|
|
; CHECK-NEXT: vshr.s32 d16, d16, #31
|
|
; CHECK-NEXT: vmov r0, r1, d16
|
|
; CHECK-NEXT: bx lr
|
|
%tst = icmp eq <2 x i32> %lhs, %rhs
|
|
%ntst = xor <2 x i1> %tst, <i1 1 , i1 undef>
|
|
%btst = sext <2 x i1> %ntst to <2 x i32>
|
|
ret <2 x i32> %btst
|
|
}
|