2caf85ad7a
Currently, LOAD_STACK_GUARD on ARM is only implemented for Mach-O targets, and other targets rely on the generic support which may result in spilling of the stack canary value or address, or may cause it to be kept in a callee save register across function calls, which means they essentially get spilled as well, only by the callee when it wants to free up this register. So let's implement LOAD_STACK GUARD for other targets as well. This ensures that the load of the stack canary is rematerialized fully in the epilogue. This code was split off from D112768: [ARM] implement support for TLS register based stack protector for which it is a prerequisite. Reviewed By: nickdesaulniers Differential Revision: https://reviews.llvm.org/D112811
36 lines
1.3 KiB
LLVM
36 lines
1.3 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target triple = "armv6kz-unknown-unknown-gnueabihf"
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; Make sure this doesn't crash, and we actually emit a tail call.
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; Unfortunately, this test is sort of fragile... the original issue only
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; shows up if scheduling happens in a very specific order. But including
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; it anyway just to demonstrate the issue.
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; CHECK: pop {r{{[0-9]+}}, lr}
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@e = external local_unnamed_addr constant [0 x i32 (i32, i32)*], align 4
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; Function Attrs: nounwind sspstrong
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define i32 @AVI_ChunkRead_p_chk(i32 %g) nounwind sspstrong "target-cpu"="arm1176jzf-s" {
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entry:
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%b = alloca i8, align 1
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%tobool = icmp eq i32 %g, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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%add = add nsw i32 %g, 1
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%arrayidx = getelementptr inbounds [0 x i32 (i32, i32)*], [0 x i32 (i32, i32)*]* @e, i32 0, i32 %add
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%0 = load i32 (i32, i32)*, i32 (i32, i32)** %arrayidx, align 4
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%call = tail call i32 %0(i32 0, i32 0) #3
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br label %return
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if.end: ; preds = %entry
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call void @c(i8* nonnull %b)
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br label %return
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return: ; preds = %if.end, %if.then
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%retval.0 = phi i32 [ %call, %if.then ], [ 0, %if.end ]
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ret i32 %retval.0
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}
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declare void @c(i8*)
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