884b919f2e
The issue that caused the revert has been fixed in:
44bd807512
-----
This switches Hexagon intrinsics to use the default attributes
(nosync, nofree, nocallback and willreturn). Especially willreturn
is needed to prevent optimization regressions in the future.
The only intrinsics I've excluded here are the load/store locked
intrinsics, which presumably aren't nosync.
Differential Revision: https://reviews.llvm.org/D137623
31 lines
1.3 KiB
LLVM
31 lines
1.3 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b < %s | FileCheck %s
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; Do not generate selectI1,Q,Q.
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; CHECK: q[[Q:[0-9]+]] = vsetq(r{{[0-9]+}})
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; CHECK: q{{[0-9]+}} = and(q{{[0-9]+}},q[[Q]])
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; CHECK-NOT: v{{[0-9]+}} = vand(q{{[0-9]+}},r{{[0-9]+}})
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target triple = "hexagon"
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declare void @llvm.hexagon.V6.vS32b.qpred.ai.128B(<128 x i1>, i8*, <32 x i32>) #0
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declare <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1
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declare <128 x i1> @llvm.hexagon.V6.pred.and.128B(<128 x i1>, <128 x i1>) #1
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define void @libjit_convertFromD32_sm_hf_wrap_3_specialized(i16* %0) local_unnamed_addr #2 {
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entry:
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%arrayidx55.i.i = getelementptr inbounds i16, i16* %0, i32 undef
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%1 = ptrtoint i16* %arrayidx55.i.i to i32
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%and.i5.i.i = and i32 %1, 127
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%2 = icmp eq i32 %and.i5.i.i, 127
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%.sroa.speculated.i13.i.i = zext i1 %2 to i32
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%3 = tail call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %.sroa.speculated.i13.i.i) #3
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%4 = tail call <128 x i1> @llvm.hexagon.V6.pred.and.128B(<128 x i1> undef, <128 x i1> %3) #3
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tail call void @llvm.hexagon.V6.vS32b.qpred.ai.128B(<128 x i1> %4, i8* nonnull undef, <32 x i32> undef) #3
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ret void
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}
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attributes #0 = { nounwind writeonly }
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attributes #1 = { nounwind readnone }
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attributes #2 = { "use-soft-float"="false" }
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attributes #3 = { nounwind }
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