facff468b6
GPR uses argument registers as the first group of registers to allocate. This patch uses vector argument registers, v8 to v23, as the first group to allocate. Differential Revision: https://reviews.llvm.org/D111304
44 lines
1.3 KiB
LLVM
44 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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%struct.Foo = type { i32, i32, i32, i16, i8 }
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@foo = global %struct.Foo { i32 1, i32 2, i32 3, i16 4, i8 5 }, align 4
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define i32 @callee(%struct.Foo* byval(%struct.Foo) %f) nounwind {
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; RV32I-LABEL: callee:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: ret
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entry:
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%0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0
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%1 = load i32, i32* %0, align 4
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ret i32 %1
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}
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define void @caller() nounwind {
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; RV32I-LABEL: caller:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: addi sp, sp, -32
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; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32I-NEXT: lui a0, %hi(foo)
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; RV32I-NEXT: lw a1, %lo(foo)(a0)
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; RV32I-NEXT: sw a1, 12(sp)
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; RV32I-NEXT: addi a0, a0, %lo(foo)
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; RV32I-NEXT: lw a1, 12(a0)
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; RV32I-NEXT: sw a1, 24(sp)
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; RV32I-NEXT: lw a1, 8(a0)
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; RV32I-NEXT: sw a1, 20(sp)
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; RV32I-NEXT: lw a0, 4(a0)
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; RV32I-NEXT: sw a0, 16(sp)
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; RV32I-NEXT: addi a0, sp, 12
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; RV32I-NEXT: call callee@plt
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; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 32
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; RV32I-NEXT: ret
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entry:
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%call = call i32 @callee(%struct.Foo* byval(%struct.Foo) @foo)
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ret void
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}
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