7b50c18360
The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S. If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included. Since most instructions are not included for Zfhmin, so most operations are promoted. The patch primarily about making f16 a legal type. RISC-V ISA info: https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D139391
46 lines
1.6 KiB
LLVM
46 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
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; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
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define half @half_imm() nounwind {
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; CHECK-LABEL: half_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
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; CHECK-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: half_imm:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECKIZFHMIN-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
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; CHECKIZFHMIN-NEXT: ret
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ret half 3.0
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}
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define half @half_imm_op(half %a) nounwind {
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; CHECK-LABEL: half_imm_op:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
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; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
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; CHECK-NEXT: fadd.h fa0, fa0, ft0
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; CHECK-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: half_imm_op:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: lui a0, %hi(.LCPI1_0)
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; CHECKIZFHMIN-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
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; CHECKIZFHMIN-NEXT: fcvt.s.h ft1, fa0
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; CHECKIZFHMIN-NEXT: fadd.s ft0, ft1, ft0
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; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, ft0
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; CHECKIZFHMIN-NEXT: ret
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%1 = fadd half %a, 1.0
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ret half %1
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}
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