ac1ec9e290
This reuses the existing optimized implementation of adjustReg, and commons up code. This has the effect of enabling two code changes for the new caller. First, we enable the "split andi" lowering (with no alignment requirement), and second we use a sub with smaller constant in register instead of a add with negative constant in register. Differential Revision: https://reviews.llvm.org/D132839
139 lines
6.9 KiB
LLVM
139 lines
6.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \
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; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
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; TODO: the quality of the generated code is poor
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define void @test() {
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; RV32I-FPELIM-LABEL: test:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: lui a0, 74565
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; RV32I-FPELIM-NEXT: addi a0, a0, 1664
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; RV32I-FPELIM-NEXT: sub sp, sp, a0
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 305419904
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; RV32I-FPELIM-NEXT: lui a0, 74565
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; RV32I-FPELIM-NEXT: addi a0, a0, 1664
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; RV32I-FPELIM-NEXT: add sp, sp, a0
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: test:
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; RV32I-WITHFP: # %bb.0:
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; RV32I-WITHFP-NEXT: addi sp, sp, -2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-WITHFP-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: .cfi_offset ra, -4
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; RV32I-WITHFP-NEXT: .cfi_offset s0, -8
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; RV32I-WITHFP-NEXT: addi s0, sp, 2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV32I-WITHFP-NEXT: lui a0, 74565
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; RV32I-WITHFP-NEXT: addi a0, a0, -352
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; RV32I-WITHFP-NEXT: sub sp, sp, a0
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; RV32I-WITHFP-NEXT: lui a0, 74565
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; RV32I-WITHFP-NEXT: addi a0, a0, -352
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; RV32I-WITHFP-NEXT: add sp, sp, a0
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; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: addi sp, sp, 2032
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; RV32I-WITHFP-NEXT: ret
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%tmp = alloca [ 305419896 x i8 ] , align 4
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ret void
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}
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; This test case artificially produces register pressure which should force
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; use of the emergency spill slot.
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define void @test_emergency_spill_slot(i32 %a) {
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; RV32I-FPELIM-LABEL: test_emergency_spill_slot:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi sp, sp, -2032
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-FPELIM-NEXT: sw s0, 2028(sp) # 4-byte Folded Spill
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; RV32I-FPELIM-NEXT: sw s1, 2024(sp) # 4-byte Folded Spill
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; RV32I-FPELIM-NEXT: .cfi_offset s0, -4
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; RV32I-FPELIM-NEXT: .cfi_offset s1, -8
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; RV32I-FPELIM-NEXT: lui a1, 97
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; RV32I-FPELIM-NEXT: addi a1, a1, 672
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; RV32I-FPELIM-NEXT: sub sp, sp, a1
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 400016
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; RV32I-FPELIM-NEXT: lui a1, 78
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; RV32I-FPELIM-NEXT: addi a2, sp, 8
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; RV32I-FPELIM-NEXT: add a1, a2, a1
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; RV32I-FPELIM-NEXT: #APP
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; RV32I-FPELIM-NEXT: nop
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; RV32I-FPELIM-NEXT: #NO_APP
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; RV32I-FPELIM-NEXT: sw a0, 512(a1)
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; RV32I-FPELIM-NEXT: #APP
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; RV32I-FPELIM-NEXT: nop
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; RV32I-FPELIM-NEXT: #NO_APP
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; RV32I-FPELIM-NEXT: lui a0, 97
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; RV32I-FPELIM-NEXT: addi a0, a0, 672
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; RV32I-FPELIM-NEXT: add sp, sp, a0
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; RV32I-FPELIM-NEXT: lw s0, 2028(sp) # 4-byte Folded Reload
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; RV32I-FPELIM-NEXT: lw s1, 2024(sp) # 4-byte Folded Reload
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; RV32I-FPELIM-NEXT: addi sp, sp, 2032
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
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; RV32I-WITHFP: # %bb.0:
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; RV32I-WITHFP-NEXT: addi sp, sp, -2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-WITHFP-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s1, 2020(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s2, 2016(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: .cfi_offset ra, -4
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; RV32I-WITHFP-NEXT: .cfi_offset s0, -8
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; RV32I-WITHFP-NEXT: .cfi_offset s1, -12
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; RV32I-WITHFP-NEXT: .cfi_offset s2, -16
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; RV32I-WITHFP-NEXT: addi s0, sp, 2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV32I-WITHFP-NEXT: lui a1, 97
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; RV32I-WITHFP-NEXT: addi a1, a1, 688
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; RV32I-WITHFP-NEXT: sub sp, sp, a1
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; RV32I-WITHFP-NEXT: lui a1, 78
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; RV32I-WITHFP-NEXT: lui a2, 98
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; RV32I-WITHFP-NEXT: addi a2, a2, -1388
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; RV32I-WITHFP-NEXT: sub a2, s0, a2
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; RV32I-WITHFP-NEXT: add a1, a2, a1
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; RV32I-WITHFP-NEXT: #APP
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; RV32I-WITHFP-NEXT: nop
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; RV32I-WITHFP-NEXT: #NO_APP
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; RV32I-WITHFP-NEXT: sw a0, 512(a1)
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; RV32I-WITHFP-NEXT: #APP
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; RV32I-WITHFP-NEXT: nop
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; RV32I-WITHFP-NEXT: #NO_APP
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; RV32I-WITHFP-NEXT: lui a0, 97
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; RV32I-WITHFP-NEXT: addi a0, a0, 688
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; RV32I-WITHFP-NEXT: add sp, sp, a0
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; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: addi sp, sp, 2032
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; RV32I-WITHFP-NEXT: ret
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%data = alloca [ 100000 x i32 ] , align 4
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%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
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%1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
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%asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0
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%asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1
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%asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2
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%asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3
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%asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 4
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%asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 5
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%asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 6
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%asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 7
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%asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 8
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%asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 9
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%asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 10
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%asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 11
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%asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 12
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%asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 13
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%asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 14
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store volatile i32 %a, i32* %ptr
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tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult0, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14)
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ret void
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}
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