b775333068
Fold the low 12 bits of an immediate offset into the offset field of the using instruction. That using instruction will be a load, store, or addi which performs an add of a signed 12-bit immediate as part of it's operation. Splitting out the low bits allows the high bits to be generated via a single LUI instead of needing an LUI/ADDI pair. The codegen effect of this is mostly converting cases where "split addi" kicks in to using LUI + a folded offset. There are a couple of straight dynamic instruction count wins, and using a canonical LUI is probably better than a chain of SP adds if the dynamic instruction count is equal. Differential Revision: https://reviews.llvm.org/D139037
278 lines
9.0 KiB
LLVM
278 lines
9.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 < %s | FileCheck --check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv32 < %s | FileCheck --check-prefix=RV32I %s
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@var = external global i32
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define void @func() {
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; RV64I-LABEL: func:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addiw a0, a0, 16
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; RV64I-NEXT: sub sp, sp, a0
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; RV64I-NEXT: .cfi_def_cfa_offset 4112
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; RV64I-NEXT: lui a0, %hi(var)
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; RV64I-NEXT: lw a1, %lo(var)(a0)
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; RV64I-NEXT: lw a2, %lo(var)(a0)
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; RV64I-NEXT: lw a3, %lo(var)(a0)
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; RV64I-NEXT: lw a4, %lo(var)(a0)
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; RV64I-NEXT: lw a5, %lo(var)(a0)
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; RV64I-NEXT: lw a6, %lo(var)(a0)
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; RV64I-NEXT: lw a7, %lo(var)(a0)
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; RV64I-NEXT: lw t0, %lo(var)(a0)
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; RV64I-NEXT: lw t1, %lo(var)(a0)
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; RV64I-NEXT: lw t2, %lo(var)(a0)
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; RV64I-NEXT: lw t3, %lo(var)(a0)
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; RV64I-NEXT: lw t4, %lo(var)(a0)
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; RV64I-NEXT: lw t5, %lo(var)(a0)
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; RV64I-NEXT: lw t6, %lo(var)(a0)
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; RV64I-NEXT: sd s0, 0(sp)
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; RV64I-NEXT: lui s0, 1
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; RV64I-NEXT: add s0, sp, s0
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; RV64I-NEXT: sw a1, 12(s0)
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; RV64I-NEXT: ld s0, 0(sp)
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; RV64I-NEXT: sw a1, %lo(var)(a0)
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; RV64I-NEXT: sw a2, %lo(var)(a0)
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; RV64I-NEXT: sw a3, %lo(var)(a0)
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; RV64I-NEXT: sw a4, %lo(var)(a0)
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; RV64I-NEXT: sw a5, %lo(var)(a0)
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; RV64I-NEXT: sw a6, %lo(var)(a0)
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; RV64I-NEXT: sw a7, %lo(var)(a0)
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; RV64I-NEXT: sw t0, %lo(var)(a0)
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; RV64I-NEXT: sw t1, %lo(var)(a0)
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; RV64I-NEXT: sw t2, %lo(var)(a0)
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; RV64I-NEXT: sw t3, %lo(var)(a0)
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; RV64I-NEXT: sw t4, %lo(var)(a0)
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; RV64I-NEXT: sw t5, %lo(var)(a0)
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; RV64I-NEXT: sw t6, %lo(var)(a0)
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addiw a0, a0, 16
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; RV64I-NEXT: add sp, sp, a0
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: func:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, 16
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; RV32I-NEXT: sub sp, sp, a0
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; RV32I-NEXT: .cfi_def_cfa_offset 4112
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; RV32I-NEXT: lui a0, %hi(var)
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; RV32I-NEXT: lw a1, %lo(var)(a0)
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; RV32I-NEXT: lw a2, %lo(var)(a0)
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; RV32I-NEXT: lw a3, %lo(var)(a0)
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; RV32I-NEXT: lw a4, %lo(var)(a0)
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; RV32I-NEXT: lw a5, %lo(var)(a0)
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; RV32I-NEXT: lw a6, %lo(var)(a0)
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; RV32I-NEXT: lw a7, %lo(var)(a0)
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; RV32I-NEXT: lw t0, %lo(var)(a0)
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; RV32I-NEXT: lw t1, %lo(var)(a0)
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; RV32I-NEXT: lw t2, %lo(var)(a0)
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; RV32I-NEXT: lw t3, %lo(var)(a0)
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; RV32I-NEXT: lw t4, %lo(var)(a0)
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; RV32I-NEXT: lw t5, %lo(var)(a0)
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; RV32I-NEXT: lw t6, %lo(var)(a0)
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; RV32I-NEXT: sw s0, 0(sp)
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; RV32I-NEXT: lui s0, 1
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; RV32I-NEXT: add s0, sp, s0
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; RV32I-NEXT: sw a1, 12(s0)
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; RV32I-NEXT: lw s0, 0(sp)
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; RV32I-NEXT: sw a1, %lo(var)(a0)
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; RV32I-NEXT: sw a2, %lo(var)(a0)
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; RV32I-NEXT: sw a3, %lo(var)(a0)
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; RV32I-NEXT: sw a4, %lo(var)(a0)
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; RV32I-NEXT: sw a5, %lo(var)(a0)
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; RV32I-NEXT: sw a6, %lo(var)(a0)
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; RV32I-NEXT: sw a7, %lo(var)(a0)
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; RV32I-NEXT: sw t0, %lo(var)(a0)
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; RV32I-NEXT: sw t1, %lo(var)(a0)
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; RV32I-NEXT: sw t2, %lo(var)(a0)
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; RV32I-NEXT: sw t3, %lo(var)(a0)
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; RV32I-NEXT: sw t4, %lo(var)(a0)
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; RV32I-NEXT: sw t5, %lo(var)(a0)
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; RV32I-NEXT: sw t6, %lo(var)(a0)
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, 16
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; RV32I-NEXT: add sp, sp, a0
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; RV32I-NEXT: ret
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%space = alloca i32, align 4
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%stackspace = alloca[1024 x i32], align 4
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;; Load values to increase register pressure.
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%v0 = load volatile i32, i32* @var
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%v1 = load volatile i32, i32* @var
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%v2 = load volatile i32, i32* @var
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%v3 = load volatile i32, i32* @var
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%v4 = load volatile i32, i32* @var
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%v5 = load volatile i32, i32* @var
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%v6 = load volatile i32, i32* @var
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%v7 = load volatile i32, i32* @var
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%v8 = load volatile i32, i32* @var
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%v9 = load volatile i32, i32* @var
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%v10 = load volatile i32, i32* @var
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%v11 = load volatile i32, i32* @var
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%v12 = load volatile i32, i32* @var
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%v13 = load volatile i32, i32* @var
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store volatile i32 %v0, i32* %space
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;; store values so they are used.
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store volatile i32 %v0, i32* @var
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store volatile i32 %v1, i32* @var
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store volatile i32 %v2, i32* @var
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store volatile i32 %v3, i32* @var
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store volatile i32 %v4, i32* @var
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store volatile i32 %v5, i32* @var
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store volatile i32 %v6, i32* @var
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store volatile i32 %v7, i32* @var
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store volatile i32 %v8, i32* @var
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store volatile i32 %v9, i32* @var
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store volatile i32 %v10, i32* @var
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store volatile i32 %v11, i32* @var
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store volatile i32 %v12, i32* @var
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store volatile i32 %v13, i32* @var
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ret void
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}
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define void @shrink_wrap(i1 %c) {
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; RV64I-LABEL: shrink_wrap:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: bnez a0, .LBB1_2
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; RV64I-NEXT: # %bb.1: # %bar
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addiw a0, a0, 16
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; RV64I-NEXT: sub sp, sp, a0
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; RV64I-NEXT: .cfi_def_cfa_offset 4112
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; RV64I-NEXT: lui a0, %hi(var)
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; RV64I-NEXT: lw a1, %lo(var)(a0)
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; RV64I-NEXT: lw a2, %lo(var)(a0)
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; RV64I-NEXT: lw a3, %lo(var)(a0)
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; RV64I-NEXT: lw a4, %lo(var)(a0)
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; RV64I-NEXT: lw a5, %lo(var)(a0)
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; RV64I-NEXT: lw a6, %lo(var)(a0)
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; RV64I-NEXT: lw a7, %lo(var)(a0)
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; RV64I-NEXT: lw t0, %lo(var)(a0)
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; RV64I-NEXT: lw t1, %lo(var)(a0)
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; RV64I-NEXT: lw t2, %lo(var)(a0)
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; RV64I-NEXT: lw t3, %lo(var)(a0)
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; RV64I-NEXT: lw t4, %lo(var)(a0)
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; RV64I-NEXT: lw t5, %lo(var)(a0)
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; RV64I-NEXT: lw t6, %lo(var)(a0)
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; RV64I-NEXT: sd s0, 0(sp)
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; RV64I-NEXT: lui s0, 1
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; RV64I-NEXT: add s0, sp, s0
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; RV64I-NEXT: sw a1, 12(s0)
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; RV64I-NEXT: ld s0, 0(sp)
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; RV64I-NEXT: sw a1, %lo(var)(a0)
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; RV64I-NEXT: sw a2, %lo(var)(a0)
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; RV64I-NEXT: sw a3, %lo(var)(a0)
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; RV64I-NEXT: sw a4, %lo(var)(a0)
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; RV64I-NEXT: sw a5, %lo(var)(a0)
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; RV64I-NEXT: sw a6, %lo(var)(a0)
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; RV64I-NEXT: sw a7, %lo(var)(a0)
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; RV64I-NEXT: sw t0, %lo(var)(a0)
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; RV64I-NEXT: sw t1, %lo(var)(a0)
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; RV64I-NEXT: sw t2, %lo(var)(a0)
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; RV64I-NEXT: sw t3, %lo(var)(a0)
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; RV64I-NEXT: sw t4, %lo(var)(a0)
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; RV64I-NEXT: sw t5, %lo(var)(a0)
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; RV64I-NEXT: sw t6, %lo(var)(a0)
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addiw a0, a0, 16
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; RV64I-NEXT: add sp, sp, a0
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; RV64I-NEXT: .LBB1_2: # %foo
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; RV64I-NEXT: ret
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;
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; RV32I-LABEL: shrink_wrap:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: bnez a0, .LBB1_2
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; RV32I-NEXT: # %bb.1: # %bar
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, 16
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; RV32I-NEXT: sub sp, sp, a0
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; RV32I-NEXT: .cfi_def_cfa_offset 4112
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; RV32I-NEXT: lui a0, %hi(var)
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; RV32I-NEXT: lw a1, %lo(var)(a0)
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; RV32I-NEXT: lw a2, %lo(var)(a0)
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; RV32I-NEXT: lw a3, %lo(var)(a0)
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; RV32I-NEXT: lw a4, %lo(var)(a0)
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; RV32I-NEXT: lw a5, %lo(var)(a0)
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; RV32I-NEXT: lw a6, %lo(var)(a0)
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; RV32I-NEXT: lw a7, %lo(var)(a0)
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; RV32I-NEXT: lw t0, %lo(var)(a0)
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; RV32I-NEXT: lw t1, %lo(var)(a0)
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; RV32I-NEXT: lw t2, %lo(var)(a0)
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; RV32I-NEXT: lw t3, %lo(var)(a0)
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; RV32I-NEXT: lw t4, %lo(var)(a0)
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; RV32I-NEXT: lw t5, %lo(var)(a0)
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; RV32I-NEXT: lw t6, %lo(var)(a0)
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; RV32I-NEXT: sw s0, 0(sp)
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; RV32I-NEXT: lui s0, 1
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; RV32I-NEXT: add s0, sp, s0
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; RV32I-NEXT: sw a1, 12(s0)
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; RV32I-NEXT: lw s0, 0(sp)
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; RV32I-NEXT: sw a1, %lo(var)(a0)
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; RV32I-NEXT: sw a2, %lo(var)(a0)
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; RV32I-NEXT: sw a3, %lo(var)(a0)
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; RV32I-NEXT: sw a4, %lo(var)(a0)
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; RV32I-NEXT: sw a5, %lo(var)(a0)
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; RV32I-NEXT: sw a6, %lo(var)(a0)
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; RV32I-NEXT: sw a7, %lo(var)(a0)
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; RV32I-NEXT: sw t0, %lo(var)(a0)
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; RV32I-NEXT: sw t1, %lo(var)(a0)
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; RV32I-NEXT: sw t2, %lo(var)(a0)
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; RV32I-NEXT: sw t3, %lo(var)(a0)
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; RV32I-NEXT: sw t4, %lo(var)(a0)
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; RV32I-NEXT: sw t5, %lo(var)(a0)
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; RV32I-NEXT: sw t6, %lo(var)(a0)
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, 16
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; RV32I-NEXT: add sp, sp, a0
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; RV32I-NEXT: .LBB1_2: # %foo
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; RV32I-NEXT: ret
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%space = alloca i32, align 4
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%stackspace = alloca[1024 x i32], align 4
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br i1 %c, label %foo, label %bar
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bar:
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;; Load values to increase register pressure.
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%v0 = load volatile i32, i32* @var
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%v1 = load volatile i32, i32* @var
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%v2 = load volatile i32, i32* @var
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%v3 = load volatile i32, i32* @var
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%v4 = load volatile i32, i32* @var
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%v5 = load volatile i32, i32* @var
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%v6 = load volatile i32, i32* @var
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%v7 = load volatile i32, i32* @var
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%v8 = load volatile i32, i32* @var
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%v9 = load volatile i32, i32* @var
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%v10 = load volatile i32, i32* @var
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%v11 = load volatile i32, i32* @var
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%v12 = load volatile i32, i32* @var
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%v13 = load volatile i32, i32* @var
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store volatile i32 %v0, i32* %space
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;; store values so they are used.
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store volatile i32 %v0, i32* @var
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store volatile i32 %v1, i32* @var
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store volatile i32 %v2, i32* @var
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store volatile i32 %v3, i32* @var
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store volatile i32 %v4, i32* @var
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store volatile i32 %v5, i32* @var
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store volatile i32 %v6, i32* @var
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store volatile i32 %v7, i32* @var
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store volatile i32 %v8, i32* @var
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store volatile i32 %v9, i32* @var
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store volatile i32 %v10, i32* @var
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store volatile i32 %v11, i32* @var
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store volatile i32 %v12, i32* @var
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store volatile i32 %v13, i32* @var
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br label %foo
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foo:
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ret void
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}
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