48904e9452
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
240 lines
6.5 KiB
YAML
240 lines
6.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
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--- |
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define void @test_insert_128_idx0() {
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ret void
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}
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define void @test_insert_128_idx0_undef() {
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ret void
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}
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define void @test_insert_128_idx1() {
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ret void
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}
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define void @test_insert_128_idx1_undef() {
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ret void
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}
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define void @test_insert_256_idx0() {
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ret void
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}
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define void @test_insert_256_idx0_undef() {
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ret void
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}
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define void @test_insert_256_idx1() {
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ret void
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}
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define void @test_insert_256_idx1_undef() {
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ret void
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}
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...
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---
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name: test_insert_128_idx0
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $ymm1
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; ALL-LABEL: name: test_insert_128_idx0
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; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
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; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 0
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; ALL: $zmm0 = COPY [[VINSERTF32x4Zrr]]
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = COPY $zmm0
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%1(<4 x s32>) = COPY $xmm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_128_idx0_undef
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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; ALL-LABEL: name: test_insert_128_idx0_undef
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; ALL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1
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; ALL: undef %2.sub_xmm:vr512 = COPY [[COPY]]
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; ALL: $zmm0 = COPY %2
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = IMPLICIT_DEF
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%1(<4 x s32>) = COPY $xmm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_128_idx1
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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; ALL-LABEL: name: test_insert_128_idx1
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; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
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; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 1
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; ALL: $zmm0 = COPY [[VINSERTF32x4Zrr]]
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = COPY $zmm0
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%1(<4 x s32>) = COPY $xmm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_128_idx1_undef
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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; ALL-LABEL: name: test_insert_128_idx1_undef
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; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
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; ALL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1
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; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[DEF]], [[COPY]], 1
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; ALL: $zmm0 = COPY [[VINSERTF32x4Zrr]]
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = IMPLICIT_DEF
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%1(<4 x s32>) = COPY $xmm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_256_idx0
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $zmm0, $ymm1
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; ALL-LABEL: name: test_insert_256_idx0
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; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1
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; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 0
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; ALL: $zmm0 = COPY [[VINSERTF64x4Zrr]]
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = COPY $zmm0
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%1(<8 x s32>) = COPY $ymm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_256_idx0_undef
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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; ALL-LABEL: name: test_insert_256_idx0_undef
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; ALL: [[COPY:%[0-9]+]]:vr256x = COPY $ymm1
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; ALL: undef %2.sub_ymm:vr512 = COPY [[COPY]]
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; ALL: $zmm0 = COPY %2
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = IMPLICIT_DEF
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%1(<8 x s32>) = COPY $ymm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_256_idx1
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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; ALL-LABEL: name: test_insert_256_idx1
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; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
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; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1
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; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 1
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; ALL: $zmm0 = COPY [[VINSERTF64x4Zrr]]
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = COPY $zmm0
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%1(<8 x s32>) = COPY $ymm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_256_idx1_undef
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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; ALL-LABEL: name: test_insert_256_idx1_undef
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; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
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; ALL: [[COPY:%[0-9]+]]:vr256x = COPY $ymm1
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; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[DEF]], [[COPY]], 1
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; ALL: $zmm0 = COPY [[VINSERTF64x4Zrr]]
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; ALL: RET 0, implicit $ymm0
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%0(<16 x s32>) = IMPLICIT_DEF
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%1(<8 x s32>) = COPY $ymm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
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$zmm0 = COPY %2(<16 x s32>)
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RET 0, implicit $ymm0
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...
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