5ecd363295
This reverts commit 122efef8ee.
- Patch fixed to not reuse definitions from predecessors in EH landing pads.
- Late review suggestions (by MaskRay) have been addressed.
- M68k/pipeline.ll test updated.
- Init captures added in processBlock() to avoid capturing structured bindings.
- RISCV has this disabled for now.
Original commit message:
A new pass MachineLateInstrsCleanup is added to be run after PEI.
This is a simple pass that removes redundant and identical instructions
whenever found by scanning the MF once while keeping track of register
definitions in a map. These instructions are typically immediate loads
resulting from rematerialization, and address loads emitted by target in
eliminateFrameInde().
This is enabled by default, but a target could easily disable it by means of
'disablePass(&MachineLateInstrsCleanupID);'.
This late cleanup is naturally not "optimal" in removing instructions as it
is done by looking at phys-regs, but still quite effective. It would be
desirable to improve other parts of CodeGen and avoid these redundant
instructions in the first place, but there are no ideas for this yet.
Differential Revision: https://reviews.llvm.org/D123394
Reviewed By: RKSimon, foad, craig.topper, arsenm, asb
115 lines
4.3 KiB
LLVM
115 lines
4.3 KiB
LLVM
; RUN: llc < %s -march=xcore | FileCheck %s
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@size = global i32 0 ; <i32*> [#uses=1]
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@g0 = external global i32 ; <i32*> [#uses=2]
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@g1 = external global i32 ; <i32*> [#uses=2]
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@g2 = external global i32 ; <i32*> [#uses=2]
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@g3 = external global i32 ; <i32*> [#uses=2]
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@g4 = external global i32 ; <i32*> [#uses=2]
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@g5 = external global i32 ; <i32*> [#uses=2]
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@g6 = external global i32 ; <i32*> [#uses=2]
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@g7 = external global i32 ; <i32*> [#uses=2]
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@g8 = external global i32 ; <i32*> [#uses=2]
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@g9 = external global i32 ; <i32*> [#uses=2]
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@g10 = external global i32 ; <i32*> [#uses=2]
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@g11 = external global i32 ; <i32*> [#uses=2]
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define void @f() nounwind {
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entry:
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%x = alloca [100 x i32], align 4 ; <[100 x i32]*> [#uses=2]
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%0 = load i32, i32* @size, align 4 ; <i32> [#uses=1]
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%1 = alloca i32, i32 %0, align 4 ; <i32*> [#uses=1]
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%2 = load volatile i32, i32* @g0, align 4 ; <i32> [#uses=1]
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%3 = load volatile i32, i32* @g1, align 4 ; <i32> [#uses=1]
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%4 = load volatile i32, i32* @g2, align 4 ; <i32> [#uses=1]
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%5 = load volatile i32, i32* @g3, align 4 ; <i32> [#uses=1]
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%6 = load volatile i32, i32* @g4, align 4 ; <i32> [#uses=1]
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%7 = load volatile i32, i32* @g5, align 4 ; <i32> [#uses=1]
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%8 = load volatile i32, i32* @g6, align 4 ; <i32> [#uses=1]
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%9 = load volatile i32, i32* @g7, align 4 ; <i32> [#uses=1]
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%10 = load volatile i32, i32* @g8, align 4 ; <i32> [#uses=1]
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%11 = load volatile i32, i32* @g9, align 4 ; <i32> [#uses=1]
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%12 = load volatile i32, i32* @g10, align 4 ; <i32> [#uses=1]
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%13 = load volatile i32, i32* @g11, align 4 ; <i32> [#uses=2]
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%14 = getelementptr [100 x i32], [100 x i32]* %x, i32 0, i32 50 ; <i32*> [#uses=1]
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store i32 %13, i32* %14, align 4
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store volatile i32 %13, i32* @g11, align 4
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store volatile i32 %12, i32* @g10, align 4
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store volatile i32 %11, i32* @g9, align 4
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store volatile i32 %10, i32* @g8, align 4
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store volatile i32 %9, i32* @g7, align 4
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store volatile i32 %8, i32* @g6, align 4
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store volatile i32 %7, i32* @g5, align 4
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store volatile i32 %6, i32* @g4, align 4
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store volatile i32 %5, i32* @g3, align 4
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store volatile i32 %4, i32* @g2, align 4
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store volatile i32 %3, i32* @g1, align 4
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store volatile i32 %2, i32* @g0, align 4
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%x1 = getelementptr [100 x i32], [100 x i32]* %x, i32 0, i32 0 ; <i32*> [#uses=1]
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call void @g(i32* %x1, i32* %1) nounwind
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ret void
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}
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declare void @g(i32*, i32*)
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; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
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; CHECK: .p2align 2
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; CHECK: [[ARG5:.LCPI[0-9_]+]]:
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; CHECK: .long 100003
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; CHECK: [[INDEX0:.LCPI[0-9_]+]]:
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; CHECK: .long 80002
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; CHECK: [[INDEX1:.LCPI[0-9_]+]]:
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; CHECK: .long 81002
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; CHECK: [[INDEX2:.LCPI[0-9_]+]]:
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; CHECK: .long 82002
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; CHECK: [[INDEX3:.LCPI[0-9_]+]]:
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; CHECK: .long 83002
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; CHECK: [[INDEX4:.LCPI[0-9_]+]]:
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; CHECK: .long 84002
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; CHECK: .text
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; !FP + large frame: spill SR+SR = entsp 2 + 100000
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; CHECK-LABEL: ScavengeSlots:
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; CHECK: entsp 65535
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; CHECK: extsp 34467
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; scavenge r11
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; CHECK: ldaw r11, sp[0]
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; scavenge r4 using SR spill slot
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; CHECK: stw r4, sp[1]
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; CHECK: ldw r4, cp[[[ARG5]]]
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; r11 used to load 5th argument
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; CHECK: ldw r11, r11[r4]
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; CHECK: ldaw r4, sp[0]
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; scavenge r5 using SR spill slot
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; CHECK: stw r5, sp[0]
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; CHECK: ldw r5, cp[[[INDEX0]]]
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; r4 & r5 used by InsertSPConstInst() to emit STW_l3r instruction.
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; CHECK: stw r0, r4[r5]
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; CHECK: ldaw r0, sp[0]
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; CHECK: ldw r5, cp[[[INDEX1]]]
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; CHECK: stw r1, r0[r5]
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; CHECK: ldw r1, cp[[[INDEX2]]]
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; CHECK: stw r2, r0[r1]
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; CHECK: ldw r1, cp[[[INDEX3]]]
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; CHECK: stw r3, r0[r1]
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; CHECK: ldw r1, cp[[[INDEX4]]]
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; CHECK: stw r11, r0[r1]
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; CHECK: ldaw sp, sp[65535]
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; CHECK: ldw r4, sp[1]
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; CHECK: ldw r5, sp[0]
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; CHECK: retsp 34467
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define void @ScavengeSlots(i32 %r0, i32 %r1, i32 %r2, i32 %r3, i32 %r4) nounwind {
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entry:
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%Data = alloca [100000 x i32]
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%i0 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 80000
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store volatile i32 %r0, i32* %i0
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%i1 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 81000
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store volatile i32 %r1, i32* %i1
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%i2 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 82000
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store volatile i32 %r2, i32* %i2
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%i3 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 83000
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store volatile i32 %r3, i32* %i3
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%i4 = getelementptr inbounds [100000 x i32], [100000 x i32]* %Data, i32 0, i32 84000
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store volatile i32 %r4, i32* %i4
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ret void
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}
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